Semiconductor device and method of forming the same

Abstract

The present invention relates to a semiconductor device and a method for forming the same, wherein a semiconductor device includes a substrate; a collector having a buried layer disposed within the substrate, a first well region located above a first portion of the buried layer, and a first conductive region at least partially disposed within the first well region; a base having a second well region located above a second portion of the buried layer and laterally adjacent to the first well region, and a second conductive region at least partially disposed within the second well region; an emitter having a third conductive region at least partially disposed within the second conductive region; an isolation element located between the first conductive region and the third conductive region; and a conductive plate located on the isolation element and electrically connected to the first conductive region. The buried layer, the first well region, the first conductive region, and the third conductive region have a first conductivity type; and the second well region and the second conductive region have a second conductivity type.

Description

Technical Field

[0001] The present invention relates generally to semiconductor devices and methods of forming semiconductor devices. More particularly, the present invention relates to electrostatic discharge (ESD) protection devices and methods of forming ESD protection devices. Background Art

[0002] As integrated circuits continue to shrink in size, they become more sensitive to electrostatic discharge (ESD). It is important to protect the core circuits from ESD by using ESD protection circuits connected to them.

[0003] Deep snapback ESD protection devices used for high voltage power clamps may cause latch-up issues. Therefore, non-snapback PNP-based ESD protection devices can be used to provide latch-up-free high voltage ESD protection.

[0004] Figure 1A 1 shows a cross-sectional view of a conventional PNP device 100 for ESD protection, Figure 1B An equivalent circuit 150 of a conventional PNP device 100 is shown.

[0005] like Figure 1A As shown, an n-type buried layer (NBL) 104 and an n-type epitaxial layer (N-Epi) 106 are disposed within a p-substrate (P-Sub) 102, and together with an N-well 108 disposed within the N-Epi layer 106, form the base region of the PNP device 100. The emitter region 120 of the PNP device 100 includes a P+ region 122 disposed within the N-well 108. An N+ region 112 is also disposed within the N-well 108, forming a resistor 110 connected between the base region and the emitter region 120 of the PNP device 100, as shown in FIG. Figure 1B As shown, the collector region 130 includes a P-well 132 disposed within the N-Epi layer 106 and a P+ region 134 disposed within the P-well 132. Conventional PNP devices 100 provide latch-free ESD protection. However, they may exhibit high on-resistance and low fault current. Summary of the Invention

[0006] According to various non-limiting embodiments, a semiconductor device is provided. The semiconductor device may include a substrate, a collector region disposed within the substrate. The collector region may include a buried layer disposed within the substrate, a first well region disposed above a first portion of the buried layer, and a first conductive region disposed at least partially within the first well region. The semiconductor device may further include a base region disposed above a second portion of the buried layer, wherein the base region may include a second well region disposed above the second portion of the buried layer and a second conductive region disposed at least partially within the second well region, wherein the first well region laterally abuts the second well region. The semiconductor device may further include an emitter region, the emitter region including a third conductive region disposed at least partially within the second conductive region, an isolation element disposed between the first conductive region and the third conductive region, and a conductive plate disposed on the isolation element and electrically connected to the first conductive region. The buried layer, the first well region, the first conductive region, and the third conductive region may have a first conductivity type, and the second well region and the second conductive region may have a second conductivity type different from the first conductivity type.

[0007] According to various non-limiting embodiments, a method for forming a semiconductor device is provided. The method may include providing a substrate, forming a buried layer within the substrate, forming a first well region above a first portion of the buried layer, forming a first conductive region at least partially within the first well region to form a collector region comprising the buried layer, the first well region, and the first conductive region. The method may include forming a second well region above a second portion of the buried layer, wherein the first well region is laterally adjacent to the second well region, forming a second conductive region at least partially within the second well region to form a base region comprising the second well region and the second conductive region, forming a third conductive region at least partially within the second conductive region to form an emitter region, forming an isolation element between the first conductive region and the third conductive region, and forming a conductive plate on the isolation element and electrically connecting the conductive plate to the first conductive region. The buried layer, the first well region, the first conductive region, and the third conductive region may have a first conductivity type. The second well region and the second conductive region may have a second conductivity type different from the first conductivity type. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In the accompanying drawings, like reference numerals generally refer to like parts throughout the different views. Furthermore, the drawings are not necessarily to scale, but rather generally focus on illustrating the principles of the invention. For purposes of illustration, embodiments of the invention will be described with reference only to the following drawings, in which:

[0009] Figure 1A shows a cross-sectional view of a conventional PNP device for ESD protection; Figure 1B The equivalent circuit of a conventional PNP device is shown.

[0010] Figure 2 Cross-sectional views of semiconductor devices according to various non-limiting embodiments are shown.

[0011] Figure 3 Cross-sectional views of semiconductor devices according to various non-limiting embodiments are shown.

[0012] Figure 4 Shown according to various non-limiting embodiments Figure 3 A top view of a semiconductor device.

[0013] Figure 5 Cross-sectional views of semiconductor devices according to various non-limiting embodiments are shown.

[0014] Figure 6A Cross-sectional views of semiconductor devices according to various non-limiting embodiments are shown.

[0015] Figure 6B Cross-sectional views of semiconductor devices according to various non-limiting embodiments are shown.

[0016] Figure 7 Shown according to various non-limiting embodiments Figure 5 、 Figure 6A and Figure 6B Equivalent circuit of a semiconductor device.

[0017] Figure 8A Exemplary doping profiles along vertical cut lines through a semiconductor device according to various embodiments are shown.

[0018] Figure 8B Exemplary doping profiles along horizontal cut lines through a semiconductor device according to various embodiments are shown.

[0019] Figure 9 shows a conventional PNP device of FIG. 1 and Figure 5 Comparison chart of 100ns transmission line pulse (TLP) data for semiconductor devices.

[0020] Figure 10 Various non-limiting embodiments are shown. Figure 5 Simulated potential diagram near the breakdown point of a semiconductor device.

[0021] Figure 11 Shown according to various non-limiting embodiments Figure 5 Schematic diagram of the simulated current density of the semiconductor device.

[0022] Figure 12 A flow chart illustrating a method of forming a semiconductor device according to various non-limiting embodiments is shown. DETAILED DESCRIPTION

[0023] Below, with reference to the non-limiting examples shown in the accompanying drawings, various aspects of the present invention and certain features, advantages and details thereof are explained more fully. Descriptions of known materials, manufacturing tools, processing techniques, etc. are omitted to avoid unnecessary obscuring the present invention in detail. However, it should be understood that while indicating various aspects of the present invention, the detailed description and specific examples are given only by way of illustration, rather than by way of limitation. According to the present invention, those skilled in the art will clearly see various replacements, modifications, additions and / or arrangements within the spirit and / or scope of the basic inventive concept.

[0024] Approximating language, as used in this specification and claims, may be used to modify any quantitative representation that could permissibly vary without resulting in a change in the basic function to which it is related. Thus, a value modified by one or more terms (e.g., "about") is not limited to the precise value specified. In some cases, approximating language may correspond to the precision of an instrument used to measure the value.

[0025] The present invention is not intended to be limited to the specific purposes of describing the present invention and is not intended to limit the present invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It should be further understood that the terms "comprise" (and any form of comprising, such as "comprises", "comprising"), "have" (and any form of having, such as "has", "having"), "include" (and any form of including, such as "includes", "including") and "contain" (and any form of containing, such as "contains", "containing") are open-ended linking verbs. Therefore, a method or apparatus that "comprises", "has", "includes" or "contains" one or more steps or elements has these one or more steps or elements, but is not limited to having only these one or more steps or elements. Similarly, a step of a method or an element of an apparatus that "comprises", "has", "includes" or "contains" one or more features has these one or more features, but is not limited to having only these one or more features. In addition, a device or structure configured in a certain manner is configured in at least that manner, but may also be configured in ways not listed.

[0026] The term "connected" (or "coupled") herein refers to a connection between two physical elements either directly or through one or more intermediate elements.

[0027] It should be understood that the terms "upper," "above," "below," "top," "bottom," "downward," "side," "back," "left," "right," "front," "lateral," "sideways," "upward," "downward," etc., used in the following description are for convenience and to help understand relative positions or directions, and are not intended to limit the direction of any device, structure, or any part of any device or structure. In addition, the singular terms "a," "an," and "the" include plural references unless the context clearly indicates otherwise. Similarly, the word "or" is intended to include "and" unless the context clearly indicates otherwise.

[0028] The non-limiting embodiments described below in the context of an apparatus are equally valid for the respective methods, and vice versa. Furthermore, it should be understood that the embodiments described below may be combined; for example, a portion of one embodiment may be combined with a portion of another embodiment.

[0029] It is understood that any property described herein for a particular device may also be applied to any device described herein. It is understood that any property described herein for a particular method may also be applied to any method described herein. Furthermore, it is understood that for any device or method described herein, not all components or steps described need to be included in the device or method, but may only include some (but not all) components or steps.

[0030] Various non-limiting embodiments relate to semiconductor devices, such as electrostatic discharge (ESD) protection devices, such as bipolar junction transistor (BJT) based ESD protection devices.

[0031] Figure 2 A cross-sectional view of a semiconductor device 200 is shown in accordance with various non-limiting embodiments.

[0032] like Figure 2As shown, a semiconductor device may include a substrate 202 and a collector region 210 disposed within the substrate 202. The collector region 210 may include a buried layer 212 disposed within the substrate 202, a first well region 214 disposed above a first portion of the buried layer 212, and a first conductive region 216 disposed at least partially within the first well region 214. The semiconductor device 200 may further include a base region 220 disposed above a second portion of the buried layer 212. The base region may include a second well region 222 disposed above the second portion of the buried layer 212, and a second conductive region 224 disposed at least partially within the second well region 222. The first well region 214 may laterally adjoin the second well region 222. The semiconductor device 200 may further include an emitter region including a third conductive region 230 disposed at least partially within the second conductive region 224. An isolation element 240 may be disposed between the first conductive region 216 and the third conductive region 230. The conductive plate 250 may be disposed on the isolation element 240, wherein the conductive plate 250 may be electrically connected to the first conductive region 216. The buried layer 212, the first well region 214, the first conductive region 216, and the third conductive region 230 may have a first conductivity type. The second well region 222 and the second conductive region 224 may have a second conductivity type different from the first conductivity type.

[0033] According to various non-limiting embodiments, the collector region 210 , the base region 220 , and the emitter region form a transistor, for example, a bipolar junction transistor (BJT).

[0034] According to various non-limiting embodiments, the first conductivity type may be either P-type or N-type, and the second conductivity type may be different from the first conductivity type, i.e., N-type or P-type, respectively. In one non-limiting embodiment, the first conductivity type is P-type and the second conductivity type is N-type, and the collector region 210, the base region 220, and the emitter region may form a PNP transistor. In an alternative non-limiting embodiment, the first conductivity type is N-type and the second conductivity type is P-type, and the collector region 210, the base region 220, and the emitter region may form an NPN transistor.

[0035] According to various non-limiting embodiments, substrate 202 may include a material including, but not limited to, silicon (Si), germanium (Ge), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), combinations thereof, or any other suitable semiconductor material. According to a non-limiting embodiment, substrate 202 may include single crystal silicon. According to various non-limiting embodiments, substrate 101 may include a semiconductor-on-insulator substrate, such as, but not limited to, a silicon-on-insulator (SOI), a germanium-on-insulator (GeOI) substrate, a silicon carbide-on-insulator (SiCOI) substrate, a gallium arsenide-on-insulator (GaAsOI) substrate, a gallium nitride-on-insulator (GaNOI) substrate, combinations thereof, or any other suitable semiconductor-on-insulator substrate.

[0036] According to various embodiments, the substrate 202 may be lightly doped, for example, with a doping concentration of about 1E15 cm -3 to about 1E16 cm -3 within the range.

[0037] According to various non-limiting embodiments, an isolation element 240 may be provided to separate the first conductive region 216 from the third conductive region 230. The isolation element 240 may be at least partially disposed in the substrate 202. In various non-limiting embodiments, the isolation element 240 may be at least partially disposed above the first well region 214 and the base region 220. In various non-limiting embodiments, the isolation element 240 may contact a top surface of the first well region 214, a top surface of the second well region 222, and / or a top surface of the second conductive region 224.

[0038] According to various non-limiting embodiments, the isolation element 240 may be at least partially disposed over a pn junction formed between the first well region 214 and the second well region 222 .

[0039] In various non-limiting embodiments, isolation element 240 may include at least one of local oxidation of silicon (LOCOS) isolation, shallow trench isolation (STI), or field oxide deposition (FOD) isolation. In a non-limiting example, LOCOS isolation may include silicon oxide. In a non-limiting example, STI may include silicon nitride. In a non-limiting example, FOD isolation may include silicon oxide.

[0040] According to various non-limiting embodiments, the conductive plate 250 may be at least partially disposed above the pn junction formed between the first well region 214 and the second well region 222. In other words, the conductive plate may at least partially overlap or bridge the pn junction formed between the first well region 214 and the second well region 222, with the isolation element 240 disposed therebetween. The conductive plate 250 (also referred to as a field plate) may include a conductive material such as, but not limited to, polysilicon or metal.

[0041] According to various non-limiting embodiments, the conductive plate 250, the isolation element 240, the second well region 222, and the buried layer 212 may form a reduced surface field (RESURF) structure that maintains a high breakdown voltage of the transistor. The RESURF structure may help minimize the lateral dimension, i.e., the width, of the second well region 222, thereby minimizing the on-resistance of the semiconductor device 200.

[0042] According to various non-limiting embodiments, there may be no terminal contacts in the base region 220 such that the base region 220 may be configured to float. In other words, no contact pads configured to receive a voltage bias from the outside are formed in the base region 220 .

[0043] In various non-limiting embodiments, the first conductive region 216 may include a third well region (not shown). Figure 2 and a termination region (not shown) at least partially disposed within the third well region. Figure 2 The terminal region may have a higher doping concentration than the third region. In various non-limiting embodiments, the terminal region may have a doping concentration of approximately 5E19 cm -3 to approximately 5E20cm -3 The third well region may have a doping concentration of approximately 1E17 cm -3 to approximately 1E19 cm -3 range of doping concentration.

[0044] In various non-limiting embodiments, the first conductive region 216 may have a higher doping concentration than the first well region 214. The first well region 214 may form a drift region of the semiconductor device 200. In various non-limiting embodiments, the first well region 214 may have a doping concentration of approximately 1E16 cm -3 to approximately 5E17 cm -3 range of doping concentration.

[0045] In various non-limiting embodiments, the second conductive region 224 may have a higher doping concentration than the second well region 222. The second well region 222 may form a drift region of the semiconductor device 200. In various non-limiting embodiments, the second conductive region 224 may have a doping concentration of approximately 1E17 cm -3 to about 1E18cm -3 The doping concentration of the second well region 222 may be about 1E16 cm -3 To about 1E17 cm -3 within the range.

[0046] According to various non-limiting embodiments, the first well region 214 may contact the buried layer 212. In other words, the first well region 214 may be disposed on a top surface of the buried layer 212. According to various non-limiting embodiments, the second well region 222 may be completely disposed on the buried layer 212 and may contact the buried layer 212. The buried layer 212 may extend horizontally below the first well region 214 and the second well region 222.

[0047] In various non-limiting embodiments, the buried layer 212 and the second well region 222 may have similar doping concentrations. In other words, the doping concentration of the buried layer 212 may be similar to (e.g., of the same order) the doping concentration of the second well region 222. In various non-limiting embodiments, the doping concentrations of the buried layer 212 and the second well region 222 may be the same. In various non-limiting embodiments, the buried layer 212 has a doping concentration of approximately 1E16 cm -3 To about 1E17 cm -3The second well region 222 has a doping concentration of about 1E16 cm -3 To about 1E17 cm -3 range of doping concentration.

[0048] In various non-limiting embodiments, the third conductive region 230 may have a conductivity of approximately 5E19 cm -3 To approximately 5E20cm -3 range of doping concentration.

[0049] According to various non-limiting embodiments, the first well region 214 and the first conductive region 216 are disposed to at least partially surround the second well region 222, the second conductive region 224, and the third conductive region 230, as will be described below with reference to FIG. Figures 3 to 6B A more detailed description is given. Figure 2 In the non-limiting embodiment shown, the first well region 214 and the first conductive region 216 are shown in the cross-sectional view to be located lateral to the second well region 222, the second conductive region 224, and the third conductive region 230. This may include an embodiment in which the first well region 214 and the first conductive region 216 are arranged in parallel with the second well region 222, the second conductive region 224, and the third conductive region 230; or may include an embodiment in which the first well region 214 and the first conductive region 216 are arranged to at least partially surround the second well region 222, the second conductive region 224, and the third conductive region 230.

[0050] According to various non-limiting embodiments, the first well region 214 and the first conductive region 216 may be disposed on a first side of the second well region 222, wherein another first well region (not shown) Figure 2 ) and another first conductive region (not shown Figure 2 (in) may be disposed on the second side of the second well region 222, as will be referred to below. Figure 3 The first side may be opposite to the second side. The buried layer 212 may extend horizontally below the first well region 214 and the second well region 222 to connect the first well region 214 to the other first well region.

[0051] According to various non-limiting embodiments, the semiconductor device 200 may further include a fourth conductive region (not shown) disposed within the substrate 202. Figure 2 ), as shown below Figure 5 、 Figure 6A and Figure 6B As shown. The fourth conductive region may be at least partially disposed below the buried layer 212 and at least partially surround the first well region 214 and the first conductive region 216, wherein the fourth conductive region has the second conductivity type. The first well region 214, the first conductive region 216, and the fourth conductive region may form a diode.

[0052] In various non-limiting embodiments, the fourth conductive region may include an epitaxial layer and a termination region at least partially disposed within the epitaxial layer. The termination region may have a higher doping concentration than the epitaxial layer. In various non-limiting embodiments, the termination region may have a doping concentration of approximately 5E19 cm -3 to about 5E20cm -3 The epitaxial layer may have a doping concentration of about 5E15cm -3 to about 5E16 cm -3 range of doping concentration.

[0053] In various non-limiting embodiments, the terminal region of the fourth conductive region may be electrically connected to the third conductive region 230, wherein the terminal region of the fourth conductive region may be electrically connected to the third conductive region 230 by another isolation element (not shown). Figure 2 ) is separated from the first conductive region 216. Therefore, a diode formed by the fourth conductive region, the first well region 214, and the first conductive region 216 can be connected in parallel with the transistor formed by the collector region 210, the base region 220, and the emitter region, and a current path can be created between the collector region 210 and the emitter region 230.

[0054] According to various non-limiting embodiments, the first conductive region 216 can be biased at a first voltage, and the third conductive region 230 can be biased at a second voltage different from the first voltage. In one non-limiting embodiment, the semiconductor device 200 includes a PNP transistor, and the second voltage can be higher than the first voltage. In another non-limiting embodiment, the semiconductor device 200 includes an NPN transistor, and the second voltage can be lower than the first voltage. When the difference between the first voltage and the second voltage exceeds a predetermined threshold (e.g., a breakdown voltage of the transistor), the semiconductor device 200 can be configured such that a first current flows laterally between the third conductive region 230 and the first conductive region 216 through the second conductive region 224, the second well region 222, and the first well region 214, and a second current flows vertically between the third conductive region 230 and the first conductive region 216 through the second conductive region 224, the second well region 222, the buried layer 212, and the first well region 214. In a non-limiting embodiment, the semiconductor device 200 includes a PNP transistor, and a first current flows from the third conductive region 230 through the second conductive region 224, the second well region 222, and the first well region 214 in sequence, laterally toward the first conductive region 216. A second current flows from the third conductive region 230 through the second conductive region 224, the second well region 222, the buried layer 212, and the first well region 214 in sequence, vertically toward the first conductive region 216. In a non-limiting embodiment, the semiconductor device 200 includes an NPN transistor, and a first current can flow from the first conductive region 216 through the first well region 214, the second well region 222, and the second conductive region 224 in sequence, laterally toward the third conductive region 230. A second current can flow from the first conductive region 216 through the first well region 214, the buried layer 212, the second well region 222, and the second conductive region 224 in sequence, vertically toward the third conductive region 230.

[0055] According to various non-limiting embodiments, the semiconductor device 200 may be an electrostatic discharge (ESD) protection device.

[0056] Figure 3 Shown along the Figure 4 AA' is a cross-sectional view of the semiconductor device 300, Figure 4 A top view of a semiconductor device 300 is shown, according to various non-limiting embodiments.

[0057] The semiconductor device 300 is similar to Figure 2 Therefore, common features are marked with the same reference numerals. Figure 2 The various embodiments described are for Figure 3 and Figure 4 The semiconductor device 300 is similarly effective, and vice versa.

[0058] Similar to the semiconductor device 200, the semiconductor device 300 may include a substrate 202 and a collector region 210 disposed within the substrate 202. The collector region 210 may include a buried layer 212 disposed within the substrate 202, a first well region 214 disposed over a first portion of the buried layer 212, and a first conductive region 216 at least partially disposed within the first well region 214.

[0059] exist Figure 3 In various non-limiting embodiments shown, the first conductive region 216 may include a third well region 317 and a termination region 318 at least partially disposed within the third well region 317. The termination region 318 may have a higher doping concentration than the third well region 317. In various non-limiting embodiments, the termination region 318 may have a doping concentration of approximately 5E19 cm -3 to approximately 5E20cm -3 The third well region 317 may have a doping concentration of approximately 1E17 cm -3 to approximately 1E19 cm -3 range of doping concentration.

[0060] Similar to semiconductor device 200, semiconductor device 300 may further include a base region 220 disposed above the second portion of buried layer 212, wherein base region 220 may include a second well region 222 disposed above the second portion of buried layer 212 and a second conductive region 224 disposed at least partially within second well region 222. First well region 214 may laterally adjoin second well region 222. Semiconductor device 300 may further include an emitter region including a third conductive region 230 disposed at least partially within second conductive region 224. Isolation element 240 may be disposed between first conductive region 216 and third conductive region 230. Conductive plate 250 may be disposed on isolation element 240, wherein conductive plate 250 may be electrically connected to first conductive region 216. Buried layer 212, first well region 214, third well region 317, termination region 318, and third conductive region 230 may have a first conductivity type. The second well region 222 and the second conductive region 224 may have a second conductivity type different from the first conductivity type.

[0061] and Figure 2 The illustrated embodiment is different in that the semiconductor device 300 has a first well region 214 and a first conductive region 216 disposed on both sides (ie, left and right) of the second well region 222 , the second conductive region 224 , and the third conductive region 230 .

[0062] In various non-limiting embodiments, the first well region 214 and the first conductive region 216 may be disposed to substantially surround (eg, at least half surround) the second well region 222 , the second conductive region 224 , and the third conductive region 230 . Figure 41 shows a top view of a non-limiting embodiment, wherein the first well region 214 and the first conductive region 216 completely surround the second well region 222, the second conductive region 224, and the third conductive region 230. The isolation element 240 and the conductive plate 250 may also completely surround the third conductive region 230, as shown in FIG. Figure 4 As shown in the non-limiting examples.

[0063] Figure 4 A non-limiting embodiment is shown in which the semiconductor device 300 is octagonal. It should be understood that in various non-limiting embodiments, the semiconductor device 300 may be provided in any other suitable shape or layout, such as, but not limited to, a rectangle, a circle, or a rounded rectangle (e.g., similar to a racetrack shape).

[0064] In various non-limiting embodiments, the first well region 214 and the first conductive region 216 may be disposed on a first side of the second well region 222 (eg, Figure 3 , wherein another first well region 214 and another first conductive region 216 may be disposed on a second side of the second well region 222 (eg, Figure 3 The first side may be opposite to the second side. Therefore, the first well region 214 on the first side and the other first well region 214 on the second side may be two independent regions, and the first conductive region 216 on the first side and the other first conductive region 216 on the second side may be two independent regions. The buried layer 212 may extend horizontally below the first well region 214 and the second well region 222 to connect the first well region 214 on the first side to the other first well region 214 on the second side. Another isolation element 240 may also be disposed between the third conductive region 230 and the other first conductive region 216 on the second side, and another conductive plate 250 may be disposed on the other isolation element 240.

[0065] Compared with the semiconductor device 200, Figure 3 The semiconductor device 300 may provide a non-limiting embodiment of a double-sided transistor structure, wherein the collector region 210 may be disposed on both sides of the base region 220 and the emitter region, or may be disposed around the periphery of the base region 220 .

[0066] Figure 5 A cross-sectional view of a semiconductor device 500 is shown in accordance with various non-limiting embodiments.

[0067] The semiconductor device 500 is similar to Figure 2 The semiconductor device 200 and Figure 3 Therefore, the same reference numerals are used to identify common features of the semiconductor device 300. Figure 2 and Figure 3 The various embodiments described are Figure 5 The same is true for the semiconductor device 500 and vice versa.

[0068] like Figure 5 As shown, the semiconductor device 500 may have a structure similar to Figure 3 The double-sided structure of the embodiment, wherein the collector region 210 may be disposed on both sides of the base region 220 and the emitter region, or be disposed to surround the periphery of the base region 220 .

[0069] For illustrative purposes, in the following description, the first conductivity type may be P-type and the second conductivity type may be N-type. However, in a non-limiting embodiment, the semiconductor device 500 may have an N-type first conductivity type and a P-type second conductivity type. Therefore, the collector region 210, the base region 220, and the emitter region may form a PNP transistor. The buried layer 212 may be a P-type buried layer (referred to herein as a PBL), and the first well region 214 may be a P-type region that forms a P-type drift region (referred to herein as a P-drift region). The third well region 317 may be a P-type well region (referred to herein as a PWell region), and the terminal region 318 may be a P-type terminal region (referred to herein as a P+ terminal region). Similarly, the third conductive region 230 may be a P-type region (referred to herein as a P+ emitter region). The second well region 222 may be an N-type region that forms an N-type drift region (referred to herein as an N-drift region), and the second conductive region 224 may be an N-type region (referred to herein as an NWell1 region). The base region 220 includes an N drift region 222 and an NWell1 224 without terminal contacts, such that the base region 220 may be configured to be floating.

[0070] It should be understood that in an alternative non-limiting embodiment where the collector region 210, the base region 220, and the emitter region can form an NPN transistor, the first conductivity type and the second conductivity type can be reversed. Thus, the P-type and N-type of the various regions / elements described above can be reversed.

[0071] and Figure 2 and Figure 3 Compared to the non-limiting embodiment, the semiconductor device 500 may further include a fourth conductive region 560 disposed in the substrate 202. The fourth conductive region 560 may be at least partially disposed below the buried layer 212 and at least partially surround the first well region 214 and the first conductive region 216 (including the third well region 317 and the terminal region 318). The fourth conductive region 560 has the second conductivity type, that is, the N-type described in the following non-limiting embodiment. The first well region 214, the third well region 317 and the fourth conductive region 560 may form a diode, such as Figure 5 shown.

[0072] In various non-limiting embodiments, the fourth conductive region 560 may include an epitaxial layer 562 (e.g., an N-type epitaxial layer, referred to herein as the N epitaxial layer) and a termination region 564 (e.g., an N+ region, referred to herein as the N+ termination region) at least partially disposed within the epitaxial layer 562. The termination region 564 may have a higher doping concentration than the epitaxial layer 562. In various non-limiting embodiments, the termination region 564 may have a doping concentration of approximately 5E19 cm -3 to approximately 5E20cm -3 The epitaxial layer 562 may have a doping concentration of approximately 5E15 cm -3 to approximately 5E16 cm -3 range of doping concentration.

[0073] In various non-limiting embodiments, the terminal region 564 of the fourth conductive region 560 can be electrically connected to the third conductive region 230, wherein the terminal region 564 of the fourth conductive region 560 is separated from the first conductive region 216 by another isolation element 570. The other isolation element 570 may include, for example, Figure 5 The non-limiting embodiment of the present invention may include shallow trench isolation (STI) as shown, or may include local oxidation of silicon (LOCOS) isolation (not shown). Figure 5 ), or may include field oxide deposition (FOD) isolation (not shown in Figure 5 middle).

[0074] In various non-limiting embodiments, the fourth conductive region 560 may optionally include a fourth well region 566 disposed at least partially within the epitaxial layer 562 and surrounding the termination region 564. The fourth well region 566 may be an N-type region (referred to herein as NWell2) having a lower doping concentration than the termination region 564. In various non-limiting embodiments, the fourth well region 566 may have a density of approximately 1E16 cm -3 to about 1E19 cm -3 range of doping concentration.

[0075] In various non-limiting embodiments, the fourth conductive region 560 may optionally include another buried layer 568 disposed below the epitaxial layer 562. The other buried layer 568 may be an N-type buried layer (referred to herein as NBL). In various non-limiting embodiments, the NBL 568 may have a thickness of approximately 5E16 cm. -3 to approximately 5E19 cm -3 range of doping concentration.

[0076] According to various non-limiting embodiments, the parasitic diode formed by the fourth conductive region 560 , the first well region 214 , and the third well region 317 is connected in parallel with the transistor formed by the collector region 210 , the base region 220 , and the emitter region, and may create a current path between the collector 210 and the emitter 230 .

[0077] In the absence of the fourth conductive region 560 Figure 2 and Figure 3 In various non-limiting embodiments, the substrate 202 may have a second conductivity type, namely an N-type substrate (referred to as N-sub). Figure 5 In various embodiments, the substrate 202 may have a first conductivity type, ie, a P-type substrate (referred to as P-sub). The substrate 202 may have a conductivity of approximately 1E15 cm -3 to about 1E16cm -3 range of doping concentration.

[0078] According to various non-limiting embodiments, isolation element 240 may be at least partially disposed above first well region 214 and base region 220. In various non-limiting embodiments, isolation element 240 may contact a top surface of first well region 214, a top surface of second well region 222, and / or a top surface of second conductive region 224.

[0079] According to various non-limiting embodiments, the isolation element 240 may be at least partially disposed over a pn junction formed between the P drift region 214 and the N drift region 222 .

[0080] In various non-limiting embodiments, the isolation element 240 may have a Figure 5 LOCOS isolation is shown in a non-limiting example.

[0081] Figure 6A FIG. 4 shows a cross-sectional view of a semiconductor device 600 according to various non-limiting embodiments. The semiconductor device 600 is similar to Figure 5 Therefore, common features are labeled with the same reference numerals. Figure 5 The various embodiments described in Figure 6A The same is true for the semiconductor device 600 and vice versa.

[0082] like Figure 6A As shown, the semiconductor device 600 is similar to the semiconductor device 500, except that the isolation element 640 disposed between the third conductive region 230 and the terminal region 318 of the first conductive region may include shallow trench isolation (STI). Figure 6A , a vertical cut line 810 is depicted that passes through the P+ emitter region 230, the NWell1 region 224, the N drift region 222, and the PBL 212 toward the N epitaxial layer 562. A horizontal cut line 820 is also depicted that passes through the PWell region 317, the P drift region 214, the N drift region 222, and the NWell1 region 224. It should be understood that the vertical cut line 810 and the horizontal cut line 820 can be similarly applied to the semiconductor devices 200, 300, and 500 described above. Figure 8A and Figure 8B Exemplary doping profiles along vertical tangent line 810 and horizontal tangent line 820 are depicted.

[0083] Figure 6B 1 shows a cross-sectional view of a semiconductor device 650 according to various non-limiting embodiments. The semiconductor device 650 is similar to Figure 5 The semiconductor device 500 and Figure 6A The semiconductor device 600 is shown in FIG. 6 , and therefore, common features are labeled with the same reference numerals. Figure 5 and Figure 6A The various embodiments described are for Figure 6B The same is true for the semiconductor device 650 and vice versa.

[0084] like Figure 6B As shown, semiconductor device 650 is similar to semiconductor devices 500 and 600, except that isolation element 645 disposed between third conductive region 230 and termination region 318 of the first conductive region may include field oxide deposition (FOD) isolation. FOD isolation 645 may be disposed on top of substrate 202, for example, on a top surface of at least a portion of the base region, the collector region including second conductive region 224, second well region 222, first well region 214, and third well region 317.

[0085] According to various non-limiting embodiments, the conductive plate 250 disposed on the isolation element 240, 640, 645 may be at least partially disposed over the pn junction formed between the P-drift region 214 and the N-drift region 222. In other words, the conductive plate 250 may at least partially overlap or bridge over the pn junction formed between the P-drift region 214 and the N-drift region 222, with the isolation element 240, 640, 645 disposed therebetween.

[0086] According to Figure 5 、 Figure 6A and Figure 6B In the various non-limiting embodiments shown, the conductive plate 250, the isolation elements 240, 640, 645, the N-drift region 222, and the PBL 212 can form a RESURF structure capable of maintaining a high breakdown voltage of the PNP transistor. The RESURF structure can also minimize the lateral dimension, i.e., the width, of the N-drift region 222, thereby minimizing the on-resistance of the semiconductor devices 500, 600, 650.

[0087] According to various non-limiting embodiments, the collector terminal region 318 may be biased at a first voltage, and the emitter terminal region 230 may be biased at a second voltage higher than the first voltage. When the difference between the first voltage and the second voltage exceeds a predetermined threshold value (e.g., the breakdown voltage of the PNP transistor), the PNP transistor of the semiconductor device 500, 600, 650 is turned on. Therefore, a first current path 582 may be generated, wherein the first current may flow laterally from the P+ emitter region 230 through the NWell1 region 224, the N drift region 222, and the P drift region 214 toward the first conductive region 216 of the collector (including the PWell region 317 and the P+ terminal region 318). A second current path 584 may be generated, wherein the second current may flow vertically from the P+ emitter region 230 through the NWell1 region 224, the N drift region 222, the PBL 212, and the P drift region 214 toward the first conductive region 216 of the collector. As Figure 5 As shown, the first current path 582 can be a lateral path and the second current path 584 can be a vertical path. When the emitter terminal 230 is biased at a higher voltage than the collector terminal 318 to turn on the PNP transistor, most of the voltage on the N drift region 222 drops, as described below. Figure 10 and Figure 11 shown.

[0088] It should be understood that Figure 5The current paths 582 and 584 shown in FIG correspond to non-limiting embodiments of semiconductor devices 500, 600, and 650 including a PNP transistor. In various non-limiting embodiments in which an NPN transistor is included in semiconductor devices 500, 600, and 650, the P-type and N-type of corresponding regions of the NPN transistor can be reversed compared to the embodiments of the PNP transistor. Furthermore, the directions of the current paths 582 and 584 can be reversed, and the voltage biases applied to the collector termination region 318 and the emitter termination region 230 can also be reversed. Illustratively, the collector termination region 318 can be biased at a first voltage, and the emitter termination region 230 can be biased at a second voltage that is lower than the first voltage. When the difference between the first and second voltages exceeds a predetermined threshold (e.g., the breakdown voltage of the NPN transistor), the NPN transistor of the semiconductor devices 500 and 600 is turned on. Therefore, a first current can flow laterally from the first conductive region 216 (including the NWell region 317 and the N+ terminal region 318) through the N-drift region 214, the P-drift region 222, and the PWell1 region 224 toward the emitter N+ terminal region 230. A second current can flow vertically from the first conductive region 216 through the N-drift region 214, the N-type buried layer 212, the P-drift region 222, and the PWell1 region 224 toward the emitter N+ terminal region 230. When the emitter terminal 230 is biased at a voltage lower than that of the collector terminal 318 to turn on the NPN transistor, most of the voltage on the P-drift region 222 drops.

[0089] according to Figure 5 、 Figure 6A and Figure 6B In various non-limiting embodiments shown, the N+ terminal region 564 of the fourth conductive region 560 can be electrically connected to the emitter terminal region 230. The N-Epi region 562 of the fourth conductive region 560 (optionally together with the NWell2 region 566) forms a parasitic diode with the collector P drift region 214 and the PWell region 317 to form a diode such as Figure 7 The current path from collector to emitter is shown.

[0090] Figure 7 Shown according to various non-limiting embodiments Figure 5 、 Figure 6A and Figure 6B An equivalent circuit 700 of the semiconductor devices 500 , 600 , and 650 .

[0091] like Figure 7 As shown, the collector region 210 , the base region 220 , and the emitter region 230 form a PNP transistor 710 . The fourth conductive region 560 and the collector region 210 form a diode 720 connected in parallel with the PNP transistor 710 .

[0092] Figure 8A shows the various embodiments of the Figure 5 、 Figure 6A and Figure 6B FIG. 8 is an exemplary doping profile 800 of the semiconductor devices 500 , 600 , 650 along a vertical cut line 810 .

[0093] The doping profile 800 is shown along a vertical tangent line from the P+ emitter region 230 through the NWell1 region 224, the N drift region 222, and the PBL 212 toward the N-Epi layer 562. Figure 8A As shown, the P+ emitter region 230 can be heavily doped at a substantially higher doping concentration than the NWell1 region 224. The NWell1 region 224 can have a higher doping concentration than the N drift region 222. The N drift region 222 can have a doping concentration comparable to that of the PBL 212, which can achieve high performance for a PNP transistor. The doping concentration of the N-Epi layer 562 can be slightly lower than that of the PBL 212. Exemplary ranges of doping concentrations for the various regions 230, 224, 222, 212, and 562 are described in the various non-limiting embodiments above.

[0094] Although referring to the above Figure 5 、 Figure 6A and Figure 6B The semiconductor devices 500, 600, 650 of FIG. 5 depict a doping profile 800, but it should be understood that in various non-limiting embodiments, Figure 2 and Figure 3 The doping profiles of the semiconductor devices 200 , 300 may be similar to the doping profile 800 , except that the N-Epi layer may not be present in the semiconductor devices 200 , 300 .

[0095] Figure 8B An exemplary doping profile 850 along a horizontal line passing through the semiconductor devices 200 , 300 , 500 , 600 , 650 is shown according to various embodiments.

[0096] The doping profile 850 is shown along a horizontal line from the PWell region 317 through the P drift region 214 and the N drift region 222 toward the NWell region 224. Figure 8B As shown, the PWell region 317 may have a higher doping concentration than the P drift region 214, and the Nwell1 region 224 may have a higher doping concentration than the N drift region 222. Exemplary ranges of doping concentrations for the various regions 317, 214, 222, 224 are described in the various non-limiting embodiments above.

[0097] Figure 9 1 shows a conventional PNP device 100 and a Figure 5FIG900 is a comparison graph of 100 ns transmission line pulse (TLP) data of the semiconductor device 500 .

[0098] like Figure 9 As shown, curve 910 represents a current-to-voltage (IV) curve of conventional PNP device 100 with an increased input stress voltage, and curve 920 represents an IV curve of semiconductor device 500 with an increased input stress voltage. The input stress voltage may be applied to conventional PNP device 100 and semiconductor device 500 at a fixed interval of 100 ns.

[0099] Curve 930 represents the leakage current of conventional PNP device 100 measured after applying each ESD stress level, and curve 940 represents the leakage current of semiconductor device 500 measured after applying each ESD stress level. If devices 100, 500 fail, the leakage current may suddenly increase.

[0100] Table 1 further illustrates the conventional PNP device 100 of FIG. 1 and Figure 5 The data of the semiconductor device 500 is compared.

[0101] Table 1: Comparison of conventional PNP device 100 and semiconductor device 500

[0102]

[0103] As shown in curves 910, 920 and Table 1, compared to the on-resistance of 23KΩ·μm achieved by the conventional PNP device 100, the on-resistance of the various non-limiting embodiments is Figure 5 The semiconductor device 500 can achieve a low on-resistance of about 6.9 KΩ·μm.

[0104] As shown in curves 930, 940 and Table 1, compared to the failure current of 1.29 mA / μm achieved by the conventional PNP device 100, the failure current of the device according to various non-limiting embodiments is Figure 5 The semiconductor device 500 can achieve a higher failure current of about 2.03 mA / μm.

[0105] Compared to the conventional PNP device 100 , the semiconductor device 500 according to various non-limiting embodiments may achieve a 57% improvement in failure current and a 70% reduction in on-resistance.

[0106] Experimental data measured on the semiconductor device 500 show that the semiconductor device 500 according to various non-limiting embodiments has good breakdown behavior even with a floating base. The three-point data also shows minimal point-to-point variation, with the breakdown voltage varying within a range of approximately 5V from -40°C to 175°C.

[0107] Figure 10 Shown according to various non-limiting embodiments Figure 5 FIG100 is a simulated potential diagram 1000 around a breakdown point of the semiconductor device 500. As described in various embodiments above, the potential of the PNP device 500 can be measured.

[0108] like Figure 10 As shown, the simulated potential on the second well region 222 (ie, the N-drift region 222 ) is mostly decreased to maintain a high breakdown voltage.

[0109] Figure 11 Shown according to various non-limiting embodiments Figure 5 1100 is a simulated current density graph of the semiconductor device 500. After the PNP device 500 is turned on, the current density of the PNP device 500 may be measured as described in the various embodiments above.

[0110] like Figure 11 As shown, the simulated current density shows that after the PNP device 500 is turned on, current flows laterally and vertically between the emitter region 230 and the collector termination region 318 .

[0111] Table 2 shows the LOCOS lengths according to various non-limiting embodiments. Figure 5 A TCAD (Technology Computer Aided Design) simulation breakdown voltage of the semiconductor device 500 is shown.

[0112] In the simulation results shown in Table 2, the breakdown voltage of semiconductor device 500 increases with increasing length of LOCOS 240. By increasing the LOCOS length (and other related doped regions), semiconductor device 500 according to various embodiments can be configured to have different breakdown voltages for different voltage ratings.

[0113] Table 2: TCAD simulated breakdown voltage of semiconductor device 500

[0114] LOCOS length (μm) Breakdown voltage (V) 2.8 57.9 3.4 75.5 4 87.7

[0115] According to various non-limiting embodiments described above, semiconductor devices 200, 300, 500, 600, and 650 are provided that achieve low on-resistance, i.e., good clamping capability as an ESD clamp, and high failure current. The semiconductor devices 200, 300, 500, 600, and 650 may be high-voltage ESD protection devices that may include PNP transistors or NPN transistors.

[0116] Hereinafter, methods of forming semiconductor devices 200 , 300 , 500 , 600 , 650 according to various non-limiting embodiments will be described.

[0117] Figure 12 A flowchart 1200 is shown of a method for forming a semiconductor device according to various non-limiting embodiments. The method may be used to form the semiconductor devices 200, 300, 500, 600, and 650 described in the various non-limiting embodiments above. The various non-limiting embodiments described in the context of the semiconductor devices 200, 300, 500, 600, and 650 are also valid for the respective methods, and vice versa.

[0118] At 1202, a substrate can be provided.

[0119] At 1204 , a buried layer can be formed within the substrate.

[0120] At 1206 , a first well region is formed over the first portion of the buried layer.

[0121] At 1208 , a first conductive region may be formed at least partially within the first well region, thereby forming a collector region including the buried layer, the first well region, and the first conductive region.

[0122] At 1210 , a second well region may be formed over a second portion of the buried layer, wherein the first well region laterally abuts the second well region;

[0123] At 1212 , a second conductive region may be formed at least partially within the second well region, thereby forming a base region including the second well region and the second conductive region.

[0124] At 1214 , a third conductive region may be formed at least partially within the second conductive region, thereby forming an emitter region.

[0125] At 1216 , an isolation element may be formed between the first conductive region and the third conductive region.

[0126] At 1218 , a conductive plate may be formed on the isolation element, and the conductive plate may be electrically connected to the first conductive region.

[0127] The buried layer, the first well region, the first conductive region, and the third conductive region may have a first conductive type. The second well region and the second conductive region may have a second conductive type different from the first conductive type.

[0128] It should be understood that, according to various embodiments, the method may not be performed in the order of 1202 - 1218. For example, according to a non-limiting embodiment, the formation of the second well region at 1210 may be performed before the formation of the first conductive region at 1208.

[0129] According to various non-limiting embodiments, an isolation element may be at least partially formed in the substrate to separate the first conductive region from the third conductive region. In various non-limiting embodiments, the isolation element may be at least partially formed above the first well region and the base region. In various non-limiting embodiments, the isolation element may be formed to contact a top surface of the first well region, a top surface of the second well region, and / or a top surface of the second conductive region.

[0130] According to various non-limiting embodiments, the method may further include disposing an isolation element at least partially over a pn junction formed between the first well region and the second well region.

[0131] In various non-limiting embodiments, the method may include forming at least one of local oxidation of silicon (LOCOS) isolation, shallow trench isolation (STI), or field oxide deposition (FOD) isolation as the isolation element.

[0132] According to various non-limiting embodiments, the method may further include disposing a conductive plate at least partially above a pn junction formed between the first well region and the second well region. In other words, the conductive plate may at least partially overlap or bridge the pn junction formed between the first well region and the second well region, with the isolation element disposed therebetween.

[0133] According to various non-limiting embodiments, terminal contacts may not be formed in the base region, such that the base region is configured to float.

[0134] In various non-limiting embodiments, forming the first conductive region may include forming a third well region and forming a termination region at least partially located within the third well region. The termination region may have a higher doping concentration than the third well region. In various non-limiting embodiments, the termination region may be formed to have a doping concentration of approximately 5E19 cm -3 to approximately 5E20cm -3 The third well region may be formed to have a doping concentration of approximately 1E17 cm -3 to approximately 1E19 cm -3 range of doping concentration.

[0135] In various non-limiting embodiments, the first conductive region may be formed with a higher doping concentration than the first well region. The first well region may form a drift region of the semiconductor device. In various non-limiting embodiments, the first well region may be formed to have a density of approximately 1E16 cm -3 to about 5E17 cm -3 range of doping concentration.

[0136] In various non-limiting embodiments, the second conductive region may be formed with a higher doping concentration than the second well region. The second well region may form a drift region of the semiconductor device. In various non-limiting embodiments, the second conductive region may be formed to have a doping concentration of approximately 1E17 cm- -3 to about 1E18cm -3 The second well region may be formed to have a doping concentration of approximately 1E16 cm -3 to about 1E17cm -3 range of doping concentration.

[0137] According to various non-limiting embodiments, the first well region can be formed to contact the buried layer. In other words, the first well region can be formed on a top surface of the buried layer. According to various non-limiting embodiments, the entire second well region can be formed on the buried layer and can contact the buried layer. The buried layer can extend horizontally below the first well region and the second well region.

[0138] In various non-limiting embodiments, the buried layer and the second well region can be formed to have comparable doping concentrations. In other words, the doping concentration of the buried layer can be similar to (e.g., at the same level) the doping concentration of the second well region. In various non-limiting embodiments, the doping concentrations of the buried layer and the second well region can be the same. In various non-limiting embodiments, the buried layer and the second well region can be formed to have comparable doping concentrations. In various non-limiting embodiments, the buried layer and the second well region can be formed to have comparable doping concentrations. -3 to approximately 1E17 cm -3 The buried layer is formed with a doping concentration in the range of about 1E16 cm -3 to approximately 1E17 cm -3 A second well region is formed with a doping concentration within a range of 100 nm.

[0139] In various non-limiting embodiments, the -3 to about 5E20cm -3 A third conductive region is formed with a doping concentration within a range of 100 Å to 200 Å.

[0140] According to various non-limiting embodiments, the first well region and the first conductive region may be formed to at least partially surround the second well region, the second conductive region, and the third conductive region.

[0141] According to various non-limiting embodiments, a first well region and a first conductive region may be formed on a first side of a second well region, wherein another first well region and another first conductive region may be formed on a second side of the second well region. The first side may be opposite to the second side. A buried layer may extend horizontally below the first well region and the second well region to connect the first well region to the other first well region.

[0142] According to various non-limiting embodiments, the method may further include forming a fourth conductive region within the substrate. The fourth conductive region may be formed at least partially below the buried layer and at least partially surrounding the first well region and the first conductive region, wherein the fourth conductive region has the second conductivity type. The first well region, the first conductive region, and the fourth conductive region may form a diode.

[0143] In various non-limiting embodiments, forming the fourth conductive region may further include forming an epitaxial layer within the substrate and forming a termination region disposed at least partially within the epitaxial layer. The termination region may be formed with a higher doping concentration than the epitaxial layer. In various non-limiting embodiments, the termination region may be formed with a doping concentration of approximately 5E19 cm -3 to approximately 5E20cm -3 The termination region is formed with a doping concentration within the range of about 5E15cm -3 to about 5E16cm -3 range of doping concentrations in the epitaxial layer.

[0144] In various non-limiting embodiments, the method may further include electrically connecting a terminal region of the fourth conductive region to the third conductive region, and forming another isolation element to isolate the terminal region of the fourth conductive region from the first conductive region. Thus, a diode formed by the fourth conductive region, the first well region, and the first conductive region is connected in parallel with a transistor formed by the collector region, the base region, and the emitter region, and a current path can be established between the collector and the emitter.

[0145] According to various non-limiting embodiments, the method may further include biasing the first conductive region at a first voltage and biasing the third conductive region at a second voltage different from the first voltage. In a non-limiting embodiment in which the semiconductor device is formed by a PNP transistor, the second voltage may be higher than the first voltage. In a non-limiting embodiment in which the semiconductor device is formed by an NPN transistor, the second voltage may be lower than the first voltage. When the difference between the first voltage and the second voltage exceeds a preset threshold value (e.g., a breakdown voltage of the transistor), the semiconductor device may be configured such that a first current flows laterally between the third conductive region and the first conductive region through the second conductive region, the second well region, and the first well region, and a second current flows vertically between the third conductive region and the first conductive region through the second conductive region, the second well region, the buried layer, and the first well region.

[0146] The semiconductor device formed according to the methods of the various non-limiting embodiments described above may be an ESD protection device.

[0147] The present invention may be embodied in other specific forms without departing from the spirit or essential characteristics of the present invention. The foregoing embodiments are therefore to be considered in all respects as illustrative rather than restrictive of the invention described herein. The scope of the present invention is therefore indicated by the appended claims rather than the foregoing description, and all changes that come within the meaning and range of equivalence of the claims are intended to be embraced therein.

Claims

1. A semiconductor device comprising: substrate; a collector region disposed in the substrate, wherein the collector region includes a buried layer disposed in the substrate, a first well region disposed above a first portion of the buried layer, and a first conductive region at least partially disposed in the first well region; a base region disposed over the second portion of the buried layer, wherein the base region includes a second well region disposed over the second portion of the buried layer and a second conductive region disposed at least partially within the second well region, wherein the first well region laterally abuts the second well region, and wherein the base region is configured to float and no contact pad is formed in the base region; an emitter region including a third conductive region at least partially disposed within the second conductive region; an isolation element disposed laterally between the first conductive region of the collector region and the third conductive region of the emitter region; and a conductive plate disposed on the isolation element, wherein the conductive plate is electrically connected to the first conductive region; The buried layer, the first well region, the first conductive region and the third conductive region have a first conductive type; and the second well region and the second conductive region have a second conductive type different from the first conductive type.

2. The semiconductor device according to claim 1, wherein The isolation element is at least partially disposed above a pn junction formed between the first well region and the second well region.

3. The semiconductor device according to claim 1, wherein The isolation element includes at least one of silicon local oxidation isolation, shallow trench isolation, or field oxide deposition isolation.

4. The semiconductor device according to claim 1, wherein The conductive plate is at least partially disposed to extend laterally over a pn junction formed between the first well region and the second well region.

5. The semiconductor device according to claim 1, wherein The conductive plate includes polysilicon or metal. The semiconductor device according to claim 1 , wherein: The conductive plate, the isolation element, the second well region and the buried layer form a reduced surface field (RESURF) structure.

7. The semiconductor device according to claim 1, wherein No terminal contacts are present in the base region.

8. The semiconductor device according to claim 1, wherein The first conductive region includes a third well region and a termination region at least partially disposed within the third well region.

9. The semiconductor device according to claim 1, wherein The second well region is entirely disposed on the buried layer and contacts the buried layer.

10. The semiconductor device according to claim 1, wherein The first well region is laterally and directly adjacent to the second well region.

11. The semiconductor device according to claim 1, wherein The first well region contacts the buried layer.

12. The semiconductor device according to claim 1, wherein The first well region and the first conductive region are disposed to at least partially surround the second well region, the second conductive region, and the third conductive region.

13. The semiconductor device according to claim 1, wherein The first well region and the first conductive region are arranged on a first side of the second well region, wherein another first well region and another first conductive region are arranged on a second side of the second well region, wherein the buried layer extends horizontally below the first well region and the second well region to connect the first well region to the another first well region.

14. The semiconductor device according to claim 1, further comprising a fourth conductive region disposed in the substrate, wherein The fourth conductive region is at least partially disposed under the buried layer and at least partially surrounds the first well region and the first conductive region, wherein the fourth conductive region has the second conductivity type.

15. The semiconductor device according to claim 14, wherein The first well region, the first conductive region, and the fourth conductive region form a diode.

16. The semiconductor device according to claim 14, wherein The fourth conductive region includes an epitaxial layer and a termination region at least partially disposed within the epitaxial layer.

17. The semiconductor device according to claim 16, wherein The terminal region of the fourth conductive region is electrically connected to the third conductive region, wherein the terminal region of the fourth conductive region is separated from the first conductive region by another isolation element.

18. The semiconductor device according to claim 1, in, The first conductive region is biased at a first voltage, the third conductive region is biased at a second voltage different from the first voltage, The semiconductor device is configured such that when the difference between the first voltage and the second voltage exceeds a predetermined threshold, a first current passes laterally between the third conductive region and the first conductive region through the second conductive region, the second well region and the first well region, and a second current passes vertically between the third conductive region and the first conductive region through the second conductive region, the second well region, the buried layer and the first well region.

19. The semiconductor device according to claim 1, wherein The semiconductor device is an electrostatic discharge protection device.

20. A method of forming a semiconductor device, the method comprising: providing a substrate; forming a buried layer in the substrate; forming a first well region above the first portion of the buried layer; forming a first conductive region at least partially located in the first well region, thereby forming a collector region including the buried layer, the first well region and the first conductive region; forming a second well region above the second portion of the buried layer, wherein the first well region is laterally adjacent to the second well region; forming a second conductive region at least partially located in the second well region, thereby forming a base region including the second well region and the second conductive region, wherein the base region is configured to float and no contact pad is formed in the base region; forming a third conductive region at least partially within the second conductive region to form an emitter region; forming an isolation element laterally located between the first conductive region of the collector region and the third conductive region of the emitter region; and forming a conductive plate on the isolation element and electrically connecting the conductive plate to the first conductive region; The buried layer, the first well region, the first conductive region and the third conductive region have a first conductive type, and the second well region and the second conductive region have a second conductive type different from the first conductive type.

21. The method according to claim 20, wherein The conductive plate is in contact with the isolation element and is separated from the collector region, the base region, and the emitter region, and further includes at least one of the following: disposing the isolation element at least partially above a pn junction formed between the first well region and the second well region; or The conductive plate is laterally extended at least partially over a pn junction formed between the first well region and the second well region.

Images