Semiconductor device and method for manufacturing semiconductor device

Abstract

The present application relates to a semiconductor device and a manufacturing method of a semiconductor device. The semiconductor device (100) has: a semiconductor substrate (1); a field effect transistor (120) disposed on the semiconductor substrate (1) and used for an analog circuit, having a P-type gate electrode (7); an interlayer insulating film (8) disposed on the field effect transistor (120); and a hydrogen barrier metal film (10) disposed on the interlayer insulating film (8) in the vicinity of above the P-type gate electrode (7) to block hydrogen.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device and a manufacturing method of a semiconductor device. BACKGROUND

[0002] Among semiconductor devices in which a fine element is formed on a semiconductor substrate such as silicon, there is an analog semiconductor device in which semiconductor elements such as MISFET (Metal-Insulator-Semiconductor Field-Effect Transistor), a resistance element, and a fuse element are combined.

[0003] As the analog semiconductor device, for example, a voltage regulator, a voltage detector, and a switching regulator, and the like can be cited. In these analog semiconductor devices, with the development of wearable devices, IoT (Internet to the Things), devices that can be driven for a long time at a low voltage and a low consumption current by a secondary battery or the like are developed. In particular, in a case where a reference voltage generation circuit is provided in a power management IC such as a voltage regulator, reduction of a deviation of the reference voltage and long-term stability become important.

[0004] However, in the MISFET used for such a reference voltage generation circuit, hydrogen generated from a passivation film or the like bonds with a dangling bond (non-bonding side) existing at an interface of a gate oxide film and a silicon substrate, and a threshold voltage sometimes has a deviation at the time of manufacturing and sometimes changes over time.

[0005] Therefore, for example, in order to prevent hydrogen from diffusing to an N-channel MOS transistor or the like, a semiconductor device in which a silicon nitride film for hydrogen shielding is formed on an N-channel MOS transistor or the like is proposed (for example, refer to Patent Document 1).

[0006] PRIOR ART DOCUMENTS

[0007] PATENT DOCUMENTS

[0008] Patent Document 1: Japanese Patent Application Publication No. 2003-152100 SUMMARY

[0009] PROBLEMS TO BE SOLVED BY THE INVENTION

[0010] An object of one aspect of the present application is to provide a semiconductor device capable of suppressing occurrence of an adverse situation caused by hydrogen without increasing a film formed.

[0011] MEANS FOR SOLVING THE PROBLEMS

[0012] The semiconductor device in one embodiment of the present application includes a semiconductor substrate; a field effect transistor disposed on the semiconductor substrate and used for an analog circuit, including a P-type gate electrode; an interlayer insulating film disposed on the field effect transistor; and a hydrogen barrier metal film disposed on the interlayer insulating film in the vicinity of above the P-type gate electrode to block hydrogen.

[0013] Effects of the Invention

[0014] According to one aspect of the present application, a semiconductor device capable of suppressing occurrence of an adverse situation caused by hydrogen without increasing a formed film can be provided. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 is a circuit diagram showing an analog circuit of a semiconductor device in the first embodiment of the present application.

[0016] Figure 2 is a schematic plan view showing a semiconductor device in the first embodiment of the present application.

[0017] Figure 3 is an explanatory diagram showing a cross section of the A-A line in Figure 2 .

[0018] Figure 4 is an explanatory diagram showing a cross section of the B-B line in Figure 2 .

[0019] Figure 5A is an explanatory diagram showing a method of manufacturing a semiconductor device in the first embodiment of the present application.

[0020] Figure 5B is an explanatory diagram showing a method of manufacturing a semiconductor device in the first embodiment of the present application.

[0021] Figure 5C is an explanatory diagram showing a method of manufacturing a semiconductor device in the first embodiment of the present application.

[0022] Figure 6 is a schematic plan view showing a modification of the first embodiment of the present application.

[0023] Figure 7 is an explanatory diagram showing a cross section of a semiconductor device in the second embodiment of the present application.

[0024] Figure 8 is an explanatory diagram showing a cross section of a semiconductor device in the third embodiment of the present application.

[0025] REFERENCE NUMERALS

[0026] 1: semiconductor substrate

[0027] 2: Oxidation film for separation

[0028] 3: Gate oxide film

[0029] 4: P-type well region

[0030] 5: Source-drain region

[0031] 6: N-type gate electrode

[0032] 7: P-type gate electrode

[0033] 8: BPSG film (interlayer insulating film)

[0034] 9: Metal wiring

[0035] 10: Hydrogen barrier metal film

[0036] 11: Passivation film

[0037] 12: BPSG film (interlayer insulating film)

[0038] 13: Wide-area hydrogen barrier metal film

[0039] 14, 15: Metal silicide film

[0040] 100: Semiconductor device

[0041] 110: Depletion-mode NMOS transistor

[0042] 120: Enhancement-mode NMOS transistor DETAILED DESCRIPTION

[0043] The semiconductor device in one embodiment of the present application has: a semiconductor substrate; a field effect transistor provided over the semiconductor substrate and used for an analog circuit, which has a P-type gate electrode; an interlayer insulating film provided over the field effect transistor; and a hydrogen barrier metal film provided over the P-type gate electrode in the vicinity of above the P-type gate electrode on the interlayer insulating film, which blocks hydrogen.

[0044] The semiconductor device in one embodiment of the present application is based on the following insight.

[0045] The characteristics required for a semiconductor device for analog use and the characteristics required for a semiconductor device for logic use for processing binary signals are quite different. For example, in a charge / discharge control circuit for a secondary battery such as a lithium ion battery, in order to reduce the discharge of a secondary battery used in a mobile device or the like as much as possible, there are many cases in recent years where a specification of several μV is required. In a reference voltage generation circuit for the charge / discharge control circuit, reliability of several μV is also required. Therefore, it is necessary to reduce the variation in threshold voltage of a field effect transistor (hereinafter referred to as "MOS transistor") provided in the reference voltage generation circuit, and the change over time that can be shown in a long-term reliability test.

[0046] In forming the MOS transistor, there are many cases where boron, phosphorus, arsenic, or the like is implanted into a polysilicon film to form a gate electrode. Boron is more likely to diffuse into a polysilicon film than phosphorus or arsenic, and to diffuse into a gate oxide film under the polysilicon film. Therefore, it is considered that the gate oxide film is more likely to be degraded in film quality and to allow a small atom such as hydrogen to pass therethrough, as compared with the case where phosphorus or arsenic is implanted. At this time, when hydrogen generated from a passivation film or the like, even in a small amount, bonds with a dangling bond (non-bonding side) existing at the interface between the gate oxide film and a silicon substrate, the threshold voltage in a semiconductor device for analog use, which needs to be adjusted in units of μV, sometimes varies at the time of manufacture or changes over time.

[0047] In this regard, in the semiconductor device described in Patent Document 1, a silicon nitride film for hydrogen shielding is arranged on a P-type gate electrode, but not only is a process for forming the silicon nitride film added, but sometimes the threshold voltage varies due to stress of the silicon nitride film arranged in the vicinity of the P-type gate electrode.

[0048] Therefore, the semiconductor device in one embodiment of the present application enlarges the area of a metal wiring layer arranged on the MOS transistor, and uses it as a hydrogen barrier metal film. That is, the semiconductor device can block hydrogen generated from a passivation film or the like by arranging a hydrogen barrier metal film serving as a metal wiring layer in the vicinity of the top of a P-type gate electrode where the threshold voltage is likely to vary, and thus can suppress the occurrence of a failure caused by hydrogen without adding a film to be formed.

[0049] Next, as an example of the semiconductor device in one embodiment of the present application, an embodiment in which an analog circuit is provided as an ED-type reference voltage generation circuit will be described with reference to the drawings.

[0050] Further, the drawings are schematic, and the relationship between the film thickness and the planar dimension, the ratio of each film thickness, and the like are different from those shown in the drawings. Further, in the semiconductor substrate, the side on which other films or layers are laminated using a semiconductor manufacturing process is referred to as an "upper surface", and the side opposite to the upper surface is referred to as a "lower surface". Furthermore, in the following, the number, position, shape, structure, size, and the like of the plurality of films or the semiconductor element obtained by structurally combining them are not limited to those shown in the following embodiments, and can be set to preferred number, position, shape, structure, size, and the like on the basis of implementing the present application.

[0051] [First Embodiment]

[0052] Figure 1 is a circuit diagram showing an analog circuit of a semiconductor device in the first embodiment of the present application. As shown in Figure 1 , the semiconductor device 100 in the present embodiment has an ED-type reference voltage generation circuit as an analog circuit, and has a depletion-mode N-channel field effect transistor 110 and an enhancement-mode N-channel field effect transistor 120.

[0053] Further, in the following, the "depletion-mode N-channel field effect transistor" is sometimes referred to as a "D-type NMOS transistor", and the "enhancement-mode N-channel field effect transistor" is sometimes referred to as an "E-type NMOS transistor".

[0054] When the drain connected to the power supply terminal 100a is applied with the power supply voltage VDD, the D-type NMOS transistor 110 functions as a constant current source that supplies a constant current independent of the power supply voltage VDD from the source to the E-type NMOS transistor 120. The E-type NMOS transistor 120 generates a reference voltage V ref in the reference voltage terminal 100c on the basis of the constant current supplied from the D-type NMOS transistor 110. Thus, the ED-type reference voltage generation circuit is formed by combining the D-type NMOS transistor 110 and the E-type NMOS transistor 120.

[0055] The source of the D-type NMOS transistor 110 is connected to the gate, the back gate, the reference voltage terminal 100c of the D-type NMOS transistor 110, and the gate and the drain of the E-type NMOS transistor 120, so that they are made to be at the same potential. Further, the source of the E-type NMOS transistor 120 is connected to the back gate and the ground terminal 100b, so that they are made to be at the same potential.

[0056] Here, when the drain current IDof the D-type NMOS transistor 110 is found, d1 if the mutual conductance at the time of non-saturation operation or at the time of saturation operation is set to gmD, it can be shown as the following equation (1). Further, as described above, since the gate of the D-type NMOS transistor 110 is connected to the source, the gate-source voltage Vg1 is 0 V. Therefore, the output current, i.e., the drain current I d1 is dependent on the threshold voltage V td .

[0057] I d1 = 1 / 2 • gmD • (V g1 - V td ) 2

[0058] = 1 / 2 • gmD • (|V td |) 2 … (1)

[0059] Next, when the drain current I d2 of the E-type NMOS transistor 120 is found, if the mutual conductance at the time of saturation operation is set as gmE, it can be shown as the following equation (2). In addition, as described above, since the gate of the E-type NMOS transistor 120 is connected to the drain, and further they are connected to the reference voltage terminal 100c, the gate-to-source voltage V g2 becomes the reference voltage V ref . Therefore, the drain current I d2 is dependent on the threshold voltage V te and the reference voltage V ref .

[0060] I d2 = 1 / 2 • gmE • (V g2 - V te ) 2

[0061] = 1 / 2 • gmE • (V ref - V te ) 2 … (2)

[0062] According to the above, since I d1 of the above equation (1) is equal to I d2 of the above equation (2), the reference voltage V ref becomes the following equation (3).

[0063] V ref ≒ V te + (gmD / gmE) 1 / 2 • |V td | … (3)

[0064] Figure 2 is a schematic plan view of a semiconductor device in the first embodiment of the present application, and is a view of the ED-type reference voltage generation circuit formed on a semiconductor substrate, viewed from above. In Figure 2In the diagram, the N-type gate electrode 6, the P-type gate electrode 7, the hydrogen barrier metal film 10 which also functions as a metal wiring layer, and the metal wiring 9a-9f connected to the hydrogen barrier metal film 10 are shown in the structure of the semiconductor device 100. Furthermore, Figure 2 The dashed lines in the diagram represent the active regions of the D-type NMOS transistor 110 and the E-type NMOS transistor 120, respectively.

[0065] In addition, a top-view diagram refers to a diagram taken from the normal direction of the semiconductor substrate when viewing the upper surface of the semiconductor substrate (top view).

[0066] When viewed from above (the normal direction of the substrate), the hydrogen barrier metal film 10 on the active region shown by the dashed line on the side of the E-type NMOS transistor 120 is configured to be larger than the area of ​​the P-type gate electrode 7 and covers the P-type gate electrode 7.

[0067] Here, refer to Figure 3 and Figure 4 Explain the cross-sections of D-type NMOS transistor 110 and E-type NMOS transistor 120.

[0068] Figure 3 It means Figure 2 An explanatory diagram of the cross section of line AA in the diagram. Figure 4 It means Figure 2 An explanatory diagram of the cross section of the BB line.

[0069] like Figure 3 and Figure 4 As shown, the device comprises a semiconductor substrate 1, a separation oxide film 2, a gate oxide film 3, a P-type well region 4, a source / drain region 5, an N-type gate electrode 6, a P-type gate electrode 7, a silicon oxide film with added phosphorus and boron (hereinafter referred to as "BPSG (Boro-PhosphoSilicate Glass) film") 8, metal wiring 9, a hydrogen barrier metal film 10, and a passivation film 11. D-type NMOS transistors 110 and E-type NMOS transistors 120 are formed by structurally combining the separation oxide film 2, gate oxide film 3, P-type well region 4, source / drain region 5, N-type gate electrode 6, and P-type gate electrode 7 on the semiconductor substrate 1.

[0070] Semiconductor substrate 1 is a wafer-shaped P-type silicon semiconductor substrate.

[0071] In addition, in this embodiment, a wafer-shaped P-type silicon semiconductor substrate is used as the semiconductor substrate 1, but it is not limited to this. The shape, structure, size, material and polarity of the semiconductor substrate 1 can be appropriately selected according to the purpose.

[0072] The separation oxide film 2 is a LOCOS (LOCal Oxidation of Silicon) formed on the semiconductor substrate 1. In order to separate the D-type NMOS transistor 110 and the E-type NMOS transistor 120, the separation oxide film 2 is provided at the outer edge of each active region.

[0073] In addition, in the present embodiment, the LOCOS is formed in order to separate the D-type NMOS transistor 110 and the E-type NMOS transistor 120, but is not limited thereto, and for example, an STI (Shallow Trench Isolation) or the like can be formed to separate them.

[0074] The D-type NMOS transistor 110 has a gate oxide film 3, a P-type well region 4, a source-drain region 5, and an N-type gate electrode 6 in which phosphorus is implanted in a polysilicon film.

[0075] The D-type NMOS transistor 110 is adjusted in impurity concentration so that the difference between the work functions of the P-type well region 4 and the N-type gate electrode 6 becomes large, and thus an electric field in the reverse direction is applied to the surface of the P-type semiconductor substrate 1, so that it becomes a low threshold voltage. In addition, since the threshold voltage can be lowered by the N-type channel doping region, the impurity implantation of the N-type gate electrode 6 and the channel doping region is appropriately controlled so that the D-type NMOS transistor 110 becomes depletion type, and the threshold voltage V td becomes 0 V or less. Thus, even if the potential of the gate is 0 V, a drain current can flow through the channel by applying a drain voltage.

[0076] In addition, the back gate is connected to the P-type well region 4 via a region (not shown) containing a high concentration of P-type impurities, and is connected to the source.

[0077] The E-type NMOS transistor 120 has a P-type gate electrode 7 formed by implanting BF2, and is adjusted in impurity concentration of the P-type gate electrode 7 and the channel doping region so that the threshold voltage V te is 0 V or more. In addition, a hydrogen barrier metal film 10 is disposed above the P-type gate electrode 7. The E-type NMOS transistor 120 is the same as the D-type NMOS transistor 110 except for this.

[0078] In addition, the shape, structure, size, material, and kind and concentration of impurities of the P-type gate electrode 7 are not particularly limited, and can be appropriately selected according to the purpose.

[0079] On the upper surface of the D-type NMOS transistor 110 and the E-type NMOS transistor 120, the surface is planarized to form the BPSG film 8 as an interlayer insulating film. In the BPSG film 8, the metal wiring 9a to 9d are buried in contact holes formed in a manner to penetrate the source-drain region 5, respectively, to form a conduction path from the source-drain region 5.

[0080] In addition, in the present embodiment, the interlayer insulating film is provided as the BPSG film 8, but is not limited thereto, and can be provided as a laminated structure of an NSG (None-doped Silicate Glass) film and a BPSG film, a laminated structure of a TEOS (Tetra-Ethyl-Ortho-Silicate) film and a BPSG film, or the like.

[0081] The hydrogen barrier metal film 10 electrically connected to the upper portion of the metal wiring 9a to 9d is formed of AlSiCu. Since the hydrogen barrier metal film 10 is present above the P-type gate electrode 7, it is possible to hinder hydrogen generated from the passivation film 11 or the like from moving from above, and the hydrogen barrier metal film 10 can prevent hydrogen from invading the vicinity of the E-type NMOS transistor 120 having the P-type gate electrode 7. That is, the semiconductor device 100 of the present embodiment, by having the hydrogen barrier metal film 10 having a function of a metal wiring layer present above the P-type gate electrode 7, can suppress the occurrence of a hydrogen-induced adverse condition without increasing the number of films formed.

[0082] As the material of the hydrogen barrier metal film 10, there is no particular limitation, and it can be appropriately selected according to the purpose, but from the viewpoint that the hydrogen barrier metal film 10 functions as a metal wiring layer, an aluminum alloy is preferable. As the aluminum alloy, for example, in addition to AlSiCu, AlNd, AlCu, AlSi, or the like can be given. In addition, it can be a manner in which tungsten is formed in a film shape on titanium of a base. If it is a manner in which tungsten is formed in a film shape on titanium of a base, it is advantageous in terms of preventing the invasion of hydrogen by tungsten and being able to absorb hydrogen by titanium of the base.

[0083] In addition, in the present embodiment, the hydrogen barrier metal film 10 is made larger than the active region of the P-type gate electrode 7, but as long as it can block hydrogen diffusing to the active region of the P-type gate electrode 7, it is not limited thereto, and the area of the hydrogen barrier metal film 10 can be equal to or smaller than the active region of the P-type gate electrode 7.

[0084] As the thickness of the hydrogen barrier metal film 10, there is no particular limitation, and it can be appropriately selected according to the purpose. However, from the viewpoint of being able to secure a thickness at which hydrogen can be blocked, the thickness of the hydrogen barrier metal film 10 is preferably 300 nm or more and 500 nm or less.

[0085] The size of the hydrogen barrier metal film 10 is not particularly limited and can be appropriately selected according to the purpose; however, it is preferred that it be larger than the P-type gate electrode 7 in the active region when viewed from above.

[0086] A passivation film 11 is provided on the top of the semiconductor device 100.

[0087] As the passivation film 11, a silicon nitride film is preferred. As the method for forming the silicon nitride film, if reduced pressure CVD (Chemical Vapor Deposition) is used, the metal wiring 9a to 9d may sometimes melt, so plasma CVD is preferred.

[0088] Furthermore, in this embodiment, the passivation film 11 is configured as a single-layer structure of silicon nitride film, but it is not limited to this; for example, it can also be configured as a double-layer structure of silicon oxide film and silicon nitride film. In addition, there are no particular limitations on the shape, structure and size of the passivation film 11, and it can be appropriately selected according to the purpose.

[0089] As described above, the semiconductor device 100 according to this embodiment includes: an E-type NMOS transistor 120 disposed on a semiconductor substrate 1 and used in an ED-type reference voltage generating circuit, having a P-type gate electrode 7; a BPSG film 8 disposed on the E-type NMOS transistor 120; and a hydrogen barrier metal film 10 disposed on the BPSG film 8 near the P-type gate electrode 7 to block hydrogen. Therefore, the semiconductor device 100 can suppress the occurrence of adverse conditions caused by hydrogen without increasing the amount of film formed.

[0090] Next, refer to Figures 5A to 5C The manufacturing method of the semiconductor device 100 of this embodiment will be described.

[0091] First, prepare a semiconductor substrate 1 and perform a LOCOS formation process to form a separation oxide film 2 on the semiconductor substrate 1.

[0092] Next, as Figure 5A As shown, using existing MOSFET manufacturing techniques such as gate oxide formation, source / drain region formation, and polysilicon-based gate electrode formation, a gate oxide 3, a P-type well region 4, a source / drain region 5, an N-type gate electrode 6, and a P-type gate electrode 7 are formed on a semiconductor substrate 1. This forms a D-type NMOS transistor 110 and an E-type NMOS transistor 120.

[0093] Specifically, to form a D-type NMOS transistor 110, boron is first implanted into a portion of each active region to form a P-type well region 4, and an N-type channel doped region is formed on a portion of the surface of the P-type well region 4. Next, a gate oxide film 3 is formed on this channel doped region, and then 5 × 10⁻⁶ ohms are implanted into the polysilicon film formed on the gate oxide film 3.16 / cm 3 The above 1 x 10 18 / cm 3 The above low concentration of phosphorus forms the N-type gate electrode 6. Then, at the position sandwiching the channel doping region under the gate oxide film 3, 1 x 10 19 / cm 3 The above high concentration of N-type source-drain region 5.

[0094] In addition, these are formed by photomasking the necessary portions.

[0095] In addition, as the thickness of the polysilicon film, there is no particular limitation, and it can be appropriately selected according to the purpose, but it is preferably 100 nm or more and 500 nm or less.

[0096] Next, as shown in FIG. 2, a BPSG film 8 is formed on the entire surface and is planarized. Figure 5B

[0097] As the method of forming the BPSG film 8, there is no particular limitation, and it can be appropriately selected according to the purpose.

[0098] As the planarization method of the BPSG film 8, there is no particular limitation, and it can be appropriately selected according to the purpose, and for example, a reflow method, an etch-back method, a CMP (Chemical Mechanical Polishing) method, and the like can be given. Regarding the reflow method, specifically, after forming an oxide film containing phosphorus or boron, planarization can be performed by heat treatment at 850°C or higher.

[0099] Next, a contact hole is opened on the BPSG film 8 by photolithography and dry etching, tungsten is buried with titanium as a base, and metal wires 9a to 9d are formed. Then, a hydrogen barrier metal film 10 is formed by photolithography and etching. This hydrogen barrier metal film 10 functions as a metal wiring layer, and therefore there is a portion that is electrically connected to the upper portion of the metal wires 9a to 9d.

[0100] Next, after the BPSG film 8 is formed and planarized, a passivation film 11 as a silicon nitride film is formed on the BPSG film 8 and the hydrogen barrier metal film 10 by plasma CVD.

[0101] ​As described above, the manufacturing method of the semiconductor device 100 of this embodiment includes the following steps: forming an E-type NMOS transistor 120, wherein the E-type NMOS transistor 120 is disposed on a semiconductor substrate 1 and is used in an ED-type reference voltage generating circuit, and includes a P-type gate electrode 7; forming a BPSG film 8 on the E-type NMOS transistor 120; and forming a hydrogen barrier metal film 10 on the BPSG film 8, near the P-type gate electrode 7, to block hydrogen. Therefore, the manufactured semiconductor device 100 can suppress the occurrence of hydrogen-induced defects without increasing the amount of film formed.

[0102] In addition, in this embodiment, such as Figure 6 As shown, the source terminal of the E-type NMOS transistor 120 can also be integrated with the hydrogen barrier metal film 10. This allows for an increase in the area of ​​the hydrogen barrier metal film 10, and since there is no gap between the source terminal and the hydrogen barrier metal film 10, it is preferable for the E-type NMOS transistor 120 equipped with the P-type gate electrode 7 in terms of making hydrogen diffusion more difficult.

[0103] [Second Implementation]

[0104] Figure 7 This is an explanatory diagram showing a cross-section of the semiconductor device according to the second embodiment of the present invention. (See diagram below.) Figure 7 As shown, in the second embodiment, in Figure 3 Based on the first embodiment shown, a wide-area hydrogen barrier metal film 13 is disposed on the hydrogen barrier metal film 10 through the BPSG film 12.

[0105] Similar to the hydrogen barrier metal film 10, the wide-area hydrogen barrier metal film 13 is made of AlSiCu. This wide-area hydrogen barrier metal film 13 exists above the P-type gate electrode 7 and the hydrogen barrier metal film 10. Therefore, in addition to the hydrogen barrier metal film 10, the wide-area hydrogen barrier metal film 13 can also prevent hydrogen from entering the E-type NMOS transistor 120 with the P-type gate electrode 7, thus further suppressing the occurrence of hydrogen-induced defects.

[0106] Furthermore, in the case where the semiconductor device 100 of this embodiment has multiple field-effect transistors, the wide-area hydrogen barrier metal film 13 is preferably disposed above the hydrogen barrier metal film 10 in such a way that it covers the entirety of the multiple field-effect transistors.

[0107] [Third Implementation Method]

[0108] Figure 8 This is an explanatory diagram showing a cross-section of the semiconductor device according to the third embodiment of the present invention.

[0109] like Figure 8 As shown, in the third embodiment, inFigure 3 On the basis of the first embodiment shown, metal silicide films 14, 15 of CoSi are formed on the upper portion of the P-type gate electrode 7 and the upper portion of the source-drain region 5. Thus, the semiconductor device 100 of the present embodiment can block the intrusion of hydrogen in the vicinity of the E-type NMOS transistor 120 having the P-type gate electrode 7 by using the metal silicide films 14, 15 in addition to the hydrogen-blocking metal film 10, and thus can further suppress the occurrence of adverse situations caused by hydrogen.

[0110] In the present embodiment, the metal silicide films 14, 15 are CoSi, but are not limited thereto, and can be, for example, WSi, TiSi, NiSi, or the like.

[0111] As described above, the semiconductor device in one embodiment of the present application includes: a semiconductor substrate; a field effect transistor disposed on the semiconductor substrate and used for an analog circuit, and including a P-type gate electrode; and a hydrogen-blocking metal film disposed on an interlayer insulating film in the vicinity of the upper portion of the P-type gate electrode, and blocking hydrogen.

[0112] Thus, the semiconductor device in one embodiment of the present application can suppress the occurrence of adverse situations caused by hydrogen without increasing the number of films formed.

[0113] In each of the above embodiments, the D-type NMOS transistor 110 includes the N-type gate electrode 6 and the E-type NMOS transistor 120 includes the P-type gate electrode, but is not limited thereto, and the D-type NMOS transistor 110 can include the P-type gate electrode.

[0114] In the present embodiment, the D-type NMOS transistor 110 and the E-type NMOS transistor 120 are both NMOS transistors, but are not limited thereto, and both can be PMOS transistors.

[0115] In each of the above embodiments, the analog circuit is an ED-type reference voltage generation circuit, but is not limited thereto, and can be, for example, a reference voltage generation circuit other than the ED-type, a circuit in which at least either of the non-inverting input terminal and the inverting input terminal of a comparator is connected to the output of the ED-type or non-ED-type reference voltage generation circuit, a current mirror circuit, or the like.

Claims

1. A semiconductor device having a reference voltage generation circuit, characterized by comprising: the reference voltage generation circuit having, on a semiconductor substrate: a depletion type field effect transistor that generates a constant current, a gate electrode of the depletion type field effect transistor being connected to a source region; and a enhancement type field effect transistor that generates a voltage based on the constant current, a drain region and a gate electrode of the enhancement type field effect transistor being connected to the source region of the depletion type field effect transistor, the gate electrode of the enhancement type field effect transistor being a P-type gate electrode, the semiconductor device having: an interlayer insulating film disposed above the depletion type field effect transistor and the enhancement type field effect transistor; and a hydrogen barrier metal film that functions as a metal wiring layer disposed above the P-type gate electrode in the vicinity of the P-type gate electrode on the interlayer insulating film, and that functions as a metal wiring layer connecting the gate electrode and the source region of the depletion type field effect transistor and the P-type gate electrode and the drain region of the enhancement type field effect transistor on the same layer as the metal wiring layer, the hydrogen barrier metal film blocking hydrogen, an area of the hydrogen barrier metal film disposed above the P-type gate electrode in the vicinity of the P-type gate electrode being at least an area of the P-type gate electrode in an active region of the field effect transistor when the semiconductor substrate is viewed in plan.

2. The semiconductor device according to claim 1, wherein the hydrogen barrier metal film is an aluminum alloy.

3. The semiconductor device according to claim 1 or 2, wherein the semiconductor device further comprises: a wide-area hydrogen barrier metal film disposed above the hydrogen barrier metal film in a manner covering the entirety or a part of the field effect transistor when the semiconductor substrate is viewed in plan.

4. The semiconductor device according to claim 1 or 2, wherein a metal silicide film is formed on an upper portion of the P-type gate electrode. ​ ​

Images