Semiconductor devices

Abstract

A semiconductor device is disclosed. The semiconductor device may include a ground pad and a lower electrode, the lower electrode being located on and connected to the ground pad and including an outer portion and an inner portion within the outer portion. The outer portion includes a first region and a second region. The semiconductor device may further include a dielectric film on the first region of the outer portion of the lower electrode and an upper electrode located on the dielectric film. The first region of the outer portion of the lower electrode may include a silicon (Si) dopant, and the dielectric film does not extend along the second region of the outer portion. The concentration of silicon dopant in the first region of the outer portion is different from the concentration of silicon dopant in the second region of the outer portion and is higher than the concentration of silicon dopant in the inner portion.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0135307, filed on October 29, 2019, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure generally relates to a semiconductor device and a method for manufacturing the semiconductor device, and more specifically, to a semiconductor device including a capacitor as a data storage element and a method for manufacturing the semiconductor device. Background Technology

[0003] In recent years, in order to achieve high capacity and high integration in semiconductor devices (such as DRAM devices), the design rules for semiconductor devices have been continuously decreasing. For a DRAM device to operate, each cell can have a minimum capacitance.

[0004] Increasing the capacitance increases the amount of charge stored in the capacitor and can improve the refresh characteristics of a semiconductor device. Improved refresh characteristics can increase the yield of a semiconductor device.

[0005] To increase capacitance, methods are being investigated to use dielectric films with high dielectric constants in capacitors or to increase the contact area between the lower electrode of the capacitor and the dielectric film. Summary of the Invention

[0006] This disclosure provides a semiconductor device that can improve the performance and reliability of a device through interface engineering between the lower electrode and the capacitor dielectric film.

[0007] This disclosure also provides a method for manufacturing a semiconductor device that can improve device performance and reliability through interface engineering between the lower electrode and the capacitor dielectric film.

[0008] According to an exemplary embodiment of the present invention, a semiconductor device includes: a ground pad located on a substrate; a lower electrode located on the ground pad, connected to the ground pad, and including an outer portion and an inner portion inside the outer portion (e.g., surrounded by the outer portion), the outer portion including a first region and a second region; a dielectric film extending along the first region of the outer portion of the lower electrode; and an upper electrode located on the dielectric film. The first region of the outer portion of the lower electrode includes a silicon (Si) dopant doped therein, the dielectric film does not extend along the second region of the outer portion, the concentration of the silicon dopant in the first region of the outer portion is different from the concentration of the silicon dopant in the second region of the outer portion, and the concentration of the silicon dopant in the first region of the outer portion is higher than the concentration of the silicon dopant in the inner portion.

[0009] According to an exemplary embodiment of the present invention, a semiconductor device includes: a ground pad located on a substrate; a lower electrode located on the ground pad, connected to the ground pad, and extending in the thickness direction of the substrate; at least one or more support patterns in contact with a portion of the lower electrode; a dielectric film extending along the outer surface of the lower electrode and the outer surface of the support patterns; and an upper electrode located on the dielectric film. The lower electrode includes silicon (Si) dopant doped along a portion of the outer surface of the lower electrode (e.g., a first region adjacent to the dielectric film), and the concentration of silicon dopant between the lower electrode and the dielectric film (e.g., the concentration of silicon dopant in the first region of the lower electrode) is higher than the concentration of silicon dopant between the lower electrode and the support patterns (e.g., the concentration of silicon dopant in a second region of the lower electrode adjacent to the support patterns).

[0010] According to an exemplary embodiment of the present invention, a semiconductor device includes: a trench located in a substrate; a gate electrode located (e.g., filling) a portion of the trench; a buried contact configured to be adjacent to a side of the gate electrode (e.g., located on at least one side of the gate electrode) and connected to the substrate; a ground pad located on the buried contact; an etch stop film located on the ground pad and exposing at least a portion of the ground pad; a first support pattern disposed on the etch stop film, spaced apart from the etch stop film, and having a first thickness; a second support pattern disposed on the first support pattern, spaced apart from the first support pattern, and having a second thickness greater than the first thickness; a lower electrode located on the ground pad and in contact with the etch stop film, the first support pattern, and the second support pattern; an insertion film located on the lower electrode; a dielectric film extending along the contours of the insertion film, the first support pattern, and the second support pattern; and an upper electrode located on the dielectric film. The lower electrode includes a silicon-doped region formed in a portion of the outer surface of the lower electrode, and the insertion film is formed on the silicon-doped region.

[0011] According to an exemplary embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming a lower electrode on a ground pad; forming a support pattern that contacts a portion of a sidewall of the lower electrode; after forming the support pattern, forming a silicon processing region on an outer surface of the lower electrode using a silicon-containing precursor; forming a dielectric film along the contour of the lower electrode including the silicon processing region and the contour of the support pattern; and forming an upper electrode on the dielectric film.

[0012] However, the aspects of this disclosure are not limited to those set forth herein. The above and other aspects of this disclosure will become more apparent to those skilled in the art upon reference to the following detailed description of the invention. Attached Figure Description

[0013] The above and other aspects and features of this disclosure will become more apparent from the description of some exemplary embodiments with reference to the accompanying drawings, in which:

[0014] Figure 1 These are diagrams used to explain some embodiments of semiconductor devices based on the concept of the present invention;

[0015] Figure 2 It is shown Figure 1 The diagram shows the lower electrode, support pattern, and etch stop film.

[0016] Figure 3 yes Figure 1 A magnified view of part P;

[0017] Figures 4 to 6 It shows along Figure 2 A schematic diagram showing the concentration of silicon (Si) dopant in lines A, B, and C;

[0018] Figure 7 It shows along Figure 2 A schematic diagram of the concentration of silicon (Si) dopant in line A;

[0019] Figure 8 It shows along Figure 2 A schematic diagram of the concentration of silicon (Si) dopant in line A;

[0020] Figure 9 It shows along Figure 2 A schematic diagram of the concentration of silicon (Si) dopant in line B;

[0021] Figures 10 to 12 These are diagrams illustrating semiconductor devices for explaining some embodiments of the concept according to the present invention;

[0022] Figure 13 and Figure 14 These are diagrams illustrating semiconductor devices for explaining some embodiments of the concept according to the present invention;

[0023] Figures 15 to 18 These are diagrams illustrating semiconductor devices for explaining some embodiments of the concept according to the present invention;

[0024] Figure 19 This is a schematic layout diagram for explaining some embodiments of a semiconductor device according to the present invention;

[0025] Figure 20 It is along Figure 19 A sectional view taken from line II; and

[0026] Figures 21 to 25 This is a diagram illustrating a method for manufacturing a semiconductor device according to some embodiments of the concept of the present invention. Detailed Implementation

[0027] Figure 1 These are diagrams used to explain some embodiments of a semiconductor device based on the concept of the present invention. Figure 2 It is shown Figure 1 The diagram shows the lower electrode, support pattern, and etch stop film. Figure 3 yes Figure 1 A magnified view of part P. Figures 4 to 6 It shows along Figure 2 A schematic diagram showing the concentration of silicon (Si) dopant in lines A, B, and C.

[0028] Reference Figures 1 to 3 A semiconductor device according to some embodiments of the present invention may include a first ground pad 120, an etch stop film 130, a lower support pattern 140, an upper support pattern 150, a lower electrode 200, a capacitor dielectric film 250, an upper electrode 260, and an upper plate electrode 270.

[0029] The first grounding pad 120 may be disposed on the substrate 100. The first grounding pad 120 may be electrically connected to a conductive area formed on or in the substrate 100.

[0030] The first grounding pad 120 can be connected to the substrate 100 via the first storage contact 115. The first grounding pad 120 can be disposed on the first storage contact 115.

[0031] The first interlayer insulating film 110 can be disposed on the substrate 100. The first storage contact 115 and the first grounding pad 120 can be disposed in the first interlayer insulating film 110 on the substrate 100.

[0032] The substrate 100 may be bulk silicon or SOI (silicon-on-insulator). In some embodiments, the substrate 100 may be a silicon substrate or may include other materials, such as, but not limited to, silicon germanium, SGOI (silicon germanium-on-insulator), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. In the following description, the substrate 100 will be described as a silicon substrate.

[0033] The first interlayer insulating film 110 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbonitride (SiOCN), and combinations thereof. The first storage contact 115 may include at least one of, for example, a doped semiconductor material, a conductive silicide compound, a conductive metal nitride, and a metal. The first ground pad 120 may include at least one of, for example, a doped semiconductor material, a conductive silicide compound, a conductive metal nitride, and a metal. In a semiconductor device according to some embodiments, the first ground pad 120 may include tungsten (W).

[0034] An etch stop film 130 may be disposed on the first interlayer insulating film 110. The etch stop film 130 may expose at least a portion of the first ground pad 120. As an example, the etch stop film 130 may be disposed on the first ground pad 120. The etch stop film 130 may include a lower electrode hole 130h. The lower electrode hole 130h may expose at least a portion of the first ground pad 120. The etch stop film 130 may include at least one of, for example, silicon nitride (SiN), silicon carbonitride (SiCN), silicon boron nitride (SiBN), silicon carbide (SiCO), silicon oxynitride (SiON), silicon oxide (SiO), and silicon carbonitride (SiOCN). For example, silicon carbide (SiCO) includes silicon (Si), carbon (C), and oxygen (O), but does not represent the ratio between silicon (Si), carbon (C), and oxygen (O). The term "part" as used herein may be used interchangeably with the term "section".

[0035] The lower electrode 200 may be disposed on the first grounding pad 120. The lower electrode 200 is connected to the first grounding pad 120. The lower electrode 200 may extend longitudinally in a second direction DR2, which is the thickness direction of the substrate 100. The length of the lower electrode 200 extending in the second direction DR2 is greater than the length of the lower electrode 200 extending in the first direction DR1. In some embodiments, the length of the lower electrode 200 extending in the second direction DR2 is greater than the width of the lower electrode 200 in the first direction DR1. The lower electrode 200 may have, for example, a columnar shape. As used herein, "an element having a columnar shape" (or similar language) means an element comprising a bottom surface and a vertical portion extending vertically from the bottom surface. The vertical portion of the element may or may not be perpendicular to the bottom surface.

[0036] Here, the second direction DR2 can be a direction parallel to the thickness direction of the substrate 100. The first direction DR1 can be a direction that intersects the second direction DR2 and is parallel to the upper surface of the substrate 100 or the upper surface of the first interlayer insulating film 110. In some embodiments, such as Figure 1 As shown, the first direction DR1 can be parallel to the surface of the substrate 100, and the second direction DR2 can be perpendicular to the first direction DR1.

[0037] The lower electrode 200 may include an outer surface 200s defining the shape of the lower electrode 200. The outer surface 200s of the lower electrode 200 may include a bottom surface 200bs facing the upper surface of the first grounding pad 120, a sidewall 200ss extending along the second direction DR2, and an upper surface 200us facing the bottom surface 200bs of the lower electrode 200. The sidewall 200ss of the lower electrode 200 connects the bottom surface 200bs and the upper surface 200us of the lower electrode 200.

[0038] In a semiconductor device according to some embodiments, a portion of the lower electrode 200 may be disposed in a lower electrode hole 130h. The lower electrode 200 may be connected to a first ground pad 120 through the lower electrode hole 130h. For example, a portion of the sidewall 200ss of the lower electrode 200 may contact the etch stop film 130. In some embodiments, such as Figure 1 As shown, a portion of the lower electrode 200 may extend through the etch stop film 130 and may contact the etch stop film 130.

[0039] The lower electrode 200 may include, for example, but not limited to, doped semiconductor materials, conductive metal nitrides (e.g., titanium nitride, tantalum nitride, niobium nitride, tungsten nitride, etc.), metals (e.g., ruthenium, iridium, titanium, tantalum, etc.), and / or conductive metal oxides (e.g., iridium oxide, niobium oxide, etc.). The term “and / or” as used herein includes any and all combinations of one or more of the associated listed items.

[0040] In a semiconductor device according to some embodiments, the lower electrode 200 may include titanium nitride (TiN). Furthermore, in a semiconductor device according to some embodiments, the lower electrode 200 may include niobium nitride (NbN).

[0041] The lower electrode 200 may include a silicon (Si) dopant. The silicon (Si) dopant may be doped in the lower electrode 200 and / or on the outer surface 200s of the lower electrode 200. The description of the lower electrode 200 and the silicon (Si) dopant will be described in detail below.

[0042] The lower support pattern 140 can be disposed on the etch stop film 130. The lower support pattern 140 is spaced apart from the etch stop film 130 in the second direction DR2. The lower support pattern 140 can contact the lower electrode 200. The lower support pattern 140 can contact a portion of the sidewall 200ss of the lower electrode 200. The lower support pattern 140 can connect to adjacent lower electrodes 200 in the first direction DR1. Although... Figure 1 The two lower electrodes 200 are shown connected by the lower support pattern 140, but this is only for ease of explanation and the inventive concept is not limited thereto.

[0043] The upper support pattern 150 can be disposed on the lower support pattern 140. The upper support pattern 150 is spaced apart from the lower support pattern 140 in the second direction DR2. The upper support pattern 150 can contact the lower electrode 200. The upper support pattern 150 can contact a portion of the sidewall 200ss of the lower electrode 200. Although Figure 1 The two lower electrodes 200 are shown connected by the upper support pattern 150, but this is only for ease of explanation and the inventive concept is not limited thereto.

[0044] The lower support pattern 140 and the upper support pattern 150 may include at least one of, for example, silicon nitride (SiN), silicon carbonitride (SiCN), silicon boron nitride (SiBN), silicon carbon oxynitride (SiCO), silicon oxynitride (SiON), silicon oxide (SiO), and silicon carbonitride oxynitride (SiOCN). In a semiconductor device according to some embodiments, the lower support pattern 140 and the upper support pattern 150 may respectively include silicon carbonitride (SiCN) or silicon nitride.

[0045] In a semiconductor device according to some embodiments, the thickness t11 of the lower support pattern 140 in the second direction DR2 may be smaller than the thickness t12 of the upper support pattern 150 in the second direction DR2. Unlike the illustrated example, a semiconductor device according to some embodiments may include only one of the lower support pattern 140 and the upper support pattern 150. In some embodiments, in a semiconductor device according to some embodiments, an additional support pattern may be disposed between the etch stop film 130 and the lower support pattern 140, or between the lower support pattern 140 and the upper support pattern 150.

[0046] A capacitor dielectric film 250 may be disposed on the lower electrode 200. The capacitor dielectric film 250 may be formed along the outer surface 200s of the lower electrode 200, the outer surface of the lower support pattern 140, the outer surface 150s of the upper support pattern 150, and the upper surface of the etch stop film 130. The capacitor dielectric film 250 may extend along the contours of the lower electrode 200, the upper support pattern 150, the lower support pattern 140, and the etch stop film 130. In some embodiments, the capacitor dielectric film 250 may have the following characteristics: Figure 1 The uniform thickness shown.

[0047] Because the lower support pattern 140 and the upper support pattern 150 are in contact with the lower electrode 200, the capacitor dielectric film 250 does not extend between the lower support pattern 140 and the lower electrode 200, nor between the upper support pattern 150 and the lower electrode 200. Furthermore, the capacitor dielectric film 250 does not extend between the etch stop film 130 and the lower electrode 200. In a semiconductor device according to some embodiments, the capacitor dielectric film 250 may be in contact with the lower electrode 200. The capacitor dielectric film 250 may be in contact with the outer surface 150s of the upper support pattern 150, the outer surface of the lower support pattern 140, and the upper surface of the etch stop film 130.

[0048] The capacitor dielectric film 250 may include, for example, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof. Although the capacitor dielectric film 250 is shown as a single film, this is merely for ease of explanation, and the inventive concept is not limited thereto.

[0049] In a semiconductor device according to some embodiments, the capacitor dielectric film 250 may include a stacked film structure in which a plurality of films (e.g., zirconium oxide, aluminum oxide, and zirconium oxide) are sequentially stacked.

[0050] In a semiconductor device according to some embodiments, capacitor dielectric film 250 may include a dielectric film containing hafnium (Hf).

[0051] In a semiconductor device according to some embodiments, the capacitor dielectric film 250 may have a stacked film structure of ferroelectric material film and paraelectric material film.

[0052] Ferroelectric material films can possess ferroelectric properties. Ferroelectric material films can have a thickness sufficient to achieve these ferroelectric properties. The thickness range of ferroelectric material films can vary depending on the ferroelectric material.

[0053] For example, ferroelectric material films can include single-metal oxide films. Here, the single-metal oxide can be a binary compound composed of a single metal and oxygen. Ferroelectric material films containing single-metal oxides can have an orthorhombic crystal system.

[0054] In some embodiments, the metal included in the single metal oxide film may be hafnium (Hf). The single metal oxide film may be a hafnium oxide film (HfO). Here, the hafnium oxide film may have a chemical formula that matches the stoichiometry or a chemical formula that does not match the stoichiometry.

[0055] In some embodiments, the metal included in the single metal oxide film may be one of the rare earth metals belonging to the lanthanides. The single metal oxide film may be a rare earth metal oxide film belonging to the lanthanides. Here, the rare earth metal oxide film belonging to the lanthanides may have a chemical formula that matches the stoichiometry, or it may have a chemical formula that does not match the stoichiometry.

[0056] Ferroelectric films may also include dopants incorporated into a single metal oxide film. Although the doping concentration can vary depending on the type of dopant, the doping concentration of dopants contained in a ferroelectric film can be 10% or lower.

[0057] In some embodiments, the single metal oxide film is a hafnium oxide film, and the dopant may include at least one selected from gadolinium (Gd), silicon (Si), aluminum (Al), yttrium (Y), lanthanum (La), scandium (Sc), cerium (Ce), dysprosium (Dy), tantalum (Ta), strontium (Sr), and niobium (Nb). In some embodiments, the single metal oxide film is a rare earth metal oxide film of lanthanides, and the dopant may include at least one selected from silicon (Si), aluminum (Al), hafnium (Hf), zirconium (Zr), and niobium (Nb).

[0058] In some embodiments, the ferroelectric material film may not include dopants doped in the single metal oxide film.

[0059] When the ferroelectric material film includes a single metal oxide film, the ferroelectric material film can have a thickness of, for example, 1 nm or larger and 10 nm or smaller.

[0060] For example, ferroelectric material films can include bimetallic oxide films. Here, the bimetallic oxide can be a ternary compound composed of two metals and oxygen. Ferroelectric material films containing bimetallic oxides can have an orthorhombic crystal system.

[0061] The metal contained in the bimetallic oxide film can be, for example, hafnium (Hf) and zirconium (Zr). The bimetallic oxide film can be a hafnium-zirconium oxide film (Hf... x Zr (1-x) In bimetallic oxide films, x can be 0.2 or greater and 0.8 or less. Here, hafnium zirconium oxide film (Hf x Zr (1-x) O) can have a chemical formula that matches the stoichiometry, or it can have a chemical formula that does not match the stoichiometry.

[0062] For example, the ferroelectric material film may also include dopants doped in the bimetallic oxide film. Dopants may include at least one of gadolinium (Gd), silicon (Si), aluminum (Al), yttrium (Y), lanthanum (La), scandium (Sc), cerium (Ce), dysprosium (Dy), tantalum (Ta), and strontium (Sr). In some embodiments, the ferroelectric material film may not include the dopants in the bimetallic oxide film.

[0063] When the ferroelectric material film includes a bimetallic oxide film, the ferroelectric material film 132 may have a thickness of, for example, 1 nm or greater and 20 nm or less.

[0064] Paraelectric materials can have a positive permittivity, while ferroelectric materials can have a negative permittivity within a certain range. In other words, paraelectric materials have a positive capacitance, while ferroelectric materials can have a negative capacitance.

[0065] Generally, if two or more capacitors with positive capacitance are connected in series, the sum of their capacitances decreases. However, if a negative capacitor with negative capacitance and a positive capacitor with positive capacitance are connected in series, the sum of their capacitances increases.

[0066] The upper electrode 260 can be disposed on the capacitor dielectric film 250. The upper electrode 260 can be formed along the contour of the capacitor dielectric film 250.

[0067] The upper electrode 260 may include, but is not limited to, doped semiconductor materials, conductive metal nitrides (e.g., titanium nitride, tantalum nitride, niobium nitride, or tungsten nitride), metals (e.g., ruthenium, iridium, titanium, or tantalum), and conductive metal oxides (e.g., iridium oxide or niobium oxide). In a semiconductor device according to some embodiments, the upper electrode 260 may include titanium nitride (TiN). Furthermore, in a semiconductor device according to some embodiments, the upper electrode 260 may include niobium nitride (NbN).

[0068] The upper electrode 270 may be disposed on the upper electrode 260. The upper electrode 270 may include at least one of an elemental semiconductor material film or a compound semiconductor material film. The upper electrode 270 may include doped n-type or p-type impurities. The elemental semiconductor material film may include, for example, a silicon film or a germanium film. The compound semiconductor material film may include, for example, a silicon-germanium film. In a semiconductor device according to some embodiments, the upper electrode 270 may include a silicon-germanium film.

[0069] Unlike the example shown, the upper plate electrode 270 may not be formed between the upper support pattern 150 and the lower support pattern 140 and / or between the lower support pattern 140 and the etch stop film 130.

[0070] exist Figure 1 and Figure 2 In this design, the lower electrode 200 may include an outer portion 210 and an inner portion 220 inside the outer portion 210. The outer portion 210 of the lower electrode 200 may enclose the inner portion 220 of the lower electrode 200. The outer portion 210 of the lower electrode 200 may include an outer surface 200s of the lower electrode 200. The outer portion 210 of the lower electrode 200 is defined as a region with thickness, while also including the outer surface 200s of the lower electrode 200. Therefore, the outer portion 210 of the lower electrode 200 may have any thickness. That is, the ratio of the thickness of the outer portion 210 of the lower electrode 200 to the width of the lower electrode 200 in the first direction DR1 may be greater than 0 and less than 0.5.

[0071] The outer portion 210 of the lower electrode 200 may include a bottom region 210bp, an upper surface region 210up, and a side surface region 210sp. The side surface region 210sp of the outer portion 210 may be a region extending from the bottom surface 200bs of the lower electrode 200 to the upper surface 200us of the lower electrode 200.

[0072] The side surface region 210sp of the outer portion 210 may include the sidewall 200ss of the lower electrode 200. Since the side surface region 210sp of the outer portion 210 extends to the bottom surface 200bs of the lower electrode 200, the bottom region 210bp of the outer portion 210 may include a portion of the bottom surface 200bs of the lower electrode 200. Since the side surface region 210sp of the outer portion 210 extends to the upper surface 200us of the lower electrode 200, the upper surface region 210up of the outer portion 210 may include a portion of the upper surface 200us of the lower electrode 200.

[0073] The side surface region 210sp of the outer portion 210 may contact the etch stop film 130, the lower support pattern 140, and the upper support pattern 150. The side surface region 210sp of the outer portion 210 that does not contact the etch stop film 130, the lower support pattern 140, and the upper support pattern 150 may be a first portion 210sp_1 of the side surface region 210sp of the outer portion 210.

[0074] The portion where the lower electrode 200 and the upper support pattern 150 contact each other can be the second_1 portion 210sp_21 of the side surface region 210sp of the outer portion 210. The portion where the lower electrode 200 and the lower support pattern 140 contact each other can be the second_2 portion 210sp_22 of the side surface region 210sp of the outer portion 210. The portion where the lower electrode 200 and the etch stop film 130 contact each other can be the second_3 portion 210sp_23 of the side surface region 210sp of the outer portion 210.

[0075] The capacitor dielectric film 250 may extend along the first portion 210sp_1 of the upper surface region 210up and the side surface region 210sp of the outer portion 210. The capacitor dielectric film 250 does not extend along the bottom region 210bp, the second portion 210sp_22 of the side surface region 210sp of the outer portion 210, and the second portion 210sp_23 of the side surface region 210sp of the outer portion 210.

[0076] The region where the capacitor dielectric film 250 is formed can be a first region of the outer portion 210 of the lower electrode 200. The region where the capacitor dielectric film 250 is not formed can be a second region of the outer portion 210 of the lower electrode 200. The second _1 portion 210sp_21 of the side surface region 210sp of the outer portion 210 that contacts the upper support pattern 150 can include both the first region and the second region of the outer portion 210 of the lower electrode 200.

[0077] The sidewall 200ss of the lower electrode 200 that does not contact the etch stop film 130, the lower support pattern 140, and the upper support pattern 150 can be a first portion 200ss_1 of the sidewall 200ss of the lower electrode 200. The portion of the lower electrode 200 that contacts the upper support pattern 150 can be a second portion 200ss_21 of the sidewall 200ss of the lower electrode 200. The portion of the lower electrode 200 that contacts the lower support pattern 140 can be a second portion 200ss_22 of the sidewall 200ss of the lower electrode 200. The portion of the lower electrode 200 that contacts the etch stop film 130 can be a second portion 200ss_23 of the sidewall 200ss of the lower electrode 200.

[0078] The second_1 portion 200ss_21 of the sidewall 200ss of the lower electrode 200 is the interface between the lower electrode 200 and the upper support pattern 150. The second_2 portion 200ss_22 of the sidewall 200ss of the lower electrode 200 is the interface between the lower electrode 200 and the lower support pattern 140. The second_3 portion 200ss_23 of the sidewall 200ss of the lower electrode 200 is the interface between the lower electrode 200 and the etch stop film 130.

[0079] The second_1 portion 210sp_21 of the side surface region 210sp of the outer portion 210 includes the second_1 portion 200ss_21 of the sidewall 200ss of the lower electrode 200. The second_2 portion 210sp_22 of the side surface region 210sp of the outer portion 210 includes the second_2 portion 200ss_22 of the sidewall 200ss of the lower electrode 200. The second_3 portion 210sp_23 of the side surface region 210sp of the outer portion 210 includes the second_3 portion 200ss_23 of the sidewall 200ss of the lower electrode 200.

[0080] The capacitor dielectric film 250 may extend along the first portion 200ss_1 of the sidewall 200ss of the lower electrode 200 and the upper surface 200us of the lower electrode 200. The capacitor dielectric film 250 does not extend along the bottom surface 200bs of the lower electrode 200, the second_1 portion 200ss_21 and the second_2 portion 200ss_22 of the sidewall 200ss of the lower electrode 200, and the second_3 portion 200ss_23 of the sidewall 200ss of the lower electrode 200.

[0081] The region where the capacitor dielectric film 250 is formed can be a first region on the outer surface 200s of the lower electrode 200. The region where the capacitor dielectric film 250 is not formed can be a second region on the outer surface 200s of the lower electrode 200.

[0082] Figure 4 This is a diagram schematically illustrating the concentration variation of silicon (Si) dopant in the side surface region 210sp of the outer portion 210 of the lower electrode 200. In some embodiments, Figure 4 The concentration variation of silicon (Si) dopant shown in the figure can be substantially the same as the concentration variation of silicon (Si) dopant on the sidewall 200ss of the lower electrode 200. Figure 4 The concentration variation of silicon (Si) dopant in the side surface region 210sp of the outer portion 210 can be shown from the upper surface 200µs of the lower electrode 200 to the bottom surface 200bs of the lower electrode 200. Figure 4 In, the concentration of silicon (Si) ( / cm³) 3 This only indicates the concentration level for each region. Figure 4 In this context, the concentration of silicon (Si) is not indicated by a quantified concentration value.

[0083] exist Figure 4 In the process, as the upper surface 200µs away from the lower electrode 200 moves further away, the concentration of silicon (Si) dopant in the second_1 portion 210sp_21 of the side surface region 210sp of the outer portion 210 decreases. Thereafter, the concentration of silicon (Si) dopant in the second_1 portion 210sp_21 of the side surface region 210sp of the outer portion 210 can be 0. The second_1 portion 210sp_21 of the side surface region 210sp of the outer portion 210 includes a first sub-region containing silicon (Si) dopant and a second sub-region not containing silicon (Si) dopant.

[0084] Here, stating "concentration is 0" does not mean that silicon (Si) dopant is absent. Instead, stating "concentration is 0" indicates that the amount of silicon (Si) dopant is less than the detection limit of the analytical device.

[0085] In the second_2 portion 210sp_22 and the second_3 portion 210sp_23 of the side surface region 210sp of the outer portion 210, the concentration of silicon (Si) dopant can be 0. On the other hand, in the first portion 210sp_1 of the side surface region 210sp of the outer portion 210, the concentration of silicon (Si) dopant can be C0.

[0086] In other words, as the upper surface 200µs of the lower electrode 200 moves away from the lower electrode 200, the concentration of silicon (Si) dopant decreases in the second_1 portion 200ss_21 of the sidewall 200ss of the lower electrode 200. Thereafter, the concentration of silicon (Si) dopant in the second_1 portion 200ss_21 of the sidewall 200ss of the lower electrode 200 can be 0. The second_1 portion 200ss_21 of the sidewall 200ss of the lower electrode 200 can include portions containing silicon (Si) dopant and portions not containing silicon (Si) dopant.

[0087] Subsequently, in the second_2 portion 200ss_22 and the second_3 portion 200ss_23 of the sidewall 200ss of the lower electrode 200, the concentration of silicon (Si) dopant can be 0. The concentration of silicon (Si) dopant in the first portion 200ss_1 of the sidewall 200ss of the lower electrode 200 can be C0.

[0088] The concentration of silicon (Si) dopant in the upper surface region 210up of the outer portion 210 can be substantially the same as the concentration of silicon (Si) dopant in the first portion 210sp_1 of the side surface region 210sp of the outer portion 210. Therefore, the concentration of silicon (Si) dopant in the upper surface region 210up of the outer portion 210 or the upper surface 200us of the lower electrode 200 can be C0.

[0089] At least a portion of the outer portion 210 of the lower electrode 200 may include a silicon (Si) dopant. In a semiconductor device according to some embodiments, the outer portion 210 of the lower electrode 200 may include a region doped with silicon (Si) dopant and a region not doped with silicon (Si) dopant.

[0090] The capacitor dielectric film 250 extends along the first portion 210sp_1 of the side surface region 210sp of the outer portion 210. However, the capacitor dielectric film 250 does not extend along the second portion 210sp_22 and the second portion 210sp_23 of the side surface region 210sp of the outer portion 210.

[0091] The concentration of silicon (Si) dopant in the first portion 210sp_1 of the side surface region 210sp of the outer portion 210 is different from the concentration of silicon (Si) dopant in the second_1 portion 210sp_21, the second_2 portion 210sp_22, and the second_3 portion 210sp_23 of the side surface region 210sp of the outer portion 210. For example, the concentration of silicon (Si) dopant in the first portion 210sp_1 of the side surface region 210sp of the outer portion 210 is greater than the concentration of silicon (Si) dopant in the second_1 portion 210sp_21, the second_2 portion 210sp_22, and the second_3 portion 210sp_23 of the side surface region 210sp of the outer portion 210.

[0092] Here, the phrase "dopane concentration in the region" can refer to the average dopant concentration in the region. In other words, although there is a portion with a high concentration of silicon (Si) dopant in the second_1 portion 210sp_21 of the side surface region 210sp of the outer portion 210, the average concentration of silicon (Si) dopant in the second_1 portion 210sp_21 of the side surface region 210sp of the outer portion 210 is less than the average concentration of silicon (Si) dopant in the first portion 210sp_1 of the side surface region 210sp of the outer portion 210.

[0093] For example, the portion of the outer portion 210 of the lower electrode 200 in which the capacitor dielectric film 250 is formed may be a region doped with silicon (Si) dopant.

[0094] The lower electrode 200 may include at least a portion of a silicon (Si) dopant along the outer surface 200s of the lower electrode 200. In a semiconductor device according to some embodiments, the outer surface 200s of the lower electrode 200 may include a region doped with silicon (Si) dopant and a region undoped with silicon (Si) dopant.

[0095] The concentration of silicon (Si) dopant in the first part 200ss_1 of the sidewall 200ss of the lower electrode 200 is greater than the concentration of silicon (Si) dopant in the second part 200ss_21, the second part 200ss_22, and the second part 200ss_23 of the sidewall 200ss of the lower electrode 200.

[0096] In other words, the concentration (C0) of silicon (Si) dopant between the lower electrode 200 and the capacitor dielectric film 250 is greater than the concentration of silicon (Si) dopant between the lower electrode 200 and the upper support pattern 150, the concentration of silicon (Si) dopant between the lower electrode 200 and the lower support pattern 140, and the concentration of silicon (Si) dopant between the lower electrode 200 and the etch stop film 130.

[0097] exist Figure 5 In the middle, the second part 210sp_21 of the side surface region 210sp of the outer part 210 that contacts the upper support pattern 150 may not contain silicon (Si) dopant. At the boundary where the upper support pattern 150 and the lower electrode 200 meet, the concentration of silicon (Si) dopant can be drastically reduced.

[0098] Since the upper support pattern 150 includes an insulating material containing silicon, the concentration of silicon (Si) shown in the upper support pattern 150 does not represent the concentration of silicon (Si) dopant contained in the outer portion 210 of the lower electrode 200.

[0099] In a semiconductor device according to some embodiments, silicon (Si) included in the upper support pattern 150 may not diffuse into the lower electrode 200. As a result, the second_1 portion 210sp_21 of the side surface region 210sp of the outer portion 210 may not contain silicon (Si) dopant. The second_2 portion 210sp_22 and the second_3 portion 210sp_23 of the side surface region 210sp of the outer portion 210 may also be the same as the second_1 portion 210sp_21 of the side surface region 210sp of the outer portion 210. The concentration of silicon (Si) dopant in each of the second_2 portion 210sp_22 and the second_3 portion 210sp_23 of the side surface region 210sp may be similar to... Figure 5 The same or similar as shown.

[0100] Figure 6 The variation in the concentration of silicon (Si) dopant in the first portion 210sp_1 of the side surface region 210sp of the outer portion 210, in which the capacitor dielectric film 250 is formed, can be shown. The concentration of silicon (Si) dopant contained in the outer portion 210 of the lower electrode 200 decreases with distance from the outer surface 200s of the lower electrode 200.

[0101] In a semiconductor device according to some embodiments, the concentration of silicon (Si) dopant in the first portion 210sp_1 of the side surface region 210sp of the outer portion 210 is greater than the concentration of silicon (Si) dopant in the inner portion 220 of the lower electrode 200.

[0102] For example, the outer portion 210 of the lower electrode 200 may contain a silicon (Si) dopant, and the inner portion 220 of the lower electrode 200 may not contain a silicon (Si) dopant. The inner portion 220 of the lower electrode 200 may be in an undoped silicon (Si) state. In some embodiments, the inner portion 220 of the lower electrode 200 may be without silicon (Si).

[0103] Figure 7 and Figure 8 Each of them is shown along Figure 2 A schematic diagram of the concentration of silicon (Si) dopant in line A. Figure 9 It shows along Figure 2 A schematic diagram of the concentration of silicon (Si) dopant in line B.

[0104] Reference Figure 7 In a semiconductor device according to some embodiments, a portion of the second_2 portion 210sp_22 of the side surface region 210sp of the outer portion 210 and a portion of the second_3 portion 210sp_23 of the side surface region 210sp of the outer portion 210 may include a silicon (Si) dopant.

[0105] The second_2 portion 210sp_22 and the second_3 portion 210sp_23 of the side surface region 210sp of the outer portion 210 include regions containing silicon (Si) dopants and regions not containing silicon (Si) dopants.

[0106] A portion of the second_2 portion 200ss_22 of the sidewall 200ss of the lower electrode 200 and a portion of the second_3 portion 200ss_23 of the sidewall 200ss of the lower electrode 200 may include silicon (Si) dopant.

[0107] Reference Figure 8 and Figure 9 Each of the second_1 portion 210sp_21, the second_2 portion 210sp_22, and the second_3 portion 210sp_23 of the side surface region 210sp of the outer portion 210 typically includes a silicon (Si) dopant.

[0108] Each of the second_1 portion 200ss_21, the second_2 portion 200ss_22, and the second_3 portion 200ss_23 of the sidewall 200ss of the lower electrode 200 typically includes a silicon (Si) dopant. The silicon (Si) dopant may be doped along the entire second_1 portion 200ss_21 of the sidewall 200ss of the lower electrode 200. The silicon (Si) dopant may be doped along the entire second_2 portion 200ss_22 of the sidewall 200ss of the lower electrode 200. The silicon (Si) dopant may be doped along the entire second_3 portion 200ss_23 of the sidewall 200ss of the lower electrode 200.

[0109] The silicon (Si) dopant contained in the second _1 portion 210sp_21 of the side surface region 210sp of the outer portion 210 may be silicon diffused from the first portion 210sp_1 of the side surface region 210sp of the outer portion 210 and / or the upper support pattern 150.

[0110] The silicon (Si) dopant contained in the second _2 portion 210sp_22 of the side surface region 210sp of the outer portion 210 may be silicon diffused from the first portion 210sp_1 of the side surface region 210sp of the outer portion 210 and / or the lower support pattern 140. The silicon (Si) dopant contained in the second _3 portion 210sp_23 of the side surface region 210sp of the outer portion 210 may be silicon diffused from the first portion 210sp_1 of the side surface region 210sp of the outer portion 210 and / or the etch stop film 130.

[0111] Figures 10 to 12 These are diagrams used to explain some embodiments of a semiconductor device according to the present invention. For ease of explanation, the description may focus on the use of... Figures 1 to 6 The differences described.

[0112] For reference only. Figures 10 to 12 Each of them is Figure 1 A magnified view of part P.

[0113] Reference Figure 10 In a semiconductor device according to some embodiments, the upper electrode 260 may include an upper silicon doped region 260sd formed along the boundary with the upper plate electrode 270.

[0114] The upper electrode 260 may include a first region 260a undoped of silicon (Si) and an upper silicon-doped region 260sd doped with silicon (Si). When the upper electrode 260 includes a TiN film, the upper silicon-doped region 260sd may include a TiN or TiSiN film doped with silicon.

[0115] Reference Figure 11 According to some embodiments, the semiconductor device may further include an insertion film 255 disposed between the lower electrode 200 and the upper electrode 260. The insertion film 255 may be disposed inside the capacitor dielectric film 250. The insertion film 255 may extend along a first portion 210sp_1 of the side surface region 210sp of the outer portion 210 and not along the second_1 portion 210sp_21, the second_2 portion 210sp_22, and the second_3 portion 210sp_23 of the side surface region 210sp of the outer portion 210. The insertion film 255 may not extend along the outer surfaces of the lower support pattern 140 and the upper support pattern 150.

[0116] The insert film 255 can promote the crystallization of the capacitor dielectric film 250. The insert film 255 allows the capacitor dielectric film 250 to be divided into a first portion 250a and a second portion 250b of the capacitor dielectric film. The insert film 255 can contact the first portion 250a and the second portion 250b of the capacitor dielectric film.

[0117] The insertion membrane 255 may include at least one of the nitrides or oxides of, for example, titanium (Ti), niobium (Nb), molybdenum (Mo), and tin (Sn). In some embodiments, the insertion membrane 255 may include at least one of ruthenium (Ru) and ruthenium oxide.

[0118] Reference Figure 12 According to some embodiments, the semiconductor device may also include an upper protective film 265 disposed between the capacitor dielectric film 250 and the upper electrode 260.

[0119] The upper protective film 265 can reduce or prevent the migration of oxygen atoms included in the capacitor dielectric film 250 to the upper electrode 260. The upper protective film 265 may include a metal oxide. The upper protective film 265 may include at least one of, for example, titanium oxide, tantalum oxide, molybdenum oxide, tin oxide, and niobium oxide.

[0120] Figure 13 and Figure 14 These are diagrams used to explain some embodiments of a semiconductor device according to the present invention. For ease of explanation, the description may focus on the use of... Figures 1 to 6 The differences described. For reference, Figure 14 It shows along Figure 2 A schematic diagram of the concentration of silicon (Si) dopant in line C.

[0121] Reference Figure 2 , Figure 13 and Figure 14In a semiconductor device according to some embodiments, the lower electrode 200 may include a metal nitride film 200_1 and a metal silicon nitride film 200_2.

[0122] For example, the lower electrode 200 may include a metal nitride. The metal nitride film 200_1 of the lower electrode 200 may be a portion composed of metal nitride. The metal silicon nitride film 200_2 of the lower electrode 200 may be a silicided portion of the metal nitride film 200_1. In some embodiments, the metal nitride film 200_1 may include a TiN film, and the metal silicon nitride film 200_2 may include a TiSiN film.

[0123] The outer portion 210 of the lower electrode 200 may include a metal nitride film 200_1 and a metal silicon nitride film 200_2. The outer portion 210 of the lower electrode 200 may also include a portion that does not contain the metal silicon nitride film 200_2.

[0124] The silicon nitride film 200_2 can extend along a first region where a capacitor dielectric film 250 is formed in the outer portion 210 of the lower electrode 200. However, the silicon nitride film 200_2 is not formed in a second region where the capacitor dielectric film 250 is not formed in the outer portion 210 of the lower electrode 200. The silicon nitride film 200_2 is not formed between the lower electrode 200 and the upper support pattern 150, between the lower electrode 200 and the lower support pattern 140, and between the lower electrode 200 and the etch stop film 130. For example, the concentration of silicon (Si) dopant in the silicon nitride film 200_2 can remain constant. However, in the silicon nitride film 200_1 in the first portion 210sp_1 of the side surface region 210sp of the outer portion 210, the concentration of silicon (Si) dopant decreases with distance from the outer surface 200s of the lower electrode 200.

[0125] Figures 15 to 18 These are diagrams used to explain some embodiments of a semiconductor device according to the present invention. For ease of explanation, the description may focus on the use of... Figures 1 to 6 The differences described.

[0126] Reference Figure 15 According to some embodiments, the semiconductor device may also include a lower protective film 245 disposed between the capacitor dielectric film 250 and the lower electrode 200.

[0127] The lower protective film 245 may extend along a first region of the outer portion 210 of the lower electrode 200 where a capacitor dielectric film 250 is formed. The lower protective film 245 does not extend along a second region of the outer portion 210 of the lower electrode 200 where no capacitor dielectric film 250 is formed. The lower protective film 245 is not formed between the lower electrode 200 and the upper support pattern 150, between the lower electrode 200 and the lower support pattern 140, and between the lower electrode 200 and the etch stop film 130. In addition, the lower protective film 245 does not extend along the outer surface of the lower support pattern 140, the outer surface of the upper support pattern 150, and the upper surface of the etch stop film 130.

[0128] The lower protective film 245 can reduce or prevent oxygen atoms contained in the capacitor dielectric film 250 from migrating to the lower electrode 200. The lower protective film 245 may include, for example, a metal oxide. The lower protective film 245 may include at least one of, for example, titanium oxide, tantalum oxide, molybdenum oxide, tin oxide, and niobium oxide.

[0129] Reference Figure 16 In a semiconductor device according to some embodiments, the thickness t11 of the lower support pattern 140 in the second direction DR2 may be equal to the thickness t12 of the upper support pattern 150 in the second direction DR2.

[0130] Reference Figure 2 and Figure 17 In a semiconductor device according to some embodiments, the lower electrode 200 may include a bottom 202 extending along the upper surface of a first ground pad 120 and a sidewall portion 201 protruding from the bottom 202. The sidewall portion 201 of the lower electrode 200 may extend along a second direction DR2.

[0131] The outer surface 200s of the lower electrode 200 may include a first sidewall 200ss1 and a second sidewall 200ss2 of the lower electrode 200. The outer surface 200s of the lower electrode 200 may include an upper surface 200us of the lower electrode 200 connecting the first sidewall 200ss1 and the second sidewall 200ss2 of the lower electrode 200. The outer surface 200s of the lower electrode 200 may include a first bottom surface 200bs_1 of the lower electrode 200 connected to the first sidewall 200ss1 of the lower electrode 200 and a second bottom surface 200bs_2 of the lower electrode 200 connected to the second sidewall 200ss2 of the lower electrode 200. The lower electrode 200 may have the shape of a bucket for containing articles. The lower electrode 200 may have, for example, a cylindrical shape.

[0132] The etch stop film 130, the lower support pattern 140, and the upper support pattern 150 can contact the first sidewall 200ss1 of the lower electrode 200. The capacitor dielectric film 250 can extend along the first sidewall 200ss1 and the second sidewall 200ss2 of the lower electrode 200. The bottom 202 of the lower electrode 200 can include an outer portion 210 and an inner portion 220. The sidewall portion 201 of the lower electrode 200 can include the outer portion 210 and the inner portion 220.

[0133] For example, the ratio of the thickness of the outer portion 210 of the lower electrode 200 to the width of the sidewall portion 201 of the lower electrode 200 in the first direction DR1 can be greater than 0 and less than 0.5. The width of the sidewall portion 201 of the lower electrode 200 in the first direction DR1 can be the distance between the first sidewall 200ss1 and the second sidewall 200ss2 of the lower electrode 200, which are opposite to each other. In some embodiments, the width of the sidewall portion 201 of the lower electrode 200 in the first direction DR1 can be at most twice the thickness of the outer portion 210 of the lower electrode 200 in the first direction DR1.

[0134] Reference Figure 18 The semiconductor device according to some embodiments of the present invention may further include an insulating pattern 160 that contacts the lower electrode 200 and extends in the second direction DR2.

[0135] An insulating pattern 160 may be disposed on the etch stop film 130. The insulating pattern 160 may include sidewalls 160s and an upper surface 160u. A first ground pad 120 may be disposed in the etch stop film 130. A lower electrode 200 may be disposed on the etch stop film 130. The lower electrode 200 may include a bottom 202 extending along the upper surface of the first ground pad 120 and a sidewall portion 201 protruding from the bottom 202. The sidewall portion 201 of the lower electrode 200 may extend along a second direction DR2. The sidewall portion 201 of the lower electrode 200 may extend along the sidewall 160s of the insulating pattern 160. For example, the lower electrode 200 may have an L-shape.

[0136] The outer surface of the lower electrode 200 may include a first sidewall 200ss1 and a second sidewall 200ss2 of the lower electrode 200. The second sidewall 200ss2 of the lower electrode 200 may face the sidewall 160s of the insulating pattern 160. The outer surface of the lower electrode 200 may include an upper surface 200us of the lower electrode 200 that connects the first sidewall 200ss1 and the second sidewall 200ss2 of the lower electrode 200. The outer surface of the lower electrode 200 may include a bottom surface 200bs of the lower electrode 200, which is connected to the second sidewall 200ss2 of the lower electrode 200 and faces the upper surface 130s of the etch stop film and the upper surface of the first ground pad 120.

[0137] The capacitor dielectric film 250 may extend along the first sidewall 200ss1 of the lower electrode 200. However, the capacitor dielectric film 250 does not extend along the second sidewall 200ss2 of the lower electrode 200. The capacitor dielectric film 250 is not disposed between the second sidewall 200ss2 of the lower electrode 200 and the sidewall 160s of the insulating pattern 160. The capacitor dielectric film 250 extends along the upper surface 160u of the insulating pattern 160.

[0138] For example, the ratio of the thickness of the outer portion 210 of the lower electrode 200 to the width of the sidewall portion 201 of the lower electrode 200 in the first direction DR1 can be greater than 0 and less than 0.5. In some embodiments, the width of the sidewall portion 201 of the lower electrode 200 in the first direction DR1 can be at most twice the thickness of the outer portion 210 of the lower electrode 200 in the first direction DR1.

[0139] In a semiconductor device according to some embodiments, the concentration of silicon (Si) dopant on the first sidewall 200ss1 of the lower electrode 200 is lower than the concentration of silicon (Si) dopant on the second sidewall 200ss2 of the lower electrode 200. The second sidewall 200ss2 of the lower electrode 200 includes a region doped with silicon (Si) dopant and a region undoped with silicon (Si) dopant.

[0140] Figure 19 This is a schematic layout diagram for explaining some embodiments of a semiconductor device according to the present invention. Figure 20 It is along Figure 19 A sectional view taken from line II. For reference, Figure 19 A layout diagram of dynamic random access memory (DRAM) is shown, which does not show the capacitor CAP, but the layout is not limited to this. Furthermore, Figure 19 The fourth direction DR4 can correspond to Figure 1 The first direction DR1.

[0141] Reference Figure 19According to some embodiments, a semiconductor device may include a plurality of active regions ACT. The active regions ACT may be formed on a substrate ( Figure 20 The component isolation film in (100) is used to ( Figure 20 (305) is limited.

[0142] As the design specifications of semiconductor devices decrease, the active region ACT can be arranged in a diagonal or oblique strip shape as shown. The active region ACT can have a strip shape extending in the fifth direction D5.

[0143] Multiple gate electrodes can be disposed on the active region ACT along a third direction DR3, spanning the active region ACT. These gate electrodes can extend parallel to each other. The gate electrodes can be, for example, multiple word lines WL. The word lines WL can be arranged at equal intervals. The width of the word lines WL or the spacing between them can be determined according to design rules. Multiple bit lines BL extending in a fourth direction DR4 perpendicular to the word lines WL can be disposed on the word lines WL. The bit lines BL can extend parallel to each other. The bit lines BL can be arranged at regular intervals. The width of the bit lines BL or the spacing between them can be determined according to design rules.

[0144] A semiconductor device according to some embodiments may include various contact arrangements formed on an active region ACT. These various contact arrangements may include, for example, direct contacts DC, buried contacts BC, a second ground pad LP, etc. Here, direct contact DC may represent a contact that electrically connects the active region ACT to the bit line BL. Buried contact BC may represent a contact that connects the active region ACT to a capacitor (…). Figure 20 The lower electrode of CAP) Figure 20 The contact element is 200. Considering the layout structure, the contact area between the buried contact element BC and the active area ACT will be small. Therefore, in order to increase the contact area with the lower electrode of the capacitor ( Figure 20 By increasing the contact area of ​​the 200) and the contact area with the active region ACT, a conductive second grounding pad LP can be introduced.

[0145] A second grounding pad LP can be disposed between the active region ACT and the buried contact BC, and can also be disposed between the buried contact BC and the lower electrode of the capacitor. In a semiconductor device according to some embodiments, the second grounding pad LP can be disposed between the buried contact BC and the lower electrode of the capacitor. By introducing the second grounding pad LP to increase the contact area, the contact resistance between the active region ACT and the lower electrode of the capacitor can be reduced.

[0146] In a semiconductor device according to some embodiments, a direct contact DC may be disposed in the central portion of an active region ACT. A buried contact BC may be disposed at both ends of the active region ACT. Since the buried contact BC is disposed at both ends of the active region ACT, a second ground pad LP may be configured to partially overlap with the buried contact BC to be adjacent to both ends of the active region ACT. In other words, the buried contact BC may be formed between the active region ACT and the device isolation film located between adjacent word lines WL and adjacent bit lines BL. Figure 20 (305) stacked.

[0147] The word line WL can be formed as a structure embedded in the substrate 100. The word line WL can be arranged across the active region ACT between the direct contact DC and the embedded contact BC. As shown, two word lines WL can be configured to intersect one active region ACT. Since the active region ACT is configured as an oblique line, the word line WL can have an angle of less than 90 degrees with the active region ACT. The direct contact DC and the embedded contact BC can be arranged symmetrically. Therefore, the direct contact DC and the embedded contact BC can be arranged on a straight line along the third direction DR3 and the fourth direction DR4.

[0148] On the other hand, unlike the direct contact DC and the buried contact BC, the second grounding pad LP can be arranged in a zigzag pattern on the fourth direction DR4 extending from the bit line BL. Furthermore, the second grounding pad LP can be arranged to overlap with the same side surface portion of each bit line BL on the third direction DR3 extending from the word line WL. For example, each of the second grounding pads LP on the first line can overlap with the left side surface of the corresponding bit line BL, and each of the second grounding pads LP on the second line can overlap with the right side surface of the corresponding bit line BL.

[0149] Reference Figure 19 and Figure 20 According to some embodiments, a semiconductor device may include gate structures 315_1 and 315_2, a second storage contact 350, a storage pad 360, and a capacitor CAP.

[0150] A device isolation film 305 can be formed in the substrate 100. The device isolation film 305 can have an STI (shallow trench isolation) structure with excellent device isolation characteristics. The device isolation film 305 can define an active region ACT on the substrate 100. The active region ACT defined by the device isolation film 305 can have, for example... Figure 19The diagram shows an island shape including a major axis and a minor axis. The active region ACT can have a slanted form with an angle of less than 90 degrees relative to the word line WL formed in the element isolation film 305. Furthermore, the active region ACT can have a slanted form with an angle of less than 90 degrees relative to the bit line BL formed on the element isolation film 305. That is, the active region ACT can extend along a fifth direction DR5 having predetermined angles in the third direction DR3 and the fourth direction DR4.

[0151] Gate structures 315_1 and 315_2 may be formed in the substrate 100 and the device isolation film 305. Gate structures 315_1 and 315_2 may be formed across the active region ACT defined by the device isolation film 305 and the device isolation film 305. Gate structures 315_1 and 315_2 include gate structure 315_1 in the active region ACT of the substrate 100 and gate structure 315_2 in the device isolation film 305.

[0152] Gate structures 315_1 and 315_2 may include a buried gate trench 320t, a gate insulating film 330, a gate electrode 320, and a gate block pattern 340 formed in the substrate 100 and the device isolation film 305. The gate electrode 320 may correspond to a word line WL. For example, the depth of the buried gate trench 320t formed in the substrate 100 may be different from the depth of the buried gate trench 320t formed in the device isolation film 305. The gate insulating film 330 may extend along the sidewalls and bottom surface of the buried gate trench 320t. The gate insulating film 330 may extend along the contour of at least a portion of the buried gate trench 320t. The gate insulating film 330 may include at least one of, for example, silicon oxide, silicon oxynitride, and a high dielectric constant material with a dielectric constant higher than that of silicon oxide.

[0153] The gate electrode 320 may be formed on the gate insulating film 330. The gate electrode 320 may fill a portion of the buried gate trench 320t. The gate electrode 320 may include at least one of the following: a doped semiconductor material, a conductive silicide compound, a conductive metal nitride, a conductive metal oxide, a conductive metal oxynitride, and a metal.

[0154] A gate block pattern 340 may be formed on the gate electrode 320. The gate block pattern 340 may fill the remaining buried gate trench 320t in which the gate electrode 320 is formed. The gate block pattern 340 may include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and combinations thereof.

[0155] A second lower interlayer insulating film 370 may be disposed on the substrate 100 and the element isolation film 305. The second lower interlayer insulating film 370 may cover the gate structures 315_1 and 315_2. A second storage contact 350 may be formed in the second lower interlayer insulating film 370. The second storage contact 350 may be connected to the substrate 100. More specifically, the second storage contact 350 may be connected to the source / drain region formed in the active region ACT of the substrate 100. The second storage contact 350 may be disposed on at least one side of the gate structures 315_1 and 315_2. For example, the second storage contact 350 may be arranged on both sides of the gate structures 315_1 and 315_2. The second storage contact 350 may correspond to a buried contact BC. Furthermore, the second storage contact 350 may correspond to Figures 1 to 18 The first storage contact 115.

[0156] Storage pad 360 can be formed on the second storage contact 350. Storage pad 360 can be electrically connected to the second storage contact 350. Here, storage pad 360 can correspond to the second ground pad LP. Additionally, storage pad 360 can correspond to... Figures 1 to 14 The first grounding pad is 120.

[0157] A second upper interlayer insulating film 375 may be formed on a second lower interlayer insulating film 370. The second upper interlayer insulating film 375 may enclose (e.g., surround) the storage pad 360. The second upper interlayer insulating film 375 and the second lower interlayer insulating film 370 may correspond to... Figures 1 to 17 The first interlayer insulating film 110. A lower electrode etch stop film 380 can be formed on the second upper interlayer insulating film 375 and the storage pad 360. The lower electrode etch stop film 380 can correspond to... Figures 1 to 18 Etching stop film 130.

[0158] The capacitor CAP can be located on the storage pad 360. The capacitor CAP can be connected to the storage pad 360. That is, the capacitor CAP can be electrically connected to the second storage contact 350.

[0159] The capacitor CAP may include a lower electrode 200, a lower protective film 245, a capacitor dielectric film 250, an upper electrode 260, and an upper plate electrode 270. The lower support pattern 140 and the upper support pattern 150 may be formed on the lower electrode etch stop film 380. The explanation of the lower electrode 200, capacitor dielectric film 250, upper electrode 260, and upper plate electrode 270 included in the capacitor CAP is consistent with the use of... Figures 1 to 18 The explanations provided are basically the same.

[0160] Figures 21 to 25 This is a diagram illustrating a method for manufacturing a semiconductor device according to some embodiments.

[0161] Reference Figure 21 A first storage contact 115 and a first grounding pad 120 can be formed in a first interlayer insulating film 110 on the substrate 100. An etch stop film 130, a lower molding film 111, a lower support film 140p, an upper molding film 112, and an upper support film 150p can be sequentially formed on the first interlayer insulating film 110.

[0162] Reference Figure 22 A lower electrode 200 can be formed on the first grounding pad 120, penetrating the etch stop film 130, the lower molding film 111, the lower support film 140p, the upper molding film 112, and the upper support film 150p. A portion of the lower electrode 200 can be disposed in the lower electrode hole 130h included in the etch stop film 130.

[0163] Reference Figure 23 An upper support pattern 150 and a lower support pattern 140 can be formed to connect adjacent lower electrodes 200. Each of the upper support pattern 150 and the lower support pattern 140 can contact a portion of the sidewall of the lower electrode 200.

[0164] The upper support pattern 150 can be formed by removing a portion of the upper support film 150p. The upper molding film 112 can be removed through the areas where the upper support pattern 150 is not formed. Subsequently, the lower support pattern 140 can be formed by removing a portion of the lower support film 140p. The lower molding film 111 can be removed through the areas where the lower support pattern 140 is not formed. Therefore, spaces can be formed between the upper support pattern 150 and the lower support pattern 140, and between the lower support pattern 140 and the etch stop film 130.

[0165] Reference Figure 24 A silicon processing region 200STR can be formed in the lower electrode 200 using a surface treatment process 50. In the surface treatment process 50, for example, a silicon-containing precursor can be used.

[0166] A silicon processing region 200STR can be formed on the outer surface of the lower electrode 200 that is not covered by the upper support pattern 150, the lower support pattern 140 and the etch stop film 130.

[0167] If the surface treatment process 50 differs from the example shown and takes a long time, the silicon treatment region 200STR can be, for example, a metal silicon nitride film.

[0168] Reference Figure 25 A capacitor dielectric film 250 can be formed along the contour of the lower electrode 200, the contour of the upper support pattern 150, the contour of the lower support pattern 140, and the upper surface of the etch stop film 130.

[0169] An upper electrode 260 can be formed on the capacitor dielectric film 250.

[0170] In concluding this detailed description, those skilled in the art will understand that many variations and modifications can be made to the exemplary embodiments described herein without substantially departing from the principles of this disclosure. Therefore, the exemplary embodiments described herein should be considered merely general and descriptive, and not for limiting purposes.

Claims

1. A semiconductor device, the semiconductor device comprising: Grounding pad, located on the base; The lower electrode is located on and connected to the grounding pad, wherein the lower electrode includes an outer portion and an inner portion surrounded by the outer portion, and the outer portion includes a first region and a second region; A dielectric film extends along a first region of the outer portion of the lower electrode; and The upper electrode is located on the dielectric film. The first region of the outer portion of the lower electrode includes silicon dopant. The dielectric film does not extend along the second region of the outer portion of the lower electrode. The concentration of silicon dopant in the first region of the outer portion is different from the concentration of silicon dopant in the second region of the outer portion, and The concentration of silicon dopant in the first region of the outer portion is higher than the concentration of silicon dopant in the inner portion.

2. The semiconductor device according to claim 1, wherein, The concentration of silicon dopant in the first region of the outer portion is higher than the concentration of silicon dopant in the second region of the outer portion.

3. The semiconductor device according to claim 1, wherein, The interior of the lower electrode does not contain silicon dopants.

4. The semiconductor device according to claim 1, further comprising: An insert membrane is located between the lower and upper electrodes. The insertion membrane extends along the first region of the outer portion and not along the second region of the outer portion.

5. The semiconductor device according to claim 1, wherein, The lower electrode includes a metal silicon nitride film extending along a first region of the outer portion.

6. The semiconductor device according to claim 5, wherein, The metal silicon nitride film does not extend on the second region of the outer portion.

7. The semiconductor device according to claim 1, further comprising: The support pattern is located on the base and in contact with the outer portion of the second area.

8. The semiconductor device according to claim 1, further comprising: Upper plate electrode, located on the upper electrode. The upper electrode includes a silicon-doped region along the interface with the upper plate electrode.

9. The semiconductor device according to claim 1, wherein, The outer portion includes a side surface region containing the sidewall of the lower electrode and an upper surface region containing the upper surface of the lower electrode. The side surface region of the outer portion includes a first region of the outer portion and a second region of the outer portion.

10. The semiconductor device according to claim 1, wherein, The lower electrode has a column shape that extends in the thickness direction of the substrate.

11. The semiconductor device according to claim 1, wherein, The lower electrode has a cylindrical shape.

12. A semiconductor device, the semiconductor device comprising: Grounding pad, located on the base; The lower electrode is located on and connected to the grounding pad, wherein the lower electrode extends in the thickness direction of the substrate; The support pattern is in contact with a portion of the lower electrode; The dielectric film extends along the outer surface of the lower electrode and the outer surface of the support pattern; and The upper electrode is located on the dielectric film. The lower electrode includes a first region adjacent to the dielectric film and containing silicon dopant, and a second region adjacent to the support pattern. The concentration of silicon dopant in the first region of the lower electrode is higher than the concentration of silicon dopant in the second region of the lower electrode.

13. The semiconductor device according to claim 12, wherein, The first region of the lower electrode includes the outer surface of the lower electrode, and The second region of the lower electrode includes a portion without silicon dopant.

14. The semiconductor device according to claim 13, wherein, The dielectric film extends along the first region of the lower electrode.

15. The semiconductor device according to claim 12, wherein, The lower electrode includes a metal silicon nitride film extending along the outer surface of the lower electrode, and The metal silicon nitride film does not extend between the lower electrode and the support pattern.

16. The semiconductor device of claim 12, further comprising: An insert membrane is located between the lower and upper electrodes. The inserted membrane does not extend along the outer surface of the support pattern.

17. A semiconductor device, the semiconductor device comprising: Trench, located in the substrate; The gate electrode is located in the trench; The buried contact is adjacent to the side of the gate electrode and connected to the substrate; Grounding pad, located on the buried contact component; An etch stop film is placed on the grounding pad and exposes at least a portion of the grounding pad; A first support pattern is located on and spaced apart from the etch stop film, and has a first thickness; The second support pattern is located on and spaced apart from the first support pattern, and has a second thickness, wherein the second thickness is greater than the first thickness; The lower electrode is located on the grounding pad and is in contact with the etching stop film, the first support pattern, and the second support pattern; An insertion membrane is located on the lower electrode; The dielectric film extends along the insertion film, the first support pattern, and the second support pattern; and The upper electrode is located on the dielectric film. The lower electrode includes a first silicon-doped region comprising a portion of the outer surface of the lower electrode, and The insertion film extends over the first silicon doped region.

18. The semiconductor device according to claim 17, wherein, The insertion film does not extend between the lower electrode and the first support pattern, does not extend between the lower electrode and the second support pattern, and does not extend between the lower electrode and the etch stop film.

19. The semiconductor device according to claim 17, wherein, The lower electrode includes a TiN film, and The first silicon-doped region includes a silicon-doped TiN film.

20. The semiconductor device of claim 17, further comprising: Upper plate electrode, located on the upper electrode. The upper electrode comprises a TiN film, and The upper electrode includes a second silicon-doped region along the interface with the upper plate electrode.

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