Pwm signal generator circuit and related integrated circuit

Abstract

Embodiments of the present disclosure relate to PWM signal generator circuits and related integrated circuits. A PWM signal generator circuit includes a multiphase clock generator that generates a plurality of n phased clock phases having a common clock period and phased by a fraction 1 / n of the clock period. For each on duration, the PWM signal generator circuit determines a first integer number and a second integer number, and for each off duration, determines a third integer number and a fourth integer number. The first integer number indicates an integer number of clock periods of the on duration, while the second integer indicates an integer number of the additional fraction 1 / n of the clock period of the on duration. The third integer indicates an integer number of clock periods of the off duration, while the fourth integer number indicates an integer number of the additional fraction 1 / n of the clock period of the off duration.

Description

TECHNICAL FIELD

[0001] Embodiments of the present specification relate to a solution for generating a pulse width modulated (PWM) signal. BACKGROUND

[0002] Generally, as shown in Figure 1 , a PWM signal is a periodic signal having a given switching period T SW , wherein the PWM signal is set to high for a given on duration T ON , and to low for a given off duration T OFF , wherein:

[0003] T SW = T ON + T OFF . (1)

[0004] Moreover, a duty cycle D of the PWM signal is generally defined, wherein D = T ON / T SW .

[0005] Such a PWM signal can be generated in various modes. For example, as shown in Figure 1 , one of the simplest solutions is based on an oscillator circuit generating a clock signal CLK, and a counter configured to increase a count value in response to the clock signal CLK. Thus, by using a comparator circuit, the PWM signal can be generated, e.g., depending on the count value provided by the counter (e.g., by comparing the count value with a given threshold value, which, for example, indicates the on duration T ON and the switching period T SW ).

[0006] However, in such a (digital) implementation, the accuracy and resolution of the PWM signal is limited by the clock period T CLK (sampling frequency) of the clock signal CLK. Moreover, with increasing clock frequency f CLK = 1 / T CLK , switching losses will also increase.

[0007] However, in many applications, a high resolution PWM signal is necessary or highly preferred. For example, as mentioned before, PWM signals can be used in many applications to control the average value of a voltage or current, such as for wireless battery chargers, switched mode power converters, motor control and lighting. For example, in such applications, a half-bridge or full-bridge can be used to drive a resonant tank circuit, which typically comprises one or more inductors and capacitors, wherein the electronic switches of the half-bridge or full-bridge are driven by means of the PWM signal.

[0008] To miniaturize the device, smaller inductors can be used, resulting in higher operating frequencies. Therefore, typically a high frequency modulated waveform PWM signal with high precision resolution should be provided in order to keep the power consumption at an acceptable value. For example, in a switching power supply, the output voltage is typically proportional to the PWM duty cycle. The smaller the adjustment to the duty cycle, the smaller the final change to the output, i.e. a more precise control of the output voltage allows to achieve better accuracy levels and system stability. Moreover, minimizing the output voltage ripple means reducing the noise level.

[0009] Alternative solutions for generating PWM signals, in particular high resolution (HR) PWM signals, are based on the use of multiple clock phases, i.e. phase-shifted clock signals with the same frequency.

[0010] For example, Figure 2 A possible circuit for generating multiple clock phases φ0..φ n via a delay locked loop (DLL) is shown.

[0011] In particular, in the considered example, the clock signal CLK generated by an oscillator OSC is fed to a cascade of multiple (identical) delay stages DU1..DU n . In particular, in the considered example, the first phase φ0corresponds to the clock signal CLK, while the other phases φ1..φ n correspond to the output signals of the delay stages DU1..DU n .

[0012] In the considered example, each of the delay stages DU1..DU n has a programmable / settable delay T DU according to a (voltage or current) control signal CTRL. For example, such delay stages DU with variable delay can be implemented using an even number of inverters, where one or more of the inverters charge a respective capacitance, such as a parasitic capacitance, connected to the output of the inverter. In this case, the control signal CTRL can indicate the current provided by the inverters for charging the respective capacitance, thereby varying the time until the subsequent inverter switches.

[0013] In the considered example, the last phase φ n (having a given delay T D = n-T DU with respect to the clock signal CLK) and the clock signal CLK are provided to a phase detector PD. The output of the phase detector PD is fed to a regulator CP (such as a charge pump) with at least an I (integral) component, where the regulator CP provides the control signal CTRL at the output. Optionally, the control signal CTRL can be passed through a loop filter LF.

[0014] Thus, essentially, the negative feedback loop implemented by the block PD / CP / LF temporally shifts the last phase φ n synchronized to the clock signal CLK. If the delay units DU are identical, all clock phases φ1..φ n will have the same frequency f CLK but are phase shifted by a delay T DU = T CLK / n with respect to the preceding phase.

[0015] Such a plurality of clock phases can also be provided by a phase-locked loop (PLL) comprising a voltage-controlled oscillator (VCO) comprising a ring oscillator with a plurality of delay stages, wherein the PLL is locked to the frequency of the clock signal CLK. Further, in this case, the locking of the PLL can be obtained by varying the delay introduced by the delay stages, e.g. by varying the current provided by an inverter stage implementing such a delay stage via a biasing circuit, until the oscillator signal at the output of the VCO corresponds to the clock signal CLK. Thus, each delay stage of the VCO can provide a respective clock phase which is phase shifted by a given fraction of the period of the clock signal CLK.

[0016] For example, Figure 3 exemplary waveforms of the phases φ1..φ 16 with n = 17 are shown, wherein the last phase φ 17 = φ0= CLK is not shown in the diagram.

[0017] Thus, as Figure 4 shown, while the counter and the respective comparator circuit can provide a coarse PWM signal (with k clock cycles of the clock signal CLK), additional clock phases φ1..φ n may be used to add a fine tuning to the coarse PWM signal, which essentially permits to add a fraction T DU of the clock signal CLK to the coarse PWM signal. Such a solution is described, for example, in document US 7,206,343 B2, the content of which is incorporated herein by reference for this purpose.

[0018] For example, the fraction can be added to the coarse PWM signal by:

[0019] directly combining the coarse PWM signal with a given selected clock phase φ, for example by using one or more logic (e.g. OR) gates, or

[0020] As described in document US 7,206,343 B2, the coarse PWM signal is indirectly passed through an additional delay stage and combined with the delayed PWM signal, e.g. via a logic (e.g. OR) gate, wherein the additional delay stage introduces a delay of n the same delay T DU , e.g. by using the same control signal CTRL for biasing the additional delay stage as for the delay stages DU1..DU n .

[0021] Hence, assuming that the counter (and the corresponding comparator circuit) provides a coarse PWM signal with a switching period T SW = i-T CLK and an on duration T ON = k-T CLK (0 < k < i), the final PWM signal can have a switching period T SW = i-T CLK and an on duration T ON = k-T CLK + l-T CLK / n (0 < l < n). Hence, the on duration T ON of the PWM signal can be selected by setting integer values for the parameters k and l. In essence, therefore, using an additional DLL or PLL permits to vary the on duration T ON (or, in general, the duty cycle D) with higher precision while the switching period T SW remains constant. SUMMARY

[0022] In view of the foregoing, various embodiments of the present disclosure provide solutions for generating a PWM signal.

[0023] According to one or more embodiments, a PWM signal generator circuit is provided having unique elements set forth in the following description. Embodiments also relate to a corresponding integrated circuit.

[0024] Various embodiments of the present disclosure relate to a PWM signal generator circuit configured to generate a pulse width modulated signal having a given switching duration, the given switching duration comprising an on duration and an off duration.

[0025] In various embodiments, the PWM signal generator circuit comprises a multi-phase clock generator configured to generate a given number n of phase-shifted clock phases, the phase-shifted clock phases having the same clock period and being phase-shifted by a time corresponding to 1 / n of the clock period.

[0026] In various embodiments, the PWM signal generator circuit is configured to:

[0027] determine, for each on-duration, a first integer number indicating an integer number of clock periods of the on-duration, and a second integer indicating an integer number of a fraction 1 / n of a clock period of the on-duration, in addition to the integer number of clock periods of the on-duration, and

[0028] determine, for each off-duration, a third integer number indicating an integer number of clock periods of the off-duration, or an integer number of clock periods of the on-duration, and a fourth integer number indicating an integer number of a fraction 1 / n of a clock period of the off-duration, in addition to the integer number of clock periods of the off-duration.

[0029] For example, in various embodiments, the PWM signal generator circuit can receive, at an input, the first integer number, the second integer number, the third integer number, and the fourth integer number.

[0030] In various embodiments, the PWM signal generator circuit includes a clock switching circuit, a timer circuit, a phase accumulator circuit, and a trigger circuit.

[0031] In various embodiments, the clock switching circuit is configured to generate the timer clock signal by selecting one of the phase-shifted clock phases as the timer clock signal in accordance with a selection signal.

[0032] For example, in various embodiments, the clock switching circuit includes:

[0033] a respective transmission gate for each of the phase-shifted clock phases, and wherein each transmission gate is configured to generate a respective gated clock phase in accordance with the selection signal; and

[0034] combinational logic circuitry configured to generate the timer clock signal by combining the gated clock phases.

[0035] In various embodiments, the timer circuit includes one or more counters and one or more comparators, wherein the timer circuit is configured to:

[0036] vary a first count value in response to the timer clock signal during the on-duration, and generate a first trigger when the first count value reaches the first integer number; and

[0037] vary a second count value in response to the timer clock signal during the off-duration, and generate a second trigger when the second count value reaches the second integer number.

[0038] For example, the timer circuit can comprise a single counter configured to generate the first count value and the second count value. In this case, the third integer number can indicate an integer number of clock periods of the off duration, and the single counter can be reset at the start of each on duration and each off duration. Alternatively, the third integer number can indicate an integer number of clock periods of the switching duration, and the single counter can be reset only at the start of each on duration.

[0039] In various embodiments, the phase accumulator circuit is configured to generate the selection signal by:

[0040] during the on duration, increasing the selection signal by the second integer number; and

[0041] during the off duration, increasing the selection signal by the fourth integer number.

[0042] Typically, a change in the selection signal can occur at any instant during the respective on duration or off duration. However, preferably, the phase accumulator circuit is configured to generate the selection signal by:

[0043] in response to the first trigger, increasing the selection signal by the second integer number; and

[0044] in response to the second trigger, increasing the selection signal by the fourth integer number.

[0045] In various embodiments, the trigger circuit is configured to:

[0046] in response to the first trigger, set the PWM signal to low; and

[0047] in response to the second trigger, set the PWM signal to high.

[0048] In such embodiments, the timer circuit thus operates with an adaptive clock signal resulting from the toggling / combining of the shifted clock phases.

[0049] The inventors have observed that toggling of the clock phase can occur while the previous clock phase was high, resulting in a loss of an edge for increasing the timer circuit.

[0050] Accordingly, to compensate for the missed edge, in various embodiments, the PWM signal generator circuit is configured to:

[0051] during the on duration, determine whether the second integer number is less than n / 2; and if the second integer number is less than n / 2, increase the first count value for a single clock cycle of the timer clock signal by two; and

[0052] during the off duration, determining whether the fourth integer number is less than n / 2; and if the fourth integer number is less than n / 2, increasing the second count value of a single clock cycle of the timer clock signal by two.

[0053] Alternatively, the PWM signal generator circuit can be configured to:

[0054] during the on duration, determining whether the second integer number is less than n / 2; and if the second integer is less than n / 2, decreasing the first integer number by 1; and

[0055] during the off duration, determining whether the fourth integer number is less than n / 2; and if the fourth integer number is less than n / 2, decreasing the third integer number by 1. BRIEF DESCRIPTION OF DRAWINGS

[0056] Embodiments of the present disclosure will now be described, by way of example only, with reference to the accompanying drawings, which are purely illustrative and non-limiting in nature, in which:

[0057] Figure 1 An example of a PWM signal is shown;

[0058] Figure 2 An example of a circuit generating a multi-phase clock signal is shown.

[0059] Figure 3 An example of waveforms of clock phases provided by a circuit of Figure 2 ;

[0060] Figure 4 An example of fine-tuning the on duration of a PWM signal by means of a multi-phase clock signal is shown;

[0061] Figure 5 An embodiment of fine-tuning both the on duration and the off duration of a PWM signal by means of a multi-phase clock signal is shown;

[0062] Figure 6A and Figure 6B An embodiment of a timer circuit according to the present disclosure is shown;

[0063] Figure 7 An example of exemplary waveforms generated by a timer circuit of Figure 6A and Figure 6B ;

[0064] Figure 8 An embodiment of a PWM generator circuit is shown; and

[0065] Figure 9A , Figure 9B , Figure 10A ,Figure 10B 、 Figure 10C 、 Figure 11A 、 Figure 11B 、 Figure 12A 、 Figure 12B 、 Figure 12C and Figure 12D various details of the circuitry of Figure 6A , Figure 6B and Figure 8 are shown. DETAILED DESCRIPTION

[0066] In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments. One or more of the embodiments can be practiced without one or more of the specific details, or through other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail in order to avoid obscuring aspects of the embodiments.

[0067] Reference throughout this specification to "an embodiment" or "one embodiment" means that a particular configuration, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily referring to one and the same embodiment. Furthermore, the particular configurations, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0068] The references used herein are provided solely for convenience and do not define, limit, or restrict the scope or meaning of the embodiments.

[0069] In the following description of Figure 5 to Figure 1 2, reference is made to the portions, elements or components described in Figure 1 to Figure 4 are designated by the same reference numerals used in these figures. These elements have been described and are not repeated in the following in order not to make this detailed description cumbersome.

[0070] As previously mentioned, various embodiments of the present specification relate to a PWM signal generator circuit configured to generate a high resolution PWM signal. In particular, in various embodiments, the PWM signal generator circuit is configured to receive a plurality of clock phases φ0..φ n and to generate rising and falling edges of the PWM signal in accordance with these clock phases φ0..φ n in order to control the PWM duty cycle and the PWM frequency with higher resolution.

[0071] Figure 5 The general operation of the first embodiment is shown.

[0072] In the embodiments considered, the PWM signal generator circuit receives a first clock phase φ0(and / or a last clock phase φ n = φ0) and an intermediate clock phase φ1..φ n-1 In some embodiments, the PWM signal generator circuit comprises a multi-phase clock generator generating the various clock phases, which multi-phase clock generator can comprise any multi-phase clock generator configured to generate the clock phases described herein. Possible solutions for generating such clock phases have been described in the introduction of the present disclosure, and the related description applies in general (see in particular the description of Figure 2 ). That is, in some embodiments, the multi-phase clock generator circuit of various embodiments of the present disclosure can be described, for example, with respect to Figure 2 .

[0073] Also, in the embodiments considered, the PWM signal generator circuit is configured to generate the PWM signal with:

[0074] The on duration T SW can be set to T SW = i · T CLK + j · T CLK / n; and

[0075] The off duration T ON can be set to T ON = k · T CLK + 1 · T CLK / n.

[0076] In various embodiments, the parameters i, j, k and 1 are integer values, wherein the parameters i, j, k and 1 can be programmable.

[0077] In particular, in the example shown in Figure 5 , assuming n = 17, for example, the PWM signal generator circuit receives the clock phases φ0..φ 16 , and the PWM signal generator circuit is configured to generate the PWM signal with:

[0078] T SW = i · T CLK + 10 · T CLK / 17 = T i + 10 · T CLK / 17,

[0079] The duty cycle is 50% (i.e. T ON = T OFF = T SW / 2), i.e.

[0080] T ON = T OFF= T i / 2 + 5-T CLK / 17.

[0081] In the considered example, for simplicity, it is assumed that i is even and k = p = i / 2.

[0082] In particular, in the considered embodiment, the PWM signal generator circuit is configured to use the phase φ0 as a clock signal for a digital counter counting the time period T i / 2 = k-T CLK and, as described in more detail below, the PWM signal generator circuit adds a fraction 5 / 17 of the period T CLK at the end by using the phase φ5.

[0083] However, as an alternative to subsequently tracking the accumulation of various fractions, the PWM signal generator circuit uses the phase φ5 (i.e. the phase for adding the fraction) as a clock signal for a timer circuit (i.e. a digital counter counting the time period p-T CLK . Moreover, the PWM signal generator circuit again adds a respective fraction 5 / 17 of the period T 10 at the end by using the phase φ CLK until the phase φ 10 is shifted by a delay 5-T CLK / 17 with respect to the phase φ5.

[0084] Next, the PWM signal generator circuit uses the phase φ 10 as a clock signal for a digital counter counting the time period k-T CLK and the PWM signal generator circuit this time adds a fraction 5 / 17 of the period T 15 at the end by using the phase φ CLK until the phase φ 15 is shifted by a delay 5-T CLK / 17 with respect to the phase φ 10 .

[0085] Likewise, the PWM signal generator circuit uses the phase φ 15 as a clock signal for a digital counter counting the time period p-T CLK and the PWM signal generator circuit this time adds a fraction 5 / 17 of the period T CLK at the end by using the phase φ3 until the phase φ3 is shifted by a delay 5-T CLK / 17 with respect to the phase φ 15 . / 17.

[0086] The operation continues for subsequent on- and off-periods as well.

[0087] In various embodiments, the PWM generator circuit is thus configured to generate the PWM signal, wherein:

[0088] The on duration corresponds to T ON = k · T CLK + l · T CLK / n; and

[0089] The off duration corresponds to T OFF = p · T CLK + q · T CLK / n.

[0090] In various embodiments, the parameter n (number of delay stages / phases) is fixed at hardware level. However, the number n can also be programmable, e.g. by using a given fixed number of delay stages (e.g. 32) in Figure 2 and selecting the nth phase (not necessarily the last one) as the feedback signal provided to the phase detector PD. In fact, in this way, the control loop is still locked to the nth phase φ n , where T DU = T CLK / n.

[0091] Hence, in various embodiments, the timer circuit (including the counter circuit and the comparator circuit) of the PWM signal generator circuit is configured to:

[0092] During the on period T ON , increase the count value from the reset value until the count value reaches the integer value k; and

[0093] During the off period T OFF , increase the count value from the reset value until the count value reaches the integer value p.

[0094] However, in general, the timer circuit can also monitor the on duration T SW , i.e. the timer circuit (including the counter circuit and the comparator circuit) of the PWM signal generator circuit can be configured to:

[0095] During the on period, increase the count value from the reset value until the count value reaches the integer k value; and

[0096] During the off period, increase the count value used during the on period until the count value reaches the integer value i.

[0097] Accordingly, in various embodiments, the PWM signal generator circuit is configured to determine the parameter k / l as well as at least one of the parameters p / q and i / j, wherein:

[0098] In case of the turn-on period T ON , k corresponds to an integer number of clock cycles of the clock signal CLK and l corresponds to an integer number of fractions 1 / n of a clock cycle of the clock signal CLK;

[0099] In case of the turn-off period T OFF , p corresponds to an integer number of clock cycles of the clock signal CLK and q corresponds to an integer number of fractions 1 / n of a clock cycle of the clock signal CLK; and

[0100] In case of the switching period T SW , i corresponds to an integer number of clock cycles of the clock signal CLK and j corresponds to an integer number of fractions 1 / n of a clock cycle of the clock signal CLK.

[0101] In particular, in view of the above definitions:

[0102] T ON = k · T CLK + l · T CLK / n (2)

[0103] T OFF = p · T CLK + q · T CLK / n (3)

[0104] T SW = T ON + T OFF = i · T CLK + j · T CLK / n (4)

[0105] The integer values i and j are related to the integer values k, l, p and q according to the following equations:

[0106] If (l+q) < n (no overflow), then:

[0107] i = k + p; j = l + q, (5)

[0108] If (l+q) > n (overflow), then:

[0109] i = k + p + 1; j = l + q - n. (6)

[0110] Accordingly, in various embodiments, the PWM generator circuit is configured to receive at least two of the parameters i, k, and p, and at least two of the parameters j, l, and q. For example, the PWM signal generator circuit can receive parameters k / l and / or p / q and / or i / j directly, such as:

[0111] data identifying (e.g., corresponding to) the parameter k / l; and

[0112] data identifying (e.g., corresponding to) the parameter p / q.

[0113] Alternatively, the PWM signal generator circuit can receive other data, permitting the parameters to be calculated according to equations (5) and (6), such as:

[0114] data identifying the switch duration T SW , such as the parameters i and j mentioned above, and one of:

[0115] data identifying (e.g., corresponding to) the parameter k / l;

[0116] data identifying (e.g., corresponding to) the parameter p / q; or

[0117] data identifying the duty cycle.

[0118] As shown in Figure 6A , in various embodiments, the PWM signal generator circuit includes a timer circuit 102 including a digital counter circuit 104 configured to cause an integer count value CNT to change (i.e., increase or decrease) in response to a clock signal CLK TMR, and a comparator circuit 106 configured to compare the count value CNT to a respective integer comparison threshold.

[0119] As shown in Figure 6A , by selecting parameter k or p as the comparison threshold, for example, via a multiplexer 108, the same counter 104 and comparator 106 can be used for both the on period and the off period. Thus, by resetting the counter 104 via a signal at the output of the comparator 106, the same counter 104 can be used to monitor both the on period and the off period. However, the counter 104 can also be used to monitor the on period and the duration T SW . For example, in this case, the multiplexer 108 can receive parameters k and i, and the counter 104 can be reset only when the count value CNT reaches the value i.

[0120] Alternatively, as shown in Figure 6BAs shown, the respective counters 104a and 104b and comparators 106a and 106b can be used for the on-period and the off-period, wherein the comparator 106a compares the count value CNTa provided by the comparison counter 104a with the parameter k, and the comparator 106b compares the count value CNTb provided by the comparison counter 104b with the parameter p.

[0121] In various embodiments, the timer circuit 102 is configured to generate one or more trigger signals when the output of the comparator indicates that the count value has reached the comparison threshold value (e.g. by using the signal EOC_TMR at the output of the comparator 106 or the signals EOC_TMRa and EOC_TMRb at the outputs of the comparators 106a and 106b).

[0122] In the considered embodiments, the signal EOC_TMR( Figure 6A ) or the signals EOC_TMRa and EOC_TMRb( Figure 6B ) are provided to a control circuit 110, which selects the clock signal CLK_TMR for the timer circuit 102 (in particular the counter 104 (104a / 104b)) depending on:

[0123] During the on-period, the parameter l; and

[0124] During the off-period, the parameter q.

[0125] In particular, even at the end of the monitoring of the switch duration T SW , it is preferred to obtain (e.g. calculate) the parameter q, e.g. according to equations (5) and (6), since this parameter indicates the additional fraction that has to be added with respect to the previous on-time.

[0126] For example, the control circuit 110 can select the clock signal CLK_TMR by driving the multiplexer 100 at the input receiving the clock phases φ0..φ n-1 at the input receiving the clock phases φ0..φ

[0127] In particular, in various embodiments, in response to the trigger in the signal EOC_TMR( Figure 6A ) or the signals EOC_TMRa and EOC_TMRb( Figure 6B ), the control circuit 110 is configured to change the logic value of the selection signal SEL1:

[0128] During the on-period, according to the parameter l; and

[0129] During the off period, according to the parameter q.

[0130] In particular, in various embodiments, the control circuit also performs a modulo operation in order to maintain the selection signal SEL1 between 0 and n-1. Thus, in response to a trigger in the signal EOC_TMR( Figure 6A ) or in the signals EOC_TMRa and EOC_TMRb( Figure 6B ), the control circuit 110 causes the selection signal SEL1 to change:

[0131] During the on period, SEL1 = (SEL1 + 1) mod n; and

[0132] During the off period, SEL1 = (SEL1 + q) mod n.

[0133] Thus, in essence, the control circuit 110 implements a phase accumulator circuit that adds either 1 or q to the currently selected phase, where the parameter q can be computed according to the parameters j and n (e.g., as shown in equations (5) and (6)).

[0134] Finally, in various embodiments, the respective period (on period or off period) is terminated, and the subsequent period starts with the next clock pulse from the selected clock phase (i.e., the next rising edge or falling edge based on which type of edge the timer circuit 102 uses).

[0135] Thus, in essence, during the on period T ON , the trigger signal EOC_TMR (or EOC_TMRa) is generated after the time k · T CLK , and the on period is terminated by changing the clock signal CLK_TMR, so that the next off period starts after the additional time l / n · T CLK . Likewise, during the off period T OFF , the trigger signal EOC_TMR (or EOC_TMRb) is generated after the time p · T CLK (e.g., which can be obtained by resetting the counter 104 and waiting for p cycles or by waiting until the count value reaches i), and the off period is terminated by changing the clock signal CLK_TMR, so that the next on period starts after the additional time q / n · T CLK .

[0136] For example, this is illustrated in Figure 7 , where during the on period, the timer circuit uses the clock phase CLK_TMR = φ x , and, for example, during the off period, the timer circuit uses the clock phase CLK_TMR = φ xEOC_TMR is set. In response to the trigger signal EOC_TMR (EOC_TMRa), the control circuit selects the new phase CLK_TMR = φ y (where y = (x + 1) mod n). Moreover, in response to a (e.g. rising) edge immediately following the signal φ y , the PWM signal generator circuit terminates the on-period and starts the subsequent off-period, thereby introducing an additional time corresponding to the fraction l / n of a clock period.

[0137] In the considered embodiment, during the subsequent off-period, the timer circuit uses the clock phase CLK_TMR = φ y , and e.g. after p = 8 periods of the phase φ y with the 9th rising edge, the trigger signal EOC_TMR is set. In response to the trigger signal EOC_TMR (EOC_TMRb), the control circuit selects the new phase CLK_TMR = φ z (where z = (y + q) mod n). In response to a (e.g. rising) edge immediately following the signal φ z , the PWM signal generator circuit terminates the off-period and starts the subsequent on-period, thereby introducing an additional time corresponding to the fraction q / n of a clock period.

[0138] In the previous embodiments, the control circuit 110 is configured to drive the selection circuit 100 so as to change the phase φ assigned to the clock signal CLK_TMR from the current phase φ(t) (e.g. φ0) to the next phase φ(t+1) (e.g. φ5) in response to the signal EOC_TMR, thereby adding the fraction (l or q) at the end of the respective on or off period.

[0139] However, in various embodiments, the switch from the current phase φ(t) to the next phase φ(t+1) can take place at any instant during the respective period. In this case, the control unit 110 can also be configured to sequentially increase / decrease the selection signal SEL1 from the old phase φ(t) to the new phase φ(t+1) (e.g. φ0, φ1, φ2, φ3, φ4, φ5) or directly increase / decrease to the new phase φ(t+1) by switching, e.g. in response to the clock signal CLK_TMR.

[0140] In general, although reference has been made to periods of the clock signal CLK, in practice the phases φ0...φ n-1 may also have different clock periods T PLL , e.g. a frequency f PLL = 1 / T PLL may be the clock frequency f CLKa multiple of T, e.g. by using a frequency divider in the feedback loop of the phase φ n-1 Thus, in general:

[0141] The on duration corresponds to k T ON = k T PLL + 1 T PLL / n; and

[0142] The off duration corresponds to p T OFF = p T PLL + q T PLL / n.

[0143] Figure 8 A second embodiment of the PWM signal generator circuit is shown.

[0144] In particular, in the considered embodiment, the PWM signal generator circuit again comprises a timer circuit 102, a clock switching circuit 100' and a control circuit / phase accumulator 110'.

[0145] In particular, for Figure 6A and Figure 6B , the clock switching circuit 100' is not implemented using only a multiplexer, but rather using a circuit which directly generates the clock signal CLK TMR for the timer circuit 102 in response to the selection signal SEL1 provided by the control circuit 110' in response to the trigger signal EOC TMR provided by the timer circuit 102. Typically, as mentioned before, any other trigger signal can also be used to assign a new clock phase to the clock signal CLK TMR in response to the selection signal SEL1.

[0146] Possible embodiments of the clock switching circuit 100' are shown, for example, in Figure 9A and Figure 9B .

[0147] In the considered embodiment, the selection signal SEL1 (indicating the next clock phase) is provided to a series of optional latches 1000 which are configured to store the value of the signal SEL1 in response to the trigger signal EOC TMR. Basically, these latches 1000 ensure that the value of the signal SEL1 is only sampled by the circuit when a trigger in the signal EOC TMR is generated.

[0148] In the considered embodiment, each clock phase φ0...φ n-1 is provided to a respective transmission gate (gated clock cell) 10020...1002 n which is enabled in response to the selection signal SEL1 or the optionally latched selection signal SEL1, thereby generating the respective (gated) signal φ 0_gtd ...φn-1_gtd For example, in various embodiments, the selection signal includes (n) bits SEL0...SEL n-1 And it uses one-hot encoding, where the positioning is given a phase φ0...φ of a given clock. n-1 Unisemantic association (i.e., bits SEL0...SEL) n-1 Only one bit is set, and it indicates the corresponding clock phase φ0...φ n-1 It can be accessed through the corresponding transmission gates 10020...1002 n-1 While other clock phases φ0...φ n-1 Unable to pass through the corresponding transmission gate 10020...1002 n-1 Generally, other encoding schemes can also be used for the selection signal (such as binary encoding), and the transmission gate can be configured to generate a signal for transmission gates 10020...1002 based on the selection signal SEL1. n-1 The decoder circuit drives the uniquely encoded drive signal.

[0149] like Figure 9B As shown, signal φ 0_gtd …φ n-1_gtd It is then provided to combinational logic circuit 1004, which is configured to output a combinational signal φ. 0_gtd ...φ n-1_gtd This is used to generate the clock signal CLK_TMR for the timer circuit 102. For example, in various embodiments, the signal φ 0_gtd …φ n-1_gtd Combining is achieved through logical OR operations, for example, by using a cascaded structure of multiple OR gates such as OR1, OR2, OR3, etc.

[0150] Figure 10A This illustrates the operation of clock switching circuit 100' at a selection signal SEL1 having values ​​k, x, and y in sequence, thereby sequentially activating clock phases φ (in response to trigger signal EOC_TMR). k_gtd φ x_gtd and φ y_gtd .

[0151] Therefore, if the selection signal SEL1 changes, the clock signal CLK_TMR will switch from the first clock phase to the second clock phase in response to the selection signal.

[0152] Specifically, such as Figure 10B As shown, when the second clock phase (φ) x_gtd ) becomes high (rising edge), and the first clock phase (φ) k_gtdWhen φ is still high, the generated clock signal CLK_TMR will have a duration higher than the clock phase φ0...φ n-1 clock cycle T PLL A single clock pulse is lost, thus essentially a clock cycle is lost.

[0153] This usually happens when the corresponding fraction l or q is less than n / 2.

[0154] On the contrary, such as Figure 10C As shown, when the second clock phase (φ) y_gtd ) becomes high (rising edge), and the first clock phase (φ) x_gtd When φ is low, the generated clock signal CLK_TMR has a duration less than the clock phase φ0...φ n-1 clock cycle T PLL A single clock pulse. This typically occurs when the corresponding fraction l or q is greater than n / 2.

[0155] Therefore, in order to correctly determine the duration of the corresponding time interval, the lost clock edges should be taken into account. Figure 10B Specifically, in various embodiments, if a clock cycle is lost (i.e., the corresponding fraction l or q is less than n / 2), the PWM signal generator circuit is configured to add an additional clock cycle to the timer circuit 102, that is, within a single clock cycle, the timer 102 increments by 2 instead of just 1.

[0156] Figure 11A A possible embodiment of the timer circuit 102 is shown.

[0157] Specifically, in the considered embodiment, counter 104 is implemented using an accumulator, which includes:

[0158] Register 1040, which provides the count value CNT at its output, is configured to store the signal REG_IN at the corresponding input in response to the clock signal CLK_TMR; and

[0159] Digital adder 1042 is configured to generate signal REG_IN at input of register 1040 by adding increment value INC to count value CNT.

[0160] In the considered embodiment, the incremental value INC can be set to "1" or "2" for example via multiplexer 1044. Specifically, the selection is driven via selection signal SEL3 provided by control circuit 110 (or similarly via control circuit 110').

[0161] Specifically, in the considered embodiment, the control circuit 110 includes:

[0162] a digital comparator 1100 configured to determine whether the fractional value I or q of the current on-period or the current off-period is greater than n / 2; and

[0163] a circuit 1102 configured to generate the selection signal SEL3 from the comparison signal generated by the comparator 1100 and a trigger signal (such as the signal EOC TMR) indicating the start of a new on-period or a new off-period; or, in the general case, from the comparison signal generated by the comparator 1100 and a general trigger signal generated at any appropriate moment during an on-period or an off-period and having a length of one CLK TMR cycle.

[0164] In particular, in the considered embodiment, the multiplexer 112 has provided the fractional value for the current period, with the selection signal SEL2 indicating whether the current period is an on-period or an off-period. Thus, the comparator 1100 can receive at the input the signal provided by the multiplexer 112 and thus generate a comparison signal indicating whether the fractional value I or q is greater than n / 2. In particular, the circuits 110 and 112 are configured to:

[0165] when the signal at the output of the comparator indicates that the fraction I or q (based on the current period) is greater than n / 2 or that the trigger signal (e.g. EOC TMR) is not set, the multiplexer 1044 is driven via the signal SEL3 so as to select the value "1", whereby the accumulator 1040 / 1042 is increased by "1" in response to the clock signal CLK TMR; and

[0166] when the signal at the output of the comparator indicates that the fraction I or q (based on the current period) is less than n / 2 and that the trigger signal (e.g. EOC TMR) is set, the multiplexer 1044 is driven via the signal SEL3 so as to select the value "2", whereby the accumulator 1040 / 1042 is increased by "2" in response to the clock signal CLK TMR.

[0167] Thus, in essence, the timer circuit 104 is configured to increase the count value by two ("2") for one clock cycle of the signal CLK TMR (i.e. a single cycle of each on-period or off-period) when the fraction I or q (based on the current period) is less than n / 2.

[0168] Conversely, Figure 11B It is shown that similar results can be obtained by directly adjusting the threshold value used by the comparator 106.

[0169] In particular, in the considered embodiment, the increment value INC is always set to "1" and an additional digital subtractor is provided, which is configured, for example, via the multiplexer 1048, to:

[0170] Subtract the value "1" from the current threshold (k or p) selected by the multiplexer 108; or

[0171] Maintain the threshold, for example, by subtracting the value "0" from the current threshold (k or p) selected by the multiplexer 108.

[0172] Generally, it is also possible to combine embodiments, that is, during the on-time duration, it can be achieved through the "plus two" mechanism ( Figure 11A ) or adjustment of threshold k ( Figure 11B This can be achieved through a "plus two" mechanism or by adjusting the threshold p during the off-duty period.

[0173] Therefore, in the considered embodiment, circuit 1100 / 1102 notifies timer circuit 102 because... Figure 9B The clock combination shown has missed or is about to miss a counting edge. This missed edge information (i.e., signal SEL3) can be calculated by the control circuit / phase accumulator machine 110 / 110', which controls the fine delay selection and generates a phase selection change SEL1 (indicating the next clock phase to be used for fine-tuning the PWM signal). In practice, if the new phase selection selects a clock with a rising edge occurring during the on-time of the running clock, the combination CLK_TMR will have a longer on-time and is used for... Figure 9B The edge of the next selected clock phase of the clock combination circuit will be missed. This occurs if the phase selection change is less than half the number of available phases, i.e., when the corresponding fraction l or q is less than n / 2 (e.g., This happens when ( ).

[0174] Using this clock to change properties, the timer can increment by "1" or "2", or the threshold of comparator 106 can be relative to, for example, Figure 11A or Figure 11B The generated internal flag is used for adjustment.

[0175] In various embodiments, in response to a new clock phase (i.e., the selected clock phase φ of the subsequent turn-on or turn-off cycle), 0_gtd ...φ n-1_gtd The PWM signal is switched on the next rising edge of the trigger signal EOC_TMR. However, if the SEL1 signal is generated at any appropriate moment during a given time slot / cycle, the PWM signal can also be changed in response to the rising edge of the trigger signal EOC_TMR.

[0176] For example, such as Figure 8As shown, the PWM signal generator circuit may include a trigger circuit 114, which is configured to respond to a signal φ. 0_gtd ...φ n-1_gtd The trigger signal EOC_TMR generates a PWM signal.

[0177] Typically, in response to the signal EOC_TMR (or EOC_TMRa and EOC_TMRb) and the new clock phase, any suitable circuit can be used to switch the level of the PWM signal.

[0178] For example, Figure 12A An embodiment of trigger circuit 114 is shown. Specifically, trigger circuit 114 includes rising edge detector circuitry. Specifically, in the considered embodiment, the trigger circuit includes circuitry for signal φ. 0_gtd ...φ n-1_gtd The corresponding rising edge detector for each signal in the array is 11400..1140 n-1 It is enabled based on the signal EOC_TMR.

[0179] Specifically, such as Figure 12B , Figure 12C and Figure 12D As shown, in response to the rising edge of the current clock phase (e.g., Figure 12C φ in k_gtd The signal EOC_TMR will be set after a short delay. In response to the triggering of the signal EOC_TMR, circuit 100' will switch to the new clock phase (e.g., Figure 12C φ in x_gtd Therefore, the additional rising edge of the old clock signal (e.g., Figure 12C φ in k_gtd ) will not occur. Therefore, in response to the subsequent rising edge in the new clock phase (e.g., Figure 12C φ in x_gtd The corresponding edge detector 1140 sets its output (e.g., sets it to high), which is also because the signal EOC_TMR is still set.

[0180] Therefore, in the considered embodiment, for this purpose, various rising edge detectors 11400...1140... n-1 The output can be connected to, for example, a combinational logic circuit that implements a logical OR function. Figure 12AA logic OR gate OR4 is schematically shown, which can correspond to the last OR gate in a chain of OR gates, e.g. including a cascade of 6 OR gates with 3 inputs, 2 OR gates with 2 inputs, and the OR gate OR4, but in general, different numbers and topologies of gates can be used to implement the various rising edge detectors 11400..1140 n-1 The output of the OR gate OR4, which can correspond to the last OR gate in a chain of OR gates, e.g. including a cascade of 6 OR gates with 3 inputs, 2 OR gates with 2 inputs, and the OR gate OR4, but in general, different numbers and topologies of gates can be used to implement the various rising edge detectors 11400..1140

[0181] Thus, in the considered embodiment, the signal TRIG can be used to drive a flip-flop FF1 in order to invert the output of the flip-flop FF1, wherein the PWM signal is generated (and preferably corresponds to) from the signal at the output of the flip-flop FF1.

[0182] For example, in the considered embodiment, the flip-flop FF1 is implemented using a D-type flip-flop, which receives the inverted output signal of the flip-flop FF1 at the data terminal D via an inverter INV1, so that the output of the flip-flop FF1 is inverted in response to the trigger signal TRIG.

[0183] Of course, the details of construction and embodiments can vary widely with respect to what is described and illustrated herein by way of example only, without thereby departing from the scope of the present disclosure, as defined by the claims hereafter, without impairing the principles of the present disclosure.

[0184] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above- described description. In general, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments, in conjunction with other features, structures, or characteristics not expressly described above. It will be appreciated that those skilled in the art will be able to devise many embodiments that, although not explicitly described herein, embody the principles of the application and are thus within the spirit and scope of the application as defined by the following claims.

Claims

1. A pulse width modulation (PWM) signal generator circuit, comprising: A multiphase clock generator is configured to generate a given number of n phase-shifted clock phases, wherein the given number of n phase-shifted clock phases have the same clock period and are phase-shifted by a fraction of 1 / n of the clock period. The PWM signal generator circuit is configured as follows: Generate a PWM signal, the PWM signal having a given switching duration, the given switching duration including an on duration and an off duration; For each on-time duration, a first integer number and a second integer number are determined, the first integer number indicating the integer number of clock cycles of the on-time duration, and the second integer number indicating the integer number of the integer number of clock cycles of the on-time duration, which is the fraction 1 / n of the clock cycles of the on-time duration. as well as For each off duration, a third integer number and a fourth integer number are determined, the third integer number indicating an integer number of clock cycles for the off duration or an integer number of clock cycles for the on duration, and the fourth integer number indicating an integer number of the fraction 1 / n of the clock cycles for the off duration, appended to the integer number of clock cycles for the off duration. as well as The clock switching circuit is configured to generate the timer clock signal by selecting one of the phase-shifted clock phases as the timer clock signal based on a selection signal; A timer circuit, including one or more counters and one or more comparators, is configured to: During the on-time duration, a first count value changes in response to the timer clock signal, and a first trigger is generated when the first count value reaches the first integer number; as well as During the off duration, a second count value changes in response to the timer clock signal, and a second trigger is generated when the second count value reaches the third integer number; The phase accumulator circuit is configured to generate the selection signal by means of the following: During the on-time duration, the selection signal is incremented by the second integer number, and During the off duration, the selection signal is incremented by the fourth integer number; as well as The trigger circuit is configured as follows: In response to the first trigger, the PWM signal is set low, and In response to the second trigger, the PWM signal is set high.

2. The PWM signal generator circuit according to claim 1, configured to receive the first integer number and the second integer number, as well as the third integer number and the fourth integer number at the input.

3. The PWM signal generator circuit according to claim 1 is configured as follows: During the on-time duration, it is determined whether the second integer count is less than n / 2, and in response to determining that the second integer count is less than n / 2, the first count value is incremented by two for a single clock cycle of the timer clock; and During the off duration, it is determined whether the fourth integer number is less than n / 2, and in response to determining that the fourth integer number is less than n / 2, the second count value is incremented by two for a single clock cycle of the timer clock.

4. The PWM signal generator circuit according to claim 1 is configured as follows: During the connection duration, it is determined whether the second integer number is less than n / 2, and in response to determining that the second integer number is less than n / 2, the first integer number is decreased by 1; and During the shutdown duration, it is determined whether the fourth integer number is less than n / 2, and in response to determining that the fourth integer number is less than n / 2, the third integer number is reduced by 1.

5. The PWM signal generator circuit of claim 1, wherein the timer circuit includes a single counter configured to generate the first count value and the second count value, and wherein the third integer number indicates the integer number of clock cycles of the off-duty duration, and the single counter is reset at the beginning of each on-duty duration and each off-duty duration.

6. The PWM signal generator circuit of claim 1, wherein the timer circuit includes a single counter configured to generate the first count value and the second count value, and wherein the third integer number indicates the integer number of clock cycles of the switching duration, and the single counter is reset only at the beginning of each on-duration.

7. The PWM signal generator circuit of claim 1, wherein the phase accumulator circuit is configured to generate the selection signal by: In response to the first trigger, the selection signal is incremented by the second integer number, and In response to the second trigger, the selection signal is incremented by the fourth integer number.

8. The PWM signal generator circuit according to claim 1, wherein the clock switching circuit comprises: For each phase-shifted clock phase in the phase-shifted clock phase, a corresponding transmission gate is configured to generate a corresponding gated clock phase based on the selection signal; as well as Combinational logic circuitry is configured to generate the timer clock signal by combining the gated clock phases.

9. An integrated circuit, comprising: The PWM signal generator circuit is configured as follows: Receive n phase-shifted clock phases, the n phase-shifted clock phases having the same clock period and being phase-shifted by a fraction of 1 / n of the clock period; Generate a PWM signal, the PWM signal having a given switching duration, the given switching duration including an on duration and an off duration; For each on-time duration, a first integer number and a second integer number are determined, the first integer number indicating the integer number of clock cycles of the on-time duration, and the second integer number indicating the integer number of the integer number of clock cycles of the on-time duration, which is the fraction 1 / n of the clock cycles of the on-time duration. For each off duration, a third integer number and a fourth integer number are determined, the third integer number indicating an integer number of clock cycles for the off duration or an integer number of clock cycles for the on duration, and the fourth integer number indicating an integer number of the fraction 1 / n of the clock cycles for the off duration, appended to the integer number of clock cycles for the off duration. The PWM signal generator circuit includes: The clock switching circuit is configured to select one of the phase-shifted clock phases as the timer clock signal based on a selection signal; A timer circuit, including one or more counters and one or more comparators, is configured to: During the on-time duration, a first count value changes in response to the timer clock signal, and a first trigger is generated when the first count value reaches the first integer number; and During the off-duration period, a second count value changes in response to the timer clock signal, and a second trigger is generated when the second count value reaches the second integer number; The phase accumulator circuit is configured to generate a selection signal via the following: During the on-time duration, the selection signal is incremented by the second integer number, and During the off duration, the selection signal is incremented by the fourth integer number, and The trigger circuit is configured as follows: In response to the first trigger, the PWM signal is set low, and In response to the second trigger, the PWM signal is set high.

10. The integrated circuit of claim 9, wherein the PWM signal generator circuit is configured as follows: During the on-time duration, it is determined whether the second integer count is less than n / 2, and in response to determining that the second integer count is less than n / 2, the first count value is incremented by two for a single clock cycle of the timer clock; and During the off duration, it is determined whether the fourth integer number is less than n / 2, and in response to determining that the fourth integer number is less than n / 2, the second count value is incremented by two for a single clock cycle of the timer clock.

11. The integrated circuit of claim 9, wherein the PWM signal generator circuit is configured as follows: During the connection duration, it is determined whether the second integer number is less than n / 2, and in response to determining that the second integer number is less than n / 2, the first integer number is decreased by one; and During the shutdown duration, it is determined whether the fourth integer number is less than n / 2, and in response to determining that the fourth integer number is less than n / 2, the third integer number is reduced by one.

12. The integrated circuit of claim 9, wherein the timer circuit includes a single counter configured to generate the first count value and the second count value, and wherein the third integer number indicates the integer number of clock cycles of the off duration, and the single counter is reset at the beginning of each on duration and each off duration.

13. The integrated circuit of claim 9, wherein the timer circuit includes a single counter configured to generate the first count value and the second count value, and wherein the third integer number indicates the integer number of clock cycles of the switch duration, and the single counter is reset only at the beginning of each on-duty duration.

14. The integrated circuit of claim 9, wherein the phase accumulator circuit is configured to generate the selection signal by: In response to the first trigger, the selection signal is incremented by the second integer number, and In response to the second trigger, the selection signal is incremented by the fourth integer number.

15. The integrated circuit of claim 9, wherein the clock switching circuit comprises: For each phase-shifted clock phase in the phase-shifted clock phase, a corresponding transmission gate is configured to generate a corresponding gated clock phase based on the selection signal; as well as Combinational logic circuitry is configured to generate the timer clock signal by combining the gated clock phases.

16. A method for generating a pulse width modulation (PWM) signal, comprising: Receive n phase-shifted clock phases, the n phase-shifted clock phases having the same clock period and being phase-shifted by a fraction of 1 / n of the clock period; Generate the PWM signal, the PWM signal having a given switching duration, the given switching duration including an on duration and an off duration; For each on-time duration, a first integer number and a second integer number are determined, the first integer number indicating the integer number of clock cycles of the on-time duration, and the second integer number indicating the integer number of the integer number of clock cycles of the on-time duration, which is the fraction 1 / n of the clock cycles of the on-time duration. For each off duration, a third integer number and a fourth integer number are determined, the third integer number indicating an integer number of clock cycles for the off duration or an integer number of clock cycles for the on duration, and the fourth integer number indicating an integer number of the fraction 1 / n of the clock cycles for the off duration, appended to the integer number of clock cycles for the off duration. as well as One of the phase-shifted clock phases is selected as the timer clock signal based on the selection signal; During the on-time duration, a first count value changes in response to the timer clock signal, and a first trigger is generated when the first count value reaches the first integer number; as well as During the off-duration period, a second count value changes in response to the timer clock signal, and a second trigger is generated when the second count value reaches the second integer number; During the on-time duration, the selection signal is incremented by the second integer number; During the off duration, the selection signal is incremented by the fourth integer number; In response to the first trigger, the PWM signal is set low; and In response to the second trigger, the PWM signal is set high.

17. A pulse width modulation (PWM) signal generator circuit, comprising: A multiphase clock generator is configured to generate phase-shifted clock phases having the same clock period and being phase-shifted by a fraction of the clock period. The PWM signal generator circuit is configured to: Generate a PWM signal, the PWM signal having a given switching duration, the given switching duration including an on duration and an off duration; For each on-time duration, determine the number of clock cycles for the on-time duration and the number of fractions of the clock cycles for the on-time duration; as well as For each shutdown duration, determine the number of clock cycles for the shutdown duration and the number of fractions of the clock cycles for the shutdown duration; The clock switching circuit is configured to select one of the phase-shifted clock phases as the timer clock signal based on a selection signal; A timer circuit, including one or more counters and one or more comparators, is configured to: During the on-duration period, a first count value changes in response to the timer clock signal, and a first trigger is generated when the first count value reaches a first integer number, the first integer number indicating the integer number of clock cycles of the on-duration period; as well as During the shutdown duration, a second count value changes in response to the timer clock signal, and a second trigger is generated when the second count value reaches a second integer number, the second integer number indicating the integer number of clock cycles of the shutdown duration; The phase accumulator circuit is configured to generate a selection signal via the following: During the on-duration, the selection signal is incremented by a third integer, the third integer indicating the number of clock cycles of the on-duration; During the shutdown duration, the selection signal is incremented by a fourth integer number, the fourth integer number indicating the number of clock cycles of the shutdown duration; as well as The trigger circuit is configured as follows: In response to the first trigger, the PWM signal is set low, and In response to the second trigger, the PWM signal is set high.

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