Switching circuit and camera device

Abstract

The switch circuit (100) comprises a first input terminal (401), an output terminal (400), and a first circuit (110) for switching whether a first voltage input to the first input terminal (401) is output to the output terminal (400); the first circuit (110) comprises a first transistor (1) and a second transistor (2) connected in series between the first input terminal (401) and the output terminal (400), and a first voltage dividing circuit (12) for dividing the first voltage and supplying it to a common node (N1) between the first transistor (1) and the second transistor (2).

Description

Technical Field

[0001] The present invention relates to a switching circuit and an imaging device having the switching circuit, and more particularly to a switching circuit including a plurality of transistors connected in series. Background Art

[0002] Conventionally, as a switch circuit for handling high voltage using a low withstand voltage transistor, a circuit structure in which a plurality of transistors are connected in series is known.

[0003] For example, in the following patent document 1 (refer to Figure 3 ), the switch circuit connected between two terminals that generate a potential difference exceeding the withstand voltage of the transistor has a structure in which three stages of NMOS transistors are connected in series. Furthermore, the following voltages are input to the gate voltages of these NMOS transistors. That is, two intermediate voltages are generated by resistor-dividing the high voltage applied between the gate of the primary NMOS transistor and the drain of the third-stage NMOS transistor, and the GND voltage Vg1 as the first intermediate voltage is input to the gate of the primary NMOS transistor, the second highest intermediate voltage Vg2 following the GND voltage Vg1 is input to the gate of the second-stage NMOS transistor, and the third highest intermediate voltage Vg3 following the GND voltage Vg1 is input to the gate of the third-stage NMOS transistor.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2013-207700 Summary of the invention

[0007] Problems to be solved by the invention

[0008] In a switching circuit including a plurality of transistors connected in series, improvement in reliability is required.

[0009] An object of the present invention is to provide a highly reliable switch circuit and an imaging device including the switch circuit.

[0010] Means used to solve problems

[0011] According to a non-limiting exemplary embodiment of the present invention, for example, the following technical solution is provided.

[0012] A switching circuit of a technical solution of the present invention comprises: a first input terminal; an output terminal; and a first circuit for switching whether a first voltage input to the first input terminal is output to the output terminal; the first circuit comprises: a first transistor and a second transistor connected in series between the first input terminal and the output terminal; and a first voltage divider circuit for dividing the first voltage and supplying it to a first node between the first transistor and the second transistor.

[0013] A camera device according to a technical solution of the present invention comprises: a semiconductor substrate; a pixel array, comprising a plurality of pixels arranged on the above-mentioned semiconductor substrate; and the above-mentioned switching circuit, located on the above-mentioned semiconductor substrate; the above-mentioned plurality of pixels respectively have a photoelectric conversion portion comprising a first electrode layer, a second electrode layer and a photoelectric conversion layer sandwiched by the above-mentioned first electrode layer and the above-mentioned second electrode layer; the above-mentioned first electrode layers respectively possessed by the above-mentioned plurality of pixels form a common electrode layer; the above-mentioned output terminal of the above-mentioned switching circuit is connected to the above-mentioned common electrode layer.

[0014] Effects of the Invention

[0015] According to an aspect of the present invention, the reliability of a switch circuit including a plurality of transistors connected in series and an imaging device including the switch circuit is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a diagram showing a configuration example of a switch circuit according to the first embodiment.

[0017] Figure 2 This is a diagram showing a specific circuit example of the switch circuit according to the first embodiment.

[0018] Figure 3 This is a diagram showing a configuration example of a switch circuit according to the second embodiment.

[0019] Figure 4 This is a diagram showing a table illustrating the states of the switching circuit according to the second embodiment.

[0020] Figure 5 This is a diagram showing a specific circuit example of a switch circuit according to the second embodiment.

[0021] Figure 6 This is a diagram showing a specific circuit example of a switch circuit according to the third embodiment.

[0022] Figure 7 This is a diagram showing a configuration example of an image sensor according to a fourth embodiment in which a switch circuit according to any of the first to third embodiments is mounted.

[0023] Figure 8 Yes means Figure 7 A timing chart showing an example of the operation of the image sensor shown. DETAILED DESCRIPTION

[0024] (To gain knowledge of one aspect of the present invention)

[0025] In the switch circuit disclosed in Patent Document 1, three transistors are connected in series, and the gates of two of the three transistors are applied with voltages Vg2 and Vg3 obtained by dividing the high voltage between the high voltage side node nd1 and the low voltage side node nd3 with a resistor. The switch circuit is configured to be turned on when the voltage of the node nd2 = the voltage of the node nd1 < 0 (i.e., negative potential), and turned off when the voltage of the node nd2 < the voltage of the node nd1, or the voltage of the node nd2 = the voltage of the node nd1 = the GND level. In the switch circuit, three transistors are connected in series so that even if a voltage exceeding the withstand voltage of the transistor is applied to the node nd1, the transistor will not be damaged and reliability can be maintained. In addition, the withstand voltage is the maximum allowable voltage that can be applied to the transistor, also known as the maximum rating. In addition, when abbreviated as "transistor", it refers to the transistor constituting the switch circuit. In addition, "high voltage" as an input voltage is a relative expression, meaning a voltage exceeding the withstand voltage of the transistor.

[0026] However, when the switch circuit is in the off state, the voltage of the source terminal and the voltage of the drain terminal of each transistor converge to a certain value according to the off leakage current of the transistor after the voltage of the gate of each transistor is divided by the resistor divider. The time required for convergence and the converged voltage value also vary according to the threshold voltage (Vth) of each transistor, the potential difference between the node nd1 and the node nd2, the size of each transistor (gate width, gate length), the off leakage current value, the power supply voltage, the junction temperature, etc. Therefore, it is difficult to reliably control the voltage between the gate-source, gate-drain, drain-source, and gate-back gate terminals to be less than the withstand voltage while frequently switching the on and off state of the switch circuit.

[0027] Furthermore, the premise of the conventional switch circuit is that, in the disconnected state, the node nd1 and the node nd2 are at the same potential. Therefore, when two or more switch circuit elements are used to construct a switch circuit having the same number of input terminals and one common output terminal as the number of these switch circuit elements, when one switch circuit element becomes an on state and the other switch circuit elements become an off state, and a potential difference is generated between the input terminal and the common output terminal of the switch circuit element in the off state, it is difficult to maintain the switch circuit element in the off state while ensuring the reliability of the transistor constituting the switch circuit element in the off state. In addition, the switch circuit is a circuit as a whole having the function of a switch. The switch circuit element is one of the elements constituting the switch circuit, and is a circuit having the function of a switch. The switch circuit is composed of one or more switch circuit elements.

[0028] Therefore, the object of the present invention is to provide a switch circuit that can speed up the switching time of the on-off state and reliably control the voltage between the terminals of each transistor to be less than the withstand voltage when a switch circuit with a high withstand voltage is formed using low withstand voltage transistors. Furthermore, the object of the present invention is to ensure the reliability of the transistor in the off state in a switch circuit that uses two or more switch circuit elements and has the same number of input terminals and one common output terminal as the number of these switch circuit elements.

[0029] In order to achieve the above object, in one embodiment of the present invention, a desired voltage generated by resistor voltage division is applied to the drain voltage terminal of the first transistor (i.e., the source voltage terminal of the second transistor), so that the voltage between the terminals of each transistor is reliably maintained below the withstand voltage, and the drain voltage of the first transistor (i.e., the source voltage terminal of the second transistor) is made to follow the response characteristics when the gate voltage is controlled. As a result, in a switch circuit that uses a low withstand voltage transistor to turn a high voltage on and off, the reliability of the low withstand voltage transistor can be maintained and the on and off state can be switched at a higher speed than the conventional technology.

[0030] Hereinafter, the embodiments will be described with reference to the accompanying drawings. In addition, the embodiments described below all represent a specific example of the present invention. The numerical values, shapes, components, configuration positions and connection forms of the components, operation timing, etc. shown in the following embodiments are examples and do not limit the meaning of the present invention. In addition, the figures are not necessarily strictly illustrated. In the figures, there are cases where the same reference numerals are given to substantially the same structures and repeated descriptions are omitted or simplified.

[0031] (Implementation Method 1)

[0032] Figure 1 FIG. 1 is a diagram showing a configuration example of a switch circuit 100 according to Embodiment 1. Figure 1In the embodiment, the switch circuit 100 includes a first input terminal 401 to which a high voltage as an example of a first voltage is input, an output terminal 400 to output the high voltage input to the first input terminal 401, and a first circuit 110 as a switch circuit element that switches whether the high voltage input to the first input terminal 401 is output to the output terminal 400. The first circuit 110 includes a first transistor 1 and a second transistor 2 connected in series, a first gate voltage control unit 10 that controls on / off of the first transistor 1, a second gate voltage control unit 11 that controls on / off of the second transistor 2, and a first voltage divider circuit 12 that divides the high voltage input to the first input terminal 401. A voltage VN1 obtained by voltage division by the first voltage divider circuit 12 is supplied to a common node N1 that is an example of a first node between the first transistor 1 and the second transistor 2. In addition, the first gate voltage control unit 10 and the second gate voltage control unit 11 are not necessarily provided in the first circuit 110 , and may be provided outside the switch circuit 100 , for example.

[0033] In the present embodiment, the first transistor 1 and the second transistor 2 are both PMOS transistors. When the switch circuit 100 is turned on, the first gate voltage control unit 10 and the second gate voltage control unit 11 respectively turn on the first transistor 1 and the second transistor, and when the switch circuit 100 is turned off, the first gate voltage control unit 10 and the second gate voltage control unit 11 respectively turn off the first transistor 1 and the second transistor.

[0034] In the switch circuit 100 of the present embodiment, two low withstand voltage transistors, namely, the first transistor 1 and the second transistor 2, are connected in series. In particular, when the switch circuit 100 is in the off state, the terminal voltage is controlled so as not to exceed the withstand voltage of the transistor between any two terminals (gate terminal-source terminal, gate terminal-drain terminal, drain terminal-source terminal, gate terminal-back gate terminal, source terminal-back gate terminal, drain terminal-back gate terminal) of each of the first transistor 1 and the second transistor 2. In addition, since the output terminal 400 becomes a floating state when the switch circuit 100 is in the off state, other voltages can also be applied to the output terminal 400 via other switch circuits.

[0035] For example, an example is shown regarding the withstand voltage Vhv=4V of the transistor, the high voltage VIN1=7V input to the first input terminal 401, the gate voltage of the transistor when the output terminal 400 is applied with the output voltage VOUT=0V when the switching circuit 100 is in the off state, and the voltage VN1 of the common node N1 between the two series-connected first transistors 1 and second transistors 2.

[0036] The first gate voltage control unit 10 applies a gate voltage Vg1=7V to the gate of the first transistor 1. As a result, the gate-source voltage of the first transistor 1 becomes Vg1-VIN=0V, and the first transistor 1 becomes an off state. The second gate voltage control unit 11 applies a gate voltage Vg2 determined as follows to the gate of the second transistor 2. That is, the gate voltage Vg2 of the second transistor is determined so as to satisfy the potential difference between the gate of the second transistor 2 and the output terminal 400, that is, (Vg2-VOUT)<4V, (Vg2-VN1)>Vth, and Vg1-VN1<4V. For example, if Vg2=3.5V and VN1=3.5V, then Vg1-VN1=3.5V and Vg2-VN1=0V are obtained, so the above conditions can be satisfied. In addition, Vth is the threshold voltage of the first transistor 1 and the second transistor 2.

[0037] In the switch circuit 100 of the present embodiment, when the switch circuit 100 is in the off state, even if the output voltage VOUT changes from 7V to 0V, a potential difference of 3.5V or more is not generated between any two terminals of the first transistor 1 and the second transistor 2 of the switch circuit 100, thereby ensuring the reliability of the transistors.

[0038] Figure 2 FIG. 1 is a diagram showing a specific circuit example of the switch circuit 100 according to the first embodiment. Figure 1 In addition to the components shown, the switch circuit 100 further includes a bias voltage generating circuit 500 and a control circuit 501. However, the bias voltage generating circuit 500 and the control circuit 501 are not necessarily provided in the switch circuit 100, and may be provided outside the switch circuit 100.

[0039] The first gate voltage control unit 10 outputs, as the gate voltage Vg1, to the gate of the first transistor 1 a voltage obtained by dividing the voltage between the first input terminal 401 and the reference voltage terminal 600 or a high voltage input to the first input terminal 401. Therefore, the first gate voltage control unit 10 includes a control transistor 301 that controls whether to output a divided voltage obtained by dividing the high voltage VIN1 input to the first input terminal 401 by voltage-dividing resistors R10 and R11 or to output the high voltage input to the first input terminal 401. Since the high voltage VIN1 input to the first input terminal 401 exceeds the withstand voltage of the transistor used in the first gate voltage control unit 10, a structure is adopted in which the control transistor 300 and the control transistor 301 are connected in series and the potential difference between the respective terminals of the control transistors 300 and 301 does not exceed the withstand voltage of the transistor.

[0040] The control circuit 501 operates by receiving a power supply voltage (e.g., 3.3 V) supplied to a SoC (System on Chip) equipped with the switch circuit 100. The bias voltage generation circuit 500 outputs a divided voltage (e.g., 4 V) obtained by dividing the voltage between the first input terminal 401 and the reference voltage terminal 600 by a resistor divider. The reference voltage terminal 600 is maintained at the same potential as the ground potential of the SoC, for example.

[0041] The second gate voltage control unit 11 outputs, as the gate voltage Vg2, either a voltage obtained by dividing the voltage between the common node N1 and the reference voltage terminal 600 or a voltage of the common node N1 to the gate of the second transistor 2. Therefore, the second gate voltage control unit 11 includes a control transistor 303, which controls whether to output a divided voltage obtained by dividing the voltage VN1 of the common node N1 by the voltage-dividing resistors R20 and R21 or to output the voltage VN1 of the common node N1. Since the voltage VN1 of the common node N1 may exceed the withstand voltage of the transistor used in the second gate voltage control unit 11, a structure is adopted in which the control transistor 302 and the control transistor 303 are connected in series, and the potential difference between the terminals of the control transistors 302 and 303 does not exceed the withstand voltage of the transistor.

[0042] The first voltage divider circuit 12 is composed of two voltage divider resistors R1 and R2 connected in series between the first input terminal 401 and the reference voltage terminal 600. The voltage divider resistors R1 and R2 are examples of the first resistance element and the second resistance element, respectively. The connection point of the voltage divider resistors R1 and R2 is connected to the common node N1. The first voltage divider circuit 12 supplies a divided voltage obtained by dividing the high voltage VIN1 input to the first input terminal 401 by the voltage divider resistors R1 and R2 to the common node N1 of the first transistor 1 and the second transistor 2.

[0043] Now, assuming that the input high voltage = 7V, the SoC power supply voltage = 3.3V, the voltage of the reference voltage terminal 600 = the SoC ground terminal = 0V, and the transistor withstand voltage = 4V, the operating state of the switch circuit 100 is described below.

[0044] When the first transistor 1 and the second transistor 2 are turned on, the control circuit 501 outputs a high level (e.g., 3.3 V). As a result, the control transistors 301 and 303 are turned on, and the voltage dividing resistors R10 and R11 and R20 and R21 of the first gate voltage control unit 10 and the second gate voltage control unit 11 are connected to the reference voltage terminal 600. Therefore, the first gate voltage control unit 10 outputs, as the gate voltage Vg1, a divided voltage obtained by dividing the high voltage input to the first input terminal 401 with the voltage dividing resistors R10 and R11 to the gate of the first transistor 1. As a result, the first transistor 1 is turned on. At this time, Vg1 = VIN1 × {R11 / (R10 + R11)}. In addition, the voltage dividing resistors R10 and R11 are set to have a resistance value such that (Vg1 - VIN1) < Vth and |Vg1 - VIN1| < 4V. Similarly, the second gate voltage control unit 11 outputs, as the gate voltage Vg2, a divided voltage obtained by dividing the voltage VN1 of the common node N1 with the voltage dividing resistors R20 and R21 to the gate of the second transistor 2. As a result, the second transistor 2 is turned on. At this time, Vg2 = VN1 × {R21 / (R20 + R21)}. In addition, the voltage dividing resistors R20 and R21 are set to have a resistance value such that (Vg2 - VN1) < Vth and |Vg2 - VN1| < 4V.

[0045] In addition, by setting the resistance values of the voltage dividing resistors R1 and R2 to be 1000 times or more the on-resistance values of the first transistor 1 and the second transistor 2, when the first transistor 1 is in the on state, the voltage of the common node N1 (VN1) is substantially equal to the high voltage VIN1 of the first input terminal 401.

[0046] On the other hand, when the first transistor 1 and the second transistor 2 are turned off, the control circuit 501 outputs a low level, i.e., the same voltage as the voltage of the reference voltage terminal 600 (e.g., the ground voltage 0V of the SoC). As a result, the control transistors 301 and 303 are turned off, and the voltage dividing resistors R10 and R11 and R20 and R21 of the first gate voltage control unit 10 and the second gate voltage control unit 11 are not connected to the reference voltage terminal 600. Therefore, the first gate voltage control unit 10 outputs, as the gate voltage Vg1, a voltage having the same potential as the high voltage VIN1 input to the first input terminal 401 to the gate of the first transistor 1. As a result, the first transistor 1 is turned off.

[0047] The first voltage divider circuit 12 is always connected between the first input terminal 401 and the reference voltage terminal 600 regardless of the output state of the control circuit 501. When the first transistor 1 is in the off state, the divided voltage VN1 provided by the voltage divider resistors R1 and R2 becomes a voltage obtained by dividing the voltage between the first input terminal 401 and the reference voltage terminal 600 by the voltage divider resistors R1 and R2. The second gate voltage control unit 11 is connected between the output terminal (i.e., the common node N1) of the first voltage divider circuit 12 and the reference voltage terminal 600. When the control transistor 303 is in the off state, VN1=VIN1×{R2 / (R1+R2)} is output as the gate voltage Vg2 to the gate of the second transistor 2. That is, the output voltage Vg2 of the second gate voltage control unit 11 is VN1. Thus, the voltage at the source terminal of the second transistor 2 (i.e., the voltage VN1 at the common node N1) - the gate voltage of the second transistor 2 (Vg2 voltage) ≈ 0 V, and the second transistor 2 is turned off. In addition, the resistance values ​​of the voltage-dividing resistors R1 and R2 are set so that |VN1-VOUT|<4V is achieved when the second transistor 2 is in the turned-off state.

[0048] As described above, according to the switch circuit 100 of the first embodiment, when the switch circuit 100 is in the off state, the voltage of the common node N1 between the first transistor 1 and the second transistor 2 can be accurately and quickly converged to a desired voltage through the first voltage divider circuit 12. In addition, it is possible to reliably perform control so as not to exceed the withstand voltage of the transistor without being affected by the Vth deviation of the transistor caused by temperature changes and manufacturing deviations.

[0049] As described above, the switching circuit 100 of the present embodiment includes a first input terminal 401, an output terminal 400, and a first circuit 110 for switching whether to output a first voltage input to the first input terminal 401 to the output terminal 400, wherein the first circuit 110 includes a first transistor 1 and a second transistor 2 connected in series between the first input terminal 401 and the output terminal 400, and a first voltage divider circuit 12 for dividing the first voltage and supplying it to a common node N1 between the first transistor 1 and the second transistor 2.

[0050] Thus, the common node N1 between the first transistor 1 and the second transistor 2 is supplied with a divided voltage obtained by dividing the first voltage input to the first input terminal 401 by the first voltage divider circuit 12. Thus, unlike the conventional technology of dividing the power supply voltage, the voltage of the common node N1 between the first transistor 1 and the second transistor 2 can be accurately and quickly converged to a desired voltage. In addition, it is possible to reliably control the transistor so as not to exceed the withstand voltage without being affected by the Vth deviation of the transistor caused by temperature changes and manufacturing deviations. As a result, the reliability of the switch circuit including a plurality of transistors connected in series is improved.

[0051] In addition, the first voltage divider circuit 12 includes a first resistor element (R1) and a second resistor element (R2) connected in series between the first input terminal 401 and the reference voltage, and the connection point between the first resistor element (R1) and the second resistor element (R2) is connected to the common node N1. Thus, the voltage of the common node N1 can be accurately and quickly converged to a desired voltage through simple resistance voltage division.

[0052] (Implementation Method 2)

[0053] Figure 3 FIG. 2 is a diagram showing a configuration example of a switch circuit 200 according to Embodiment 2. Figure 3 In the embodiment, the switch circuit 200 includes: a first input terminal 401 to which a high voltage as an example of a first voltage is input; a second input terminal 402 to which a low voltage as an example of a second voltage is input; an output terminal 400 to selectively output the high voltage input to the first input terminal 401 or the low voltage input to the second input terminal 402; a first circuit 110 as a switch circuit element, which controls the on / off of outputting / not outputting the input high voltage by taking the high voltage as an example of the first voltage as an input; and a second circuit 120 as a switch circuit element, which controls the on / off of outputting / not outputting the input low voltage by taking the low voltage as an example of the second voltage as an input. In addition, in the present embodiment, the low voltage input to the second input terminal 402 is set to a voltage not exceeding the withstand voltage of any one of the third transistor 3 and the fourth transistor 4. The same reference numerals are given to the same components as those in the first embodiment, and their descriptions are omitted.

[0054] The second circuit 120 includes a third transistor 3 and a fourth transistor 4 connected in series, a third gate voltage control unit 13 that controls on / off of the third transistor 3, a fourth gate voltage control unit 14 that controls on / off of the fourth transistor 4, and a second voltage divider circuit 15 that divides the voltage of the output terminal 400. The voltage obtained by the voltage division of the second voltage divider circuit 15 is supplied to a common node N2 as an example of a second node between the third transistor 3 and the fourth transistor 4. In addition, the third gate voltage control unit 13 and the fourth gate voltage control unit 14 do not necessarily have to be provided in the second circuit 120, and may be provided outside the switch circuit 200, for example.

[0055] Figure 4 Yes Figure 3The figure is a table illustrating the states of the switch circuit 200. The output voltage VOUT of the switch circuit 200, the on / off state of the first circuit 110, and the on / off state of the second circuit 120 in each of the three states ("state 1", "state 2", and "state 3") of the switch circuit 200 are shown. In addition, in "state 3", the output terminal 400 of the switch circuit 200 becomes a floating state, and the output voltage VOUT of the switch circuit 200 becomes indefinite ("-" in the figure).

[0056] Figure 5 This is a diagram showing a specific circuit example of the switch circuit 200 according to the second embodiment.

[0057] In the switch circuit 200, the first circuit 110 is connected to the Figure 2 In the switch circuit 200, the second circuit 120 has the same structure as the circuit shown in FIG. Figure 3 In addition to the components shown, the switch circuit 200 also includes a bias generating circuit 502, a control circuit 503, and voltage dividing resistors R31 and R32. However, the bias generating circuit 502, the control circuit 503, and the voltage dividing resistors R31 and R32 are not necessarily provided in the switch circuit 200, and may be provided outside the switch circuit 200.

[0058] In the second circuit 120 , the input terminal is connected to a second input terminal 402 to which a low voltage (a voltage not exceeding the transistor withstand voltage) is input, and the output terminal is connected to the same node as the output terminal 400 of the first circuit 110 .

[0059] The third gate voltage control unit 13 includes a control circuit 504 that receives a power supply voltage (e.g., 3.3 V) of the SoC and outputs a gate voltage Vg3 to the gate of the third transistor 3. The fourth gate voltage control unit 14 outputs a voltage obtained by dividing the voltage between the first input terminal 401 and the reference voltage terminal 600 to the gate of the fourth transistor 4 as a gate voltage Vg4.

[0060] The second voltage divider circuit 15 is connected between the output terminal 400 and the reference voltage terminal 600, and is composed of two voltage divider resistors R3 and R4 connected in series. The voltage divider resistors R3 and R4 are examples of the third resistor element and the fourth resistor element, respectively. The connection point of the voltage divider resistors R3 and R4 is connected to the common node N2. The second voltage divider circuit 15 divides the voltage between the output terminal 400 and the reference voltage terminal 600 by the voltage divider resistors R3 and R4, and supplies the obtained divided voltage VN2 to the common node N2 between the third transistor 3 and the fourth transistor 4.

[0061] The switch circuit 200 is as follows Figure 4As shown, three states can be obtained through the combination of the on / off states of the first circuit 110 and the second circuit 120. Hereinafter, it is assumed that the high voltage VIN1 = 7V input to the first input terminal 401, the low voltage VIN2 = 0.5V input to the second input terminal 402, the SoC power supply voltage = 3.3V, the voltage of the reference voltage terminal 600 = the SoC ground terminal = 0V, and the transistor breakdown voltage = 4V, and the circuit operations in each of the three states 1 to 3 shown will be described. Figure 4 The circuit operations in each of the three states 1 to 3 shown.

[0062] In Figure 4 In the state 1 shown, the first circuit 110 is in the on state (i.e., the first transistor 1 and the second transistor 2 are in the conducting state), and the second circuit 120 is in the off state (i.e., the third transistor 3 and the fourth transistor 4 are in the cutoff state).

[0063] Regarding the conducting states of the first transistor 1 and the second transistor 2, since they are the same as the conducting states of the first transistor 1 and the second transistor 2 of the Figure 2 switching circuit 100, the detailed operation description thereof is omitted.

[0064] In order to make the third transistor 3 and the fourth transistor 4 in the cutoff state, the control circuits 503 and 504 output the same voltage as the reference voltage terminal 600 (for example, the ground voltage 0V of the SoC). In addition, when the voltage input to the third transistor 3 is below the breakdown voltage, it can also be controlled by the same potential as the power supply voltage of the SoC. Since the control circuit 504 outputs the same voltage as the reference voltage terminal 600 to the gate of the third transistor 3, (Vg3 - VIN2) < Vth, and the third transistor 3 becomes in the cutoff state. Here, Vth in this embodiment is the threshold voltage of the third transistor 3 and the fourth transistor 4.

[0065] Next, the output voltage of the fourth gate voltage control unit 14 (i.e., the gate voltage Vg4 of the fourth transistor 4) will be described. When the first circuit 110 is in the ON state, the output voltage VOUT = VIN1, and the high voltage VIN1 input to the first input terminal 401 is output as the output voltage VOUT. Therefore, it is necessary to keep the fourth transistor 4 in the cut-off state while a high voltage VIN1 is applied to the drain terminal of the fourth transistor 4. Thus, the fourth gate voltage control unit 14 generates the gate voltage Vg4 using the high voltage VIN1 input to the first input terminal 401. Specifically, since the control transistor 305 of the fourth gate voltage control unit 14 is in the cut-off state, a voltage obtained by dividing the high voltage VIN1 input to the first input terminal 401 with the voltage dividing resistors R31 and R32 is output as the gate voltage Vg4. At this time, the voltages of VIN2, Vg3, Vg4, the voltage VN2 at the common node N2, and VOUT must respectively satisfy the relationships of |VOUT - Vg4| < 4V, (Vg4 - VN2) < Vth, |VOUT - VN2| < 4V, |VN2 - Vg3| < 4V, and |VN2 - VIN2| < 4V. In addition, the voltages of VN2 and Vg4 can be calculated as VN2 = VOUT × {R4 / (R3 + R4)} and Vg4 = VIN1 × {R32 / (R31 + R32)}, respectively. For example, if it is designed such that VN2 = 3.0V and Vg4 = 3.0V, the above five relational expressions can be satisfied, and the fourth transistor 4 can be made into the cut-off state. In this way, by generating the gate voltage Vg4 of the fourth transistor 4 and the voltage VN2 of the common node N2 between the third transistor 3 and the fourth transistor 4 from the high voltage VIN1 input to the first input terminal 401 and the output voltage VOUT, respectively, reliable control not exceeding the breakdown voltage of the transistor connected at the boundary between the high voltage and the low voltage can be achieved, and the reliability of the switching circuit can be ensured.

[0066] In Figure 4 the state 2 shown, the first circuit 110 is in the OFF state (i.e., the first transistor 1 and the second transistor 2 are in the cut-off state), and the second circuit 120 is in the ON state (i.e., the third transistor 3 and the fourth transistor 4 are in the conducting state).

[0067] Regarding the cut-off state of the first transistor 1 and the second transistor 2, since it is the same as the cut-off state of the first transistor 1 and the second transistor 2 of the Figure 2 switching circuit 100, the detailed description of its operation is omitted.

[0068] To turn on the third transistor 3 and the fourth transistor 4, the control circuits 503 and 504 output an H level, that is, a voltage equal to the SoC power supply voltage (eg, 3.3 V). As a result, (Vg3-VIN2)>Vth, so the third transistor 3 turns on.

[0069] Next, the output voltage of the fourth gate voltage control unit 14 (i.e., the gate voltage Vg4 of the fourth transistor 4) is described. Since the fourth gate voltage control unit 14 controls the transistor 305 to be in the on state, Vg4 = VIN1 × {(R32 / / R33) / {R31+(R32 / / R33)}} (in addition, R32 / / R33 = R32 × R33 / (R32+R33)) is output to the gate of the fourth transistor 4 as the gate voltage Vg4. At this time, if (Vg4-VIN2)>Vth, |Vg4-VIN2|<4V, the fourth transistor is in the on state, and the output voltage VOUT = VIN2. In addition, by setting the resistance values ​​of the voltage-dividing resistors R3 and R4 of the second voltage-dividing circuit 15 to more than 1000 times the on-resistance values ​​of the third transistor 3 and the fourth transistor 4, when the fourth transistor 4 is in the on state, the voltage VN2 of the common node N2 is substantially equal to the voltage of the second input terminal 402.

[0070] exist Figure 4 In the state 3 shown, the first circuit 110 is in the disconnected state (i.e., the first transistor 1 and the second transistor 2 are in the off state), and the second circuit 120 is in the disconnected state (i.e., the third transistor 3 and the fourth transistor 4 are in the off state). In this state 3, the output terminal 400 of the switch circuit 200 is in the floating state.

[0071] The details of the disconnection state of the first circuit 110 are as follows: Figure 2 The first transistor 1 and the second transistor 2 of the switch circuit 100 are the same as the off state. On the other hand, the details of the off state of the second circuit 120 are the same as the off state of the second circuit 120 in the state 1 of the switch circuit 200 (that is, the off state of the third transistor 3 and the fourth transistor 4). Therefore, the detailed operation description of the first circuit 110 and the second circuit 120 is omitted.

[0072] As described above, according to the switch circuit 200 of the second embodiment, even in the case where a switch circuit that outputs a high voltage and a low voltage from the same terminal is constructed, when the switch circuit element is in the off state, the voltage of the common node N1 between the first transistor 1 and the second transistor 2 and the voltage of the common node N2 between the third transistor 3 and the fourth transistor 4 can be accurately and quickly converged to a desired voltage. In addition, it is possible to reliably control not to exceed the withstand voltage of the transistor without being affected by the Vth deviation of the transistor caused by temperature changes and manufacturing deviations, and it is possible to provide a switch circuit that satisfies the reliability of the transistor and can switch between high voltage and low voltage.

[0073] As described above, the switch circuit 200 of this embodiment further includes a second input terminal 402 and a second circuit 120 for switching whether the second voltage input to the second input terminal 402 is output to the output terminal 400, relative to the switch circuit 100 of embodiment 1. The second circuit 120 includes a third transistor 3 and a fourth transistor 4 connected in series between the second input terminal 402 and the output terminal 400, and a second voltage divider circuit 15 for dividing the voltage of the output terminal 400 and supplying it to the common node N2 between the third transistor 3 and the fourth transistor 4.

[0074] Thus, the first voltage input to the first input terminal 401 or the second voltage input to the second input terminal 402 can be selectively output from the output terminal 400. In addition, the divided voltage obtained by dividing the voltage of the output terminal 400 by the second voltage divider circuit 15 is supplied to the common node N2 between the third transistor 3 and the fourth transistor 4. Thus, unlike the conventional technology of dividing the power supply voltage, the voltage of the common node N2 between the third transistor 3 and the fourth transistor 4 can be accurately and quickly converged to a desired voltage. In addition, it is possible to reliably control the transistor so as not to exceed the withstand voltage without being affected by the Vth deviation of the transistor caused by temperature changes and manufacturing deviations. As a result, a switch circuit with improved reliability that includes a plurality of switch circuit elements and selectively outputs one of two or more input voltages is realized.

[0075] In addition, the second voltage divider circuit 15 includes a third resistor element (R3) and a fourth resistor element (R4) connected in series between the output terminal 400 and the reference voltage, and the connection point between the third resistor element (R3) and the fourth resistor element (R4) is connected to the common node N2. Thus, the voltage of the common node N2 can be accurately and quickly converged to a desired voltage through simple resistance voltage division.

[0076] In addition, a high voltage exceeding the maximum rating of at least one of the first transistor 1 and the second transistor 2 is input to the first input terminal 401, a low voltage not exceeding the maximum rating of either the third transistor 3 or the fourth transistor 4 is input to the second input terminal 402, and the output terminal 400 selectively outputs the high voltage input to the first input terminal 401 and the low voltage input to the second input terminal 402.

[0077] Thus, even if a high voltage exceeding the maximum rating of the transistor is input, the potential difference between any two terminals of the transistor is below the maximum rating, thereby realizing a switch circuit that selectively outputs a high voltage input to the first input terminal 401 and a low voltage input to the second input terminal 402.

[0078] (Implementation 3)

[0079] Figure 6 is a diagram showing a specific circuit example of the switch circuit 210 according to the third embodiment. The switch circuit 210 is equivalent to Figure 5 A variation of the switch circuit 200 of Embodiment 2 shown. More specifically, the switch circuit 210 has the following structure: in the switch circuit 200, the two transistors connected in series (the first transistor 1 and the second transistor 2) are replaced by three transistors connected in series, and the two transistors connected in series (the third transistor 3 and the fourth transistor 4) are replaced by three transistors connected in series.

[0080] Specifically, the switch circuit 210 includes: a first input terminal 401 to which a high voltage is input; a second input terminal 402 to which a low voltage is input; an output terminal 400 to output the high voltage input to the first input terminal 401 or the low voltage input to the second input terminal 402; a first circuit 110a as a switch circuit element, which controls the on / off of outputting / not outputting the input high voltage with a high voltage as input; and a second circuit 120a as a switch circuit element, which controls the on / off of outputting / not outputting the input low voltage with a low voltage as input. The same reference numerals are given to the same components as those in Embodiment 2, and their descriptions are omitted.

[0081] The first circuit 110a includes a first transistor 1, a second transistor 2 and a fifth transistor 5 connected in series, a first gate voltage control unit 10a for controlling the on / off state of the first transistor 1, a second gate voltage control unit 11a for controlling the on / off state of the second transistor 2, a fifth gate voltage control unit 16 for controlling the on / off state of the fifth transistor 5, a first voltage divider circuit 12a, bias voltage generating circuits 500 and 500a, and a control circuit 501. The first voltage divider circuit 12a divides the high voltage input to the first input terminal 401, and supplies the obtained two divided voltages to a common node N3 as an example of a third node between the second transistor 2 and the fifth transistor 5 and a common node N1, respectively.

[0082] In addition, the first circuit 110a of the present embodiment has a structure in which a fifth transistor 5 is added to the subsequent stage of the first transistor 1 and the second transistor 2 of the first circuit 110 of the second embodiment. However, the fifth transistor 5 may be connected to the previous stage of the first transistor 1 and the second transistor 2 or between them. That is, the first circuit 110a of the present embodiment has a structure in which three transistors are connected in series, unlike the second embodiment in which two transistors are connected in series.

[0083] The fifth transistor 5 is a PMOS transistor in the present embodiment, similarly to the first transistor 1 and the second transistor 2 .

[0084] The bias voltage generating circuit 500 outputs a divided voltage (e.g., a divided voltage of 2 / 3 of the high voltage) obtained by dividing the voltage between the first input terminal 401 and the reference voltage terminal 600 by a resistor voltage divider. The bias voltage generating circuit 500a outputs a divided voltage (e.g., a divided voltage of 1 / 3 of the high voltage) obtained by dividing the voltage between the first input terminal 401 and the reference voltage terminal 600 by a resistor voltage divider.

[0085] The first gate voltage control unit 10a is a circuit for controlling on / off of the first transistor 1, and has a structure in which the two control transistors 300 and 301 connected in series in the first gate voltage control unit 10 of the second embodiment are replaced with three control transistors 300, 306 and 301 connected in series.

[0086] The second gate voltage control unit 11a is a circuit for controlling on / off of the second transistor 2, and has a structure in which the two control transistors 302 and 303 connected in series in the second gate voltage control unit 11 of the second embodiment are replaced with three control transistors 302, 307 and 303 connected in series.

[0087] The fifth gate voltage control unit 16 has basically the same structure as the second gate voltage control unit 11a, that is, the fifth gate voltage control unit 16 is composed of voltage dividing resistors R20a and R20b connected in series between the common node N3 and the reference voltage terminal 600, and control transistors 302a, 308, and 303a.

[0088] The first voltage divider circuit 12a is composed of three voltage divider resistors R1a, R2a and R2b connected in series between the first input terminal 401 and the reference voltage terminal 600. The connection point of the voltage divider resistors R1a and R2a is connected to the common node N1 and one end of the second gate voltage control unit 11a (i.e., one end of the voltage divider resistor R20). In addition, the connection point of the voltage divider resistors R2a and R2b is connected to the common node N3 and one end of the fifth gate voltage control unit 16 (i.e., one end of the voltage divider resistor R20a).

[0089] The second circuit 120a comprises: a third transistor 3, a sixth transistor 6 and a fourth transistor 4 connected in series, a third gate voltage control unit 13 for controlling the on / off state of the third transistor 3, a fourth gate voltage control unit 14a for controlling the on / off state of the sixth transistor 6 and the fourth transistor 4, a second voltage divider circuit 15a, a bias voltage generating circuit 502 and a control circuit 503, wherein the second voltage divider circuit 15a divides the voltage output to the output terminal 400, and supplies the obtained two divided voltages to a common node N4 as an example of a fourth node between the third transistor 3 and the sixth transistor 6 and a common node N2, respectively.

[0090] In addition, the second circuit 120a of this embodiment has a structure in which a sixth transistor 6 is added between the third transistor 3 and the fourth transistor 4 of the second circuit 120 of the second embodiment. However, the sixth transistor 6 may be connected before or after the third transistor 3 and the fourth transistor 4. That is, the second circuit 120a of this embodiment has a structure in which three transistors are connected in series, unlike the second embodiment in which two transistors are connected in series.

[0091] The sixth transistor 6 is an NMOS transistor in the present embodiment, similarly to the third transistor 3 and the fourth transistor 4 .

[0092] The fourth gate voltage control unit 14a is a circuit for controlling the on / off of the fourth transistor 4 and the sixth transistor 6, and basically has the same structure as the fourth gate voltage control unit 14 of the second embodiment. However, in addition to the function of the fourth gate voltage control unit 14 of the second embodiment, the fourth gate voltage control unit 14a has a function of applying the voltage applied to the gate of the control transistor 304 as the gate voltage Vg6 to the gate of the sixth transistor 6 as it is. In addition, in this embodiment, the gate voltage Vg6 can be the same voltage regardless of whether the second circuit 120a is turned on or off, and is the same voltage as the bias voltage applied to the gate voltage of the control transistor 304, so the voltage applied to the gate of the control transistor 304 is applied to the gate of the sixth transistor as the gate voltage Vg6 as it is. However, when the number of transistors connected in series in the second circuit 120a is different from that in the present embodiment, such as four or five, instead of three, or when the voltages of the high voltage VIN1 and the low voltage VIN2 are different from those in the present embodiment, the voltage applied to the gate of the control transistor 304 is not necessarily applied to the gate of the sixth transistor as the gate voltage Vg6. In such a case, a gate control unit is provided that outputs an appropriate voltage required for turning on / off each transistor connected in series as a gate voltage.

[0093] The second voltage divider circuit 15a is composed of three voltage divider resistors R3a, R4a and R4b connected in series between the output terminal 400 and the reference voltage terminal 600. The connection point between the voltage divider resistors R3a and R4a is connected to the common node N1, and the connection point between the voltage divider resistors R4a and R4b is connected to the common node N4.

[0094] The switch circuit 210 of the present embodiment configured as described above operates as follows. Figure 4 The switch circuit 210 is in the same state as the second embodiment shown in the figure. That is, when the first circuit 110a is in the on state and the second circuit 120a is in the off state, the switch circuit 210 is in the state 1, and the high voltage input to the first input terminal 401 is output from the output terminal 400. On the other hand, when the first circuit 110a is in the off state and the second circuit 120a is in the on state, the switch circuit 210 is in the state 2, and the low voltage input to the second input terminal 402 is output from the output terminal 400. Furthermore, when the first circuit 110a is in the off state and the second circuit 120a is in the off state, the switch circuit 210 is in the state 3, and the output terminal 400 is in the floating state.

[0095] In the first circuit 110a, the control circuit 501 outputs an H level when the first circuit 110a is turned on, and outputs an L level when the first circuit 110a is turned off, similarly to Embodiment 2. When the first circuit 110a is turned off, which is a case where the withstand voltage of the transistor may become a problem, the voltages of the terminals of the transistors constituting the first circuit 110a are as follows.

[0096] That is, the high voltage (e.g., 7.5V) input to the first input terminal 401 is applied to the source of the first transistor 1, the gate voltage Vg1 (e.g., 7.5V) is applied from the first gate voltage control unit 10a to the gate of the first transistor 1, and the divided voltage VN1 (e.g., 5V) is applied from the first voltage divider circuit 12a to the drain of the first transistor 1. As a result, the first transistor 1 is maintained in the off state, and a potential difference between any terminals does not exceed the withstand voltage (e.g., 3V).

[0097] Furthermore, the divided voltage VN1 (e.g., 5V) from the first voltage divider circuit 12a is applied to the source of the second transistor 2, the gate voltage Vg2 (e.g., 5V) is applied from the second gate voltage control unit 11a to the gate of the second transistor 2, and the divided voltage VN3 (e.g., 2.5V) is applied from the first voltage divider circuit 12a to the drain of the second transistor 2. As a result, the second transistor 2 is maintained in the off state, and a potential difference between any terminals does not exceed the withstand voltage (e.g., 3V).

[0098] Furthermore, the divided voltage VN3 (e.g., 2.5V) is applied to the source of the fifth transistor 5 from the first voltage divider circuit 12a, the gate voltage Vg5 (e.g., 2.5V) is applied to the gate of the fifth transistor 5 from the fifth gate voltage control unit 16, and the drain of the fifth transistor 5 is in a floating state or is applied with the output voltage (e.g., 0.5V) of the second circuit 120a. As a result, the fifth transistor 5 is maintained in an off state, and a potential difference not exceeding the withstand voltage (e.g., 3V) is formed between any of the terminals.

[0099] In addition, since the three control transistors constituting the first gate voltage control unit 10a, the second gate voltage control unit 11a and the fifth gate voltage control unit 16 are connected in series between the high voltage (e.g., 7.5V) input to the first input terminal 401 and the reference voltage terminal 600, the potential difference between any terminals of each control transistor does not exceed the withstand voltage (e.g., 3V).

[0100] In the second circuit 120a, the control circuits 503 and 504 output an H level when the second circuit 120a is turned on, and output an L level when the second circuit 120a is turned off, similarly to Embodiment 2. When the second circuit 120a is turned off, which is a case where the withstand voltage of the transistor may become a problem, and the first circuit 110a is turned on, the voltages of the terminals of the transistors constituting the second circuit 120a are as follows.

[0101] That is, the voltage of the output terminal 400 (e.g., 7.5V) is applied to the drain of the fourth transistor 4, the gate voltage Vg4 (e.g., 5V) is applied to the gate of the fourth transistor 4 from the fourth gate voltage control unit 14a, and the divided voltage VN2 (e.g., 5V) is applied to the source of the fourth transistor 4 from the second voltage divider circuit 15a. As a result, the fifth transistor 5 is maintained in an off state, and a potential difference between any terminals does not exceed the withstand voltage (e.g., 3V).

[0102] Furthermore, the divided voltage VN2 (e.g., 5V) is applied to the drain of the sixth transistor 6 from the second voltage dividing circuit 15a, the gate voltage Vg6 (e.g., 2.5V) is applied to the gate of the sixth transistor 6 from the fourth gate voltage control unit 14a, and the divided voltage VN4 (e.g., 2.5V) is applied to the source of the sixth transistor 6 from the second voltage dividing circuit 15a. As a result, the sixth transistor 6 is maintained in an off state, and a potential difference between any terminals does not exceed the withstand voltage (e.g., 3V).

[0103] Furthermore, the divided voltage VN4 (e.g., 2.5V) is applied to the drain of the third transistor 3 from the second voltage divider circuit 15a, the gate voltage Vg3 (e.g., 0V) is applied to the gate of the third transistor 3 from the third gate voltage control unit 13, and the low voltage (e.g., 0.5V) input to the second input terminal 402 is applied to the source of the third transistor 3. As a result, the fifth transistor 5 is maintained in the off state, and a potential difference not exceeding the withstand voltage (e.g., 3V) is formed between any terminals.

[0104] As described above, the switch circuit 210 of this embodiment is relative to the switch circuit 200 of embodiment 2, and the first circuit 110a also includes a fifth transistor 5 connected in series with the first transistor 1 and the second transistor 2 between the first input terminal 401 and the output terminal 400, and the first voltage divider circuit 12a also divides the first voltage and supplies it to the common node N3 between the fifth transistor 5 and the first transistor 1 or the second transistor 2.

[0105] Thus, three transistors are connected in series between the first input terminal 401 and the output terminal 400 , thereby realizing a switch circuit that has a higher withstand voltage and can reliably switch the on and off states.

[0106] In addition, the second circuit 120a also includes a sixth transistor 6 connected in series with the third transistor 3 and the fourth transistor 4 between the second input terminal 402 and the output terminal 400, and the second voltage divider circuit 15a also divides the voltage of the output terminal 400 and supplies it to the common node N4 between the sixth transistor 6 and the third transistor 3 or the fourth transistor 4.

[0107] Thus, three transistors are connected in series between the second input terminal 402 and the output terminal 400 , thereby realizing a switch circuit that has a higher withstand voltage and can reliably selectively output two input voltages.

[0108] In addition, in the present embodiment, three transistors are provided in series between the first input terminal 401 and the output terminal 400 in the first circuit 110a, and three transistors are provided in series in each of the gate voltage control units (10a, 11a, 16), but the number of transistors connected in series is not limited thereto, and may be 4 or more. The number may be appropriately determined in consideration of the maximum voltage input to the switch circuit and the withstand voltage of the transistor so that the voltage applied between the terminals of each transistor does not exceed the withstand voltage.

[0109] (Implementation 4)

[0110] Figure 7 The figure shows a configuration example of an image sensor 70 as an imaging device according to Embodiment 4, which is equipped with a switch circuit according to any of Embodiments 1 to 3 (in this embodiment, the switch circuit 200 according to Embodiment 2). The image sensor 70 is a semiconductor integrated circuit of one chip (i.e., an image sensor chip), and includes a semiconductor substrate 71 and circuits located on the semiconductor substrate 71 (i.e., a pixel array 50a including a plurality of pixels 50, two horizontal readout circuits 59a and 59b, a vertical scanning circuit 57, and four switch circuits 200).

[0111] Each pixel 50 is composed of a photoelectric conversion unit 60 and a readout circuit (a circuit composed of a selection transistor 61, a detection transistor 62, and a reset transistor 63). The photoelectric conversion unit 60 is an element that can change its sensitivity depending on a voltage applied from the outside, such as an organic imaging element. The photoelectric conversion unit 60 has a layer structure in which a photoelectric conversion layer is sandwiched by two electrodes facing each other (i.e., an upper electrode as an example of a first electrode layer and a lower electrode as an example of a second electrode layer). The upper electrode of each pixel 50 forms a common electrode layer and is connected to a sensitivity control voltage line 56. The lower electrode of each pixel 50 is connected to a charge accumulation node 64 of each pixel. In each pixel 50, the signal charge generated by the photoelectric conversion unit 60 is accumulated in the charge accumulation node 64, and in the pixel where the selection transistor 61 is in the on state, the charge signal is read out by the detection transistor 62 whose drain is connected to the power supply line 52. The charge signal read out from the pixel is read out to the outside via the vertical signal line 58 and the horizontal readout circuit 59a or 59b. The sensitivity control voltage line 56 is connected to the output terminal 400 of the switch circuit 200 via the terminal 51. The first input terminal 401 and the second input terminal 402 of the switch circuit 200 are provided as external connection terminals of the image sensor chip and are connected to a voltage generating circuit outside the image sensor chip.

[0112] The selection transistor 61 is turned on / off by a control signal for each row output from the vertical scanning circuit 57 via the address control line 54. The drain of the reset transistor 63 is connected to the reset voltage line 53, and is turned on / off by a control signal for each row output from the vertical scanning circuit 57 via the reset control line 55, thereby resetting the charge storage node 64.

[0113] like Figure 7 As shown in the figure, in this embodiment, the image sensor 70 has four switch circuits 200 of Embodiment 2, and the switch circuits 200 are provided at the four corners of the image sensor chip. That is, the semiconductor substrate 71 has a rectangular shape in a plan view. The four switch circuits 200 are respectively located near the four corners of the semiconductor substrate 71 in a plan view. In addition, the vicinity of the four corners refers to an area close to each of the four corners of the rectangle, and more specifically, a position closer to the corner than the center of each of the four sides constituting the rectangle.

[0114] In addition, the required number of switch circuits 200 is not limited to 4, and can be appropriately determined according to the pixel array area of ​​the image sensor chip. In addition, the switch circuit of the image sensor 70 is not limited to the switch circuit 200 of the second embodiment, and can also be the switch circuit 100 of the first embodiment or the switch circuit 210 of the third embodiment, or a mixture of the switch circuits of the first to third embodiments.

[0115] Figure 8Yes means Figure 7 The timing chart of the operation example of the image sensor 70 shown in the figure. The timing chart shown here shows the relationship between the switch control using the switch circuit 200 and the exposure and readout of the image sensor chip. In this figure, Vss represents the timing of the fall (or rise) of the vertical synchronization signal, and Hss represents the timing of the fall (or rise) of the horizontal synchronization signal. The waveform represented by V1 for the H level and V2 for the L level represents the voltage applied from the switch circuit 200 to the upper electrode of the photoelectric conversion unit 60. The strip-shaped figure shows the exposure state of each row of the pixel array 50a. For simplicity, the operation example in the case where the pixel array 50a is composed of 8 rows (R0 to R7) of pixels 50 is described.

[0116] Focus on Figure 8 For example, in row R0, the hollow rectangle schematically represents the exposure period, the gray (dot pattern) rectangle schematically represents the non-exposure period, and the oblique line rectangle schematically represents the pixel readout period. In addition, it is assumed that the photoelectric conversion sensitivity is high when a high voltage is applied to the upper electrode of the photoelectric conversion unit 60, and the photoelectric conversion sensitivity becomes low when a low voltage is applied. Specifically, it is assumed that the photoelectric conversion is performed at V1 = 7V, and the photoelectric conversion sensitivity decreases at V2 = 0.5V, and the photoelectric conversion does not occur substantially.

[0117] The period from time t0 to t1 is called the 1H period, which means the period from when a row is selected to when the next row is selected, and the period from t0 to t15 from when a row is selected to when the row is read out again is called the 1V period. Figure 8 In the example of , a 1V period is equivalent to 1 frame. During the 1V period, the image sensor 70 performs exposure + pixel signal reading. For example, during the period from t0 to t7, a high voltage V1 is applied to the photoelectric conversion unit 60. At this time, the photoelectric conversion unit 60 outputs a signal charge proportional to the amount of light incident on the pixel. Then, during the period from t7 to t15, a low voltage V2 is applied to the photoelectric conversion unit 60. At this time, since the photoelectric conversion unit 60 hardly performs photoelectric conversion, the voltage of the charge accumulation node 64 of each pixel 50 does not change. That is, t0 to t7 is the exposure period, and t7 to t15 is the exposure stop period, and the exposure of the entire pixel array 50a covered by the photoelectric conversion unit 60 can be controlled. During the exposure stop period, rows R0 to R7 can be read out in sequence, which is a function equivalent to a global shutter. By using the switch circuit 200 of the present invention, an image sensor 70 that switches the sensitivity characteristics of the photoelectric conversion unit 60 can be realized without providing an external switch circuit or using a high-voltage transistor in the image sensor chip.

[0118] As described above, the image sensor 70 of embodiment 4 includes a semiconductor substrate 71, a pixel array 50a including a plurality of pixels 50 arranged on the semiconductor substrate 71, and a switching circuit 200 located on the semiconductor substrate 71, the plurality of pixels 50 respectively include a photoelectric conversion unit 60 including a first electrode layer, a second electrode layer and a photoelectric conversion layer sandwiched by the first electrode layer and the second electrode layer, the first electrode layers respectively included in the plurality of pixels 50 form a common electrode layer, and the output terminal 400 of the switching circuit 200 is connected to the common electrode layer.

[0119] Thus, an output voltage is applied to the common electrode layer by a highly reliable switch circuit that outputs a high voltage using a low withstand voltage transistor, thereby realizing a highly reliable image sensor 70 that can change the sensitivity of photoelectric conversion depending on the voltage applied to the photoelectric conversion unit 60.

[0120] In addition, the image sensor 70 includes a plurality of switch circuits 200, and the output terminals 400 of the plurality of switch circuits 200 are connected to the common electrode layer. For example, the image sensor 70 includes four switch circuits 200, the semiconductor substrate 71 has a rectangular shape in a plan view, and the four switch circuits 200 are respectively located near the four corners of the semiconductor substrate 71 in a plan view.

[0121] Thus, since voltage is supplied to four locations of the common electrode layer from the switching circuit, voltage drop in the common electrode layer is suppressed, and deviations in the value and timing of the voltage applied to the photoelectric conversion unit 60 of each pixel 50 are suppressed, thereby realizing a highly reliable image sensor 70.

[0122] The switch circuit and the camera device of the present invention are described above based on Embodiments 1 to 4, but the present invention is not limited to these embodiments. As long as it does not deviate from the main purpose of the present invention, various forms after deformation thought of by those skilled in the art to each embodiment, and other forms constructed by combining some of the constituent elements of each embodiment are also included in the scope of the present invention.

[0123] In the above-mentioned first to third embodiments, a structure using a resistor element to generate a divided voltage potential is exemplified, but a structure in which a divided voltage potential is generated by control other than the resistor element may be used.

[0124] In addition, in the above-mentioned embodiments 1 to 3, the first circuit 110 and 110a are composed of two or more PMOS transistors connected in series, and the second circuit 120 and 120a are composed of two or more NMOS transistors connected in series, but depending on the input voltage, it can also be composed of a CMOS type switch using both PMOS and NMOS.

[0125] Furthermore, the bias voltage generating circuits 500 , 500 a , and 502 may output a voltage obtained by dividing a voltage input to the first input terminal 401 , or may output a voltage inside or outside the SoC.

[0126] In addition, all the numbers used in the description of the above-mentioned Embodiments 1 to 4 are exemplified in order to specifically describe the present invention, and the present invention is not limited to the exemplified numbers.

[0127] In addition, the elements of each constituent element shown in the above are all exemplified for the purpose of specifically explaining the disclosure, and are not limited to the elements exemplified in the present invention. In addition, the connection relationship between the constituent elements is exemplified for the purpose of specifically explaining the present invention, and the connection relationship for realizing the functions of the present invention is not limited thereto.

[0128] Industrial Applicability

[0129] The switch circuit of the present invention has the advantages of ensuring reliability by using low-voltage transistors and controlling high voltages, and is useful as a switch circuit that selects and outputs multiple voltages. In addition, it can also be applied to a voltage-controlled switch of an image sensor that needs to apply a potential to a photoelectric conversion layer to change the sensitivity. The camera device of the present invention can be used as a highly reliable image sensor that can change the sensitivity of photoelectric conversion depending on the voltage applied to the photoelectric conversion unit, for example, as an organic image sensor.

[0130] Description of symbols

[0131] 1.1 Transistor

[0132] 2.2nd transistor

[0133] 3. The third transistor

[0134] 4.4th transistor

[0135] 5. 5th Transistor

[0136] 6.6th Transistor

[0137] 10. 10a First gate voltage control unit

[0138] 11. 11a Second gate voltage control unit

[0139] 12.12a The first voltage divider circuit

[0140] 13. 3rd gate voltage control unit

[0141] 14, 14a Fourth gate voltage control unit

[0142] 15.15a Second voltage divider circuit

[0143] 16 5th gate voltage control unit

[0144] N1, N2, N3, N4 common nodes

[0145] R1, R1a, R2, R2a, R2b, R3, R3a, R4, R4a, R4b, R10, R11, R20, R20a, R20b, R21, R31, R32, R33 voltage divider resistor

[0146] 50 pixels

[0147] 50a Pixel Array

[0148] 51 terminal

[0149] 52 Power cord

[0150] 53 Reset voltage line

[0151] 54 address control lines

[0152] 55 Reset control line

[0153] 56 Sensitivity control voltage line

[0154] 57 Vertical scanning circuit

[0155] 58 vertical signal line

[0156] 59a, 59b horizontal readout circuit

[0157] 60 Photoelectric conversion unit

[0158] 61 Select transistor

[0159] 62 Detection transistor

[0160] 63 Reset transistor

[0161] 64 Charge storage nodes

[0162] 70 Image Sensor

[0163] 71 Semiconductor substrate

[0164] 100, 200, 210 switch circuit

[0165] 110, 110a 1st circuit

[0166] 120, 120a Second circuit

[0167] 300, 301, 302, 302a, 303, 303a, 304, 305, 306, 307, 308 control transistor

[0168] 400 Output Terminals

[0169] 401 1st input terminal

[0170] 402 2nd input terminal

[0171] 500, 500a, 502 bias voltage generating circuit

[0172] 501, 503, 504 control circuit

[0173] 600 Reference voltage terminal

Claims

1. A switching circuit, characterized in that: have: 1st input terminal; output terminals; and a first circuit for switching whether to output the first voltage input to the first input terminal to the output terminal; The first circuit comprises: Reference voltage terminal; a first transistor and a second transistor connected in series between the first input terminal and the output terminal; and a first voltage dividing circuit that divides a potential difference between the first input terminal and the reference voltage terminal and supplies the voltage to a first node between the first transistor and the second transistor; The reference voltage terminal is not located on a current path from the first input terminal to the output terminal.

2. The switch circuit according to claim 1, characterized in that: Also available: a second input terminal; and a second circuit for switching whether to output the second voltage input to the second input terminal to the output terminal; The second circuit comprises: a third transistor and a fourth transistor connected in series between the second input terminal and the output terminal; and The second voltage dividing circuit divides the voltage of the output terminal and supplies the divided voltage to a second node between the third transistor and the fourth transistor.

3. The switch circuit according to claim 1 or 2, characterized in that: The first voltage divider circuit includes a first resistor element and a second resistor element connected in series between the first input terminal and a reference voltage; A connection point between the first resistance element and the second resistance element is connected to the first node.

4. The switch circuit according to claim 2, characterized in that: The second voltage dividing circuit includes a third resistor element and a fourth resistor element connected in series between the output terminal and the reference voltage; A connection point between the third resistor and the fourth resistor is connected to the second node.

5. The switch circuit according to claim 2 or 4, characterized in that: A first voltage exceeding a maximum rating of at least one of the first transistor and the second transistor is input to the first input terminal; A second voltage not exceeding a maximum rating of either the third transistor or the fourth transistor is input to the second input terminal; The output terminal outputs the first voltage in a first period, and outputs the second voltage in a second period different from the first period.

6. The switch circuit according to any one of claims 1 to 5, characterized in that: The first circuit further includes a fifth transistor connected in series with the first transistor and the second transistor between the first input terminal and the output terminal; The first voltage dividing circuit further divides the first voltage and supplies the divided voltage to a third node between the fifth transistor and the first transistor or the second transistor.

7. The switch circuit according to claim 2, 4 or 5, characterized in that: The second circuit further includes a sixth transistor connected in series with the third transistor and the fourth transistor between the second input terminal and the output terminal; The second voltage dividing circuit further divides the voltage of the output terminal and supplies the divided voltage to a fourth node between the sixth transistor and the third transistor or the fourth transistor.

8. A camera device, characterized in that: have: Semiconductor substrates; A pixel array, comprising a plurality of pixels arranged on the semiconductor substrate; and The switch circuit according to any one of claims 1 to 7, located on the semiconductor substrate; Each of the plurality of pixels includes a photoelectric conversion portion including a first electrode layer, a second electrode layer, and a photoelectric conversion layer sandwiched by the first electrode layer and the second electrode layer; The first electrode layers respectively provided in the plurality of pixels are electrically connected to each other; The output terminal of the switch circuit is connected to the first electrode layer.

9. The imaging device according to claim 8, wherein: Having a plurality of the above-mentioned switch circuits; The output terminal of each of the plurality of switch circuits is connected to the first electrode layer.

10. The imaging device according to claim 8 or 9, wherein: Having 4 of the above switch circuits; The semiconductor substrate has a rectangular shape in a plan view; The four switch circuits are respectively located near four corners on the semiconductor substrate in the plan view.

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