Field effect transistor circuit, method, device, chip and battery management system

Abstract

The present disclosure provides a field effect transistor circuit, comprising: a field effect transistor, comprising a gate, a source, a drain, a substrate, a first parasitic diode and a second parasitic diode, wherein the first parasitic diode and the second parasitic diode are connected in reverse series, one end of a series circuit of the first parasitic diode and the second parasitic diode is connected to the source, and the other end of the series circuit is connected to the drain, and a connection point of the first parasitic diode and the second parasitic diode is connected to the substrate; and a switch, one end of the switch is connected to the connection point, and the other end of the switch is connected to the source. The present disclosure also provides a control method of a field effect transistor, a charge and discharge control device, a chip, a battery management system, and an electrical device.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a field effect transistor circuit, a control method of a field effect transistor, a charge and discharge control device, a chip, a battery management system, and an electric device. BACKGROUND

[0002] In a battery system, overcharge and overdischarge of a battery not only reduce the service life of the battery, but also can cause a safety accident such as explosion and fire. The battery is, for example, a lithium battery pack.

[0003] Figure 1 A conventional overcurrent detection mode according to the prior art is shown.

[0004] When the battery is normally discharged, the voltage of the output control signal OD and the OC port of the driving unit is usually about VDD, 5V or 15V, and the control signals OD and OC are connected to the gate (G) of the protection MOS transistors M1 and M2, respectively. At this time, M1 and M2 work in the linear region, and the drain (D) and source (S) of M1 and M2 are equivalent to a conduction resistance, and the conduction resistance value is R on .

[0005] The discharge current I dsg flows from the P- terminal to the B- terminal, and the voltage of the P- terminal is higher. When the voltage difference (I dsg *R on ) between the P- terminal and the B- terminal reaches a certain limit value, the voltage of the control signal OD changes from, for example, VDD to VB- (the voltage of the B- terminal), thereby turning off M1 and cutting off the discharge path. The control signal OC can still maintain, for example, the VDD potential, and M2 can still be in the on state.

[0006] Similarly, when the battery is normally charged, the gate voltage of M1 and M2 is VDD. The current flows from the B- terminal to the P- terminal, and the voltage of the P- terminal is lower. When the voltage difference (I chg *R on ) between the B- terminal and the P- terminal reaches a certain limit value, the voltage of the control signal OC changes from, for example, VDD to VB-, thereby turning off M2 and cutting off the charging path. The control signal OD can still maintain, for example, the VDD potential, and M1 can still be in the on state.

[0007] In the circuit structure shown in Figure 1 , during normal charging, the conduction resistance R on of M1 and M2 is in series in the loop of the battery and the external charger, so the power loss P Loss =I chg *[2*R on ] 2This power loss is directly converted into heat generation in the system. Therefore, the temperature rise during system charging due to the heat loss between M1 and M2 is ΔT = P. Loss / (C*m), where C is the specific heat coefficient of the system and m is the mass of the system.

[0008] The safe operating temperature of a lithium battery system is typically around 45°C. Therefore, in order to control the system temperature rise caused by heat dissipation due to the on-resistance of M1 and M2, the maximum value of the charging current I must be controlled. chg(max) =P Loss(max) / ([2*R on ] 2 This reduces the charging current, which will inevitably prolong the system's charging time.

[0009] Similarly, during the discharge process, the on-resistance R of M1 and M2 on The series connection between the battery and the load (R) Load In the circuit, the heat loss P caused by the on-resistance of M1 and M2 is... Loss =I dsg *[2*R on ] 2 This power loss reduces the battery's energy utilization efficiency and limits the maximum discharge current. The heat loss from M1 and M2 during system discharge results in a ΔT = P. Loss / (C*m), where C is the specific heat coefficient of the system and m is the mass of the system. The safe operating temperature of a lithium battery system is typically around 45℃. Therefore, in order to control the system temperature rise caused by the heat dissipation due to the on-resistance of M1 and M2, the maximum value of the charging current I must be controlled. dsg(max) =P Loss(max) / ([2*P on ] 2 This will limit the maximum current that the battery system can output. Summary of the Invention

[0010] To address one of the aforementioned technical problems, this disclosure provides a field-effect transistor circuit, a control method for a field-effect transistor, a charge / discharge control device, a chip, a battery management system, and an electrical device.

[0011] According to one aspect of this disclosure, a field-effect transistor circuit includes:

[0012] A field effect transistor including a gate, a source, a drain, a substrate, a first parasitic diode and a second parasitic diode, wherein the first parasitic diode and the second parasitic diode are connected in reverse series, one end of a series circuit of the first parasitic diode and the second parasitic diode is connected to the source, and the other end of the series circuit is connected to the drain, and a connection point of the first parasitic diode and the second parasitic diode is connected to the substrate; and

[0013] A switch having one end connected to the connection point and the other end connected to the source,

[0014] The field effect transistor is turned on and the switch is turned on so that the source is in communication with the substrate, the field effect transistor is turned off and the switch is turned off so that the source is not in communication with the substrate, and the substrate is in a floating state.

[0015] According to at least one embodiment of the present disclosure, when the field effect transistor is turned on and the switch is turned on so that the source is in communication with the substrate, a conductive channel of the field effect transistor is formed, and when the field effect transistor is turned off and the switch is turned off so that the source is not in communication with the substrate, the conductive channel of the field effect transistor is not formed and the substrate is in a floating state.

[0016] According to at least one embodiment of the present disclosure, the series circuit of the first parasitic diode and the second parasitic diode is configured so that no conductive path is formed through the series circuit between the source and the drain.

[0017] According to at least one embodiment of the present disclosure, the field effect transistor is an NMOS transistor, which is turned on when a gate-source voltage between the gate and the source is greater than a turn-on threshold voltage of the field effect transistor, and which is turned off when the gate-source voltage is less than the turn-on threshold voltage; or

[0018] The field effect transistor is a PMOS transistor, which is turned on when a gate-source voltage between the gate and the source is less than a turn-on threshold voltage of the field effect transistor, and which is turned off when the gate-source voltage is greater than the turn-on threshold voltage.

[0019] According to at least one embodiment of the present disclosure, when the field effect transistor is an NMOS transistor, an anode of the first parasitic diode is connected to an anode of the second parasitic diode, a cathode of the first parasitic diode is connected to the drain, and a cathode of the second parasitic diode is connected to the source; or

[0020] When the field effect transistor is a PMOS transistor, the cathode of the first parasitic diode is connected to the cathode of the second parasitic diode, the anode of the first parasitic diode is connected to the drain, and the anode of the second parasitic diode is connected to the source.

[0021] According to at least one embodiment of the present disclosure, the switch is a NMOS and / or PMOS transistor switch, the gate of the transistor switch is connected to the gate of the field effect transistor, the source of the transistor switch is connected to the connection point, and the drain of the transistor switch is connected to the source of the field effect transistor.

[0022] According to at least one embodiment of the present disclosure, the switch is a transistor, the base of the transistor is connected to the gate of the field effect transistor via a first resistor, the emitter / collector of the transistor is connected to the connection point, and the collector / emitter of the transistor is connected to the source of the field effect transistor.

[0023] According to at least one embodiment of the present disclosure, a second switch is connected between the gate and the drain of the field effect transistor,

[0024] The second switch is configured to ensure that the gate oxide layer of the field effect transistor is not broken down and / or the field effect transistor does not form a conductive channel when the field effect transistor is turned off.

[0025] According to at least one embodiment of the present disclosure, a second switch is connected between the gate and the drain of the field effect transistor, and the second switch is a voltage-resistant diode,

[0026] When the field effect transistor is a NMOS transistor, the anode of the voltage-resistant diode is directly or indirectly connected to the gate of the field effect transistor, and the cathode of the voltage-resistant diode is directly or indirectly connected to the drain of the field effect transistor; or when the field effect transistor is a PMOS transistor, the cathode of the voltage-resistant diode is directly or indirectly connected to the gate of the field effect transistor, and the anode of the voltage-resistant diode is directly or indirectly connected to the drain of the field effect transistor.

[0027] According to at least one embodiment of the present disclosure, a transistor is connected between the gate and the drain of the field effect transistor, the emitter / collector of the transistor is connected to the gate of the field effect transistor, and the collector / emitter of the transistor is connected to the drain of the field effect transistor.

[0028] According to at least one embodiment of the present disclosure, a second switch is connected between the gate and the drain of the field effect transistor,

[0029] When the field effect transistor is an NMOS transistor, the second switch is a second NMOS transistor switch, the second NMOS transistor switch has a third parasitic diode, a source of the second NMOS transistor and one end of the third parasitic diode are directly or indirectly connected with a gate of the field effect transistor, a drain of the second NMOS transistor and the other end of the third parasitic diode are directly or indirectly connected with a drain of the field effect transistor; or

[0030] When the field effect transistor is a PMOS transistor, the second switch is a second PMOS transistor switch, the second PMOS transistor switch has a third parasitic diode, a source of the second PMOS transistor and one end of the third parasitic diode are directly or indirectly connected with a gate of the field effect transistor, a drain of the second PMOS transistor and the other end of the third parasitic diode are directly or indirectly connected with a drain of the field effect transistor.

[0031] According to at least one embodiment of the present disclosure, the switch is replaced by a first Schottky diode and a second Schottky diode,

[0032] When the field effect transistor is an NMOS transistor, a cathode of the first Schottky diode is connected with a cathode of the second Schottky diode and connected with the substrate, an anode of the first Schottky diode is connected with the drain, and an anode of the second Schottky diode is connected with the source; or,

[0033] When the field effect transistor is a PMOS transistor, an anode of the first Schottky diode is connected with an anode of the second Schottky diode and connected with the substrate, a cathode of the first Schottky diode is connected with the drain, and a cathode of the second Schottky diode is connected with the source.

[0034] According to at least one embodiment of the present disclosure, a gate of the field effect transistor is connected with a drain of the field effect transistor through a second switch,

[0035] The second switch is configured to ensure that a gate oxide layer of the field effect transistor is not broken down and / or the field effect transistor does not form a conductive channel when the field effect transistor is turned off.

[0036] According to at least one embodiment of the present disclosure, a gate of the field effect transistor is connected with a drain of the field effect transistor through a second switch, the second switch is a voltage-resistant diode,

[0037] When the field effect transistor is an NMOS transistor, the anode of the voltage-resistant diode is directly or indirectly connected to the gate of the field effect transistor, and the cathode of the voltage-resistant diode is directly or indirectly connected to the drain of the field effect transistor; or when the field effect transistor is a PMOS transistor, the cathode of the voltage-resistant diode is directly or indirectly connected to the gate of the field effect transistor, and the anode of the voltage-resistant diode is directly or indirectly connected to the drain of the field effect transistor.

[0038] According to at least one embodiment of the present disclosure, a second switch is connected between the gate and the drain of the field effect transistor,

[0039] When the field effect transistor is an NMOS transistor, the second switch is a second NMOS transistor switch, the second NMOS transistor switch has a third parasitic diode, the source of the second NMOS transistor is directly or indirectly connected to the gate of the field effect transistor and one end of the third parasitic diode, and the drain of the second NMOS transistor is directly or indirectly connected to the drain of the field effect transistor and the other end of the third parasitic diode; or

[0040] When the field effect transistor is a PMOS transistor, the second switch is a second PMOS transistor switch, the second PMOS transistor switch has a third parasitic diode, the source of the second PMOS transistor switch and one end of the third parasitic diode are directly or indirectly connected to the gate of the field effect transistor, and the drain of the second PMOS transistor and the other end of the third parasitic diode are directly or indirectly connected to the drain of the field effect transistor.

[0041] According to another aspect of the present disclosure, a control method of a field effect transistor circuit as described above, characterized in that the method comprises:

[0042] the field effect transistor is controlled to be turned on, and the switch is controlled to be turned on so that the source is in communication with the substrate; and

[0043] the field effect transistor is controlled to be turned off, and the switch is controlled to be turned off so that the source is disconnected from the substrate, and the substrate is in a floating state.

[0044] According to still another aspect of the present disclosure, a charge / discharge control device for controlling a charging current and / or a discharging current of a battery / battery pack, characterized in that it comprises:

[0045] a field effect transistor circuit as described above; and

[0046] a drive circuit that provides a drive signal to a gate of the field effect transistor of the field effect transistor circuit so that the field effect transistor is turned on when the charging current and / or the discharging current is normal, and the field effect transistor is turned off when the charging current and / or the discharging current is abnormal.

[0047] According to still another aspect of the present disclosure, the field effect transistor circuit is provided on a positive electrode side or a negative electrode side of the battery / battery pack.

[0048] According to at least one embodiment of the present disclosure, further comprising:

[0049] a detection circuit that detects the charging current and / or the discharging current; and

[0050] a control logic circuit that provides a switching control signal to the drive circuit based on a detection signal of the detection circuit.

[0051] According to still another aspect of the present disclosure, a chip that integrates the field effect transistor circuit as described above, or that integrates the charge / discharge control device as described above.

[0052] According to still another aspect of the present disclosure, a battery management system that includes the field effect transistor circuit as described above, or that includes the charge / discharge control device as described above.

[0053] According to still another aspect of the present disclosure, an electric device that includes:

[0054] a battery / battery pack that supplies power to other components in the electric device; and

[0055] the field effect transistor circuit as described above that controls a charging current or a discharging current of the battery / battery pack, or the charge / discharge control device as described above that controls a charging current or a discharging current of the battery / battery pack, or the chip as described above that controls a charging current or a discharging current of the battery / battery pack. BRIEF DESCRIPTION OF DRAWINGS

[0056] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure.

[0057] Figure 1 A battery management diagram of the prior art is shown.

[0058] Figure 2A battery management schematic is shown.

[0059] Figure 3 A battery management schematic is shown.

[0060] Figure 4 A battery management schematic is shown.

[0061] Figure 5 A battery management schematic is shown.

[0062] Figure 6 A battery management schematic is shown.

[0063] Figure 7 A battery management schematic according to an embodiment of the present disclosure is shown.

[0064] Figure 8 A battery management schematic according to an embodiment of the present disclosure is shown.

[0065] Figure 9 A battery management schematic according to an embodiment of the present disclosure is shown.

[0066] Figure 10 A battery management schematic according to an embodiment of the present disclosure is shown.

[0067] Figure 11 A battery management schematic according to an embodiment of the present disclosure is shown.

[0068] Figure 12 A battery management schematic according to an embodiment of the present disclosure is shown.

[0069] Figure 13 A battery management schematic according to an embodiment of the present disclosure is shown.

[0070] Figure 14 A battery management schematic according to an embodiment of the present disclosure is shown.

[0071] Figure 15 A battery management schematic according to an embodiment of the present disclosure is shown.

[0072] Figure 16 A battery management schematic according to an embodiment of the present disclosure is shown.

[0073] Figure 17 A battery management schematic according to an embodiment of the present disclosure is shown.

[0074] Figure 18 A battery management schematic according to an embodiment of the present disclosure is shown.

[0075] Figure 19 A flow chart of a battery management method is shown according to an embodiment of the present disclosure.

[0076] Figure 20 A schematic diagram of battery management is shown according to an embodiment of the present disclosure.

[0077] Figure 21 A schematic diagram of battery management is shown according to an embodiment of the present disclosure.

[0078] Figure 22 A schematic diagram of an electric device is shown according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0079] The present disclosure will be described in further detail below with reference to the drawings and embodiments. It can be understood that the specific embodiments described herein are only intended to explain the related content, and not to limit the present disclosure. In addition, it should be noted that only parts related to the present disclosure are shown in the drawings for ease of description.

[0080] It should be noted that the embodiments and features in the embodiments in the present disclosure can be combined with each other without conflict. The technical solutions of the present disclosure will be described in detail below with reference to the drawings and in combination with the embodiments.

[0081] Unless otherwise specified, the exemplary embodiments / instances shown will be understood to provide exemplary features of various details that can implement the technical concepts of the present disclosure in practice. Therefore, unless otherwise specified, the features of various embodiments / instances can be additionally combined, separated, interchanged and / or rearranged without departing from the technical concepts of the present disclosure.

[0082] When a component is referred to as "connected to" or "combined to" another component, the component can be directly on, directly connected to or directly combined to the other component, or there can be an intermediate component. However, when a component is referred to as "directly connected to" or "directly combined to" another component, there is no intermediate component. For this reason, the term "connected" can refer to a physical connection, an electrical connection, etc., with or without an intermediate component.

[0083] In order to solve the problems existing in the prior art, for example, in order to solve the power loss caused by the charging switch and the discharging switch, thereby affecting the performance of the battery system, it is necessary to reduce the series on-resistance of the MOS transistor in the current path. Therefore, only the MOS transistor M1 or M2 shown in the figure can be used as the charging switch and the discharging switch. Obviously, when one MOS transistor is used, the on-resistance can be reduced by half, and the power consumption is reduced to one fourth of the original. Figure 1 The MOS transistors M1 or M2 shown in the figure are connected in series in the current path, and one of the MOS transistors is used as the charging switch and the discharging switch. Obviously, when one MOS transistor is used, the on-resistance can be reduced by half, and the power consumption is reduced to one fourth of the original.

[0084] The following will be described in the case of using one MOS transistor as the charging switch and the discharging switch.

[0085] Figure 2 The case of discharging the battery is shown. The case of using only MOS transistor Ml and omitting MOS transistor M2 is described as an example, as shown in FIG. 2. Figure 2 The source S of MOS transistor Ml is connected to the B- terminal of the battery, and the drain D of MOS transistor Ml is connected to the P- terminal of the external load, and MOS transistor Ml has a parasitic diode Dl. The gate G of MOS transistor Ml receives a control signal from the drive unit to be turned on and off. The source S of MOS transistor Ml is shorted to the bulk (B terminal) of MOS transistor Ml. By using one MOS transistor Ml, the on-resistance R on of the charge-discharge switch is apparently reduced to half.

[0086] When the battery discharges to the external load, the current flows in the circuit in the direction of discharging current I dsg from the P- terminal to the B- terminal, and the voltage of the B- terminal is higher than that of the P- terminal. When the voltage difference (I dsg *R on ) between the P- terminal and the B- terminal is detected to reach a certain threshold value, the voltage of the control signal of the gate of MOS transistor Ml is changed from high level (for example, VDD, the supply voltage of the drive unit) to VP- (the voltage of the P- terminal), thereby turning off Ml and turning off the discharging path.

[0087] Figure 3 The case of charging the battery is shown. The case of using only Ml and omitting M2 is described as an example, as shown in FIG. 3. Figure 3 The source S of MOS transistor Ml is connected to the B- terminal of the battery, and the drain D of MOS transistor Ml is connected to the P- terminal of the external load, and MOS transistor Ml has a parasitic diode Dl. The gate G of MOS transistor Ml receives a control signal from the drive unit to be turned on and off. The source S of MOS transistor Ml is shorted to the bulk (B terminal) of MOS transistor Ml. By using one MOS transistor Ml, the on-resistance R on of the charge-discharge switch is apparently reduced to half.

[0088] When the battery is charged by the external charger, the current flows in the circuit in the direction of charging current I chg from the B- terminal to the P- terminal, and the voltage of the P- terminal is higher than that of the B- terminal. When the voltage difference (I chg *R on) reaches a certain threshold, in order to turn off Ml, the control signal voltage of the gate of MOS transistor Ml changes from high level (VDD, driving circuit supply voltage) to VB-, i.e. the gate G and the source S are shorted, VG= VS= VB-.

[0089] Dl is the natural parasitic diode of MOS transistor Ml, the positive terminal (anode, P-type doping) of the parasitic diode Dl is the P-well (Bulk) of MOS transistor Ml, and the negative terminal (cathode, N-type doping) of the parasitic diode Dl is the drain D of MOS transistor Ml. Therefore, even if the voltage of the control signal of the gate G of MOS transistor Ml is VB-, MOS transistor Ml is turned off (the conduction channel is not formed), but the charging current still continues to flow through the parasitic diode Dl, continuing to charge the battery.

[0090] Therefore, due to the existence of the parasitic diode Dl, MOS transistor Ml still cannot completely turn off the charging current in the case of charging overcurrent.

[0091] The following describes the case where Ml is omitted and only M2 is used for the charge-discharge switch.

[0092] Figure 4 An example in the case of discharging is shown as follows: Figure 4 As shown, the drain D of MOS transistor M2 is connected to the B- terminal of the battery, and the source S of MOS transistor M2 is connected to the P- terminal of the external load, and MOS transistor M2 has a parasitic diode Dl. The gate G of MOS transistor M2 receives a control signal from the driving unit to turn on and off. The source S of MOS transistor M2 is shorted to the substrate (Bulk, B terminal) of MOS transistor M2. By using one MOS transistor M2, it is obvious that the on-resistance R on of the charge-discharge switch will be reduced to half.

[0093] When the battery discharges to the load, the flow direction of the current in the circuit is: the discharge current I dsg flows from the P- terminal to the B- terminal, and the B- terminal voltage is higher. When the voltage difference (I dsg * R on) reaches a certain threshold value, in order to turn off the discharging path, the voltage of the gate control signal of MOS transistor M2 changes from high level (VDD, driving circuit supply voltage) to VP-, the gate G and the source S are shorted, VG=VS=VP-. Although VG-VS=0, the conductive channel of M2 disappears. But because the positive terminal of the parasitic diode Dl is the P-type bulk region of MOS transistor M2 and is connected to the source S, that is, the P- terminal, and the negative terminal of Dl is connected to the drain D of MOS transistor M2, the battery can still continue to discharge the load through the parasitic diode Dl of MOS transistor M2, and the discharging path cannot be completely turned off.

[0094] Figure 5 An example in the charging case is shown as follows: Figure 5 As shown, the drain D of MOS transistor M2 is connected to the B- terminal of the battery, and the source S of MOS transistor M2 is connected to the P- terminal of the external load, and MOS transistor M2 has a parasitic diode Dl. The gate G of MOS transistor M2 receives a control signal from the driving unit to turn on and turn off. In which the source S of MOS transistor M2 is shorted with the bulk (B terminal) of MOS transistor M2. By using one MOS transistor M2, it is obvious that the on-resistance R on of the charge-discharge switch will be reduced to half.

[0095] When the battery is charged by an external charger, the current in the loop flows in the direction: the charging current I chg flows from the B- terminal to the P- terminal, and the voltage at the P- terminal is higher. When the voltage difference (I chg *R on ) between the B- terminal and the P- terminal is detected to reach a certain threshold value, in order to turn off MOS transistor M2, the voltage of the control signal of MOS transistor M2 changes from high level (VDD, driving circuit supply voltage) to VB-, that is, the gate G and the source S are shorted, VG=VS=VB-, the conductive channel of MOS transistor M2 disappears, so that MOS transistor M2 is turned off.

[0096] According to the description of Figures 2 to 5 , it can be seen that although the use of MOS transistor Ml or M2 alone can reduce the on-resistance, when the charging current or discharging current overflows, the current path cannot be completely turned off.

[0097] Figure 6 Another example is given, in which MOS transistor M3 is used, in which the bulk of MOS transistor M3 is floating (suspended).

[0098] The source S of the MOS transistor M3 is connected to the B- terminal of the battery, and the drain D of the MOS transistor M3 is connected to the P- terminal of the external charger. The MOS transistor M3 has parasitic diodes D31 and D32. The positive terminal of the parasitic diode D31 is connected to the substrate (B terminal) of the MOS transistor M3, and the negative terminal of the parasitic diode D31 is connected to the drain D. The positive terminal of the parasitic diode D32 is connected to the substrate (B terminal) of the MOS transistor M3, and the negative terminal of the parasitic diode D32 is connected to the source S. The gate G of the MOS transistor M3 receives a control signal from the driving unit to turn on and off. By using one MOS transistor M3, the on-resistance R on of the charge and discharge switch is reduced to half.

[0099] For Figure 6 the example shown, the MOS transistor M3 is taken as an example of the charge over-current shutdown MOS transistor. The same applies when discharging over-current, which will not be described here.

[0100] If the gate G and the source S are shorted, i.e. V(G) = V(S) = V(B-). According to the KVL law, [V(B+)-V(B-)]+[V(B-)-V(P-)]+[V(P-)-V(P+)] = 0. V(B+)-V(B-) = the voltage across the battery. V(P+)-V(P-) = the voltage across the charger = V(charger). V(B-) = 0, the "ground" potential of the system, i.e. zero potential. In the extreme case, after the battery is fully discharged, V(B+)-V(B-) ≈ 0V, then V(P-) = V(B-)+[V(P-)-V(P+)] = -[V(P+)-V(P-)] = -V(charger).

[0101] For a charger for a 1-section lithium battery, the voltage V(charger) across the charger = 4.5V ~ 5V. For a charger for n-section lithium batteries connected in series, the voltage across the charger is usually V(charger) = 4.5*nV ~ 5*nV.

[0102] V(bulk) = -V(charger)+V(D31) = -V(charger)+0.7V. Where V(D31) is the voltage difference across the parasitic diode D31, which is usually 0.7V. The voltage V(bulk) of the P-type substrate of the MOS transistor M3 is <-5*n+0.7V <-4.3V.

[0103] Because V(G) = V(S) = 0V, the P-type substrate of MOS transistor M3 is inverted to an n-type channel, and the current flows from the source S to the drain D through the inverted channel, so the channel of MOS transistor M3 cannot be completely turned off, and the charging current cannot be turned off by MOS transistor M3, and MOS transistor M3 cannot function as a protection switch during overcurrent charging.

[0104] If the gate G is shorted to the drain D, that is, V(G) = V(D) = V(P-). From the above KVL law analysis, it can be known that V(G) = V(D) = V(P-) = -5*n + 0.7V <-4.3V.

[0105] If it is an application of 10 series lithium batteries, V(G) = V(D) = V(P-) ≈ -40V, because V(S) = 0V, V(S)-V(G) = 40V, the gate oxide layer of MOS transistor M3 will be broken down. V(S)-V(Bulk) = 40V, the parasitic diode D32 of MN3 will be broken down, so that the charging current cannot be turned off.

[0106] From the above, it can be known that if only one MOS transistor is used in series in the current path, Figures 2 to 6 the connection mode cannot completely turn off the charging current or the discharging current.

[0107] For the above embodiments, the MOS transistor is in the form of an NMOS transistor, but those skilled in the art should understand that a PMOS transistor can also be used, and the principle is the same as described above. For the sake of brevity, it will not be repeated here.

[0108] The present disclosure proposes a novel circuit structure, which can use only one MOS transistor in series in the current loop, and can completely turn off the current, and will not occur breakdown phenomenon. In the following embodiments, the drain of the field effect transistor is connected to the external power supply or load, so generally for the field effect transistor, the withstand voltage of the drain will be much higher than that of the source.

[0109] Figure 7 A field effect transistor circuit according to the present disclosure is shown. In this embodiment, an NMOS transistor is taken as an example for illustration.

[0110] As Figure 7 shown, the field effect transistor circuit includes a field effect transistor M4 and a switch M5.

[0111] The field effect transistor M4 includes a gate G, a source S, a drain D, a substrate B, a first parasitic diode D41, and a second parasitic diode D42, wherein the first parasitic diode D41 and the second parasitic diode D42 are connected in reverse series, one end of a series circuit of the first parasitic diode D41 and the second parasitic diode D42 is connected to the source S, and the other end of the series circuit is connected to the drain D, and a connection point of the first parasitic diode D41 and the second parasitic diode D42 is connected to the substrate B.

[0112] The anode of the first parasitic diode D41 is connected to the anode of the second parasitic diode D42, the cathode of the first parasitic diode D41 is connected to the drain, and the cathode of the second parasitic diode D42 is connected to the source.

[0113] The series circuit of the first parasitic diode D41 and the second parasitic diode D42 is configured so that no conductive path is formed through the series circuit between the source S and the drain D of the field effect transistor M4.

[0114] One end of a switch is connected to the connection point, and the other end of the switch is connected to the source S. As one example, the field effect transistor is an NMOS transistor and the switch is an NMOS transistor. The gate G of the NMOS transistor M5 of the switch is connected to the gate G of the NMOS transistor M4 of the field effect transistor, the source S of the NMOS transistor M5 of the switch is connected to the connection point B, and the drain D of the NMOS transistor M5 is connected to the source S of the NMOS transistor M4 of the field effect transistor.

[0115] When the gate-source voltage V GS of the field effect transistor M4 between the gate G and the source S is greater than the on threshold voltage V TH of the field effect transistor, the field effect transistor M4 is turned on, and the switch is turned on to make the source S of the field effect transistor M4 communicate with the substrate B, and when the gate-source voltage V GS is less than the on threshold voltage V TH , the field effect transistor M4 is turned off, and the switch is turned off to make the source S of the field effect transistor M4 not communicate with the substrate B, and the substrate B is in a floating state.

[0116] When the source S of the field effect transistor M4 is made to communicate with the substrate B through the switch and the field effect transistor M4 is turned on, a conductive channel of the field effect transistor M4 is formed, and when the source S of the field effect transistor M4 is made not to communicate with the substrate B through the switch, the conductive channel of the field effect transistor M4 is not formed.

[0117] A second switch DZ is connected between the gate G and the drain D of the field effect transistor M4. The second switch is configured to ensure that the gate oxide layer of the field effect transistor is not broken down and / or the field effect transistor does not form a conductive channel when the field effect transistor is turned off.

[0118] In some cases, when the voltage of the drain D of the field effect transistor M4 is ≤ 0, for example, when it is 0V ~ 40V, the second switch DZ is turned on to connect the gate G and the drain D of the field effect transistor M4, and when the voltage of the drain D of the field effect transistor M4 is > 0, the second switch DZ is turned off to disconnect the gate G and the drain D of the field effect transistor M4. Or in some cases, when the drain voltage is greater than the gate voltage, the second switch is turned off, and when the drain voltage is less than or equal to the gate voltage, the second switch is turned on. Or in some cases, when the drain voltage is less than or equal to the gate voltage minus the on voltage of the second switch, the second switch is turned on.

[0119] The second switch DZ is a voltage-resistant diode, one end of the voltage-resistant diode is directly or indirectly connected to the gate G of the field effect transistor M4, and the other end of the voltage-resistant diode is directly or indirectly connected to the drain D of the field effect transistor M4. In the case of direct connection, one end of the voltage-resistant diode is connected to the gate G of the field effect transistor M4, and the other end of the voltage-resistant diode is connected to the drain D of the field effect transistor M4. In the case of indirect connection, the second switch DZ can form a series circuit with the resistor R, one end of the series circuit is connected to the gate G of the field effect transistor M4, and the other end of the series circuit is connected to the drain D of the field effect transistor M4. It should be noted that there is no limitation on the series order of the second switch DZ and the resistor R.

[0120] In Figure 7 The second switch DZ is shown in the form of a Zener diode, and the second switch DZ can also be a Schottky diode, etc.

[0121] In addition, according to other examples, the second switch can be an NMOS transistor. For example Figure 8 As shown, the NMOS transistor M6 has a parasitic diode D6, one end of the parasitic diode D6 is directly or indirectly connected to the gate G of the field effect transistor M6, and the other end of the parasitic diode D6 is directly or indirectly connected to the drain D of the field effect transistor M6. In the case of direct connection, one end of the field effect transistor M6 is connected to the gate G of the field effect transistor M4, and the other end of the field effect transistor M6 is connected to the drain D of the field effect transistor M4. In the case of indirect connection, the field effect transistor M6 can form a series circuit with the resistor R, one end of the series circuit is connected to the gate G of the field effect transistor M4, and the other end of the series circuit is connected to the drain D of the field effect transistor M4. It should be noted that there is no limitation on the series order of the field effect transistor M6 and the resistor R.

[0122] In the case of using an NMOS transistor as the second switch, the parasitic diode D6 of the NMOS transistor M6 is used as a voltage-resistant diode, thereby playing the role of the second switch.

[0123] The use of the second switch can prevent the high voltage at the drain terminal D of NMOS transistor M4 from damaging NMOS transistor M4, such as by breaking down the gate oxide layer.

[0124] When the circuit is charging normally, the conductive channel of NMOS transistor M4 is formed, and NMOS transistor M4 is turned on, so that the substrate Bulk region of NMOS transistor M4 is connected to the source S of NMOS transistor M4.

[0125] When the circuit is overcharged, the conductive channel of NMOS transistor M4 will not form, and the channel of NMOS transistor M4 will be in the off state. The Bulk region of NMOS transistor M4 is disconnected from the source S, and the Bulk region is in a floating state.

[0126] Because parasitic diodes D41 and D42 are connected in reverse series, the series circuit of parasitic diodes D41 and D42 cannot conduct. Therefore, there is no current path from the source S to the drain D of NMOS transistor M4. According to this disclosure, the gate oxide layer of NMOS transistor M4 will not be broken down.

[0127] like Figure 9 As shown, when the battery discharges to an external load, the direction of current flow in the circuit is: discharge current I dsg The current flows from terminal P- to terminal B-, and the voltage at terminal B- is higher than the voltage at terminal P-. When the voltage difference (I) between terminal P- and terminal B- is detected... dsg *R on When a certain threshold is reached, the MOS transistor M4 is turned off, cutting off the discharge path. The parasitic diodes D41 and D42 connected in reverse series will not form a current path.

[0128] Figure 10 Another embodiment according to this disclosure is provided. For example... Figure 10 As shown, the field-effect transistor circuit includes a field-effect transistor M4, wherein the field-effect transistor M4 is an NMOS transistor.

[0129] The field-effect transistor M4 includes a gate G, a source S, a drain D, a substrate B, a first parasitic diode D41, and a second parasitic diode D42. The first parasitic diode D41 and the second parasitic diode D42 are connected in reverse series. One end of the series circuit of the first parasitic diode D41 and the second parasitic diode D42 is connected to the source S, and the other end of the series circuit is connected to the drain D. The connection point of the first parasitic diode D41 and the second parasitic diode D42 is connected to the substrate B.

[0130] The anode of the first parasitic diode D41 is connected to the anode of the second parasitic diode D42, the cathode of the first parasitic diode D41 is connected to the drain, and the cathode of the second parasitic diode D42 is connected to the source.

[0131] The series circuit of the first parasitic diode D41 and the second parasitic diode D42 is configured so that no conductive path is formed through the series circuit between the source S and the drain D of the field effect transistor M4.

[0132] The anode of the first Schottky diode D61 and the anode of the second Schottky diode D62 are connected, the cathode of the first Schottky diode D61 is connected to the drain of the field effect transistor M4, and the first Schottky diode D61 is connected to the source of the field effect transistor M4. The connection point of the anode of the first Schottky diode D61 and the anode of the second Schottky diode D62 is connected to the substrate B.

[0133] In this embodiment, because the on voltage of the Schottky diode is smaller than the voltage of the parasitic diode, when the Schottky diode is turned on, the parasitic diode will not be turned on.

[0134] When the circuit is normally charged, a conductive channel of the NMOS transistor M4 is formed, the NMOS transistor M4 is turned on, and the substrate Bulk region of the NMOS transistor M4 is connected to the source S of the NMOS transistor M4.

[0135] When the circuit is overcharged, no conductive channel of the NMOS transistor M4 is formed, and the channel of the NMOS transistor M4 is in an off state. The Bulk region of the NMOS transistor M4 is disconnected from the source S, and the Bulk region is in a floating state. Because the parasitic diodes D41 and D42 are connected in reverse series, the series circuit of the parasitic diodes D41 and D42 cannot be turned on, so there is no current path from the source S of the NMOS transistor M4 to the drain D of the NMOS transistor M4. Moreover, the gate oxide layer of the NMOS transistor M4 will not be broken down.

[0136] When the battery discharges to an external load, the reverse series connected parasitic diodes D41 and D42 do not form a current path.

[0137] The above description of the control method is described with reference to the NMOS transistor, but the principle is the same for the PMOS transistor, and the case of the PMOS transistor will be described in detail below.

[0138] Figure 11 A field effect transistor circuit according to the present disclosure is shown. In this embodiment, a PMOS transistor is taken as an example for illustration.

[0139] As shown in Figure 11 The field effect transistor circuit includes a field effect transistor M4 (PMOS transistor) and a switch M5.

[0140] The field effect transistor M4 includes a gate G, a source S, a drain D, a substrate B, a first parasitic diode D41, and a second parasitic diode D42, wherein the first parasitic diode D41 and the second parasitic diode D42 are connected in reverse series, one end of a series circuit of the first parasitic diode D41 and the second parasitic diode D42 is connected to the source S, and the other end of the series circuit is connected to the drain D, and a connection point of the first parasitic diode D41 and the second parasitic diode D42 is connected to the substrate B.

[0141] The cathode of the first parasitic diode D41 is connected to the cathode of the second parasitic diode D42, the anode of the first parasitic diode D41 is connected to the drain, and the anode of the second parasitic diode D42 is connected to the source.

[0142] The series circuit of the first parasitic diode D41 and the second parasitic diode D42 is configured so that no conduction path is formed through the series circuit between the source S and the drain D of the field effect transistor M4.

[0143] One end of the switch M5 is connected to the connection point of the first parasitic diode D41 and the second parasitic diode D42, and the other end of the switch is connected to the source.

[0144] As one example, the field effect transistor is a PMOS transistor and the switch M5 is a PMOS transistor. The gate G of the PMOS transistor M5 is connected to the gate G of the PMOS transistor M4 of the field effect transistor, the drain D of the PMOS transistor M5 is connected to the connection point B (Bulk (B end) of the substrate of the MOS transistor M4), and the source S of the PMOS transistor M5 is connected to the source S of the PMOS transistor M4 of the field effect transistor.

[0145] When the gate-source voltage V GS of the field effect transistor M4 between the gate G and the source S is smaller than the on threshold voltage V TH of the field effect transistor, the field effect transistor M4 is turned on, and the switch is turned on to make the source S of the field effect transistor M4 communicate with the substrate B, and when the gate-source voltage V GS is greater than the on threshold voltage V TH , the field effect transistor M4 is turned off, and the switch is turned off to make the source S of the field effect transistor M4 not communicate with the substrate B, and the substrate B is in a floating state.

[0146] When the source S of the field effect transistor M4 is made to communicate with the substrate B by the switch and the field effect transistor M4 is turned on, a conduction channel of the field effect transistor M4 is formed, and when the source S of the field effect transistor M4 is made not to communicate with the substrate B by the switch, the conduction channel of the field effect transistor M4 is not formed.

[0147] A second switch DZ is connected between the gate G and the drain D of the field effect transistor M4. The second switch is configured to ensure that the gate oxide of the field effect transistor is not broken down and / or the field effect transistor does not form a conduction channel when the field effect transistor is off. The second switch DZ is turned on to connect the gate G and the drain D of the field effect transistor M4 when the voltage of the drain D of the field effect transistor M4 is > 0, and the second switch DZ is turned off to disconnect the gate G and the drain D of the field effect transistor M4 when the voltage of the drain D of the field effect transistor M4 is < 0. Alternatively in some cases, the second switch is turned off when the drain voltage is less than or equal to the gate voltage, and the second switch is turned on when the drain voltage is greater than the gate voltage. Alternatively in some cases, the second switch is turned on when the drain voltage is greater than the gate voltage plus the on voltage of the second switch.

[0148] The second switch DZ is a voltage-resistant diode, one end of the voltage-resistant diode is directly or indirectly connected to the gate G of the field effect transistor M4, and the other end of the voltage-resistant diode is directly or indirectly connected to the drain D of the field effect transistor M4. In the case of direct connection, one end of the voltage-resistant diode is connected to the gate G of the field effect transistor M4, and the other end of the voltage-resistant diode is connected to the drain D of the field effect transistor M4. In the case of indirect connection, the second switch DZ can form a series circuit with a resistor R, one end of the series circuit is connected to the gate G of the field effect transistor M4, and the other end of the series circuit is connected to the drain D of the field effect transistor M4. It should be noted that there is no limitation on the series order of the second switch DZ and the resistor R.

[0149] In Figure 11 the second switch DZ is in the form of a Zener diode, and the second switch DZ can also be a Schottky diode, etc.

[0150] In addition, according to other examples, the second switch can be a PMOS transistor. For example Figure 12 As shown, the PMOS transistor M6 has a parasitic diode D6, one end of the parasitic diode D6 is directly or indirectly connected to the gate G of the field effect transistor M6, and the other end of the parasitic diode D6 is directly or indirectly connected to the drain D of the field effect transistor. In the case of direct connection, one end of the field effect transistor M6 is connected to the gate G of the field effect transistor M4, and the other end of the field effect transistor M6 is connected to the drain D of the field effect transistor M4. In the case of indirect connection, the field effect transistor M6 can form a series circuit with a resistor R, one end of the series circuit is connected to the gate G of the field effect transistor M4, and the other end of the series circuit is connected to the drain D of the field effect transistor M4. It should be noted that there is no limitation on the series order of the field effect transistor M6 and the resistor R.

[0151] When using a PMOS transistor as a second switch, the parasitic diode D6 of the PMOS transistor M6 is used as a voltage-degrading diode, thus serving as a second switch.

[0152] The use of the second switch can prevent the high voltage at the drain terminal D of PMOS transistor M4 from damaging PMOS transistor M4.

[0153] When the circuit is charging normally, the conductive channel of PMOS transistor M4 is formed, PMOS transistor M4 is turned on, and the substrate Bulk region of PMOS transistor M4 is connected to the source S of PMOS transistor M4.

[0154] When the circuit is overcharged, the conductive channel of PMOS transistor M4 will not form, and the channel of PMOS transistor M4 will be in the off state. This disconnects the Bulk region of PMOS transistor M4 from the source S, leaving the Bulk region in a floating state. Since parasitic diodes D41 and D42 are connected in reverse series, their series circuit cannot conduct. Therefore, there is no current path from the source S to the drain D of PMOS transistor M4. Furthermore, the gate oxide layer of PMOS transistor M4 will not be broken down.

[0155] like Figure 13 As shown, when the battery discharges to an external load, the direction of current flow in the circuit is: discharge current I dsg The current flows from terminal B+ to terminal P+. The voltage at terminal P+ is higher than the voltage at terminal B+. When the voltage difference (I) between terminals B+ and P+ is detected... dsg *R on When a certain threshold is reached, the MOS transistor M4 is turned off, i.e., the discharge path is cut off. The parasitic diodes D41 and D42 connected in reverse series will not form a current path.

[0156] Figure 14 Another embodiment according to this disclosure is provided. For example... Figure 14 As shown, the field-effect transistor circuit includes a field-effect transistor M4, wherein the field-effect transistor M4 is an NMOS transistor.

[0157] The field-effect transistor M4 includes a gate G, a source S, a drain D, a substrate B, a first parasitic diode D41, and a second parasitic diode D42. The first parasitic diode D41 and the second parasitic diode D42 are connected in reverse series. One end of the series circuit of the first parasitic diode D41 and the second parasitic diode D42 is connected to the source S, and the other end of the series circuit is connected to the drain D. The connection point of the first parasitic diode D41 and the second parasitic diode D42 is connected to the substrate B.

[0158] The cathode of the first parasitic diode D41 is connected to the cathode of the second parasitic diode D42, the anode of the first parasitic diode D41 is connected to the drain, and the anode of the second parasitic diode D42 is connected to the source.

[0159] The series circuit of the first parasitic diode D41 and the second parasitic diode D42 is configured so that no conductive path is formed through the series circuit between the source S and the drain D of the field effect transistor M4.

[0160] The cathode of the first Schottky diode D61 is connected to the cathode of the second Schottky diode D62, the anode of the first Schottky diode D61 is connected to the drain of the field effect transistor M4, and the first Schottky diode D61 is connected to the source of the field effect transistor M4. The connection point of the cathode of the first Schottky diode D61 and the cathode of the second Schottky diode D62 is connected to the substrate B.

[0161] In this embodiment, because the on voltage of the Schottky diode is smaller than the voltage of the parasitic diode, when the Schottky diode is turned on, the parasitic diode will not be turned on.

[0162] When the circuit is normally charged, a conductive channel of the PMOS transistor M4 is formed, the PMOS transistor M4 is turned on, and the substrate Bulk region of the PMOS transistor M4 is connected to the source S of the PMOS transistor M4.

[0163] When the circuit is overcharged, no conductive channel of the PMOS transistor M4 is formed, and the channel of the PMOS transistor M4 is in an off state. Thus, the Bulk region of the PMOS transistor M4 is disconnected from the source S, and the Bulk region is in a floating state. Because the parasitic diodes D41 and D42 are connected in reverse series, the series circuit of the parasitic diodes D41 and D42 cannot be turned on, so there is no current path from the source S of the PMOS transistor M4 to the drain D of the PMOS transistor M4. Moreover, the gate oxide layer of the PMOS transistor M4 will not be broken down.

[0164] When the battery discharges to an external load, the reverse series connected parasitic diodes D41 and D42 will not form a current path.

[0165] In the above description, the switch is described by taking the NMOS transistor M5 as an example, but other types of switches can also be used in the present disclosure, such as a triode. Figures 15 to 18 An embodiment using a triode is shown. In the embodiment, the base B of the triode is connected to the gate of the field effect transistor M4 through a resistor RT, and the collector or the emitter of the triode can be connected to the Bulk terminal, and the emitter or the collector of the triode can be connected to the source of the field effect transistor M4. In addition, the second switch M6 / DZ can also be in the form of a triode, for exampleFigure 17 and 18 wherein the collector or the emitter of the triode can be directly or indirectly connected to the gate of the field effect transistor M4, and the emitter or the collector of the triode can be directly or indirectly connected to the drain of the field effect transistor M4.

[0166] In addition, for the case that the field effect transistor M4 is in the form of a PMOS transistor, it is the same as the case of Figures 15 to 18 .

[0167] According to another embodiment of the present disclosure, a control method of a field effect transistor is also provided, wherein the control circuit of the field effect transistor is as described in the above embodiments, which will not be repeated here.

[0168] Taking an NMOS transistor as an example, as shown in Figure 19 , the control method comprises: detecting whether there is an overcurrent, if there is no overcurrent, the driving unit provides a control signal so that the gate-source voltage between the gate and the source is greater than the turn-on threshold voltage of the field effect transistor, the field effect transistor is controlled to be turned on, and the switch is controlled to be turned on to make the source communicate with the substrate, if there is an overcurrent, the driving unit provides a control signal so that the gate-source voltage is less than the turn-on threshold voltage, the field effect transistor is controlled to be turned off, and the switch is controlled to be turned off to make the source disconnected with the substrate, and the substrate is in a floating state.

[0169] The conductive channel of the field effect transistor is formed by the switch connecting the source and the substrate and the field effect transistor being turned on, and the conductive channel of the field effect transistor is not formed when the switch disconnects the source and the substrate.

[0170] No conductive path is formed between the source and the drain through the series circuit of the first parasitic diode and the second parasitic diode.

[0171] The anode of the first parasitic diode is connected to the anode of the second parasitic diode, the cathode of the first parasitic diode is connected to the drain, and the cathode of the second parasitic diode is connected to the source.

[0172] The field effect transistor is an NMOS transistor and the switch is an NMOS transistor.

[0173] The gate of the NMOS transistor of the switch is connected to the gate of the NMOS transistor of the field effect transistor, the source of the NMOS transistor of the switch is connected to the connection point, and the drain of the NMOS transistor is connected to the source of the NMOS transistor of the field effect transistor.

[0174] A second switch is connected between the gate and the drain of the field effect transistor, and when the voltage of the drain of the field effect transistor is ≤ 0, the second switch is turned on to connect the gate and the drain of the field effect transistor, and when the voltage of the drain of the field effect transistor is > 0, the second switch is turned off to disconnect the gate and the drain of the field effect transistor.

[0175] The second switch is a voltage-resistant diode, the anode of the voltage-resistant diode is directly or indirectly connected with the gate of the field effect transistor, and the cathode of the voltage-resistant diode is directly or indirectly connected with the drain of the field effect transistor.

[0176] The second switch is a second NMOS transistor, the second NMOS transistor has a parasitic diode, the source of the NMOS transistor and one end of the parasitic diode are directly or indirectly connected with the gate of the field effect transistor, and the drain of the NMOS transistor and the other end of the parasitic diode are directly or indirectly connected with the drain of the field effect transistor.

[0177] Taking the PMOS transistor as an example, the control method comprises: detecting whether there is overcurrent, if not, the driving unit provides a control signal so that the gate-source voltage between the gate and the source is less than the turn-on threshold voltage of the field effect transistor, the field effect transistor is controlled to be turned on, and the switch is controlled to be turned on to make the source communicate with the substrate, if yes, the driving unit provides a control signal so that the gate-source voltage is greater than the turn-on threshold voltage, the field effect transistor is controlled to be turned off, and the switch is controlled to be turned off to make the source disconnected with the substrate, and the substrate is in a floating state.

[0178] When the source is communicated with the substrate through the switch, a conductive channel of the field effect transistor is formed, and when the source is disconnected with the substrate through the switch, the conductive channel of the field effect transistor is not formed.

[0179] No conductive path is formed between the source and the drain through the series circuit of the first parasitic diode and the second parasitic diode.

[0180] The anode of the first parasitic diode is connected with the anode of the second parasitic diode, the cathode of the first parasitic diode is connected with the drain, and the cathode of the second parasitic diode is connected with the source.

[0181] The field effect transistor is a PMOS transistor, and the switch is a PMOS transistor.

[0182] The gate of the PMOS transistor of the switch is connected with the gate of the PMOS transistor of the field effect transistor, the source of the PMOS transistor of the switch is connected with the connection point, and the drain of the PMOS transistor is connected with the source of the PMOS transistor of the field effect transistor.

[0183] A second switch is connected between the gate and the drain of the field effect transistor, and when the voltage of the drain of the field effect transistor is > 0, the second switch is turned on to connect the gate and the drain of the field effect transistor, and when the voltage of the drain of the field effect transistor is ≤ 0, the second switch is turned off to disconnect the gate and the drain of the field effect transistor.

[0184] The second switch is a voltage-resistant diode, the anode of the voltage-resistant diode is directly or indirectly connected to the gate of the field effect transistor, and the cathode of the voltage-resistant diode is directly or indirectly connected to the drain of the field effect transistor.

[0185] The second switch is a second PMOS transistor, the second PMOS transistor has a parasitic diode, the source of the PMOS transistor and one end of the parasitic diode are directly or indirectly connected to the gate of the field effect transistor, and the drain of the PMOS transistor and the other end of the parasitic diode are directly or indirectly connected to the drain of the field effect transistor.

[0186] In addition, in each of the above embodiments, a resistor or a series circuit of a resistor and a switch, etc. can be connected between the gate and the source of the field effect transistor.

[0187] According to another embodiment of the present disclosure, as shown in Figure 20 a charging / discharging control device for controlling the charging current and / or discharging current of a battery / battery pack is provided, which includes the field effect transistor circuit as described above and a driving circuit for providing a driving signal to the gate of the field effect transistor M4 of the field effect transistor circuit, so that the field effect transistor is turned on when the charging current and / or discharging current is normal, and the field effect transistor is turned off when the charging current and / or discharging current is abnormal. At the same time, the driving circuit also provides a control signal to the gate of the field effect transistor M5.

[0188] The charging / discharging control device further includes a detection circuit for detecting the charging current and / or discharging current, and a control logic circuit for providing a switching control signal to the driving circuit based on the detection signal of the detection circuit.

[0189] The charging / discharging control device can further include a VDD generator for generating a VDD voltage for use by other components. A voltage acquisition unit can also be included for acquiring the voltage of each battery cell and providing the acquired voltage of each battery cell to the control logic circuit. The control logic circuit turns off the field effect transistor M4 for charging control and discharging control when an abnormality occurs.

[0190] It should be noted that the field effect transistor M4 can be arranged in the current path on the high-voltage side of the battery or in the current path on the low-voltage side of the battery.

[0191] According to another embodiment of the present disclosure, a chip is provided, which is integrated with the field effect transistor circuit as described above, for example, in Figure 21 dashed line box. The chip can also be integrated with the charge and discharge control device as described above, for example, in Figure 21 dotted line box. Figure 21 The NMOS transistor is taken as an example for drawing, and the principle for the PMOS transistor is the same, which will not be repeated here.

[0192] According to another embodiment of the present disclosure, according to another embodiment of the present disclosure, the battery management system includes the field effect transistor circuit as described above, or includes the charge and discharge control device as described above.

[0193] As shown in Figure 22 The present disclosure also provides an electrical device, which can include a battery / battery pack for powering other components in the electrical device; the electrical device can also include the field effect transistor circuit, the charge and discharge control device, or the chip as described above.

[0194] According to the technical solution of the present disclosure, the control of the charging and discharging current is realized by using one MOS transistor, and the MOS transistor can be effectively turned off completely. By using one MOS transistor, the on-resistance is reduced by half compared with the prior art, which can effectively reduce the power consumption.

[0195] At the same time, because in the same physical structure and manufacturing process, the silicon area of the MOS transistor with an on-resistance of x ohm is twice the silicon area of the MOS transistor with an on-resistance of 2x ohm. However, by using one transistor to realize the functions realized by two transistors, the silicon area of the MOS transistor can be effectively reduced, and low on-resistance is also achieved.

[0196] In the description of the present specification, the description of the terms "one embodiment / way", "some embodiments / ways", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment / way or example are included in at least one embodiment / way or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment / way or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments / ways or examples. In addition, the skilled in the art can combine and combine the different embodiments / ways or examples described in the present specification and the features of the different embodiments / ways or examples without contradiction.

[0197] Furthermore, the terms "first", "second", etc. are used herein for descriptive purposes only and should not be construed as indicating or implying relative importance or an ordered ranking of indicated technical features. Thus, features defined with "first", "second" etc. can include, explicitly or implicitly, at least one of such features. In the description of the application, the meaning of "plurality" is at least two, e.g. two, three, etc., unless explicitly specified otherwise.

[0198] Those skilled in the art will understand that the above-described embodiments are merely intended to clarify the present disclosure, and are not intended to limit the scope of the present disclosure. Other changes or modifications can be made by those skilled in the art based on the above disclosure, and such changes or modifications are still within the scope of the present disclosure.

Claims

1. A field effect transistor circuit, characterized by Comprise: a field effect transistor comprising a gate, a source, a drain, a substrate, a first parasitic diode and a second parasitic diode, wherein the first parasitic diode and the second parasitic diode are connected in reverse series, one end of a series circuit of the first parasitic diode and the second parasitic diode is connected to the source, and the other end of the series circuit is connected to the drain, and a connection point of the first parasitic diode and the second parasitic diode is connected to the substrate; and a first switch, one end of which is connected to the connection point of the first parasitic diode and the second parasitic diode, and the other end of which is connected to the source of the field effect transistor, the first switch is configured to be turned on when the field effect transistor is turned on, so that the source is in communication with the substrate, a conductive channel of the field effect transistor is formed, and the first switch is turned off when the field effect transistor is turned off, so that the source is disconnected from the substrate, the conductive channel of the field effect transistor is not formed, and the substrate is in a floating state; a second switch is connected between the gate and the drain of the field effect transistor, the second switch is configured to ensure that the gate oxide layer of the field effect transistor is not broken down and / or the field effect transistor does not form a conductive channel when the field effect transistor is turned off; the second switch is a voltage-resistant diode, when the field effect transistor is an NMOS transistor, the anode of the voltage-resistant diode is directly or indirectly connected to the gate of the field effect transistor, and the cathode of the voltage-resistant diode is directly or indirectly connected to the drain of the field effect transistor; or when the field effect transistor is a PMOS transistor, the cathode of the voltage-resistant diode is directly or indirectly connected to the gate of the field effect transistor, and the anode of the voltage-resistant diode is directly or indirectly connected to the drain of the field effect transistor; in the case of indirect connection, the second switch and a resistor R form a series circuit, one end of the series circuit is connected to the gate of the field effect transistor, and the other end is connected to the drain of the field effect transistor; or, when the field effect transistor is an NMOS transistor, the second switch is a second NMOS transistor switch, the second NMOS transistor switch has a third parasitic diode, the source of the second NMOS transistor is directly or indirectly connected to the gate of the field effect transistor and one end of the third parasitic diode, and the drain of the second NMOS transistor is directly or indirectly connected to the drain of the field effect transistor and the other end of the third parasitic diode, in the case of indirect connection, the second NMOS transistor switch and a resistor R form a series circuit, one end of the series circuit is connected to the gate of the field effect transistor, and the other end is connected to the drain of the field effect transistor. Or, when the field effect transistor is a PMOS transistor, the second switch is a second PMOS transistor switch, the second PMOS transistor switch has a third parasitic diode, one end of the third parasitic diode and the source of the second PMOS transistor switch are directly or indirectly connected to the gate of the field effect transistor, the other end of the third parasitic diode and the drain of the second PMOS transistor are directly or indirectly connected to the drain of the field effect transistor, in the case of indirect connection, the second PMOS transistor switch and the resistor R form a series circuit, one end of the series circuit is connected to the gate of the field effect transistor, and the other end is connected to the drain of the field effect transistor.

2. The field effect transistor circuit of claim 1, wherein The series circuit of the first parasitic diode and the second parasitic diode is arranged such that no conductive path is formed between the source and the drain through the series circuit.

3. The field effect transistor circuit of claim 2, wherein, The field effect transistor is an NMOS transistor, which is turned on when the gate-source voltage between the gate and the source is greater than the turn-on threshold voltage of the field effect transistor, and is turned off when the gate-source voltage is less than the turn-on threshold voltage. Or, The field effect transistor is a PMOS transistor, which is turned on when the gate-source voltage between the gate and the source is less than the turn-on threshold voltage of the field effect transistor, and is turned off when the gate-source voltage is greater than the turn-on threshold voltage.

4. The field effect transistor circuit of claim 3, wherein, When the field effect transistor is an NMOS transistor, the anode of the first parasitic diode is connected to the anode of the second parasitic diode, the cathode of the first parasitic diode is connected to the drain, and the cathode of the second parasitic diode is connected to the source; or When the field effect transistor is a PMOS transistor, the cathode of the first parasitic diode is connected to the cathode of the second parasitic diode, the anode of the first parasitic diode is connected to the drain, and the anode of the second parasitic diode is connected to the source.

5. The field effect transistor circuit of claim 4, wherein, The first switch is an NMOS and / or PMOS transistor switch, the gate of the transistor switch is connected to the gate of the field effect transistor, the source of the transistor switch is connected to the connection point, and the drain of the transistor switch is connected to the source of the field effect transistor.

6. The field effect transistor circuit of claim 4, wherein, The first switch is a transistor, the base of the transistor is connected to the gate of the field effect transistor via a first resistor, the emitter / collector of the transistor is connected to the connection point, and the collector / emitter of the transistor is connected to the source of the field effect transistor.

7. The field effect transistor circuit of claim 4, wherein, The second switch is a transistor, the emitter / collector of the transistor is connected to the gate of the field effect transistor, and the collector / emitter of the transistor is connected to the drain of the field effect transistor.

8. The field effect transistor circuit of claim 1, wherein, The first switch is replaced by a first Schottky diode and a second Schottky diode, When the field effect transistor is an NMOS transistor, the cathode of the first Schottky diode is connected to the cathode of the second Schottky diode and to the substrate, the anode of the first Schottky diode is connected to the drain, and the anode of the second Schottky diode is connected to the source; or, When the field effect transistor is a PMOS transistor, the anode of the first Schottky diode is connected to the anode of the second Schottky diode and to the substrate, the cathode of the first Schottky diode is connected to the drain, and the cathode of the second Schottky diode is connected to the source.

9. A control method of a field effect transistor circuit according to any one of claims 1 to 8, characterized by, The method comprises: the field effect transistor is controlled to be on, and the first switch is controlled to be on, so that the source is in communication with the substrate; and the field effect transistor is controlled to be off, and the first switch is controlled to be off, so that the source is disconnected from the substrate, and the substrate is in a floating state.

10. A charge / discharge control device for controlling a charge current and / or a discharge current of a battery / battery pack, characterized by, Comprise: a field effect transistor circuit according to any one of claims 1 to 8; and a driving circuit for providing a driving signal to the gate of the field effect transistor of the field effect transistor circuit, so that the field effect transistor is on when the charging current and / or discharging current is normal, and the field effect transistor is off when the charging current and / or discharging current is abnormal.

11. The charge and discharge control device according to claim 10, wherein The field effect transistor circuit is arranged on the positive side or the negative side of the battery / battery pack.

12. The charge and discharge control device according to claim 10, wherein Further comprise: a detection circuit for detecting the charging current and / or discharging current; and a control logic circuit for providing a switching control signal to the driving circuit based on the detection signal of the detection circuit.

13. A chip, characterized by The chip integrates the field effect transistor circuit according to any one of claims 1 to 8, or the charging and discharging control device according to any one of claims 10 to 12.

14. A battery management system, characterized by, Comprise the field effect transistor circuit according to any one of claims 1 to 8, or the charging and discharging control device according to any one of claims 10 to 12.

15. An electrical device, characterized by Comprise: a battery / battery pack for powering other components in the electrical device; and a field effect transistor circuit according to any one of claims 1 to 8 for controlling the charging current or discharging current of the battery / battery pack, or a charging and discharging control device according to any one of claims 10 to 12 for controlling the charging current or discharging current of the battery / battery pack, or a chip according to claim 13 for controlling the charging current or discharging current of the battery / battery pack.

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