Semiconductor device and method of manufacturing the semiconductor device

Abstract

The inventive concept relates to a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a first active pattern and a second active pattern on a substrate, the first and second active patterns being adjacent to each other in a first direction and a first trench being between the first active pattern and the second active pattern. The semiconductor device includes a third active pattern and a fourth active pattern on the substrate, the third and fourth active patterns being adjacent to each other in the first direction and a second trench being between the third active pattern and the fourth active pattern. The semiconductor device includes a first device isolation layer in the first trench and a second device isolation layer in the second trench. A width of the second trench in the first direction is greater than a width of the first trench in the first direction. The second device isolation layer includes a first protrusion and a second protrusion protruding from a top surface of the second device isolation layer.

Description

TECHNICAL FIELD

[0001] Embodiments of the present inventive concept relate to semiconductor devices, and more particularly, to semiconductor devices including field effect transistors and methods of manufacturing the same. BACKGROUND

[0002] Semiconductor devices are widely used in the electronic industry due to their small size, multi-functional characteristics, and / or low manufacturing cost. Some semiconductor devices can be classified as semiconductor memory devices for storing logic data, semiconductor logic devices for processing logic data, and hybrid semiconductor devices having both the functions of semiconductor memory devices and the functions of semiconductor logic devices. As the electronic industry develops, there is a demand for semiconductor devices having excellent characteristics. For example, there is an increasing demand for highly reliable, high-speed, and / or multi-functional semiconductor devices. To meet these demands, semiconductor devices are highly integrated, and structures in semiconductor devices become more complex. SUMMARY

[0003] Embodiments of the present inventive concept can provide semiconductor devices having improved electrical characteristics.

[0004] Embodiments of the present inventive concept can also provide methods of manufacturing semiconductor devices having improved electrical characteristics.

[0005] In some embodiments, a semiconductor device can include a first active pattern and a second active pattern on a substrate, the first active pattern and the second active pattern being adjacent to each other in a first direction with a first trench between the first active pattern and the second active pattern; a third active pattern and a fourth active pattern on the substrate, the third active pattern and the fourth active pattern being adjacent to each other in the first direction with a second trench between the third active pattern and the fourth active pattern; a first device isolation layer in the first trench; and a second device isolation layer in the second trench. A width of the second trench in the first direction can be greater than a width of the first trench in the first direction. The second device isolation layer can include a first protrusion and a second protrusion protruding from a top surface of the second device isolation layer.

[0006] In some embodiments, a semiconductor device can include a substrate including an active region; a device isolation layer on the substrate defining an active pattern on the active region. The active pattern can be in a first direction. The semiconductor device includes a source / drain pattern in an upper portion of the active pattern such that a gate electrode crosses the active pattern and extends in the first direction. The gate electrode is in a second direction crossing the first direction, and an interlayer insulating layer overlaps the source / drain pattern and the gate electrode. The active pattern can include a first active pattern and a second active pattern adjacent to each other in the first direction and a third active pattern and a fourth active pattern adjacent to each other in the first direction. The device isolation layer can include a first device isolation layer between the first active pattern and the second active pattern and a second device isolation layer between the third active pattern and the fourth active pattern. A width of the second device isolation layer in the first direction can be greater than a width of the first device isolation layer in the first direction. The second device isolation layer can include a first protrusion and a second protrusion protruding from a top surface of the second device isolation layer.

[0007] In some embodiments, a semiconductor device can include a first active pattern and a second active pattern on a substrate, a first trench between the first active pattern and the second active pattern; a third active pattern and a fourth active pattern on the substrate, a second trench between the third active pattern and the fourth active pattern; a first device isolation layer in the first trench; a second device isolation layer in the second trench; and a plurality of semiconductor patterns vertically stacked on the active patterns; and a gate electrode overlapping the active patterns, the first trench, and the second trench and extending between semiconductor patterns of the plurality of semiconductor patterns, wherein a first distance between the first active pattern and the second active pattern is less than a second distance between the third active pattern and the fourth active pattern, and wherein the second device isolation layer includes a first protrusion and a second protrusion protruding from a top surface of the second device isolation layer. BRIEF DESCRIPTION OF DRAWINGS

[0008] The present inventive concepts will become more apparent from the detailed description in conjunction with the accompanying drawings.

[0009] FIG. 1 is a flowchart illustrating a method of manufacturing a semiconductor device according to some embodiments of the present inventive concepts.

[0010] FIGS. 2A-2E is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to some embodiments of the present inventive concepts.

[0011] FIG. 3 and FIG. 5 is a plan view illustrating a method of manufacturing a semiconductor device according to some embodiments of the present inventive concepts.

[0012] FIG. 4 andFIG. 6A They are along FIG. 3 and FIG. 5 A sectional view taken by line A-A'.

[0013] FIG. 6B It is along FIG. 5 The sectional view taken by line B-B'.

[0014] FIG. 6C It is along FIG. 5 A sectional view taken by line C-C'.

[0015] FIG. 7 This is a top view illustrating some embodiments of a semiconductor device according to the present invention.

[0016] FIG. 8A , FIG. 8B and FIG. 8C They are along FIG. 7 A sectional view taken from lines A-A', B-B', and C-C'.

[0017] FIGS. 9A-9E This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to some embodiments of the concept of the present invention.

[0018] FIG. 10 , FIG. 12 , FIG. 14 and FIG. 16 This is a top view illustrating a method for manufacturing a semiconductor device according to some embodiments of the concept of the present invention.

[0019] FIG. 11A , FIG. 13A , FIG. 15A and FIG. 17A They are along FIG. 10 , FIG. 12 , FIG. 14 and FIG. 16 A sectional view taken by line A-A'.

[0020] FIG. 11B , FIG. 13B , FIG. 15B and FIG. 17B They are along FIG. 10 , FIG. 12 , FIG. 14 and FIG. 16 The sectional view taken by line B-B'.

[0021] FIG. 13C , FIG. 15C and FIG. 17C They are along FIG. 12 , FIG. 14 and FIG. 16 A sectional view taken by line C-C'.

[0022] FIG. 3-9E This is a top view illustrating some embodiments of a semiconductor device according to the present invention.

[0023] FIG. 3-9E , FIG. 10 and FIG. 11A They are along FIG. 11B A sectional view taken from lines A-A', B-B', and C-C'.

[0024] FIG. 12 This is a top view illustrating some embodiments of a semiconductor device according to the present invention.

[0025] FIG. 13A-13C and FIG. 14 They are along FIG. 15A-15C A sectional view taken by lines A-A' and B-B'. Detailed Implementation

[0026] FIG. 16 This is a flowchart illustrating a method for manufacturing a semiconductor device according to some embodiments of the concept of the present invention. FIG. 17A-17C This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to some embodiments of the concept of the present invention.

[0027] Reference FIG. 18 and FIG. 19A A substrate 100 may be provided. The substrate 100 may be patterned to form an active pattern AP. The active pattern AP may include first to fourth active patterns AP1, AP2, AP3 and AP4. A first trench TR1 may be formed between the first active pattern AP1 and the second active pattern AP2, and a second trench TR2 may be formed between the third active pattern AP3 and the fourth active pattern AP4 (S10). The width W2 of the second trench TR2 in the first direction D1 may be greater than the width W1 of the first trench TR1 in the first direction D1.

[0028] Reference FIG. 19B and FIG. 19C A first insulating layer IL1 may be formed or deposited on the first trench TR1 and the second trench TR2 (S20). The first insulating layer IL1 may include an insulating material such as silicon oxide.

[0029] The first insulating layer IL1 can be formed by chemical vapor deposition (CVD) process.

[0030] Reference FIG. 18 and FIG. 7 A pad layer LIN can be formed on the first insulating layer IL1 (S30). The pad layer LIN can comprise polycrystalline silicon or amorphous silicon. The pad layer LIN can be formed by a CVD process.

[0031] Referring to FIG. 8A-8C and FIG. 7 A second insulating layer IL2 is formed or deposited on the liner layer LIN (S40). The second insulating layer IL2 can include an insulating material such as silicon oxide. The second insulating layer IL2 can be formed by a CVD process.

[0032] Referring to FIG. 8A-8C and FIG. 18 An annealing process can be performed on the substrate 100 after the formation of the second insulating layer IL2 (S50). For example, a rapid thermal annealing (RTA) process can be performed as the annealing process.

[0033] After the annealing process is performed, an etching process can be performed on the second insulating layer IL2 to form a first device isolation layer ST1 and a second device isolation layer ST2 (S60). The first device isolation layer ST1 and the second device isolation layer ST2 can be formed by an anisotropic etching process (e.g., a back etching process) and / or an isotropic etching process. The first device isolation layer ST1 can be formed in the first trench TR1, and the second device isolation layer ST2 can be formed in the second trench TR2. In other words, the first device isolation layer ST1 can be formed between the first active pattern AP1 and the second active pattern AP2, and the second device isolation layer ST2 can be formed between the third active pattern AP3 and the fourth active pattern AP4. A width T2 of the second device isolation layer ST2 in the first direction D1 can be greater than a width T1 of the first device isolation layer ST1 in the first direction D1.

[0034] The proportionality of the device isolation layers can be characterized by an aspect ratio based on a height and a width of the device isolation layers. For example, an aspect ratio of the first device isolation layer ST1 can be greater than an aspect ratio of the second device isolation layer ST2. For example, the aspect ratio of the first device isolation layer ST1 can be in a range of 25 to 100, and the aspect ratio of the second device isolation layer ST2 can be in a range of 1 to 20. Here, the aspect ratio of the first device isolation layer ST1 can be a ratio of a distance from a top surface to a bottom surface (i.e., in the third direction D3) of the first device isolation layer ST1 to a maximum width of the first device isolation layer ST1 in the first direction D1. The aspect ratio of the second device isolation layer ST2 can be a ratio of a distance from a top surface to a bottom surface (i.e., in the third direction D3) of the second device isolation layer ST2 to a maximum width of the second device isolation layer ST2 in the first direction D1.

[0035] As FIG. 19A-19CAs shown, the boundaries of the first insulating layer IL1, the liner layer LIN, and the second insulating layer IL2 can disappear because the etching process is performed. For example, when the liner layer LIN includes polysilicon or amorphous silicon, the polysilicon or the amorphous silicon can be oxidized in the etching process to form silicon oxide.

[0036] The second device isolation layer ST2 can include a first protrusion OH1 and a second protrusion OH2 protruding from a top surface thereof. The first protrusion OH1 and the second protrusion OH2 can be formed of the liner layer LIN. In detail, the polysilicon or the amorphous silicon included in the liner layer LIN can be oxidized to form silicon oxide having a purity higher than respective purities of silicon oxide included in the first insulating layer IL1 and the second insulating layer IL2. As a result, the silicon oxide formed of the liner layer LIN can have an etching resistance higher than respective etching resistances of the first insulating layer IL1 and the second insulating layer IL2. Accordingly, portions of the liner layer LIN can remain to form the first protrusion OH1 and the second protrusion OH2.

[0037] For example, a distance L1 between the third active pattern AP3 and the first protrusion OH1 can be substantially equal to a distance L2 between the fourth active pattern AP4 and the second protrusion OH2.

[0038] FIG. 19B and FIG. 20 are top views showing a method of manufacturing a semiconductor device according to some embodiments of the inventive concept. FIG. 21A and FIG. 21B are cross-sectional views taken along lines A-A' of FIG. 20 and FIG. 18 , respectively. FIG. 19A-19C is a cross-sectional view taken along lines B-B' of FIG. 18 . FIG. 19A-19C is a cross-sectional view taken along lines C-C' of FIG. 20 . Hereinafter, for ease and convenience of explanation, descriptions of technical features common to those mentioned with reference to FIG. 21A and FIG. 21B may be omitted. In other words, differences between embodiments of FIG. 2C , FIG. 2D , ​ , ​ , ​ and ​ and embodiments of ​ and ​ will be mainly described.

[0039] Reference will now be made to ​ and ​A substrate 100 including an active region AR can be provided. The substrate 100 can be patterned to form first to fourth active patterns AP1, AP2, AP3, and AP4 on the active region AR. A first trench TR1 can be formed between the first active pattern AP1 and the second active pattern AP2 adjacent to each other, and a second trench TR2 can be formed between the third active pattern AP3 and the fourth active pattern AP4 adjacent to each other. A depth of the first trench TR1 can be substantially equal to a depth of the second trench TR2.

[0040] A first device isolation layer ST1 and a second device isolation layer ST2 can fill the first trench TR1 and the second trench TR2, respectively. The first device isolation layer ST1 and the second device isolation layer ST2 can be formed by the same method or a similar method as described above with reference to ​

[0041] Referring to ​ and ​ , a sacrificial pattern PP can be formed to cross the first to fourth active patterns AP1, AP2, AP3, and AP4. The sacrificial pattern PP can have a linear or strip shape extending in the first direction D1. For example, the formation of the sacrificial pattern PP can include forming a sacrificial layer on the entire top surface of the substrate 100, forming a hard mask pattern MA on the sacrificial layer, and patterning the sacrificial layer using the hard mask pattern MA as an etching mask. The sacrificial layer can include polysilicon.

[0042] A gate spacer GS can be formed on a sidewall of each of the sacrificial patterns PP. The gate spacer GS can also be formed on an upper portion of a sidewall of each of the first to fourth active patterns AP1, AP2, AP3, and AP4. The upper portion of the sidewall of each of the first to fourth active patterns AP1, AP2, AP3, and AP4 can not be covered by or can not overlap with the first device isolation layer ST1 and the second device isolation layer ST2 and the sacrificial pattern PP, but can be exposed.

[0043] The formation of the gate spacer GS can include conformally forming a gate spacer layer on the entire top surface of the substrate 100 and anisotropically etching the gate spacer layer. For example, the gate spacer layer can include at least one of SiCN, SiCON, and SiN. In some embodiments, the gate spacer layer can be formed of a multi-layer including at least two of SiCN, SiCON, and SiN.

[0044] ​ FIG. 1 is a plan view illustrating a semiconductor device according to some embodiments of the inventive concept. ​ , ​ and ​ are cross-sectional views taken along lines A-A', B-B', and C-C' of FIG. 1, respectively.​​ A sectional view taken from lines A-A', B-B', and C-C'.

[0045] Reference ​ and ​ The substrate 100 may include an active region AR. In some embodiments, the active region AR may be a PMOSFET region or an NMOSFET region.

[0046] First to fourth active patterns AP1, AP2, AP3, and AP4 can be provided on the active region AR. The first to fourth active patterns AP1, AP2, AP3, and AP4 can be formed by patterning the substrate 100. The first to fourth active patterns AP1, AP2, AP3, and AP4 can be vertically projecting portions of the substrate 100. The first to fourth active patterns AP1, AP2, AP3, and AP4 can extend parallel to each other in the second direction D2. A first trench TR1 can be formed between adjacent first active patterns AP1 and second active patterns AP2, and a second trench TR2 can be formed between adjacent third active patterns AP3 and fourth active patterns AP4.

[0047] First device isolation layer ST1 and second device isolation layer ST2 can respectively fill first trench TR1 and second trench TR2. First device isolation layer ST1 and second device isolation layer ST2 can be configured with reference to the above. ​ The same or similar methods described are used for formation. The width T2 of the second device isolation layer ST2 may be greater than the width T1 of the first device isolation layer ST1. The second device isolation layer ST2 may include a first protrusion OH1 and a second protrusion OH2 projecting from the top surface of the second device isolation layer ST2. For example, the distance L1 between the third active pattern AP3 and the first protrusion OH1 may be substantially equal to the distance L2 between the fourth active pattern AP4 and the second protrusion OH2.

[0048] The upper portions of the first to fourth active patterns AP1, AP2, AP3, and AP4 can protrude vertically upward from the first device isolation layer ST1 and the second device isolation layer ST2. Each of the upper portions of the first to fourth active patterns AP1, AP2, AP3, and AP4 can have a fin shape. The first device isolation layer ST1 and the second device isolation layer ST2 can not cover or can not overlap the upper portions of the first to fourth active patterns AP1, AP2, AP3, and AP4. The first device isolation layer ST1 and the second device isolation layer ST2 can cover, overlap, or can be in contact with sidewalls of lower portions of the first to fourth active patterns AP1, AP2, AP3, and AP4.

[0049] A source / drain pattern SD can be provided in the upper portions of the first to fourth active patterns AP1, AP2, AP3, and AP4. The source / drain pattern SD can be a P-type or N-type dopant region. A channel pattern CH can be disposed between a pair of source / drain patterns SD.

[0050] The source / drain pattern SD can include an epitaxial pattern formed using a selective epitaxial growth (SEG) process. Upon forming the source / drain pattern SD, the channel pattern CH can be defined between the source / drain patterns SD. For example, the SEG process can include a CVD process or a molecular beam epitaxy (MBE) process.

[0051] In some embodiments, a top surface of the source / drain pattern SD can be substantially coplanar with a top surface of the channel pattern CH. In some embodiments, the top surface of the source / drain pattern SD can be higher than the top surface of the channel pattern CH with respect to the substrate.

[0052] The source / drain pattern SD can include a second semiconductor element for which a lattice constant is greater than a lattice constant of a first semiconductor element of the substrate 100. For example, the first semiconductor element can be silicon (Si), and the second semiconductor element can be germanium (Ge). In some embodiments, the source / drain pattern SD can be formed of a plurality of stacked semiconductor layers. The formation of the source / drain pattern SD can include sequentially forming the semiconductor layers. For example, the semiconductor layers can include a buffer layer, a main layer, and a cap layer.

[0053] The gate electrode GE can extend in the first direction D1 to cross the first to fourth active patterns AP1, AP2, AP3, and AP4. The gate electrode GE can be aligned in the second direction D2. The gate electrode GE can overlap the channel pattern CH perpendicularly with respect to the third direction D3.

[0054] A pair of gate spacers GS can be disposed on two sidewalls of each gate electrode GE, respectively. The gate spacers GS can extend along the gate electrode GE in the first direction D1. A top surface of the gate spacer GS can be higher than a top surface of the gate electrode GE in the third direction D3 with respect to the substrate. The top surface of the gate spacer GS can be coplanar with a top surface of the first interlayer insulating layer 110, which will be described later. The gate spacer GS can include at least one of SiCN, SiCON, and SiN. In some embodiments, each gate spacer GS can have a multi-layer structure formed of at least two of SiCN, SiCON, and SiN.

[0055] A gate cap pattern GP can be provided on each gate electrode GE. The gate cap pattern GP can extend along the gate electrode GE in the first direction D1. The gate cap pattern GP can include a material having etch selectivity with respect to the first interlayer insulating layer 110 and the second interlayer insulating layer 120, which will be described later. For example, the gate cap pattern GP can include at least one of SiON, SiCN, SiCON, and SiN.

[0056] A gate dielectric pattern GI can be disposed between the gate electrode GE and the active patterns AP1 to AP4. The gate dielectric pattern GI can extend along a bottom surface of the gate electrode GE thereon. For example, the gate dielectric pattern GI can cover or overlap a top surface and sidewalls of the channel pattern CH. The gate dielectric pattern GI can cover or overlap a top surface of the device isolation layers ST1 and ST2 under the gate electrode GE. The gate dielectric pattern GI can cover or overlap a top surface of the first and second protrusions OH1 and OH2 on the second device isolation layer ST2.

[0057] In some embodiments, the gate dielectric pattern GI can include a high-k dielectric material having a dielectric constant higher than that of silicon oxide. For example, the high-k dielectric material can include at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0058] The gate electrode GE can include a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern can be provided on the gate dielectric pattern GI and can be adjacent to the channel pattern CH. The first metal pattern can include a work function metal for adjusting a threshold voltage of the transistor. A desired threshold voltage can be obtained by adjusting a thickness and / or composition of the first metal pattern.

[0059] The first metal pattern can include a metal nitride layer. For example, the first metal pattern can include nitrogen (N) and at least one metal selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo). The first metal pattern can further include carbon (C). In some embodiments, the first metal pattern can include a plurality of stacked work function metal layers.

[0060] The second metal pattern can include a metal having a lower electrical resistance than the first metal pattern. For example, the second metal pattern can include at least one metal selected from the group consisting of tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta).

[0061] A first interlayer insulating layer 110 can be provided on the substrate 100. The first interlayer insulating layer 110 can cover the gate spacers GS and the source / drain pattern SD, overlap the gate spacers GS and the source / drain pattern SD, or be adjacent to the gate spacers GS and the source / drain pattern SD. A top surface of the first interlayer insulating layer 110 can be substantially coplanar with a top surface of the gate cap pattern GP and a top surface of the gate spacer GS. A second interlayer insulating layer 120 can be provided on the first interlayer insulating layer 110, covering or overlapping the gate cap pattern GP.

[0062] The active contacts AC can penetrate the second interlayer insulating layer 120 and the first interlayer insulating layer 110, thereby electrically connecting to the source / drain pattern SD. Each active contact AC can be provided between a pair of gate electrodes GE.

[0063] The active contacts AC can be self-aligned contacts. In other words, the active contacts AC can be formed to be self-aligned using the gate cap pattern GP and the gate spacer GS. For example, the active contacts AC can cover, overlap, or be adjacent to at least a portion of a sidewall of the gate spacer GS. Even though not shown in the drawings, the active contacts AC can cover, overlap, or be adjacent to a portion of a top surface of the gate cap pattern GP.

[0064] A silicide pattern SC can be disposed between the active contact AC and the source / drain pattern SD. The active contact AC can be electrically connected to the source / drain pattern SD through the silicide pattern SC. The silicide pattern SC can include a metal silicide, and can include at least one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide, for example.

[0065] The active contact AC can include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. For example, the conductive pattern FM can include at least one metal of aluminum, copper, tungsten, molybdenum, and cobalt. The barrier pattern BM can cover, overlap, or be adjacent to a bottom surface and sidewalls of the conductive pattern FM. The barrier pattern BM can include a metal layer / metal nitride layer. The metal layer can include at least one of titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride layer can include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN).

[0066] Referring again to ​ , the gate electrode GE can surround a top surface and two sidewalls of each channel pattern CH. In other words, the transistor according to the present embodiment can be a three-dimensional (3D) field effect transistor (e.g., a FinFET) in which the gate electrode GE three-dimensionally surrounds the channel pattern CH.

[0067] ​ is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to some embodiments of the present inventive concept. Hereinafter, for ease and convenience of explanation, the description of the same technical features mentioned with reference to ​ and ​ will be omitted. In other words, the differences between the present embodiment and the embodiments of ​ and ​ will be mainly described.

[0068] Referring to ​ , the sacrificial layers SAC and the semiconductor layers SEL can be alternately and repeatedly stacked over the entire top surface of the substrate 100. In ​ , three semiconductor layers SEL are stacked. However, embodiments of the present inventive concept are not limited thereto. In some embodiments, the sacrificial layers SAC can include a material having etch selectivity with respect to the semiconductor layers SEL. In other words, the semiconductor layers SEL can include a material that can not be etched in a process of etching the sacrificial layers SAC. For example, the sacrificial layers SAC can include silicon germanium (SiGe) or germanium (Ge), and the semiconductor layers SEL can include silicon (Si).

[0069] The sacrificial layer SAC, semiconductor layer SEL, and substrate 100 can be patterned to form first to fourth active patterns AP1, AP2, AP3, and AP4. A first trench TR1 can be formed between the first active pattern AP1 and the second active pattern AP2, and a second trench TR2 can be formed between the third active pattern AP3 and the fourth active pattern AP4. (Refer to the above.) ​ The first insulating layer IL1, the padding layer LIN, and the second insulating layer IL2 can be sequentially deposited on the first trench TR1 and the second trench TR2, and the deposited layers IL1, LIN and IL2 can be etched to form the first device isolation layer ST1 and the second device isolation layer ST2.

[0070] ​ , ​ , ​ and ​ This is a top view illustrating a method for manufacturing a semiconductor device according to some embodiments of the concept of the present invention. ​ , ​ , ​ and ​ They are along ​ , ​ , ​ and ​ A sectional view taken by line A-A'. ​ , ​ , ​ and ​ They are along ​ , ​ , ​ and ​ The sectional view taken by line B-B'. ​ , ​ and ​ They are along ​ , ​ and ​ The sectional view is taken along line C-C'. For ease of explanation and convenience, references will be omitted in the following text. ​ The description will focus on the same technical features mentioned. In other words, the description will primarily focus on this embodiment and... ​ Differences between implementation methods.

[0071] Reference ​ , ​ and ​ An initial pattern PAP can be formed on the active region AR of the substrate 100 by patterning an alternately and repeatedly stacked sacrificial layer SAC and a semiconductor layer SEL on the substrate 100. In the patterning process, the upper part of the substrate 100 can be etched to form a first trench TR1 and a second trench TR2 defining the first to fourth active patterns AP1, AP2, AP3 and AP4.

[0072] The initial pattern PAP can be disposed on the active patterns AP1 to AP4, respectively. The initial pattern PAP can vertically overlap the active patterns AP1 to AP4 in a direction perpendicular to the substrate, respectively. In other words, a planar shape of each initial pattern PAP can be substantially the same as a planar shape of a corresponding one of the active patterns AP1 to AP4. The initial pattern PAP and the active patterns AP1 to AP4 can have a linear or strip shape extending in the second direction D2.

[0073] Referring to ​ and ​ , the sacrificial patterns PP can be formed to cross the initial pattern PAP. Each sacrificial pattern PP can have a linear or strip shape extending in the first direction D1. The sacrificial patterns PP can be formed using the mask pattern MA thereon as an etching mask. A pair of gate spacers GS can be formed on two side walls of each sacrificial pattern PP, respectively.

[0074] Referring to ​ and ​ , the initial pattern PAP can be etched using the mask pattern MA and the gate spacers GS as etching masks, thereby forming a channel pattern CH. The semiconductor layer SEL of the initial pattern PAP can be patterned to form first to third semiconductor patterns SP1, SP2, and SP3. The channel pattern CH can include the first to third semiconductor patterns SP1, SP2, and SP3.

[0075] In addition, by etching the initial pattern PAP, a pair of recesses can be formed on both sides of the channel pattern CH, respectively. A source / drain pattern SD can be formed to fill the recesses. Formation of the source / drain pattern SD can include performing a selective epitaxial growth (SEG) process using the active patterns AP1 to AP4 and the first to third semiconductor patterns SP1, SP2, and SP3 as seed layers.

[0076] Referring to ​ and ​ , the first interlayer insulating layer 110 can be formed on the substrate 100. Next, a planarization process can be performed on the first interlayer insulating layer 110 until a top surface of the sacrificial pattern PP is exposed.

[0077] The sacrificial pattern PP exposed by the planarization process can be selectively removed. By removing the sacrificial pattern PP, an empty space can be formed between a pair of gate spacers GS adjacent to each other. The empty space can expose the first to third semiconductor patterns SP1, SP2, and SP3 and the sacrificial layer SAC.

[0078] The sacrificial layer SAC exposed by the empty space can be selectively removed. For example, when the sacrificial layer SAC includes silicon germanium (SiGe) and the first to third semiconductor patterns SP1, SP2, and SP3 include silicon (Si), a selective etching process can be performed using an etching solution including peracetic acid. The etching solution can also include a hydrofluoric acid (HF) aqueous solution and deionized water.

[0079] ​ FIG. 1 is a plan view illustrating a semiconductor device according to some embodiments of the inventive concept. ​ 、 ​ and ​ are cross-sectional views taken along lines A-A', B-B', and C-C' of ​ , respectively. Hereinafter, for ease and convenience of explanation, the description of the same technical features mentioned with reference to ​ and ​ will be omitted. In other words, the differences between the present embodiments and the embodiments of ​ and ​ will be mainly described.

[0080] Referring to ​ and ​ , a substrate 100 including an active region AR can be provided. The substrate 100 can be patterned to form first to fourth active patterns AP1, AP2, AP3, and AP4 on the active region AR. A first device isolation layer ST1 can be formed between the first active pattern AP1 and the second active pattern AP2, and a second device isolation layer ST2 can be formed between the third active pattern AP3 and the fourth active pattern AP4. A width T2 of the second device isolation layer ST2 can be greater than a width T1 of the first device isolation layer ST1. The second device isolation layer ST2 can include a first protrusion OH1 and a second protrusion OH2 protruding from a top surface thereof.

[0081] Each of the first to fourth active patterns AP1 to AP4 can include a channel pattern CH including vertically stacked semiconductor patterns SP1 to SP3. The stacked semiconductor patterns SP1 to SP3 can be spaced apart from each other in a third direction D3 perpendicular to the substrate 100. The stacked semiconductor patterns SP1 to SP3 can vertically overlap each other. The stacked semiconductor patterns SP1 to SP3 can function as a channel region. The semiconductor patterns SP1 to SP3 can include at least one of silicon (Si), germanium (Ge), and silicon germanium (SiGe).

[0082] The first to fourth active patterns AP1, AP2, AP3, and AP4 can further include a source / drain pattern SD. A stacked semiconductor pattern SP1 to SP3 can be disposed between a pair of source / drain patterns SD adjacent to each other. The stacked semiconductor pattern SP1 to SP3 can connect the pair of source / drain patterns SD adjacent to each other.

[0083] The gate electrode GE can cross the channel pattern CH and can extend in the first direction Dl. The gate electrode GE can overlap the channel pattern CH perpendicularly. A pair of gate spacers GS can be respectively disposed on two sidewalls of the gate electrode GE. A gate cap pattern GP can be provided on the gate electrode GE.

[0084] A gate dielectric pattern GI can be provided between the gate electrode GE and each of the semiconductor patterns SP1 to SP3. The gate dielectric pattern GI can surround each of the semiconductor patterns SP1 to SP3. The gate dielectric pattern GI can cover or overlap a top surface of the first and second protrusions OH1 and OH2 on the second device isolation layer ST2.

[0085] The first and second interlayer insulating layers 110 and 120 can be provided on the entire top surface of the substrate 100. The active contact AC can penetrate the second interlayer insulating layer 120 and the first interlayer insulating layer 110, thereby connecting to the source / drain pattern SD.

[0086] The gate electrode GE can surround each of the semiconductor patterns SP1 to SP3 (see ​ ). The gate electrode GE can be provided on a top surface, at least one sidewall, and a bottom surface of each of the semiconductor patterns SP1 to SP3. In other words, the gate electrode GE can surround a top surface, a bottom surface, and two sidewalls of each of the semiconductor patterns SP1 to SP3. In other words, in addition to being adjacent to the semiconductor patterns SP1 to SP3 in the first direction Dl parallel to the substrate 100, the gate electrode GE can be between the semiconductor patterns SP1 to SP3. The transistor according to the present embodiment can be a 3D field effect transistor (e.g., MBCFET) in which the gate electrode GE three-dimensionally surrounds each of the semiconductor patterns SP1 to SP3.

[0087] ​ is a plan view showing a semiconductor device according to some embodiments of the present inventive concept. ​ and ​ are cross-sectional views taken along lines A-A' and B-B' of ​ , respectively. Hereinafter, for ease and convenience of explanation, the description of the reference numerals common to the drawings for the reference numerals of ​ and ​The description of the same technical features referred to. In other words, the differences between the embodiments of the present application will be mainly described with ​ and ​ .

[0088] Referring to ​ , ​ and ​ , the width A1 of the first active pattern AP1 and the second active pattern AP2 adjacent to the first device isolation layer ST1 in the first direction D1 can be equal to each other. The width A2 of the third active pattern AP3 and the fourth active pattern AP4 adjacent to the second device isolation layer ST2 in the first direction D1 can be equal to each other. In some embodiments, the width A2 of each of the third active pattern AP3 and the fourth active pattern AP4 in the first direction D1 can be greater than the width A1 of each of the first active pattern AP1 and the second active pattern AP2 in the first direction D1.

[0089] According to the embodiments of the inventive concept, a liner layer can be deposited on the insulating layer in the process of forming the device isolation layer, as shown in ​ and ​ . Accordingly, the etch resistance (e.g., wet etch resistance) of the device isolation layer having a relatively large width can be improved.

[0090] Although the inventive concept has been described with reference to example embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the inventive concept. It is therefore intended that such changes and modifications be within the scope of the inventive concept as defined by the appended claims and their equivalents, and should not be restricted or limited by the foregoing description or illustration. Accordingly, the above embodiments are not restrictive, but illustrative. Therefore, the scope of the inventive concept will be determined by the widest permissible interpretation of the appended claims and their equivalents, and should not be bound or limited by the foregoing description or illustration.

[0091] This application claims priority to Korean Patent Application No. 10-2019-0130689, filed on October 21, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

Claims

1. A semiconductor device comprising: a first active pattern and a second active pattern on a substrate, the first active pattern and the second active pattern adjacent to each other in a first direction with a first trench between the first active pattern and the second active pattern; a third active pattern and a fourth active pattern on the substrate, the third active pattern and the fourth active pattern adjacent to each other in the first direction with a second trench between the third active pattern and the fourth active pattern; a first device isolation layer in the first trench; and a second device isolation layer in the second trench, wherein a width of the second trench in the first direction is greater than a width of the first trench in the first direction, wherein the second device isolation layer includes a first protrusion and a second protrusion protruding from a top surface of the second device isolation layer, wherein the first protrusion and the second protrusion are spaced apart from the third active pattern and the fourth active pattern, and wherein the first protrusion and the second protrusion include a same material as the second device isolation layer.

2. The semiconductor device of claim 1, wherein a distance between the third active pattern and the first protrusion is substantially equal to a distance between the fourth active pattern and the second protrusion.

3. The semiconductor device of claim 1, wherein an aspect ratio of the first device isolation layer is in a range of 25 to 100.

4. The semiconductor device of claim 1, wherein an aspect ratio of the second device isolation layer is in a range of 1 to 20.

5. The semiconductor device of claim 1, wherein a width of each of the third active pattern and the fourth active pattern in the first direction is greater than a width of each of the first active pattern and the second active pattern in the first direction.

6. The semiconductor device of claim 1, further comprising: a source / drain pattern provided in an upper portion of the first active pattern to the fourth active pattern; and a gate electrode crossing the first active pattern to the fourth active pattern.

7. The semiconductor device of claim 6, wherein the upper portion of the first active pattern to the fourth active pattern protrudes from the first device isolation layer and the second device isolation layer in a direction perpendicular to the substrate.

8. The semiconductor device of claim 6, wherein each of the first active pattern to the fourth active pattern includes a channel pattern, the channel pattern including a vertically stacked semiconductor pattern, and wherein the gate electrode is on a top surface, a bottom surface, and two sidewalls of each of the semiconductor pattern.

9. A semiconductor device comprising: a substrate including an active region; a device isolation layer on the substrate, the device isolation layer defining active patterns on the active region, wherein the active patterns are spaced apart in a first direction; a source / drain pattern in an upper portion of the active patterns; a gate electrode crossing the active patterns and extending in the first direction, wherein the gate electrode is in a second direction crossing the first direction; and ​ an interlayer insulating layer overlapping the source / drain pattern and the gate electrode, wherein the active pattern includes a first active pattern and a second active pattern adjacent to each other in the first direction and a third active pattern and a fourth active pattern adjacent to each other in the first direction, wherein the device isolation layer includes a first device isolation layer between the first active pattern and the second active pattern and a second device isolation layer between the third active pattern and the fourth active pattern, wherein a width of the second device isolation layer in the first direction is greater than a width of the first device isolation layer in the first direction, wherein the second device isolation layer includes a first protrusion and a second protrusion protruding from a top surface of the second device isolation layer, wherein the first protrusion and the second protrusion are spaced apart from the third active pattern and the fourth active pattern, and wherein the first protrusion and the second protrusion include a same material as the second device isolation layer.

10. The semiconductor device of claim 9, wherein the active region is a PMOSFET region or an NMOSFET region.

11. The semiconductor device of claim 9, wherein a distance between the third active pattern and the first protrusion is substantially equal to a distance between the fourth active pattern and the second protrusion.

12. The semiconductor device of claim 9, wherein an aspect ratio of the first device isolation layer is in a range of 25 to 100.

13. The semiconductor device of claim 9, wherein an aspect ratio of the second device isolation layer is in a range of 1 to 20.

14. The semiconductor device of claim 9, wherein a width of each of the third active pattern and the fourth active pattern in the first direction is greater than a width of each of the first active pattern and the second active pattern in the first direction.

15. A semiconductor device, comprising: a first active pattern and a second active pattern on a substrate, a first trench between the first active pattern and the second active pattern; a third active pattern and a fourth active pattern on the substrate, a second trench between the third active pattern and the fourth active pattern; a first device isolation layer in the first trench; a second device isolation layer in the second trench; a plurality of semiconductor patterns vertically stacked on the active patterns; and a gate electrode overlapping the active patterns, the first trench, and the second trench and extending between semiconductor patterns of the plurality of semiconductor patterns, wherein a first distance between the first active pattern and the second active pattern is less than a second distance between the third active pattern and the fourth active pattern, wherein the second device isolation layer includes a first protrusion and a second protrusion protruding from a top surface of the second device isolation layer, wherein the first protrusion and the second protrusion are spaced apart from the third active pattern and the fourth active pattern, and wherein the first protrusion and the second protrusion include a same material as the second device isolation layer.

16. The semiconductor device of claim 15, wherein the first protrusion and the second protrusion protrude into the gate electrode.

17. The semiconductor device of claim 15, further comprising: a gate dielectric pattern on top surfaces of the first protrusion and the second protrusion, overlapping the second device isolation layer.

18. The semiconductor device of claim 15, wherein a distance between the third active pattern and the first protrusion is substantially equal to a distance between the fourth active pattern and the second protrusion.

19. The semiconductor device of claim 15, wherein an aspect ratio of the first device isolation layer is in a range of 25 to 100.

20. The semiconductor device of claim 15, wherein an aspect ratio of the second device isolation layer is in a range of 1 to 20.

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