Array of strings extending across the height of a memory cell and method of forming the same

Abstract

The present application relates to an array of strings extending in height of memory cells and methods of forming the same. The memory cells individually include programmable charge storage transistors, and a substrate includes a first region containing the memory cells and a second region transverse to the first region that does not contain the memory cells. The first region includes vertical alternating stacks of insulating material and control gate material. The second region includes vertical alternating stacks of insulating materials of different compositions transverse to the first region. Channel pillars including semiconducting channel material extend in height through multiple of the vertical alternating stacks in the first region. Tunnel insulators, programmable charge storage materials, and control gate blocking insulators are interposed between the channel pillars and the control gate material of individual ones of the stacks of the control gate material in the first region.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application of the Chinese invention patent application entitled “Array of strings extending at the height of memory cells and method for forming the same”, application number 201710677023.X, and application date August 9, 2017. Technical Field

[0003]

[0014] Embodiments disclosed herein relate to arrays of highly extended strings of memory cells comprising programmable charge storage transistors and to methods of forming such arrays. Background Art

[0004] Memory provides data storage for electronic systems. Flash memory is a type of memory with numerous uses in computers and other devices. For example, a personal computer may have the BIOS stored on a flash memory chip. As another example, flash memory is used in solid-state drives to replace rotating hard disk drives. As yet another example, flash memory is used in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized and provides the ability to remotely upgrade devices to obtain improved or enhanced features.

[0005] Typical flash memory includes a memory array comprising a large number of memory cells arranged in rows and columns. Flash memory can be erased and reprogrammed in blocks. NAND may be the basic architecture of flash memory. A NAND cell unit includes at least one select device coupled in series to a series combination of memory cells (where the series combination is often referred to as a NAND string). An exemplary NAND architecture is described in U.S. Patent No. 7,898,850.

[0006] Memory cell strings can be arranged to extend horizontally or vertically. Compared to horizontally extending memory cell strings, vertical memory cell strings reduce the horizontal area of ​​the substrate occupied by the memory cells, although typically at the expense of increased vertical thickness. At least some conductive vias of the memory circuitry may need to extend through the increased vertical thickness, for example, to connect to control circuitry (either laterally adjacent to the array of memory cell strings or located below the array). Summary of the Invention

[0007] In some embodiments, a method of forming an array of vertically extending strings of memory cells, wherein each of the memory cells comprises a programmable charge storage transistor, comprises forming a stack comprising vertically alternating layers of insulating materials of different compositions. A vertically extending channel opening is formed through the alternating layers, and a vertically extending wall opening is formed through the alternating layers. The wall opening is laterally spaced from a row of the channel openings and extends horizontally alongside the row of the channel openings. A programmable charge storage material and a semiconducting channel material are formed into the channel openings and into the wall openings to form, for each of the vertically extending strings, vertically extending pillars comprising the semiconducting channel material and the programmable charge storage material in each of the channel openings and vertically extending walls in the wall openings. The walls comprise the programmable charge storage material and the semiconducting channel material and extend horizontally alongside the channel openings along the row. The walls comprise a first side facing the pillars and a second side opposite the first side facing away from the pillars. After forming the wall, an access opening is formed on the first side of the wall through the alternating stacks of insulating materials of different compositions. An insulating material of one composition of the insulating materials of different compositions, interposed between the stacks of insulating materials of another composition, is isotropically etched through the access opening. The insulating material of one composition is replaced on the first side of the wall with the control gate material of the memory cell. During the isotropic etching, the wall restricts lateral passage of an etching fluid from the first side of the wall to the second side of the wall. Finally, a height-extending conductive via is provided on the second side of the wall through the alternating stacks of insulating materials of different compositions.

[0008] In some embodiments, an array of vertically extending strings of memory cells, each of which comprises a programmable charge storage transistor, comprises a substrate comprising a first region containing memory cells and a second region laterally disposed therefrom that does not contain memory cells. The first region comprises a vertically alternating stack of insulating material and control gate material. The second region comprises a vertically alternating stack of insulating material of a different composition laterally disposed therefrom. A channel pillar comprising a semiconducting channel material extends vertically through multiple of the vertically alternating stacks within the first region. A tunnel insulator, a programmable charge storage material, and a control gate blocking insulator are interposed between the channel pillar and the control gate material of each of the stacks of control gate material within the first region. A conductive via extends vertically through the vertically alternating stack in the second region. A vertically extending wall is laterally disposed therebetween. The wall comprises the programmable charge storage material and the semiconducting channel material.

[0009] In some embodiments, an array of vertically extending strings of memory cells, wherein each of the memory cells comprises a programmable charge storage transistor, comprises a substrate comprising a first region containing the memory cells and a second region lateral to the first region that does not contain the memory cells. The first region comprises a vertically alternating stack of insulating material and control gate material. The second region comprises a vertically alternating stack of insulating material of a different composition lateral to the first region. A channel pillar comprising a semiconducting channel material extends vertically through multiple of the vertically alternating stacks within the first region. A tunnel insulator, a programmable charge storage material, and a control gate blocking insulator are interposed between the channel pillar and the control gate material of each of the stacks of control gate material within the first region. A conductive via extends vertically through the vertically alternating stack in the second region. A vertically extending wall completely surrounds an island comprising the conductive via. The wall comprises the programmable charge storage material and the semiconducting channel material.

[0010] In compliance with the statute, the subject matter disclosed herein has been described in language more or less specific with respect to structural and methodological features. However, it should be understood that, since the methods disclosed herein include exemplary embodiments, the claims are not limited to the specific features shown and described. Accordingly, the claims are to be given the full scope given by their literal language and appropriately interpreted in accordance with the doctrine of equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a diagrammatic top plan view of a configuration under fabrication of an array including elevated strings of memory cells in accordance with an embodiment of the present invention.

[0012] Figure 2 It passes through Figure 1 A cross-sectional view taken along line 2-2 in FIG.

[0013] Figure 3 is in the Figure 1 The processing steps after the steps shown are Figure 1 Constructed view.

[0014] Figure 4 It passes through Figure 3 A cross-sectional view taken along line 4-4 in FIG.

[0015] Figure 5 is in the Figure 3 The processing steps after the steps shown are Figure 3 Constructed view.

[0016] Figure 6It passes through Figure 5 A cross-sectional view taken along line 6-6 in FIG.

[0017] Figure 7 is in the Figure 5 The processing steps after the steps shown are Figure 5 Constructed view.

[0018] Figure 8 It passes through Figure 7 A cross-sectional view taken along line 8-8 in FIG.

[0019] Figure 9 is in the Figure 7 The processing steps after the steps shown are Figure 7 Constructed view.

[0020] Figure 10 It passes through Figure 9 A cross-sectional view taken along line 10-10 in FIG.

[0021] Figure 11 is in the Figure 9 The processing steps after the steps shown are Figure 9 Constructed view.

[0022] Figure 12 It passes through Figure 11 A cross-sectional view taken along line 12-12 in FIG.

[0023] Figure 13 is in the Figure 11 The processing steps after the steps shown are Figure 11 Constructed view.

[0024] Figure 14 It passes through Figure 13 A cross-sectional view taken along line 14-14 in FIG.

[0025] Figure 15 is in the Figure 13 The processing steps after the steps shown are Figure 13 Constructed view.

[0026] Figure 16 It passes through Figure 15 A cross-sectional view taken along line 16-16 in FIG.

[0027] Figure 17 is a diagrammatic top plan view of a configuration under fabrication of an array including elevated strings of memory cells in accordance with an embodiment of the present invention.

[0028] Figure 18 It passes through Figure 17 A cross-sectional view taken along line 18-18 in FIG. DETAILED DESCRIPTION

[0029] Embodiments of the present invention encompass methods of forming arrays of height-extending strings of memory cells and arrays of height-extending strings of memory cells independent of fabrication methods. Regardless, the memory cells individually comprise programmable charge storage transistors. In this document, "height-extending" and "extending in height" refer to directions angled at least 45° away from a major surface relative to which the substrate is processed during fabrication and which can be considered to define a generally horizontal direction. Furthermore, as used herein, "vertical" and "horizontal" refer to directions that are generally perpendicular to one another in three-dimensional space, independent of the orientation of the substrate. Furthermore, and unless otherwise stated, "height-extending," "higher," "upper," "lower," "top," "above," "below," "below," "under," "upward," and "downward" are generally referenced to vertical directions. Furthermore, "height-extending" and "extending in height" relative to a field effect transistor are referenced to the orientation of the transistor's channel length, along which current flows between the source / drain regions during operation.

[0030] refer to Figure 1 and 2 , the substrate segment or construction 10 may be considered to include a base substrate 12, which may include any one or more of a conductive / conductive / conductive (i.e., herein electrical), semiconductive, or insulating / insulator / insulating (i.e., herein electrical) material. Various materials are shown above the base substrate 12. The materials may be Figure 1 and 2 Next to the depicted material, Figure 1 and 2 The depicted materials are depicted vertically inward or vertically outward. For example, other partially or completely fabricated integrated circuit components may be located somewhere on, around, or within substrate 12. Control and / or other peripheral circuits for operating components within the memory array may also be fabricated and may or may not be completely or partially located within the memory array or subarray. Further, multiple subarrays may also be fabricated and operated independently, in series, or otherwise relative to each other. As used in this document, "subarray" may also be considered an array. In any event, any of the materials, regions, and structures described herein may be homogeneous or inhomogeneous, and in any event may be continuous or discontinuous over any material overlying such materials, regions, and structures. Further, unless otherwise stated, each material may be formed using any suitable or yet-to-be-developed technique, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation being examples.

[0031] Construction 10 can be viewed as including a first region 14 that will contain memory cells and a second region 16 that will not contain memory cells and that is laterally adjacent to first region 14 (in one embodiment and as shown, laterally adjacent to first region 14). First region 14 and second region 16 can be laterally continuous across a substrate or a memory array region of a substrate, or can include only respective portions thereof. First region 14 and second region 16 can both be part of or located within a memory array. Alternatively, as an example, first region 14 can be part of a memory array and second region 16 can be located laterally to the memory array. Regardless, regions 14 and 16 can be used to define horizontal regions that will contain (14) and will not contain (16) memory cells, regardless of the size, shape, etc. of those regions.

[0032] An exemplary substrate 12 includes a semiconductor material 17 (e.g., single crystal silicon) having a conductively doped source material 19 formed thereon or therein within a first region 14, and may include a portion of the circuitry for a string extending vertically for the memory cell being fabricated. An insulator 20 (e.g., doped or undoped silicon dioxide and / or silicon nitride) is shown laterally adjacent to material 19 and extending into a second region 16, and an insulator 18 (e.g., doped or undoped silicon dioxide and / or silicon nitride) is shown located in the first and second regions 14, 16, vertically between semiconductor material 17 and materials 19, 20. Exemplary source material 19 is conductively doped polysilicon approximately 500 angstroms thick located above an underlying tungsten silicide approximately 900 angstroms thick. Insulator 20 may have the same thickness as source material 19, as shown. An exemplary thickness for insulator 18 is from approximately 2,000 angstroms to 5,000 angstroms.

[0033] In this document, "thickness" by itself (without the aforementioned directional adjectives) is defined as the average straight-line distance perpendicularly through a given material or region from the closest surface of the adjacent material or adjacent region of different composition. In addition, the various materials or regions described herein may have a substantially constant thickness or a variable thickness. If having a variable thickness, then the thickness refers to the average thickness, unless otherwise indicated, and such material or region will have some minimum thickness and some maximum thickness due to the variable thickness. As used herein, "different compositions" only require that those portions of the two stated materials or regions that can directly abut each other are chemically and / or physically different (for example, assuming that such materials or regions are not homogeneous). If the two stated materials or regions do not directly abut each other, then "different compositions" only require that those portions of the two stated materials or regions that are closest to each other are chemically and / or physically different (assuming that such materials or regions are not homogeneous). In this document, a stated material, region, or structure is "directly abutting" another when there is at least some physical touching contact of the materials, regions, or structures relative to each other. In contrast, "over," "on," "along," and "against" without being preceded by "directly" encompass "directly against" as well as configurations in which intervening materials, regions, or structures do not result in physical touching contact of the stated materials, regions, or structures relative to each other.

[0034] Semiconductor material 17 is shown having a conductive region 22 therein, which is located within second region 16 and to which the conductive via to be formed will be electrically coupled (in one embodiment, directly electrically coupled). In this document, regions / materials / components are "electrically coupled" relative to one another if, during normal operation, current can flow continuously from one region / material / component to the other, primarily through the movement of subatomic positive and / or negative charges (if such charges are sufficiently generated). Another electronic component may be interposed between the regions / materials / components and electrically coupled to them. In contrast, when regions / materials / components are referred to as "directly electrically coupled," no intervening electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) are interposed between the directly electrically coupled regions / materials / components.

[0035] Stack 24 has been formed over substrate 12 and includes vertically alternating layers of insulating materials 26 and 28 of varying composition. Exemplary such materials are silicon dioxide and silicon nitride, regardless of their order in the depicted material stack. An exemplary thickness for each layer is from about 200 angstroms to about 400 angstroms, and these need not have the same respective thicknesses or be the same thickness relative to one another (when materials 26 and 28 are individually of constant thickness). Stack 24 is shown with thirteen vertically alternating layers, but fewer or potentially more (e.g., dozens, hundreds, etc.) may be formed. The top layer 26 of stack 24 may be made thicker or thinner than shown, or an alternative material (not shown) may be provided over the top layer as an etch stop or polish stop, if desired, to better ensure a planar, level substrate, if desired. The second region 16 may contain a "stair" (not shown), where the "stair steps" are created by at least some of the pairs of adjacent materials 26 and 28 extending further in the horizontal direction into the end portion of the stack, moving deeper into the stack in the end portion.

[0036] refer to Figure 3 and 4 , channel openings 30 extending in height have been formed in the first region 14 through the alternating stacks 26, 28. By way of example only, this is shown as groups or columns 21 arranged in staggered rows with four openings 30 per row. In one embodiment and as shown, the channel openings 30 have been formed into the source material 19. Any alternative existing or yet to be developed arrangement and construction may be used. The use of "rows" and "columns" in this document is for convenience in distinguishing one series or orientation of features from another series or orientation of features and along which components have been or will be formed. "Rows" and "columns" are used synonymously with respect to any series of regions, components and / or features, independent of function. In any case, rows can be straight and / or curved and / or parallel and / or non-parallel relative to each other, as can columns. Further, rows and columns can intersect each other at 90° or at one or more other angles.

[0037] A vertically extending wall opening 32 has been formed through the alternating stacks 26, 28 and, in one embodiment, is substantially between the first and second regions 14, 16 as shown. In one embodiment, the wall opening 32 can be considered the first wall opening and forms at least one additional wall opening (e.g., a second wall opening 33, a third wall opening 34, and / or a fourth wall opening 35), wherein at least one of such wall openings is angled relative to the first wall opening 32 (i.e., at a different angle than a straight angle). The additional wall opening can join the first wall opening (for example, each of the wall openings 33 and 34 is shown as joining the first wall opening 32) and, in one embodiment, is located at the horizontal end of the first wall opening 32. In one embodiment, any of the wall openings 33 and / or 34, as joined with the first wall opening 32, can be considered an angled extension of the first wall opening 32. In one embodiment and as shown, the wall openings 32, 33, 34, and 35 form a radially inner island 25 of the alternating stacks 26, 28. Stair steps (not shown), as described above, can be located within the island 25. Two wall openings 32 (and associated wall openings 33 , 34 , and 35 ) are shown in construction 10 , although more or only one wall opening 32 may be used (regardless of the presence of wall openings 33 , 34 , and 35 ), with the discussion primarily being with respect to a single wall opening 32 .

[0038] The wall openings 32 are laterally spaced apart from a row 36 of channel openings 30, wherein the wall openings 32 extend horizontally along such a row, alongside the channel openings 30 in the row 36. An exemplary row 36 is any one of the rows 36 within a column 21 of such a row that is closest to the wall opening 32. Alternatively, and by way of example only, the referenced row 36 may be considered a combination of two or more rows 36 in different columns 21 and closest to the wall openings 32. In one embodiment and as shown, the wall openings 32 extend along a row 36, alongside a plurality of the channel openings 30 in the row, in one embodiment along at least four such channel openings in the row, and in one embodiment along more than four channel openings in the row. Figure 3 and 4 The embodiment shows wall openings 32 extending completely across nine channel openings 30, but this can extend across fewer or more channel openings. In one embodiment and as shown, wall openings 32 are formed as horizontal straight lines, but curves, combinations of straight and curved segments, etc. can be used. Regardless, and in one embodiment, wall openings 32 are formed parallel to rows 36, and in one embodiment, rows 36 are horizontal straight lines.

[0039] Exemplary techniques for forming channel opening 30 include photolithographic patterning and etching with or without pitch multiplication. Openings 30 and 32 can each be formed using a single masking step, and can be formed simultaneously using the same single masking step, so that two or more masking steps are not used to form openings 32 and 30. Similarly, in one embodiment, openings 33, 34, and 35 are formed commensurate with the formation of wall openings 32 and channel opening 30. In one embodiment, channel opening 30 and wall opening 32 are formed vertically or within 10° of vertical. Channel opening 30 and wall opening 32 are shown as including straight and vertical sidewalls in the depicted vertical cross-section, but this need not and may not be the case. Further and regardless, channel opening 30 individually can be circular, elliptical, rectangular, or have other shapes in horizontal cross-section. As just one example, channel opening 30 may be generally circular, having a maximum horizontal opening dimension of about 850 to 1,250 angstroms at its outermost portion of its height and tapering (not shown) to a horizontal opening dimension that is approximately 5% to 10% smaller at its innermost portion of its height where it meets source material 19. Wall openings 32 may similarly have a minimum horizontal opening dimension that is similar to the maximum horizontal dimension of channel opening 30 and may also be tapered (not shown). The maximum and minimum respective horizontal opening dimensions of channel opening 30 and wall openings 32 need not be identical relative to one another. Further, where additional wall openings (e.g., 33, 34, 35) are formed, such additional wall openings need not be the same size as wall opening 32.

[0040] refer to Figure 5 and 6 , materials 40 and 42 have been formed into channel opening 30 and wall opening 32, and in the depicted embodiment, are formed in wall openings 33, 34, and 35. Material 40 comprises a programmable charge storage material and material 42 comprises a semiconductive channel material. Example charge storage materials include any one or more of silicon nitride, ruthenium oxide, silicon oxynitride, nanodots, polysilicon, and silicon dioxide. Semiconductive channel material 42 (e.g., polysilicon) is suitably doped with conductivity-enhancing impurities, with example conductivity impurity doping ranging from 5×10 17 atoms / cm 3 to 5x10 18 atoms / cm 3 In one embodiment and as shown, the channel material 42 is formed as a hollow channel pillar 85 ( Figure 6 ) and may ultimately have its radially inwardly formed dielectric material ( Figure 5 and 6 (not shown). Alternatively, non-hollow channels may be used.

[0041] In any event, programmable charge storage material 40 and semiconductive channel material 42 form, in individual channel openings 30, vertically extending pillars 44 comprising the semiconductive channel material and the programmable charge storage material for individual ones of the vertically extending string of memory cells being formed. Further, programmable charge storage material 40 and semiconductive channel material 42 form vertically extending walls 46 in wall openings 32 (e.g., which are in two separate portions, for example, as shown, at least at this point in the process), the vertically extending walls comprising the programmable charge storage material and the semiconductive channel material and running horizontally along rows 36 alongside channel openings 30. Thus, walls 46 can have similar properties as wall openings 32 with respect to size range, shape, and orientation. Walls 46 can be considered to include a first side 48 facing toward pillars 44 and a second side 50 opposite first side 48 facing away from pillars 44. Similarly in the depicted embodiment, a second wall 52 including opposing sides 53 , 54 , a third wall 56 including opposing sides 57 , 58 , and a fourth wall 60 including opposing sides 61 , 62 are also formed and include programmable charge storage material 40 and semiconducting channel material 42 .

[0042] One or both (ideally, both) of the programmable charge storage material and the semiconductive channel material are formed simultaneously into the channel openings and into the wall openings. Semiconductive channel material 42 is ideally electrically coupled directly to source material 19. One technique for achieving this without providing separate interconnects, therefore, and as shown, includes first depositing programmable charge storage material 40 into line openings 30 and 32, followed by polishing back to at least the outermost surface at the height of the top layer of material 26, followed by a wet diluted HF isotropic or anisotropic etch to remove material 40 from intermediate above the substrate of openings 30 and 32. This is then followed by deposition of semiconductive channel material 42, polishing back thereof, and then etching to remove this semiconductive channel material from intermediate above the substrate of openings 30 and 32. Alternatively, semiconductive channel material 42 may not be removed from intermediate above the substrate of openings 30 and 32 (not shown).

[0043] Ideally, material 40 comprises a first deposited control gate blocking insulator (e.g., Al2O3 and / or a silicon dioxide / silicon nitride / silicon dioxide composite), followed by deposition of the programmable charge storage material, and then subsequently by deposition of a tunnel insulator, which will thereby be interposed between the charge storage material and the semiconducting channel material. The tunnel insulator may comprise a composite of a variety of dielectric materials of varying composition and thickness (as will be appreciated by those skilled in the art) and is not a material of the invention disclosed herein. In any case, in this case, wall 46 (as well as walls 52, 56, and 60) will also comprise a tunnel insulator and a control gate blocking insulator, with the control gate insulator forming the lateral outermost surface of the respective wall on opposing sides 48 / 50, 53 / 54, 57 / 58, and 61 / 62 of the respective wall, in one embodiment.

[0044] refer to Figure 7 and 8 , dielectric material 64 (e.g., silicon nitride and / or doped or undoped silicon dioxide) has been deposited to fill the remaining open volume of channel opening 30 and the wall openings, followed by planarization of this dielectric material back to at least the outermost surface at the level of the top layer of material 26. Thus, in one embodiment, this forms wall 46 (and walls 52, 56, and 60) to include lateral outer linings of materials 40 and 42 and a central core comprising dielectric material 64. In one such embodiment, wall 46 (and walls 52, 56, and 60) comprises a lateral outermost lining of the control gate blocking insulator.

[0045] refer to Figure 9 and 10 , access opening 66 ( Figure 9 ) have been formed on first side 48 of wall 46 through alternating stacks 26, 28. Access openings 66 provide access for an etchant to subsequently contact the material of alternating stacks 26, 28. The lateral edges of access openings 66 may also define the lateral edges of access / control gate lines that will be subsequently formed.

[0046] refer to Figure 11 and 12, an isotropic etch of one insulating material of different composition (e.g., material 28, which is not shown) between layers of another insulating material of another composition (e.g., material 26) has been performed through access opening 66. This can be performed selectively to one insulating material relative to the other insulating material. In this document, selective etching or removal is etching or removal in which one stated material is removed at a rate of at least 2:1 relative to the other stated material. During this isotropic etching, wall 46 restricts lateral passage of etching fluid from first side 48 of wall 46 to second side 50 of wall 46. Further in the depicted embodiment, during this isotropic etching, walls 52, 56, and 60 restrict lateral passage of etching fluid from first sides 53, 57, and 61 to second sides 54, 58, and 62, respectively.

[0047] Ideally, the etching is isotropically selective with respect to at least some of the material of the wall, but this need not be the case. For example, and by way of example only, the wall may be made of a material that is etched by the etchant at a rate greater than 1:2, even though the wall is laterally thick enough to prevent the etchant from passing from first side 48 to second side 50 if the wall itself is laterally etched (although not completely through the wall). Thus, and regardless, the wall may be laterally etched by the etchant regardless of whether the wall comprises a material that is etched at a rate less than 1:2 relative to the etching of another material (e.g., material 28 in the depicted embodiment). In the depicted embodiment, and where selective etching is performed as described in the preceding paragraph, the material of wall 46 relative to which material 28 is selectively etched may or may not include the programmable charge storage material and / or the semiconducting channel material. For example, and by way of example only, where wall 46 comprises an outer liner of a control gate blocking insulator, the insulator may block the etchant from reaching the programmable charge storage material.

[0048] After etching of material 28, Figure 11 and 12 The deposition of conductive control gate material 75 is shown, effectively replacing the removed insulating material (e.g., material 28, which is not shown). In one embodiment, to clarify the lateral extent of control gate material 75, this material is shown densely packed with Figure 11 However, this material will not be clearly visible in the top view, at least because the top layer 26 is located above this material and only in the Figure 116. In one embodiment, the control gate material 75 is located within the access opening 66. In one embodiment, and as shown, replacing the insulating material (e.g., 28) with the control gate material 75 results in a separate stack of control gate material 75 directly abutting wall 46 on first wall side 48. Likewise, the control gate material 75 may also directly abut side 53 of wall 52, side 57 of wall 56, and side 61 of wall 60. Regardless, and in one embodiment, the control gate material 75 does not directly abut either the programmable charge storage material or the semiconducting channel material of wall 46. For example, and by way of example only, and as described above with respect to one exemplary embodiment, a control gate blocking insulator may be interposed between the programmable charge storage material and the control gate material, and in one embodiment, the control gate material may directly abut the control gate blocking insulator of wall 46 on first wall side 48, and similarly with respect to walls 52, 56, and 60.

[0049] refer to Figure 13 and 14 , control gate material 75 has been removed from access opening 66 (e.g., by isotropically selective etching relative to materials 26, 40, 42, and 64). Dielectric material 68 (e.g., silicon nitride and / or silicon dioxide) has then been deposited into access opening 66 and planarized back to fill access opening 66, thus forming array 11 of strings 80 extending the height of individual memory cells 88. Construction 10 is shown as including a single memory cell 88 surrounding a channel pillar in each stack of strings extending the height of the memory cell. Alternatively, and by way of example only, any existing or yet to be developed construction may be used in which two or more memory cells are spaced circumferentially around a channel pillar in a single stack in a given string (not shown).

[0050] refer to Figure 15 and 16, electrically conductive via openings 71 extending in height have been formed on the second wall side 50 of the wall 46 through the alternating stacks 26, 28 of insulating materials of different compositions. In just one example, the via openings 71 can be generally circular, having a maximum horizontal opening dimension at their respective height outermost portions that is larger than the maximum horizontal opening dimension of the channel opening 30 (e.g., from about 2,000 angstroms to 4,000 angstroms), and can also taper (not shown) to a smaller horizontal opening dimension at their height innermost portions where they meet the conductive region 22. The via openings 71 have been filled with a conductive material to form electrically conductive vias 72. At least some of the electrically conductive vias 72 can be through-array vias (TAVs) (as shown) that extend to memory array control and / or read / write circuitry (not shown, but in addition to region 22) constructed beneath the array 11. The formation of TAVs (e.g., 72) may be performed comparable to the formation of conductive vias (not shown) connected to the stair steps (not shown) of the individual control gate lines of the corresponding stacks, and whether or not on side 50 of wall 46. Alternatively, the TAVs and other conductive vias (not shown) may be formed at separate times.

[0051] In the depicted example, access openings 66 enable the etchant to access material 28 and remove material 28 by selectively etching material 26. In addition to material 28 being removed by the etchant laterally between access openings 66 (e.g., in the "x" direction of the diagram), the material is also removed longitudinally outward from the ends of access openings 66 (e.g., in the "y" direction of the diagram). Removed material 28 is replaced by conductive control gate material 75. This material should not touch conductive via 72 to prevent an undesirable short circuit between the two. In previous methods prior to the present invention, the conductive via must be sufficiently spaced laterally and longitudinally from access openings 66 so that at the end of the timed etching of material 28, some of material 28 remains laterally adjacent to where conductive via 72 will be located. The use of walls 46 (and walls 52, 56, 60) enables this lateral and longitudinal spacing between access openings 66 and conductive via 72 to be reduced, thereby increasing circuit density. Moreover, using only one or more walls 46 (e.g., without walls 52, 56, and / or 60) would enable a reduction in the longitudinal spacing but would likely not reduce the lateral spacing. In any event, while the present invention is so intended, it is not so limited unless so stated in the claims being analyzed.

[0052] The above described process is shown in Figure 9 The etching shown provides conductive vias 72. Alternatively, by way of example, the formation of conductive vias 72 may occur after Figure 9Before the depicted etching (including before or after forming wall openings 32 or walls 46 and also including before or after forming channel openings 30 and pillars 44). For example and by way of example only, Figure 17 and 18 The process is shown relative to an alternative construction 10a. Like numerals from the above described embodiments have been used where appropriate, with some construction differences being indicated by the suffix "a". Figure 17 and 18 An exemplary embodiment is shown in which the via openings 71 and the conductive vias 72 are already formed in the above-described embodiments. Figure 3 and 4 Any of the structures shown in is formed before.

[0053] Embodiments of the present invention include an array of strings extending across the height of memory cells, independent of the method of fabrication, wherein the memory cells individually comprise programmable charge storage transistors. However, such an array may include any of the structural aspects described above with respect to the method embodiments. Regardless, such an array would include a substrate (e.g., construction 10 / 10a) comprising a first region (e.g., 14) containing memory cells (e.g., 88) and a second region (e.g., 16) lateral to the first region that does not contain memory cells. The first region comprises a vertically alternating stack of insulating material (e.g., 26) and control gate material (e.g., 75). The second region comprises a vertically alternating stack of insulating material (e.g., 26, 28) of different composition lateral to the first region.

[0054] Channel pillars (e.g., 85) comprising semiconductive channel material extend vertically through multiple of the vertically alternating stacks in the first region. Tunnel insulators, programmable charge storage materials, and control gate blocking insulators are interposed between the channel pillars and the control gate material of individual ones of the control gate material stacks in the first region. Conductive vias (e.g., 72) extend vertically through the vertically alternating stacks in the second region. A vertically extending wall (e.g., 46) is laterally located between the first and second regions. The wall comprises programmable charge storage material and semiconductive channel material. Any other attributes or aspects as shown and / or described above may be used.

[0055] For example, and by way of example only, in one embodiment, the wall is laterally spaced apart from a row of channel pillars and extends along the row beside a plurality of the channel pillars in the row. In one such embodiment, the wall extends along at least four channel pillars in the row, in one such embodiment, the wall is parallel to the row, in one such embodiment, the wall is horizontally rectilinear, and in one such embodiment, the wall is horizontally rectilinear and the wall is parallel to the row. In one embodiment, the vertically extending wall (e.g., 46, 52, 56, 60 in combination) completely surrounds the island (e.g., 25) comprising the conductive via, wherein the wall comprises programmable charge storage material and semiconducting channel material, and in one embodiment, also comprises a tunnel insulator and a control gate blocking insulator. Again, any other attributes or aspects as shown and / or described above may be used.

Claims

1. An array of strings extending in height of memory cells, the memory cells individually comprising programmable charge storage transistors, the array comprising: A substrate comprising a first region containing memory cells and a second region lateral to the first region without memory cells, wherein the first region comprises a vertical alternating stack of insulating materials and control gate materials, and the second region comprises a vertical alternating stack of insulating materials of different compositions lateral to the first region; a channel pillar comprising a semiconductive channel material extending in height through a plurality of the vertically alternating stacks within the first region; a programmable charge storage material between the channel pillar and the control gate material of individual ones of the stack of control gate material in the first region; an electrically conductive via extending in height through said vertically alternating stack of layers in said second region; and A wall extending in height is laterally located between the first region and the second region, the wall comprising the programmable charge storage material and the semiconducting channel material.

2. The array of claim 1 wherein the wall is laterally spaced apart from a row of the channel posts and extends along the row alongside a plurality of the channel posts in the row.

3. The array of claim 2, wherein the walls are parallel to the rows.

4. The array of claim 2, wherein the walls are horizontally rectilinear.

5. The array of claim 1 wherein the individual stacks of control gate material are directly against the wall on the first region side of the wall.

6. The array of claim 5 wherein the control gate material does not directly abut against either the programmable charge storage material or the semiconducting channel material of the wall.

7. The array of claim 1 wherein the walls comprise lateral outer liners of the programmable charge storage material and the semiconducting channel material and a central core comprising a dielectric material.

8. The array according to claim 1, wherein: The wall is a first wall; and The array further comprises: A second wall extending in height includes the programmable charge storage material and the semiconductive channel material, the second wall being angled relative to the first wall.

9. The array of claim 8, wherein the second wall is joined to the first wall and comprises an angled extension of the first wall.

10. The array of claim 1 wherein the walls are vertical or within 10° of vertical.

11. An array of height-extending strings of memory cells, the memory cells individually comprising programmable charge storage transistors, the array comprising: A substrate comprising a first region containing memory cells and a second region lateral to the first region without memory cells, wherein the first region comprises a vertical alternating stack of insulating materials and control gate materials, and the second region comprises a vertical alternating stack of insulating materials of different compositions lateral to the first region; a channel pillar comprising a semiconductive channel material extending in height through a plurality of the vertically alternating stacks within the first region; a programmable charge storage material between the channel pillar and the control gate material of individual ones of the stack of control gate material in the first region; an electrically conductive via extending in height through the vertically alternating stack in the second region; and A wall extending in height completely surrounds the island including the conductive via, the wall including the programmable charge storage material and the semiconductive channel material.

12. An array of height-extending strings of memory cells, the memory cells individually comprising programmable charge storage transistors, the array comprising: A substrate comprising a first region containing memory cells and a second region lateral to the first region without memory cells, wherein the first region comprises a vertical alternating stack of insulating materials and control gate materials, and the second region comprises a vertical alternating stack of insulating materials of different compositions lateral to the first region; a channel pillar comprising a semiconductive channel material extending in height through a plurality of the vertically alternating stacks within the first region; a programmable charge storage material between the channel pillar and the control gate material of individual ones of the stack of control gate material in the first region; an electrically conductive via extending in height through the vertically alternating stack in the second region; and A wall extending in height is laterally located between the first region and the second region, the wall is laterally spaced apart from a row of the channel pillars and extends along the row beside a plurality of the channel pillars in the row, and the wall includes the programmable charge storage material and the semiconductive channel material.

13. The array of claim 12, wherein the walls are parallel to the rows.

14. An array of height-extending strings of memory cells, the memory cells individually comprising programmable charge storage transistors, the array comprising: A substrate comprising a first region containing memory cells and a second region lateral to the first region without memory cells, wherein the first region comprises a vertical alternating stack of insulating materials and control gate materials, and the second region comprises a vertical alternating stack of insulating materials of different compositions lateral to the first region; a channel pillar comprising a semiconductive channel material extending in height through a plurality of the vertically alternating stacks within the first region; a programmable charge storage material between the channel pillar and the control gate material of individual ones of the stack of control gate material in the first region; an electrically conductive via extending in height through the vertically alternating stack in the second region; and A wall extending in height that completely surrounds the island including the conductive via, the wall being laterally spaced apart from a row of the channel pillars and including portions extending along the row alongside a plurality of the channel pillars in the row, and the wall including the programmable charge storage material and the semiconductive channel material.

15. An array of height-extending strings of memory cells, the memory cells individually comprising programmable charge storage transistors, the array comprising: A substrate comprising a first region containing memory cells and a second region lateral to the first region without memory cells, wherein the first region comprises a vertical alternating stack of insulating materials and control gate materials, and the second region comprises a vertical alternating stack of insulating materials of different compositions lateral to the first region; a channel pillar comprising a semiconductive channel material extending in height through a plurality of the vertically alternating stacks within the first region; a programmable charge storage material between the channel pillar and the control gate material of individual ones of the stack of control gate material in the first region; an electrically conductive via extending in height through the vertically alternating stack in the second region; and A height-extending wall is located in the second region, the wall being laterally spaced apart from a row of the channel pillars and longitudinally elongated at an angle relative to the row, and the wall comprising the programmable charge storage material and the semiconductive channel material.

16. The array of claim 15 wherein the walls are longitudinally elongated orthogonally relative to the rows.

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