Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device with reduced parasitic capacitance is provided. A semiconductor device includes a first insulating layer; a first oxide semiconductor layer over the first insulating layer; a second oxide semiconductor layer over the first oxide semiconductor layer; a source electrode layer and a drain electrode layer over the second oxide semiconductor layer; a second insulating layer over the first insulating layer, the source electrode layer, and the drain electrode layer; a third insulating layer over the second insulating layer; a third oxide semiconductor layer over the second oxide semiconductor layer; a gate insulating layer over the third oxide semiconductor layer; and a gate electrode layer over the gate insulating layer. The second insulating layer is an oxygen barrier layer and has a region in contact with side surfaces of the first oxide semiconductor layer, the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer. The third oxide semiconductor layer has a region in contact with side surfaces of the second oxide semiconductor layer, the source electrode layer, the drain electrode layer, the second insulating layer, and the third insulating layer.

Description

[0001] This invention application is a divisional application of the invention patent application entitled "Semiconductor Device and Method of Manufacturing Thereof" with international application number PCT / IB2016 / 050420, international application date of January 28, 2016, and Chinese national phase application number 201680008409.5. Technical Field

[0002] This invention relates to an object, method, or manufacturing process. Additionally, it relates to a process, machine, product, or composition of matter. In particular, the invention relates, for example, to a semiconductor device, display device, light-emitting device, energy storage device, imaging device, a method for driving or manufacturing these devices. Especially, one aspect of the invention relates to a semiconductor device or a method for manufacturing it.

[0003] Note that in this specification, "semiconductor device" refers to any device capable of operating by utilizing the characteristics of semiconductors. Transistors and semiconductor circuits are types of semiconductor devices. Additionally, storage devices, display devices, and electronic devices sometimes include semiconductor devices. Background Technology

[0004] The technique of constructing transistors using semiconductor films formed on substrates with insulating surfaces has attracted attention. These transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (display devices). Silicon-based semiconductor materials are well-known as semiconductor thin films that can be used in transistors. In addition, oxide semiconductors are also attracting attention as other materials.

[0005] For example, Patent Document 1 discloses a transistor whose active layer comprises an amorphous oxide semiconductor containing indium (In), gallium (Ga) and zinc (Zn).

[0006] [Patent Document 1] Japanese Patent Application Publication No. 2006-165528

[0007] When miniaturizing semiconductor devices, parasitic capacitance near transistors is a major problem.

[0008] When a transistor is operating, the time required for the parasitic capacitance to charge in the channel (e.g., between the source and drain electrodes) leads to a decrease in the transistor's responsiveness, and even a decrease in the responsiveness of the semiconductor device.

[0009] Furthermore, with the development of miniaturization, controlling the various processes in transistor formation (especially film deposition and processing) has become more difficult, and deviations in the manufacturing process have a significant impact on the characteristics and reliability of transistors.

[0010] In addition, with miniaturization, problems have arisen in transistor manufacturing, such as the difficulty in pattern formation due to the resolution limitations of the exposure equipment, resulting in increasingly higher equipment investment costs.

[0011] Therefore, one objective of this invention is to reduce parasitic capacitance near transistors. Another objective of this invention is to provide a semiconductor device with good electrical characteristics. Another objective of this invention is to provide a semiconductor device with high reliability. Another objective of this invention is to provide a method for manufacturing a transistor or semiconductor device capable of forming patterns below the resolution limit of an exposure apparatus. Another objective of this invention is to reduce characteristic deviations in transistors or semiconductor devices caused by manufacturing processes. Another objective of this invention is to provide a semiconductor device comprising an oxide semiconductor layer with few oxygen defects. Another objective of this invention is to provide a semiconductor device that can be formed with a simple process. Another objective of this invention is to provide a semiconductor device having a structure that can reduce the interface energy level near the oxide semiconductor layer. Another objective of this invention is to provide a semiconductor device with low power consumption. Another objective of this invention is to provide a novel method for manufacturing a semiconductor device that reduces development costs. Another objective of this invention is to provide a novel semiconductor device, etc. Another objective of this invention is to provide a method for manufacturing the aforementioned semiconductor device.

[0012] Note that the description of these objectives does not preclude the existence of other objectives. Furthermore, one embodiment of the invention does not necessarily require achieving all of the aforementioned objectives. Additionally, objectives other than these are readily apparent from the description, drawings, claims, etc., and can be extracted from said description. Summary of the Invention

[0013] One aspect of the semiconductor device of the present invention includes: a first insulating layer; a first oxide semiconductor layer on the first insulating layer; a second oxide semiconductor layer on the first oxide semiconductor layer; a source electrode layer and a drain electrode layer on the second oxide semiconductor layer; a second insulating layer on the first insulating layer, the source electrode layer, and the drain electrode layer; a third insulating layer on the second insulating layer; a third oxide semiconductor layer on the second oxide semiconductor layer; a gate insulating layer on the third oxide semiconductor layer; and a gate electrode layer on the gate insulating layer. The second insulating layer is an oxygen barrier layer and has regions that contact the side surfaces of the first oxide semiconductor layer, the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer. The third oxide semiconductor layer has regions that contact the side surfaces of the second oxide semiconductor layer, the source electrode layer, the drain electrode layer, the second insulating layer, and the third insulating layer.

[0014] Another aspect of the semiconductor device of the present invention includes: a first insulating layer; a first oxide semiconductor layer on the first insulating layer; a second oxide semiconductor layer on the first oxide semiconductor layer; a source electrode layer and a drain electrode layer on the second oxide semiconductor layer; a first conductive layer and a second conductive layer having regions contacting the sides of the second oxide semiconductor layer; a second insulating layer on the first insulating layer, the source electrode layer, and the drain electrode layer; a third insulating layer on the second insulating layer; a third oxide semiconductor layer on the second oxide semiconductor layer; a gate insulating layer on the third oxide semiconductor layer; and a gate electrode layer on the gate insulating layer. The second insulating layer is an oxygen barrier layer, and the sides of the first electrode layer and the second electrode layer contact the second insulating layer at their side portions. The third oxide semiconductor layer has regions contacting the sides of the first insulating layer, the first oxide semiconductor layer, the second oxide semiconductor layer, the source electrode layer, the drain electrode layer, the second insulating layer, and the third insulating layer.

[0015] Another aspect of the semiconductor device of the present invention includes: a first insulating layer; a first oxide semiconductor layer on the first insulating layer; a second oxide semiconductor layer on the first oxide semiconductor layer; a source electrode layer and a drain electrode layer on the second oxide semiconductor layer; a second insulating layer on the first insulating layer, the source electrode layer, and the drain electrode layer; a third insulating layer on the second insulating layer; a fourth insulating layer formed on the source electrode layer and the drain electrode layer in contact with the sides of the second insulating layer and the third insulating layer; a third oxide semiconductor layer on the second oxide semiconductor layer; a gate insulating layer on the third oxide semiconductor layer; and a gate electrode layer on the gate insulating layer. The second insulating layer is an oxygen barrier layer and has regions in contact with the sides of the first oxide semiconductor layer, the sides of the second oxide semiconductor layer, the sides of the source electrode layer, and the sides of the drain electrode layer. The third oxide semiconductor layer has regions in contact with the sides of the first insulating layer, the sides of the first oxide semiconductor layer, the sides of the second oxide semiconductor layer, the sides of the source electrode layer, the sides of the drain electrode layer, and the sides of the fourth insulating layer.

[0016] In addition, the second insulating layer is preferably an aluminum oxide layer.

[0017] Another aspect of the semiconductor device of the present invention includes: a first conductive layer; a first insulating layer on the first conductive layer; a first oxide semiconductor layer on the first insulating layer; a second oxide semiconductor layer on the first oxide semiconductor layer; a source electrode layer and a drain electrode layer on the second oxide semiconductor layer; a second insulating layer on the first insulating layer, the source electrode layer, and the drain electrode layer; a third insulating layer on the second insulating layer; a third oxide semiconductor layer on the second oxide semiconductor layer; a gate insulating layer on the third oxide semiconductor layer; a gate electrode layer on the gate insulating layer; and a fourth insulating layer on the third insulating layer, the third oxide semiconductor layer, the gate insulating layer, and the gate electrode layer. The second insulating layer is an oxygen barrier layer and is in contact with the side surfaces of the first oxide semiconductor layer, the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer. The third oxide semiconductor layer has a region in contact with the side surfaces of the first insulating layer, the first oxide semiconductor layer, the second oxide semiconductor layer, the source electrode layer, the drain electrode layer, the second insulating layer, and the third insulating layer. The fourth insulating layer is an oxygen barrier layer.

[0018] In addition, the second and fourth insulating layers are preferably made of aluminum oxide film.

[0019] Another aspect of the present invention provides a method for manufacturing a semiconductor device comprising the following steps: forming a first insulating layer; forming a first oxide semiconductor film on the first insulating layer; forming a second oxide semiconductor film on the first oxide semiconductor film; performing a first heat treatment; forming a first conductive film on the second oxide semiconductor film; etching a portion of the first oxide semiconductor film and a portion of the second oxide semiconductor film using a first mask and the first conductive film to form the first oxide semiconductor layer and the second oxide semiconductor layer into an island shape; forming a second insulating layer on the first insulating layer and the first conductive film; while forming the second insulating layer, forming a mixed layer of the first insulating layer and the second insulating film and simultaneously adding oxygen to the mixed layer or the first insulating layer; performing... A second heat treatment diffuses oxygen into the second oxide semiconductor layer; a third insulating film is formed on the second insulating layer; the third insulating layer is planarized to form a third insulating layer; the third insulating layer and the second insulating layer are selectively etched using a second mask; the first conductive film is selectively etched using the second mask and the second insulating layer to form a source electrode layer and a drain electrode layer; a third oxide semiconductor film is formed on the third insulating layer and the second oxide semiconductor layer; a fourth insulating film is formed on the third oxide semiconductor film; a second conductive film is formed on the fourth insulating film; and the second conductive film, the third insulating film, and the third oxide semiconductor film are chemically mechanically polished to form a third oxide semiconductor layer, a gate insulating layer, and a gate electrode layer.

[0020] Another aspect of the present invention provides a method for manufacturing a semiconductor device, comprising the following steps: forming a first insulating layer; forming a first oxide semiconductor film on the first insulating layer; forming a second oxide semiconductor film on the first oxide semiconductor film; performing a first heat treatment; forming a first conductive film on the second oxide semiconductor film; selectively etching the first oxide semiconductor film and the second oxide semiconductor film using a first mask and the first conductive film to form the first oxide semiconductor layer and the second oxide semiconductor layer into an island shape; forming a second insulating film on the first insulating layer and the first conductive film; forming a mixed layer of the first insulating layer and the second insulating film during the formation of the second insulating film; adding oxygen to the mixed layer or the first insulating layer; performing a second heat treatment to diffuse oxygen into the second oxide semiconductor layer to reduce oxygen defects in the second oxide semiconductor layer; and so on. A third insulating film is formed on the second insulating film; the third insulating film is planarized; a portion of the third insulating film and a portion of the second insulating film are etched using a second mask to form a third insulating layer and a second insulating layer; a fourth insulating film is formed on the first conductive layer and the third insulating layer; anisotropic etching is used to form a fourth insulating layer that contacts the sides of the second insulating layer and the third insulating layer; a portion of the first conductive film is etched using the fourth insulating layer as a mask to form a source electrode and a drain electrode; a third oxide semiconductor film is formed on the third insulating layer and the second oxide semiconductor layer; a fifth insulating film is formed on the third oxide semiconductor film; a second conductive film is formed on the fifth insulating film; the second conductive film, the third insulating film, and the third oxide semiconductor film are chemically and mechanically polished to form a third oxide semiconductor layer, a gate insulating layer, and a gate electrode layer.

[0021] In addition, the second insulating film is preferably formed using sputtering and oxygen gas.

[0022] In addition, the second insulating film is preferably formed on a silicon oxide film by sputtering and using an alumina target under conditions where the oxygen gas content is 50% by volume or more.

[0023] In addition, the second heat treatment is preferably performed at a temperature of 300°C or higher and 450°C or lower.

[0024] Alternatively, a structure using semiconductor devices, microphones, speakers, and housings can be adopted.

[0025] By using one aspect of the present invention, parasitic capacitance near the transistor can be reduced. Furthermore, by using one aspect of the present invention, a semiconductor device with good electrical characteristics can be provided. Furthermore, by using one aspect of the present invention, a semiconductor device with high reliability can be provided. Furthermore, by using the present invention, a method for manufacturing a transistor or semiconductor device capable of forming patterns below the resolution limit of an exposure device can be provided. Furthermore, by using one aspect of the present invention, characteristic deviations of the transistor or semiconductor device caused by manufacturing processes can be reduced. Furthermore, by using one aspect of the present invention, a semiconductor device including an oxide semiconductor layer with few oxygen defects can be provided. Furthermore, by using one aspect of the present invention, a semiconductor device that can be formed with a simple process can be provided. Furthermore, by using one aspect of the present invention, a semiconductor device having a structure that can reduce the interface energy level near the oxide semiconductor layer can be provided. Furthermore, by using one aspect of the present invention, a semiconductor device with low power consumption can be provided. Furthermore, one object of using the present invention is to provide a novel method for manufacturing a semiconductor device that reduces development costs. Furthermore, an object of using one aspect of the present invention is to provide a novel semiconductor device, etc. Furthermore, by using one aspect of the present invention, a method for manufacturing the above-mentioned semiconductor device can be provided.

[0026] Note that the description of these effects does not preclude the existence of other effects. Furthermore, one embodiment of the invention does not necessarily require all of the aforementioned effects. Additionally, effects other than these are readily apparent from the description, drawings, claims, etc., and can be extracted from said description. Attached Figure Description

[0027] FIG. 1A , FIG. 1B , FIG. 1C These are top views and cross-sectional views illustrating a transistor;

[0028] FIG. 2A , FIG. 2B , FIG. 2C These are top views and cross-sectional views illustrating a transistor;

[0029] FIG. 3A , FIG. 3B These are top views and cross-sectional views illustrating a transistor;

[0030] FIG. 4A , FIG. 4B These are the energy band diagram of the oxide semiconductor layer and the magnified cross-sectional view of the transistor;

[0031] FIG. 5A , FIG. 5B , FIG. 5C , FIG. 5DThis is the ALD film formation principle;

[0032] FIG. 6A , FIG. 6B This is a schematic diagram of an ALD device;

[0033] FIG. 7A , FIG. 7B , FIG. 7C These are top and cross-sectional views illustrating the manufacturing process of transistors;

[0034] FIG. 8A , FIG. 8B , FIG. 8C These are top and cross-sectional views illustrating the manufacturing process of transistors;

[0035] FIG. 9A , FIG. 9B , FIG. 9C These are top and cross-sectional views illustrating the manufacturing process of transistors;

[0036] FIG. 10A , FIG. 10B , FIG. 10C These are top and cross-sectional views illustrating the manufacturing process of transistors;

[0037] FIG. 11A , FIG. 11B , FIG. 11C These are top and cross-sectional views illustrating the manufacturing process of transistors;

[0038] FIG. 12A , FIG. 12B , FIG. 12C These are top and cross-sectional views illustrating the manufacturing process of transistors;

[0039] FIG. 13A , FIG. 13B , FIG. 13C These are top and cross-sectional views illustrating the manufacturing process of transistors;

[0040] FIG. 14A , FIG. 14B , FIG. 14C These are top views and cross-sectional views illustrating a transistor;

[0041] FIG. 15A , FIG. 15B , FIG. 15C These are top views and cross-sectional views illustrating a transistor;

[0042] FIG. 16A , FIG. 16B , FIG. 16C These are top and cross-sectional views illustrating the manufacturing process of transistors;

[0043] FIG. 17A , FIG. 17B , FIG. 17CThese are top views and cross-sectional views illustrating a transistor;

[0044] FIG. 18 These are top views and cross-sectional views illustrating a transistor;

[0045] FIG. 19A , FIG. 19B , FIG. 19C These are top views and cross-sectional views illustrating a transistor;

[0046] FIG. 20A , FIG. 20B , FIG. 20C These are top and cross-sectional views illustrating the manufacturing process of transistors;

[0047] FIG. 21A , FIG. 21B , FIG. 21C These are top and cross-sectional views illustrating the manufacturing process of transistors;

[0048] FIG. 22A , FIG. 22B , FIG. 22C These are top and cross-sectional views illustrating the manufacturing process of transistors;

[0049] FIG. 23A , FIG. 23B , FIG. 23C These are top and cross-sectional views illustrating the manufacturing process of transistors;

[0050] FIG. 24A , FIG. 24B , FIG. 24C , FIG. 24D This is a Cs-corrected high-resolution TEM image of CAAC-OS in a cross section and a schematic diagram of the CAAC-OS cross section;

[0051] FIG. 25A , FIG. 25B , FIG. 25C , FIG. 25D It is a Cs-corrected high-resolution TEM image in the plane of CAAC-OS;

[0052] FIG. 26A , FIG. 26B , FIG. 26C This is a diagram illustrating the structural analysis of CAAC-OS and single-crystal oxide semiconductors using XRD;

[0053] FIG. 27A , FIG. 27B This is a diagram showing the electron diffraction pattern of CAAC-OS;

[0054] FIG. 28 This is a diagram showing the changes in the crystallization region of In-Ga-Zn oxide due to electron irradiation;

[0055] FIG. 29A , FIG. 29B , FIG. 29C , FIG. 29D These are cross-sectional views and circuit diagrams of semiconductor devices;

[0056] FIG. 30A , FIG. 30B , FIG. 30C These are cross-sectional views and circuit diagrams of semiconductor devices;

[0057] FIG. 31A , FIG. 31B This is a plan view showing the imaging device;

[0058] FIG. 32A , FIG. 32B This is a plan view showing the pixels of the imaging device;

[0059] FIG. 33A , FIG. 33B This is a cross-sectional view showing the imaging device;

[0060] FIG. 34A , FIG. 34B This is a cross-sectional view showing the imaging device;

[0061] FIG. 35 This is a diagram illustrating the structure of an RF tag;

[0062] FIG. 36 This is a diagram illustrating the structure of a CPU;

[0063] FIG. 37 It is a circuit diagram of the storage element;

[0064] FIG. 38A , FIG. 38B , FIG. 38C It is a diagram illustrating the structure of a display device and a circuit diagram of a pixel;

[0065] FIG. 39 This is a diagram illustrating the display module;

[0066] FIG. 40A , FIG. 40B This is a perspective view showing the cross-sectional structure of a package using a leadframe type insert;

[0067] FIG. 41A , FIG. 41B , FIG. 41C , FIG. 41D , FIG. 41E It is a diagram illustrating an electronic device;

[0068] FIG. 42A , FIG. 42B , FIG. 42C , FIG. 42D It is a diagram illustrating an electronic device;

[0069] FIG. 43A , FIG. 43B , FIG. 43C It is a diagram illustrating an electronic device;

[0070] FIG. 44A , FIG. 44B , FIG. 44C , FIG. 44D , FIG. 44E , FIG. 44F It is a diagram illustrating an electronic device. Detailed Implementation

[0071] The embodiments will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and those skilled in the art will readily understand that its methods and details can be varied in many ways without departing from the spirit and scope of the invention. Therefore, the present invention should not be construed as limited only to the description of the embodiments shown below. Note that in the structure of the invention described below, the same reference numerals are used in different drawings to denote the same parts or parts having the same function, and repeated descriptions are omitted. Note that sometimes the shading of the same constituent elements is appropriately omitted or changed in different drawings.

[0072] For example, in this specification, when it is explicitly stated as "X and Y are connected", the following situations are disclosed in this specification: X and Y are electrically connected; X and Y are functionally connected; and X and Y are directly connected. Therefore, connection relationships other than those shown in the drawings or text are also described in the drawings or text, not limited to those specified in the drawings or text.

[0073] Here, X and Y are objects (e.g., devices, components, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0074] As an example of a case where X and Y are directly connected, one could cite a case where there is no component (e.g., switch, transistor, capacitor, inductor, resistor, diode, display element, light-emitting element, and load) connecting X and Y, and X and Y are not connected by any component (e.g., switch, transistor, capacitor, inductor, resistor, diode, display element, light-emitting element, and load) connecting X and Y.

[0075] As an example of an X and Y electrical connection, more than one component capable of electrically connecting X and Y (e.g., switch, transistor, capacitor, inductor, resistor, diode, display element, light-emitting element, load, etc.) can be connected between X and Y. Furthermore, the switch has the function of controlling whether conduction or shutdown. In other words, the switch has the function of controlling whether current flows through it by being in a conducting state (on state) or a non-conducting state (off state). Alternatively, the switch has the function of selecting and switching the current path. Additionally, X and Y electrical connections also include cases where X and Y are directly connected.

[0076] As an example of a functional connection between X and Y, more than one circuit capable of functionally connecting X and Y can be connected between them (e.g., logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (DA converters, AD converters, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boost circuits, buck circuits, etc.), level shifter circuits that change the potential level of a signal, etc.), voltage sources, current sources, switching circuits, amplification circuits (circuits that can increase signal amplitude or current, operational amplifiers, differential amplifiers, source follower circuits, buffer circuits, etc.), signal generation circuits, storage circuits, control circuits, etc.). Note that, for example, even if other circuits are sandwiched between X and Y, when the signal output from X is transmitted to Y, it can be said that X and Y are functionally connected. Furthermore, the functional connection of X and Y includes both direct connection and electrical connection.

[0077] Furthermore, when explicitly stated as "X and Y are electrically connected," this specification discloses the following cases: X and Y are electrically connected (in other words, X and Y are connected with other components or circuits in between); X and Y are functionally connected (in other words, X and Y are functionally connected with other circuits in between); and X and Y are directly connected (in other words, X and Y are connected without other components or circuits in between). In other words, when explicitly stated as "electrically connected," this specification discloses the same content as when only explicitly stated as "connected."

[0078] Note that, for example, in the case where the source (or first terminal, etc.) of the transistor is electrically connected to X via Z1 (or not via Z1), and the drain (or second terminal, etc.) of the transistor is electrically connected to Y via Z2 (or not via Z2), and in the case where the source (or first terminal, etc.) of the transistor is directly connected to a portion of Z1, and another portion of Z1 is directly connected to X, and the drain (or second terminal, etc.) of the transistor is directly connected to a portion of Z2, and another portion of Z2 is directly connected to Y, it can be represented as follows.

[0079] For example, it can be represented as "X, Y, the source (or first terminal, etc.) of the transistor, and the drain (or second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y." Alternatively, it can be represented as "The source (or first terminal, etc.) of the transistor is electrically connected to X, the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in sequence." Or, it can be represented as "X is electrically connected to Y through the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.), and Y are sequentially connected to each other." By specifying the connection order in the circuit structure using the same representation as this example, the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor can be distinguished, thus determining the scope of the technology.

[0080] Alternatively, as another representation, it can be expressed as: "The source (or first terminal, etc.) of the transistor is electrically connected to X at least through a first connection path, wherein the first connection path does not have a second connection path, and the second connection path is a path between the source (or first terminal, etc.) and the drain (or second terminal, etc.) of the transistor, wherein the first connection path is a path through Z1, and the drain (or second terminal, etc.) of the transistor is electrically connected to Y at least through a third connection path, wherein the third connection path does not have the second connection path, and the third connection path is a path through Z2." Or, it can also be expressed as: "The source (or first terminal, etc.) of the transistor is electrically connected to X at least through Z1 on a first connection path, wherein the first connection path does not have a second connection path, and the second connection path has a connection path through the transistor, and the drain (or second terminal, etc.) of the transistor is electrically connected to Y at least through Z2 on a third connection path, wherein the third connection path does not have the second connection path." Alternatively, it can be expressed as "the source (or first terminal, etc.) of the transistor is electrically connected to X via Z1 through at least a first electrical path, wherein the first electrical path does not have a second electrical path, wherein the second electrical path is an electrical path from the source (or first terminal, etc.) of the transistor to the drain (or second terminal, etc.) of the transistor, wherein the drain (or second terminal, etc.) of the transistor is electrically connected to Y via Z2 through at least a third electrical path, wherein the third electrical path does not have a fourth electrical path, wherein the fourth electrical path is an electrical path from the drain (or second terminal, etc.) of the transistor to the source (or first terminal, etc.) of the transistor." By specifying the connection paths in the circuit structure using the same formulation as these examples, the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor can be distinguished to determine the scope of the technology.

[0081] Note that this representation is an example and is not limited to the representation described above. Here, X, Y, Z1, and Z2 refer to objects (e.g., devices, components, circuits, wiring, electrodes, terminals, conductive films and layers, etc.).

[0082] Furthermore, even when independent components are electrically connected to each other in a circuit diagram, sometimes one component performs the function of multiple components. For example, when a portion of a wiring is used as an electrode, a conductive film performs the function of both the wiring and the electrode. Therefore, the scope of "electrical connection" in this specification also includes such cases where a conductive film performs the function of multiple components.

[0083] The embodiments will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and those skilled in the art will readily understand that its methods and details can be varied in many ways without departing from the spirit and scope of the invention. Therefore, the present invention should not be construed as being limited only to the contents described in the embodiments shown below. Note that in the structure of the invention described below, the same reference numerals are used across different drawings to denote the same part or parts having the same function, and repeated descriptions are omitted.

[0084] <Addendum regarding the description of the accompanying drawings>

[0085] In this specification, for convenience, terms such as "upper" and "lower" are used to indicate configuration and to illustrate the positional relationship of the constituent elements with reference to the accompanying drawings. Furthermore, the positional relationship of the constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the use of terms not limited to those described in this specification may be appropriately replaced as needed.

[0086] Furthermore, terms such as "above" or "below" are not limited to situations where the constituent elements are positioned "directly above" or "directly below" and in direct contact. For example, if the statement is "electrode B on insulating layer A," it is not necessary for electrode B to be formed in direct contact with insulating layer A; it can also include situations where other constituent elements are included between insulating layer A and electrode B.

[0087] In this specification, "parallel" means the angle between two straight lines is -10° or higher and less than 10°. This also includes angles between -5° or higher and less than 5°. "Approximately parallel" means the angle between two straight lines is -30° or higher and less than 30°. "Perpendicular" means the angle between two straight lines is 80° or higher and less than 100°. This also includes angles between 85° or higher and less than 95°. "Approximately perpendicular" means the angle between two straight lines is 60° or higher and less than 120°.

[0088] In addition, in this specification, the hexagonal crystal system includes the trigonal crystal system and the rhombohedral crystal system.

[0089] For ease of explanation, sizes, layer thicknesses, or regions are arbitrarily shown in the accompanying drawings. Therefore, the invention is not limited to the dimensions shown in the drawings. The drawings are schematic for clarity and are not limited to the shapes or values ​​shown in the drawings.

[0090] In accompanying drawings such as top views (also known as plan views or layout views) or perspective views, some constituent elements are sometimes omitted for clarity.

[0091] Furthermore, in the case of "identical", they can have both the same area and the same shape. Due to the manufacturing process, the shapes of the constituent elements may not be exactly the same, so "roughly the same" can also be called "identical".

[0092] <Notes regarding replaceable records>

[0093] In this specification, when describing the connection relationship of a transistor, it is expressed as "one of the source and drain" (or the first electrode or the first terminal), or "the other of the source and drain" (or the second electrode or the second terminal). This is because the source and drain of a transistor may be interchanged depending on the transistor's structure or operating conditions. Note that, depending on the circumstances, the source and drain of a transistor may be appropriately referred to as source (drain) terminals or source (drain) electrodes, etc.

[0094] Note that in this specification and other materials, terms such as "electrode" or "wiring" do not functionally limit their constituent elements. For example, sometimes "electrode" is used as part of "wiring," and vice versa. Furthermore, terms such as "electrode" or "wiring" also include cases where multiple "electrodes" or "wiring" are formed as a single unit.

[0095] In this specification and the like, a transistor is a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source.

[0096] Here, because the source and drain are interchanged depending on the transistor's structure or operating conditions, it is difficult to definitively identify which is the source and which is the drain. Therefore, sometimes the part used as the source or the part used as the drain is not referred to as the source or drain, but one of the source and drain is called the first electrode and the other of the source and drain is called the second electrode.

[0097] Note that the ordinal numbers such as "first," "second," and "third" used in this specification are appended to avoid confusion among the constituent elements, and are not intended to limit the number.

[0098] In addition, in this specification and the like, devices on which such as FPC (Flexible Printed Circuits) or TCP (Tape Carrier Package) are mounted on the substrate of a display panel, or devices on which ICs (integrated circuits) are directly mounted on the substrate in the form of COG (Chip On Glass), are sometimes referred to as display devices.

[0099] In this specification and other materials, the terms "film" and "layer" may be interchanged depending on the circumstances or situation. For example, "conductive layer" may sometimes be replaced with "conductive film." Furthermore, "insulating film" may sometimes be replaced with "insulating layer."

[0100] <Notes on the definition of words and phrases>

[0101] The definitions of each term in the above embodiments will be explained below.

[0102] In this specification, "groove" or "slot" refers to a narrow, strip-shaped recess.

[0103] Additionally, in this specification, silicon oxynitride films are sometimes referred to as SiO. x N y At this point, x and y can be either natural numbers or numbers with a decimal point.

[0104] <About Connections>

[0105] In this specification, "A and B connection" includes not only the case where A and B are directly connected, but also the case where A and B are electrically connected. Here, "A and B electrical connection" means that when there are objects with some electrical interaction between A and B, it is possible to transmit and receive electrical signals between A and B.

[0106] Note that these expressions are merely examples and are not limited to those described above. Here, X, Y, Z1, and Z2 represent objects (e.g., devices, components, circuits, wiring, electrodes, terminals, conductive films, and layers, etc.).

[0107] Note that the content (or part thereof) described in one embodiment may be applied to, combined with or replaced by other content (or part thereof) described in that embodiment and / or content (or part thereof) described in one or more other embodiments.

[0108] Note that the content described in the embodiments refers to the content illustrated in the various drawings in each embodiment or the content recorded in the specification document.

[0109] Furthermore, more drawings can be formed by combining the drawings (or a portion thereof) shown in one embodiment with other portions of the drawings, other drawings (or a portion thereof) shown in that embodiment, and / or drawings (or a portion thereof) shown in one or more other embodiments.

[0110] Implementation Method 1

[0111] In this embodiment, a semiconductor device and its manufacturing method according to one aspect of the present invention will be described using the accompanying drawings.

[0112] FIG. 1A , FIG. 1B , FIG. 1C This is a top view and a cross-sectional view of a transistor 10 according to one embodiment of the present invention. FIG. 1A It is a top view. FIG. 1B It is along FIG. 1A The cross-sectional view shown is the dotted-dash line A1-A2. FIG. 1C This is a cross-sectional view along the dashed-dot line A3-A4. Note that... FIG. 1A In this text, for clarity, some constituent elements are enlarged, reduced, or omitted. Sometimes the direction of the dashed line A1-A2 is called the channel length direction, and the direction of the dashed line A3-A4 is called the channel width direction.

[0113] Transistor 10 includes a substrate 100, an insulating layer 110, an oxide semiconductor layer 121, an oxide semiconductor layer 122, an oxide semiconductor layer 123, a source electrode layer 130, a drain electrode layer 140, a gate insulating layer 150, a gate electrode layer 160, an insulating layer 170, and an insulating layer 175. The insulating layer 110 is formed on the substrate 100. The oxide semiconductor layer 121 is formed on the insulating layer 110. The oxide semiconductor layer 122 is formed on the oxide semiconductor layer 121. The source electrode layer 130 and the drain electrode layer 140 are formed on the oxide semiconductor layer 122 and electrically connected thereto. The insulating layer 170 is formed on the insulating layer 110, the source electrode layer 130, and the drain electrode layer 140 and contacts the sides of the oxide semiconductor layers 121 and 122. The insulating layer 175 is formed on the insulating layer 170 and contacts the oxide semiconductor layer 123 on its side. The oxide semiconductor layer 123 is formed on the oxide semiconductor layer 122. The oxide semiconductor layer 123 is in contact with the side surfaces of the insulating layer 170, the insulating layer 175, the source electrode layer 130, and the drain electrode layer 140. A gate insulating layer 150 is formed on the oxide semiconductor layer 123. A gate electrode layer 160 is formed on the gate insulating layer 150.

[0114] Note that in FIG. 1B The diagram shows an example where the gate electrode layer 160 is a single layer, but the gate electrode layer 160 can also be a stack of gate electrode layers 161 and 162, which will be described later. The ends of the oxide semiconductor layer 123 and the gate insulating layer 150 included in the transistor 10 are located outside the gate electrode layer 160. In the above structure, the oxide semiconductor layers 122 and 123 are in contact with the source electrode layer 130 and the drain electrode layer 140, thus exhibiting a high heat dissipation effect for the heat generated in the oxide semiconductor layers 121, 122, and 123 during the operation of the transistor 10.

[0115] Furthermore, in transistor 10, when the insulating layer 170, which serves as the second insulating film, is formed, a mixture of the material of the insulating layer 110 and the material of the second insulating film, or the gas used in forming the second insulating film, is formed at the interface with the insulating layer 110. Oxygen (referred to as excess oxygen or exO) is added to this mixture or the insulating layer 110. Moreover, by performing a heat treatment, this oxygen diffuses into the oxide semiconductor layer 121 and the oxide semiconductor layer 122, thereby filling oxygen defects present in the oxide semiconductor layer 121 and the oxide semiconductor layer 122. This improves transistor characteristics (e.g., threshold voltage and reliability).

[0116] Note that, due to factors such as voltage, power, plasma, or substrate temperature applied during film formation by sputtering, the excess oxygen added during the formation of the second insulating film exists in various states, such as oxygen free radicals, oxygen ions, or oxygen atoms. At this time, the excess oxygen is in a state with more energy than its stable state and can enter the insulating layer 110.

[0117] Note that the method of adding oxygen is not limited to the above method. The excess oxygen can be included when forming the insulating layer 110, or other methods (such as ion implantation, plasma immersion ion implantation, etc.) can be used after forming the insulating layer 110.

[0118] In transistor 10, such as FIG. 1CAs shown in the cross-sectional view along A3-A4, in the channel width direction, the gate electrode layer 160 is opposite to the sides of oxide semiconductor layers 121, 122, and 123, separated by the gate insulating layer 150. That is, when a voltage is applied to the gate electrode layer 160, oxide semiconductor layers 121, 122, and 123 are surrounded by the electric field of the gate electrode layer 160 in the channel width direction. The structure of a transistor in which the semiconductor layers are surrounded by the electric field of the gate electrode layer 160 is called a surrounded channel (S-channel) structure. Because the transistor 10 can utilize slots to form the gate, source, and drain electrodes in a self-aligned manner, the alignment accuracy is high, and miniaturized transistors can be easily manufactured. This structure is called a self-aligned s-channel FET (SA s-channel FET) structure, a trench gate s-channel FET (Trenchgate s-channel FET) structure, a TGSA FET (Trench Gate Self Align) structure, or a GLSA FET (Gate Last Self Align FET).

[0119] Here, when oxide semiconductor layers 121, 122, and 123 are collectively referred to as oxide semiconductor layer 120, in the SA s-channel structure transistor, the channel is formed throughout the entire oxide semiconductor layer 120 (within the block) in the on-state, thus increasing the on-state current. On the other hand, in the off-state, since the entire channel region formed in the oxide semiconductor layer 120 is depleted, the off-state current can be further reduced.

[0120] Therefore, when the oxide semiconductor layer 123, the gate insulating layer 150, and the gate electrode layer 160 are formed in the trench 174, the embedding properties of each film can be improved, and the transistor 10 can be easily manufactured.

[0121] When transistor 10 has a TGSA structure, the parasitic capacitance generated between the gate electrode and the source electrode or between the gate electrode and the drain electrode can be reduced, and the cutoff frequency characteristics of transistor 10 are improved, so transistor 10 can perform high-speed response.

[0122] Note that the top surface of the source electrode layer 130 or the drain electrode layer 140 may also be located below, above, or at the same position as the bottom surface of the gate electrode layer 160.

[0123] Additionally, in transistor 10, FIG. 2A The groove 174 in the transistor can also have a straight shape. Additionally, in transistor 10, such as... FIG. 2B The top surface of the gate electrode layer 160 shown can also be lower than the top surface of the insulating layer 175. Additionally, in the transistor 10, it can also be as follows... FIG. 2C The insulating film 150a and the third oxide semiconductor film 123a are not planarized as shown. Alternatively, in the transistor 10, it is also possible to perform a similar process. FIG. 3A The ends of the source electrode layer 130 and the drain electrode layer shown can be shorter than or longer than the oxide semiconductor layer 122.

[0124] <Regarding the length of the trench>

[0125] For example, channel length refers to the distance between the source (source region or source electrode) and drain (drain region or drain electrode) in the region where the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in the on-state) overlaps with the gate electrode, or in the region forming the channel, in a top view of the transistor. Furthermore, the channel length in a transistor is not necessarily the same in all regions. That is, the channel length of a transistor is sometimes not limited to a single value. Therefore, in this specification, channel length refers to any value, maximum value, minimum value, or average value in the region forming the channel.

[0126] <Regarding the width of the trench>

[0127] Additionally, channel width refers, for example, to the length of the region where the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in the on state) overlaps with the gate electrode. Furthermore, the channel width in a transistor is not necessarily the same across all regions. That is, the channel width of a transistor is sometimes not limited to a single value. Therefore, in this specification, channel width refers to any value, maximum, minimum, or average value in the region forming the channel.

[0128] Furthermore, depending on the transistor's structure, the actual channel width in the region forming the channel (hereinafter referred to as the effective channel width) differs from the channel width shown in the transistor's top view (hereinafter referred to as the apparent channel width). For example, in transistors with a three-dimensional structure, the effect cannot be ignored because the effective channel width is sometimes greater than the apparent channel width shown in the transistor's top view. For instance, in micro-transistors with a three-dimensional structure, the proportion of the channel region formed on the semiconductor side surface is sometimes greater than the proportion formed on the semiconductor top surface. In this case, the effective channel width that actually forms the channel is greater than the apparent channel width shown in the top view.

[0129] In transistors with three-dimensional structures, it is sometimes difficult to estimate the effective channel width through actual measurements. For example, to estimate the effective channel width based on design values, it is necessary to assume that the shape of the semiconductor is known. Therefore, when the shape of the semiconductor is unclear, it is difficult to accurately measure the effective channel width.

[0130] <About SCW>

[0131] Therefore, in this specification, the channel width appearing in the region where the semiconductor and gate electrode overlap in a top view of the transistor is sometimes referred to as the "surrounded channel width (SCW)". Furthermore, in this specification, when simply described as "channel width", it sometimes refers to the surrounding channel width or the apparent channel width. Alternatively, in this specification, when simply described as "channel width", it sometimes refers to the actual channel width. Note that the values ​​of channel length, channel width, actual channel width, apparent channel width, surrounding channel width, etc., can be determined by obtaining cross-sectional TEM images and analyzing those images.

[0132] Furthermore, when calculating the field-effect mobility of a transistor or the current value per channel width, calculations are sometimes performed around the channel width. In such cases, the obtained values ​​may differ from those calculated using the actual channel width.

[0133] <Enhanced Features in Miniaturization>

[0134] To achieve high integration in semiconductor devices, transistor miniaturization is essential. However, it is known that transistor miniaturization leads to a deterioration in their electrical characteristics. The reduction in channel width results in a decrease in on-state current.

[0135] For example, in FIG. 1A , FIG. 1B , FIG. 1C In the transistor of one embodiment of the present invention shown, as described above, a third oxide semiconductor layer 123 is formed to cover the oxide semiconductor layer 122 in which the channel is formed, and the channel forming layer is not in contact with the gate insulating layer. Therefore, carrier scattering generated at the interface between the channel forming layer and the gate insulating layer can be suppressed, thereby increasing the on-state current of the transistor.

[0136] In one embodiment of the transistor of the present invention, a gate electrode layer 160 is formed such that it electrically surrounds the oxide semiconductor layer 122 used as a channel in the channel width direction, thereby applying a gate electric field to the oxide semiconductor layer 1223 in the lateral direction in addition to the vertical direction. In other words, a gate electric field is applied to the entire oxide semiconductor layer, and current flows through the entire oxide semiconductor layer 122, thereby further increasing the on-state current.

[0137] Furthermore, in one embodiment of the present invention, the transistor, by forming an oxide semiconductor layer 123 on oxide semiconductor layers 121 and 122, has the effect of making it less prone to forming interface energy levels. Moreover, by making the oxide semiconductor layer 122 the intermediate layer, it can simultaneously eliminate the influence of impurities introduced from above and below. Therefore, in addition to increasing the on-state current of the transistor, it can also achieve threshold voltage stabilization and a decrease in the S-value (subthreshold). Thus, Icut (the current when the gate voltage VG is 0V) can be reduced, thereby reducing power consumption. Furthermore, since the threshold voltage of the transistor is stable, the long-term reliability of the semiconductor device can be improved.

[0138] Note that in this embodiment, an oxide semiconductor layer 120 or the like is shown as being used as a channel, but one embodiment of the present invention is not limited to this. For example, depending on the situation or condition, materials including silicon (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or organic semiconductors can be used to form the channel, the vicinity of the channel, the source region, the drain region, etc.

[0139] <Transistor Structure>

[0140] The structure of the transistor in this embodiment is shown below.

[0141] Substrate 100

[0142] The substrate 100 can be, for example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. Alternatively, it can be a single-crystal semiconductor substrate or a polycrystalline semiconductor substrate made of materials such as silicon or silicon carbide, a compound semiconductor substrate made of materials such as silicon-germanium, an SOI (Semiconductor on Insulator) substrate, etc., and semiconductor elements can be disposed on the aforementioned substrates and used as the substrate 100. The substrate 100 is not limited to a simple support material and can also be a substrate on which other devices such as transistors are formed. In this case, one of the gate electrode layer 160, source electrode layer 130, and drain electrode layer 140 of the transistor can also be electrically connected to the aforementioned other devices.

[0143] Furthermore, a flexible substrate can also be used as substrate 100. Another method for forming a transistor on a flexible substrate is to form a transistor on a non-flexible substrate, then peel off the transistor and transfer it to substrate 100 on the flexible substrate. In this case, it is preferable to provide a release layer between the non-flexible substrate and the transistor. Furthermore, a sheet, film, or foil containing fibers can also be used as substrate 100. Additionally, substrate 100 can also be stretchable. Furthermore, substrate 100 can have the property of returning to its original shape when bending or stretching stops. Alternatively, substrate 100 can also have the property of not returning to its original shape. The thickness of substrate 100 is, for example, 5 μm or more and 700 μm or less, preferably 10 μm or more and 500 μm or less, more preferably 15 μm or more and 300 μm or less. When the thickness of substrate 100 is very small, the semiconductor device can be made lighter. Furthermore, when the thickness of substrate 100 is very small, even when using glass or the like, it may sometimes have the property of stretchability or returning to its original shape when bending or stretching stops. Therefore, it is possible to mitigate the impact on the semiconductor device on the substrate 100 caused by drops or other factors. In other words, it is possible to provide a semiconductor device with high durability.

[0144] The substrate 100, as a flexible substrate, can be made of materials such as metal, alloy, resin, glass, or its fibers. A lower coefficient of linear expansion of the substrate 100 is preferred, as deformation due to environmental factors is more suppressed. Materials with a coefficient of linear expansion of 1×10⁻³ / K or less, 5×10⁻⁵ / K or less, or 1×10⁻⁵ / K or less can be used as the flexible substrate 100. Examples of resins include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic resin, and polytetrafluoroethylene (PTFE). Aromatic polyamides, in particular, have a low coefficient of linear expansion and are therefore suitable for use as flexible substrates.

[0145] Insulation Layer 110

[0146] In addition to preventing the diffusion of impurities from the substrate 100, the insulating layer 110 can also supply oxygen to the oxide semiconductor layer 120. Therefore, the insulating layer 110 is preferably an oxygen-containing insulating film, and more preferably an insulating film containing more oxygen than its stoichiometric composition. For example, the insulating layer 110 has an oxygen release amount equivalent to oxygen atoms measured using TDS (Thermal Desorption Spectroscopy) of 1.0 × 10⁻⁶. 19 atoms / cm 3The above refers to the film. Note that the surface temperature of the film during the TDS analysis is preferably 100°C or higher and 700°C or lower, or 100°C or higher and 500°C or lower. Furthermore, as described above, when the substrate 100 is a substrate on which other devices are formed, the insulating layer 110 is also used as an interlayer insulating film. In this case, planarization treatment using methods such as CMP (Chemical Mechanical Polishing) is preferred to make its surface flat.

[0147] Oxide semiconductor layer 121, oxide semiconductor layer 122, oxide semiconductor layer 123

[0148] The oxide semiconductor layer 122 is an oxide semiconductor film containing In or Zn, typically In-Ga oxide, In-Zn oxide, In-Mg oxide, Zn-Mg oxide, In-M-Zn oxide (M is Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg or Nd).

[0149] For example, the oxide semiconductors that can be used as oxide semiconductor layers 121, 122, and 123 preferably contain at least indium (In) or zinc (Zn). It is preferable to contain both In and Zn. Furthermore, in order to reduce electrical characteristic deviations in transistors using this oxide semiconductor, in addition to the elements mentioned above, a stabilizer is preferably also included.

[0150] Examples of stabilizers include gallium (Ga), tin (Sn), hafnium (Hf), aluminum (Al), and zirconium (Zr). Other examples of stabilizers include lanthanide elements such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu).

[0151] Furthermore, when the oxide semiconductor layer 123 is an In-M-Zn oxide, the atomic ratio of In to M is preferably 25 atomic% or more for In and less than 75 atomic% for M, more preferably 34 atomic% or more for In and less than 66 atomic% for M.

[0152] The content of indium or gallium in the oxide semiconductor layer 123 can be compared by time-of-flight secondary ion mass spectrometry (TOF-SIMS), X-ray photoelectron spectroscopy (XPS), or ICP mass spectrometry (ICP-MS).

[0153] Since the bandgap of the oxide semiconductor layer 122 is 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more, the off-state current of the transistor 10 can be reduced.

[0154] The thickness of the oxide semiconductor layer 122 is 3 nm or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, and more preferably 3 nm or more and 50 nm or less.

[0155] Oxide semiconductor layers 121 and 123 are oxide insulating films composed of one or more of the elements constituting oxide semiconductor layer 122. Therefore, interface scattering is less likely to occur at the interfaces between oxide semiconductor layers 122 and oxide semiconductor layers 122 and 124. Consequently, since carrier movement is not hindered at these interfaces, the field-effect mobility of transistor 10 is increased.

[0156] The oxide semiconductor layers 121 and 123 are typically In-Ga oxide, In-Zn oxide, In-Mg oxide, Ga-Zn oxide, Zn-Mg oxide, or In-M-Zn oxide (M is Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd), and their conduction band bottom energy levels are closer to the vacuum energy level than those of the oxide semiconductor layer 122. Typically, the energy difference between the conduction band bottom energy levels of the oxide semiconductor layers 121 and 123 and the conduction band bottom energy level of the oxide semiconductor layer 122 is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.2 eV or more and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less. In other words, the difference between the electron affinity of oxide semiconductor layers 121 and 123 and the electron affinity of oxide semiconductor layer 122 is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.2 eV or more and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less. Furthermore, the electron affinity represents the energy difference between the vacuum level and the conduction band bottom.

[0157] By including Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd in oxide semiconductor layers 121 and 123 with a higher atomic ratio than In, the following effects can sometimes be obtained: (1) the band gap of oxide semiconductor layers 121, 122, and 124 is increased; (2) the electron affinity of oxide semiconductor layers 121 and 123 is decreased; (3) impurities from the outside are shielded; (4) the insulation of oxide semiconductor layers 121 and 123 is higher than that of oxide semiconductor layer 122; (5) because Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd are metal elements with strong bonding with oxygen, it is not easy to generate oxygen defects by including Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd in a higher atomic ratio than In.

[0158] The oxide semiconductor layers 121 and 123 have higher insulation properties than the oxide semiconductor layer 122, and therefore have the same function as the gate insulating layer.

[0159] When the oxide semiconductor layer 121 and the oxide semiconductor layer 123 are In-M-Zn oxides, the percentage of In and M atoms other than Zn and O is preferably 50 atomic% or less for In and 50 atomic% or more for M, more preferably 25 atomic% or less for In and 75 atomic% or more for M.

[0160] Furthermore, when oxide semiconductor layers 121 and 123 are In-M-Zn oxides (M being Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd), the number of M (Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd) atoms contained in oxide semiconductor layers 121 and 123 is higher than that in oxide semiconductor layer 122, typically 1.5 times or more, preferably 2 times or more, and more preferably 3 times or more. The bonding force between the element represented by M and oxygen is stronger than that of indium, thus it has the function of suppressing oxygen defects in oxide semiconductor layers 121 and 123. In other words, oxide semiconductor layers 121 and 123 are oxide semiconductor films that are less prone to oxygen defects compared to oxide semiconductor layer 122.

[0161] The indium content of the oxide semiconductor layer 122 is preferably higher than that of the oxide semiconductor layers 121 and 123. In an oxide semiconductor, the s orbitals of heavy metals mainly contribute to carrier conduction, and by increasing the ratio of In, the overlap of s orbitals is increased. As a result, the mobility of an oxide with a higher ratio of In than M is higher than that of an oxide with a ratio of In equal to or less than M. Therefore, by using an oxide with a high indium content for the oxide semiconductor layer 122, a transistor with a high field-effect mobility can be achieved.

[0162] When the oxide semiconductor layer 122 is an In-M-Zn oxide (M is Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd), in the case where the atomic ratio of the metal elements in the target used to form the oxide semiconductor layer 122 is In:M:Zn = x1:y1:z1, x1 / y1 is preferably 1 / 3 or more and 6 or less, more preferably 1 or more and 6 or less, and z1 / y1 is preferably 1 / 3 or more and 6 or less, more preferably 1 or more and 6 or less. By making z1 / y1 1 or more and 6 or less, it becomes easy to form a CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor) film used as the oxide semiconductor layer 122. Typical examples of the atomic ratio of the metal elements in the target are In:M:Zn = 1:1:1, 1:1:1.2, 2:1:1.5, 2:1:2.3, 2:1:3, 3:1:2, 4:2:3, 4:2:4.1, etc.

[0163] When the oxide semiconductor layers 121 and 123 are In-M-Zn oxides (M is Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd), in the case where the atomic ratio of the metal elements in the targets used to form the oxide semiconductor layers 121 and 123 is In:M:Zn = x2:y2:z2, it is preferably x2 / y2 < x1 / y1, and z2 / y2 is 1 / 3 or more and 6 or less, more preferably 1 or more and 6 or less. By making z2 / y2 1 or more and 6 or less, it becomes easy to form a CAAC-OS film used as the oxide semiconductor layers 121 and 123. Typical examples of the atomic ratio of the metal elements in the targets are In:M:Zn = 1:3:2, 1:3:4, 1:3:6, 1:3:8, 1:4:4, 1:4:5, 1:4:6, 1:4:7, 1:4:8, 1:5:5, 1:5:6, 1:5:7, 1:5:8, 1:6:8, 1:6:4, 1:9:6, etc.

[0164] In addition, the atomic number ratio of oxide semiconductor layer 121 and oxide semiconductor layer 123 includes a variation of ±40% of the above atomic number ratio as an error.

[0165] The oxide semiconductor layer 123 can be a metal oxide, such as aluminum oxide (AlO). x Gallium oxide (GaO) x ), Hafnium oxide (HfO) x ), silicon dioxide (SiO) x germanium oxide (GeO) x ), or zirconium oxide (ZrO) x Alternatively, the metal oxide described above can be included on the oxide semiconductor layer 123.

[0166] Note that the atomic ratio is not limited to the above; an appropriate atomic ratio can also be set according to the necessary semiconductor characteristics.

[0167] Furthermore, the oxide semiconductor layer 121 and oxide semiconductor layer 123 can have the same composition. For example, as oxide semiconductor layer 121 and oxide semiconductor layer 123, In-Ga-Zn oxides with an atomic ratio of In:Ga:Zn of In:Ga:Zn = 1:3:2, 1:3:4 or 1:4:5 can be used.

[0168] Alternatively, the compositions of oxide semiconductor layer 121 and oxide semiconductor layer 123 can be different. For example, In-Ga-Zn oxide, in which the atomic ratio of the metal elements of the target material used in sputtering is In:Ga:Zn = 1:3:4, can be used as oxide semiconductor layer 121, and In-Ga-Zn oxide, in which the atomic ratio of the metal elements of the target material is In:Ga:Zn = 1:3:2, can be used as oxide semiconductor layer 123.

[0169] The thickness of oxide semiconductor layer 121, oxide semiconductor layer 122, and oxide semiconductor layer 123 is preferably 3 nm or more and 100 nm or more and 50 nm or less.

[0170] Here, the thickness of the oxide semiconductor layer 122 can be at least smaller, larger, or the same as that of the oxide semiconductor layer 121. For example, the thicker the oxide semiconductor layer 122, the higher the on-state current of the transistor. Furthermore, the thickness of the oxide semiconductor layer 121 only needs to suppress the formation of interface energy levels in the oxide semiconductor layer 122. For example, the thickness of the oxide semiconductor layer 122 can be greater than twice the thickness of the oxide semiconductor layer 121, or it can be more than twice, four times, or six times the thickness of the oxide semiconductor layer 121. Additionally, when it is not necessary to increase the on-state current of the transistor, the thickness of the oxide semiconductor layer 121 can be greater than or equal to the thickness of the oxide semiconductor layer 122. For example, when the insulating layer 110 or the insulating layer 175 contains excess oxygen, oxygen defects contained in the oxide semiconductor layer 122 can be reduced by heat treatment to diffuse the oxygen, thereby stabilizing the electrical characteristics of the semiconductor device.

[0171] Similarly, the thickness of the oxide semiconductor layer 123, as with the oxide semiconductor layer 121, is only required to suppress the formation of interface energy levels in the oxide semiconductor layer 122. For example, the thickness of the oxide semiconductor layer 123 can be equal to or less than that of the oxide semiconductor layer 121. When the oxide semiconductor layer 123 is very thick, the electric field from the gate electrode layer 160 (or, the gate electrode layer 161, the gate electrode layer 162) may not be easily applied to the oxide semiconductor layer 122, so it is preferable to form the oxide semiconductor layer 123 thin. For example, the thickness of the oxide semiconductor layer 123 can be smaller than that of the oxide semiconductor layer 122. However, this is not a limitation; the thickness of the oxide semiconductor layer 123 can be appropriately set according to the voltage of the driving transistor, taking into account the withstand voltage of the gate insulating layer 150.

[0172] When the compositions of oxide semiconductor layer 121, oxide semiconductor layer 122 and oxide semiconductor layer 123 are different, the interface can sometimes be observed using STEM (Scanning Transmission Electron Microscope).

[0173] <Regarding hydrogen concentration>

[0174] In oxide semiconductor layers 121, 122, and 123, hydrogen reacts with oxygen bonded to metal atoms to form water. Simultaneously, oxygen defects form in the lattice where oxygen has detached (or in the detached portion). When hydrogen enters this oxygen defect, electrons are sometimes generated as charge carriers. Additionally, when a portion of the hydrogen bonds with oxygen bonded to metal atoms, electrons are sometimes generated as charge carriers. Therefore, transistors using hydrogen-containing oxide semiconductors tend to have always-on characteristics.

[0175] Therefore, it is preferable to minimize oxygen defects and hydrogen at the interfaces between oxide semiconductor layers 121, 122, and 123. For example, the hydrogen concentration at the interfaces between oxide semiconductor layers 121, 122, and 123, as measured by secondary ion mass spectrometry (SIMS), is 1 × 10⁻⁶. 16 atoms / cm 3 Above and 2×10 20 atoms / cm 3 The following is preferred: 1×10 16 atoms / cm 3 Above and 5×10 19 atoms / cm 3 Hereinafter, 1×10 is more preferred. 16 atoms / cm 3 Above and 1×10 19 atoms / cm 3 Hereinafter, 1×10 is further preferred. 16 atoms / cm 3 Above and 5×10 18 atoms / cm 3 As a result, transistor 10 can have a positive threshold voltage (also known as normally off characteristic).

[0176] <Regarding carbon concentration and silicon concentration>

[0177] When the interfaces between oxide semiconductor layers 121, 122, and 123 contain silicon or carbon, which are elements of Group 14, oxygen defects increase in oxide semiconductor layers 121, 122, and 123, resulting in the formation of n-type regions. Therefore, it is preferable to reduce the silicon and carbon concentrations at the interfaces between oxide semiconductor layers 121, 122, and 123. For example, the silicon or carbon concentration at the interfaces between oxide semiconductor layers 121, 122, 123, and 124, as measured by SIMS, is 1 × 10⁻⁶. 16 atoms / cm 3 Above and 1×10 19 atoms / cm 3 The following is preferred: 1×10 16 atoms / cm 3 Above and 5×10 18atoms / cm 3 Hereinafter, 1×10 is more preferred. 16 atoms / cm 3 Above and 2×10 18 atoms / cm 3 As a result, transistor 10 has a positive threshold voltage (also known as normally off characteristic).

[0178] <Regarding Alkali Metal Concentration>

[0179] Sometimes, when alkali metals and alkaline earth metals bond with oxide semiconductors, charge carriers are generated, increasing the off-state current of the transistor. Therefore, it is preferable to reduce the concentration of alkali metals or alkaline earth metals at the interfaces between oxide semiconductor layers 121, 122, and 123. For example, the concentration of alkali metals or alkaline earth metals at the interfaces between oxide semiconductor layers 121, 122, and 123, as measured by secondary ion mass spectrometry, is preferably 1 × 10⁻⁶. 18 atoms / cm 3 The following is more preferably 2×10 16 atoms / cm 3 As a result, transistor 10 can have a positive threshold voltage (also known as normally off characteristic).

[0180] <Regarding nitrogen concentration>

[0181] Furthermore, when nitrogen is present at the interfaces between oxide semiconductor layers 121, 122, and 123, electrons are generated as charge carriers, thus increasing the charge carrier density and forming an n-type region. As a result, transistors using nitrogen-containing oxide semiconductors tend to have always-on characteristics. Therefore, it is preferable to minimize nitrogen concentration at the interfaces between oxide semiconductor layers 121, 122, and 123. For example, the nitrogen concentration at the interfaces between oxide semiconductor layers 121, 122, and 123, as measured by SIMS, is 1 × 10⁻⁶. 15 atoms / cm 3 Above and 5×10 19 atoms / cm 3 The following is preferred: 1×10 15 atoms / cm 3 Above and 5×10 18 atoms / cm 3 Hereinafter, 1×10 is more preferred. 15 atoms / cm 3 Above and 1×10 18atoms / cm 3 Hereinafter, 1×10 is further preferred. 15 atoms / cm 3 Above 5×10 17 atoms / cm 3 As a result, transistor 10 can have a positive threshold voltage (also known as normally off characteristic).

[0182] <Regarding carrier density>

[0183] By reducing impurities in oxide semiconductor layers 121, 122, and 123, the carrier density of oxide semiconductor layers 121, 122, and 123 can be reduced. Therefore, the carrier density of oxide semiconductor layers 121, 122, and 123 is 1 × 10⁻⁶. 15 pcs / cm 3 The following is preferred: 1×10 13 pcs / cm 3 Below, less than 8×10 is preferred. 11 pcs / cm 3 Further optimization of less than 1×10 11 pcs / cm 3 The optimal choice is less than 1×10. 10 pcs / cm 3 And it is 1×10 -9 pcs / cm 3 above.

[0184] By using oxide semiconductor films with low impurity concentration and low defect level density as oxide semiconductor layers 121, 122, and 123, transistors with superior electrical characteristics can be fabricated. Here, the state of low impurity concentration and low defect level density (few oxygen defects) is referred to as high-purity intrinsic or substantially high-purity intrinsic. Because high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors have fewer carrier generation sources, the carrier density can sometimes be reduced. Therefore, transistors with channel regions formed in this oxide semiconductor film tend to have a positive threshold voltage (also known as normally-off characteristics). Furthermore, high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor films have a low defect level density, and therefore sometimes a low trap state density. Moreover, the off-state current of high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor films is significantly small; when the voltage between the source and drain electrodes (drain voltage) is in the range of 1V to 10V, the off-state current can be below the measurement limit of a semiconductor parameter analyzer, being 1×10⁻⁶. -13Below A. Therefore, sometimes the electrical characteristics of transistors with channel regions formed in this oxide semiconductor film vary little, thus making the transistor a highly reliable transistor.

[0185] Furthermore, transistors using highly purified oxide semiconductor films, as described above, in the channel formation region exhibit extremely low off-state currents. For example, with a source-drain voltage of approximately 0.1V, 5V, or 10V, the off-state current, normalized to the transistor's channel width, can be reduced to a few μA / μm to a few zA / μm.

[0186] The oxide semiconductor layers 121, 122, and 123 can be, for example, non-single-crystal structures. Non-single-crystal structures can have, for example, CAAC-OS, polycrystalline, microcrystalline, or amorphous structures as described later. Among non-single-crystal structures, amorphous structures have the highest defect level density, while CAAC-OS has the lowest.

[0187] The oxide semiconductor layers 121, 122, and 123 may, for example, have a microcrystalline structure. The microcrystalline oxide semiconductor layers 121, 122, and 123 may, for example, contain microcrystals with a size of 1 nm or more and less than 10 nm. Alternatively, the oxide film and oxide semiconductor film with the microcrystalline structure may, for example, have a mixed-phase structure having crystalline portions of 1 nm or more and less than 10 nm in the amorphous phase.

[0188] Oxide semiconductor layers 121, 122, and 123 may, for example, have an amorphous structure. Amorphous oxide semiconductor layers 121, 122, and 123 may, for example, have disordered atomic arrangement and lack crystalline components. Alternatively, the amorphous oxide film may be, for example, a completely amorphous structure without crystalline regions.

[0189] Alternatively, oxide semiconductor layers 121, 122, and 123 can also be hybrid films having two or more regions selected from CAAC-OS, microcrystalline structures, and amorphous structures. Examples of hybrid films include monolayer structures having amorphous, microcrystalline, and CAAC-OS regions. Alternatively, examples of hybrid films include stacked structures having amorphous, microcrystalline, and CAAC-OS regions.

[0190] The oxide semiconductor layer 121, oxide semiconductor layer 122 and oxide semiconductor layer 123 may also have a single crystal structure, for example.

[0191] By providing an oxide semiconductor film, which is less prone to oxygen defects compared to oxide semiconductor layer 122, in a manner that creates vertical contact with oxide semiconductor layer 122, oxygen defects in oxide semiconductor layer 122 can be reduced. Furthermore, since oxide semiconductor layer 122 is in contact with oxide semiconductor layers 121 and 123 containing one or more of the metal elements constituting oxide semiconductor layer 122, the interface energy level densities at the interfaces between oxide semiconductor layers 121 and 122, and between oxide semiconductor layers 122 and 123, are extremely low. For example, although oxygen is added to insulating layer 110 and then moves from oxide semiconductor layer 121 to oxide semiconductor layer 122 via heat treatment, the oxygen is not easily trapped by the interface energy levels, thus enabling efficient movement of oxygen contained in oxide semiconductor layer 121 to oxide semiconductor layer 122. As a result, oxygen defects contained in oxide semiconductor layer 122 can be reduced. Additionally, since oxygen is also added to oxide semiconductor layer 121, oxygen defects in oxide semiconductor layer 121 can be reduced. In other words, at least the local energy level density of the oxide semiconductor layer 122 can be reduced.

[0192] Furthermore, when the oxide semiconductor layer 122 contacts an insulating film with different constituent elements (e.g., a gate insulating layer containing a silicon oxide film), an interface energy level may sometimes be formed, and this interface energy level forms a channel. In this case, a second transistor with a different threshold voltage may sometimes appear, resulting in a variation in the threshold voltage of the transistor. However, since the oxide semiconductor layer 121 and oxide semiconductor layer 123, which contain one or more of the metal elements constituting the oxide semiconductor layer 122, are in contact with the oxide semiconductor layer 122, interface energy levels are less likely to form at the interfaces between oxide semiconductor layers 121 and 122, and at the interfaces between oxide semiconductor layers 123 and 122.

[0193] In addition, oxide semiconductor layers 121 and 123 can be used as barrier films to suppress the incorporation of constituent elements of insulating layer 110 and gate insulating layer 150 into oxide semiconductor layer 122, thereby forming energy levels caused by impurities.

[0194] For example, when a silicon-containing insulating film is used as insulating layer 110 or gate insulating layer 150, silicon in gate insulating layer 150 or carbon in insulating layer 110 and gate insulating layer 150 may sometimes be mixed into the portion of oxide semiconductor layer 121 or oxide semiconductor layer 123 that is a few nm away from the interface. If impurities such as silicon and carbon are mixed into oxide semiconductor layer 122, they will form impurity energy levels, which may sometimes become donors and generate electrons, thus becoming n-type.

[0195] However, if the film thickness of oxide semiconductor layer 121 and oxide semiconductor layer 123 is more than a few nm, the impurities such as silicon and carbon mixed in will not reach oxide semiconductor layer 122, thus reducing the influence of impurity energy levels.

[0196] In other words, by setting oxide semiconductor layer 121 and oxide semiconductor layer 123, the non-uniformity of the threshold voltage and other electrical characteristics of the transistor can be reduced.

[0197] Furthermore, when the gate insulating layer 150 contacts the oxide semiconductor layer 122 and a channel is formed at their interface, interface scattering occurs at the interface, resulting in a decrease in the field-effect mobility of the transistor. However, by providing oxide semiconductor layers 121 and 123 containing one or more of the metal elements constituting oxide semiconductor layer 122 in contact with oxide semiconductor layer 122, carrier scattering is less likely to occur at the interface between oxide semiconductor layer 122 and oxide semiconductor layers 121 and 123, thereby improving the field-effect mobility of the transistor.

[0198] In this embodiment, not only can the oxygen defect amount in the oxide semiconductor layer 122 be reduced, but the oxygen defect amount in the oxide semiconductor layers 121 and 123 that are in contact with the oxide semiconductor layer 122 can also be reduced, thus reducing the local energy level density of the oxide semiconductor layer 122. As a result, the threshold voltage variation of the transistor 10 shown in this embodiment is small and the reliability is high. In addition, the transistor 10 shown in this embodiment has excellent electrical characteristics.

[0199] Furthermore, silicon-containing insulating films are mostly used as the gate insulating layer of transistors. For the reasons mentioned above, it is preferable that the region of the oxide semiconductor layer used as the channel is not in contact with the gate insulating layer, as in the transistor of one embodiment of the present invention. Additionally, when a channel is formed at the interface between the gate insulating layer and the oxide semiconductor layer, carrier scattering sometimes occurs at this interface, reducing the field-effect mobility of the transistor. From the above viewpoint, it is preferable to separate the region of the oxide semiconductor layer used as the channel from the gate insulating layer.

[0200] Therefore, by having the oxide semiconductor layer 120 have a stacked structure of oxide semiconductor layer 121, oxide semiconductor layer 122 and oxide semiconductor layer 123, a channel can be formed in the oxide semiconductor layer 123, thereby forming a transistor with high field-effect mobility and stable electrical characteristics.

[0201] Note that the oxide semiconductor does not necessarily have to be three layers; it can also be a single layer, two layers, four layers, or five or more layers. When the oxide semiconductor layer is a single layer, a layer equivalent to the oxide semiconductor layer 122 shown in this embodiment can be used.

[0202] <with pictures>

[0203] Here, the strip diagram is explained. For ease of understanding, the energy level (Ec) of the conduction band bottom of insulating layer 110, oxide semiconductor layer 121, oxide semiconductor layer 122, oxide semiconductor layer 123 and gate insulating layer 150 is shown in the strip diagram.

[0204] like FIG. 4A and FIG. 4B As shown, the energy levels at the bottom of the conduction band change continuously in oxide semiconductor layers 121, 122, and 123. This is understandable because, since oxide semiconductor layers 121, 122, and 123 are composed of the same elements, oxygen readily diffuses into each other. Therefore, although oxide semiconductor layers 121, 122, and 123 are stacks of different films, they can be considered to be continuous in terms of physical properties.

[0205] The stacked oxide semiconductor films, which are composed of the same main components, are not simply stacked layers, but rather formed in a manner that creates continuous bonding (specifically, U-shaped well structures where the energy levels at the conduction band bottoms of the layers change continuously). The stacked structure is formed so that impurities that could form defect energy levels such as trapping or recombination centers are absent at the interfaces between the layers. If impurities are introduced into the interlayer spaces of the stacked multilayer films, the energy bands lose their continuity, and charge carriers are trapped or recombine at the interfaces and disappear.

[0206] Notice, FIG. 4B Although the oxide semiconductor layer 121 and the oxide semiconductor layer 123 are shown to have the same Ec, they can also be different from each other.

[0207] Depend on FIG. 4B As can be seen, since the oxide semiconductor layer 122 forms a well, the channel in the transistor 10 is formed in the oxide semiconductor layer 122. Alternatively, the channel of the U-shaped well structure with the conduction band bottom continuously changing energy level as the bottom of the oxide semiconductor layer 122 can also be called a buried channel.

[0208] Trapping levels caused by impurities or defects may form near the interfaces of oxide semiconductor layers 121 and 123 with insulating films such as silicon oxide films. The presence of oxide semiconductor layers 121 and 123 can keep oxide semiconductor layer 122 away from these trapping levels. However, when the energy difference between Ec of oxide semiconductor layer 121 or 123 and Ec of oxide semiconductor layer 122 is small, electrons from oxide semiconductor layer 122 may sometimes cross this energy difference and reach the trapping level. Electrons that become negatively charged are captured by the trapping level, resulting in a negative fixed charge at the interface of the insulating film, which causes the threshold voltage of the transistor to drift in the positive direction. Moreover, there is a concern that in long-term transistor holding experiments, the trapping may not be fixed, leading to characteristic variations.

[0209] Therefore, in order to reduce the variation in the threshold voltage of the transistor, it is necessary to generate an energy difference between the Ec of the oxide semiconductor layer 121 and oxide semiconductor layer 123 and the oxide semiconductor layer 122. This energy difference is preferably 0.1 eV or more, and more preferably 0.2 eV or more.

[0210] Furthermore, it is preferable that oxide semiconductor layers 121, 122, and 123 contain crystals. In particular, the use of c-axis oriented crystals can stabilize the electrical characteristics of the transistor.

[0211] In addition, in such FIG. 4B In the diagram shown, the oxide semiconductor layer 123 may be omitted, and instead, In-Ga oxide (e.g., In-Ga oxide with an atomic ratio of In:Ga = 7:93) or gallium oxide may be provided between the oxide semiconductor layer 123 and the gate insulating layer 150. With the oxide semiconductor layer 123 included, either In-Ga oxide or gallium oxide can be provided between the oxide semiconductor layer 123 and the gate insulating layer 150.

[0212] The oxide semiconductor layer 122 uses an oxide whose electron affinity is greater than that of the oxide semiconductor layers 121 and 123. For example, the oxide semiconductor layer 122 can use an oxide whose electron affinity is greater than that of the oxide semiconductor layers 121 and 123 by 0.07 eV or more and 1.3 eV or less, preferably greater than 0.1 eV or more and 0.7 eV or less, and more preferably greater than 0.2 eV or more and 0.4 eV or less.

[0213] The transistor shown in this embodiment has oxide semiconductor layers 121 and 123 containing one or more of the metal elements constituting oxide semiconductor layer 122. Therefore, interface energy levels are less likely to form at the interfaces between oxide semiconductor layers 121 and 122, and between oxide semiconductor layers 123 and 122. Thus, by providing oxide semiconductor layers 121 and 123, non-uniformity or variation in the threshold voltage and other electrical characteristics of the transistor can be reduced.

[0214] Source electrode layer 130, drain electrode layer 140

[0215] The source electrode layer 130 and the drain electrode layer 140 are preferably single layers or stacks of conductive layers containing the following materials: copper (Cu), tungsten (W), molybdenum (Mo), gold (Au), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), nickel (Ni), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt (Co), ruthenium (Ru), platinum (Pt), iridium (Ir), strontium (Sr), etc.; alloys thereof; or compounds containing oxygen, nitrogen, fluorine, silicon, etc., with the above materials as the main components. For example, in the case of a stack, the conductive layer on the lower side in contact with the oxide semiconductor layer 122 (e.g., FIG. 15A - FIG. 15C The source electrode layer 131 and drain electrode layer 141 shown may contain materials that readily bond with oxygen, and the upper conductive layer (e.g., FIG. 15A - FIG. 15C The source electrode layer 132 and drain electrode layer 142 shown may contain materials with high oxidation resistance. Furthermore, high-melting-point materials such as tungsten or molybdenum, which have heat resistance and conductivity, are preferably used. Additionally, the conductive layer is preferably formed using a low-resistance conductive material such as aluminum or copper. Moreover, when a Cu-Mn alloy is used, manganese oxide forms at the interface with the oxygen-containing insulator, and this manganese oxide can suppress Cu diffusion, so it is preferred.

[0216] When a conductive material that readily bonds with oxygen is brought into contact with an oxide semiconductor layer, oxygen diffuses from the oxide semiconductor layer to the side of the conductive material. Oxygen defects occur near the region in contact with the source or drain electrode layer of the oxide semiconductor layer. Trace amounts of hydrogen contained in the film enter these oxygen defects, causing the region to become significantly n-type. Therefore, this n-type region can be used as the source or drain of a transistor.

[0217] For example, by employing a stacked structure in which W is used as the lower conductive layer and Pt is used as the upper conductive layer, the oxide semiconductor of the contact can be n-type while the oxidation of the conductive layer caused by the contact with the insulating layer 170 can be suppressed.

[0218] Gate Insulating Layer 150

[0219] The gate insulating layer 150 may contain oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge), yttrium (Y), zirconium (Zr), lanthanum (La), neodymium (Nd), hafnium (Hf), tantalum (Ta), titanium (Ti), etc. For example, aluminum oxide (AlO) may be used. x ), magnesium oxide (MgO) x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y ), silicon oxynitride (SiN) x O y ), silicon nitride (SiN) x Gallium oxide (GaO) x germanium oxide (GeO) x ), Yttrium oxide (YO) x Zirconium oxide (ZrO) x ), Lanthanum oxide (LaO) x ), neodymium oxide (NdO) x ), Hafnium oxide (HfO) x ) and tantalum oxide (TaO) x The gate insulating layer 150 may be one or more of the above-mentioned materials. The gate insulating layer 150 may also contain lanthanum (La), nitrogen, zirconium (Zr), etc., as impurities.

[0220] Another example of the stacked structure of the gate insulating layer 150 is described. The gate insulating layer 150 includes, for example, oxygen, nitrogen, silicon, hafnium, etc. Specifically, it preferably includes hafnium oxide and silicon oxide or hafnium oxide and silicon oxynitride.

[0221] Hafnium oxide has a higher relative permittivity than silicon oxide or silicon oxynitride. Therefore, the physical thickness can be larger than the equivalent oxide thickness, and even if the equivalent oxide thickness is set to less than 10 nm or 5 nm, leakage current caused by tunneling current can be reduced. That is, transistors with low off-state current can be realized. Furthermore, hafnium oxide with a crystalline structure has a higher relative permittivity than hafnium oxide with an amorphous structure. Therefore, hafnium oxide with a crystalline structure is preferred for forming transistors with low off-state current. Examples of crystalline structures include monoclinic or cubic crystal systems. However, one aspect of the invention is not limited to these.

[0222] Furthermore, the surface of hafnium oxide, which has a crystalline structure, sometimes exhibits interface energy levels caused by defects. These interface energy levels are sometimes used as trap centers. Consequently, when hafnium oxide is disposed near the channel region of a transistor, these interface energy levels cause degradation of the transistor's electrical characteristics. Therefore, to reduce the influence of the interface energy levels, it is sometimes preferable to provide another film between the channel region of the transistor and the hafnium oxide to separate them. This film has a buffering function. The buffering film can be contained in the gate insulating layer 150 or in an oxide semiconductor film. That is, silicon oxide, silicon oxynitride, oxide semiconductors, etc., can be used as the buffering film. Alternatively, a semiconductor or insulator with a band gap larger than that of the semiconductor forming the channel region can be used as the buffering film. Alternatively, a semiconductor or insulator with an electron affinity smaller than that of the semiconductor forming the channel region can be used as the buffering film. Alternatively, a semiconductor or insulator with an ionization energy larger than that of the semiconductor forming the channel region can be used as the buffering film.

[0223] On the other hand, by trapping charges at the interface energy levels (trap centers) in the surface of hafnium oxide having the aforementioned crystalline structure, the threshold voltage of a transistor can sometimes be controlled. To ensure the stable existence of this charge, an insulator with a larger band gap than hafnium oxide can be provided between the channel region and the hafnium oxide, for example. Alternatively, a semiconductor or insulator with a smaller electron affinity than hafnium oxide can be provided. Furthermore, as a buffer film, a semiconductor or insulator with a larger ionization energy than hafnium oxide can be provided. By using such an insulator, the charges trapped at the interface energy levels are not easily released, thereby maintaining the charge for a long period.

[0224] Examples of insulators include silicon oxide and silicon oxynitride. By moving electrons from the oxide semiconductor film to the gate electrode layer 160, charge can be trapped at the interface energy level of the gate insulating layer 150. Specifically, conditions can be given such that the gate electrode layer 160 is held at a high temperature (e.g., above 125°C and below 450°C, typically above 150°C and below 300°C) for more than one second, typically more than one minute, with the potential of the gate electrode layer 160 being higher than that of the source electrode layer 130 or the drain electrode layer 140.

[0225] Thus, in a transistor that traps a desired amount of electrons at the interface energy level of the gate insulating layer 150, the threshold voltage shifts in the positive direction. The amount of electrons trapped (the change in threshold voltage) can be controlled by adjusting the voltage of the gate electrode layer 160 or the duration of the applied voltage. Alternatively, charge can also be trapped in layers other than the gate insulating layer 150. Furthermore, a multilayer film with the same structure can be used for other insulating layers.

[0226] Gate electrode layer 160

[0227] The gate electrode layer 160 can be made of conductive films such as aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), copper (Cu), yttrium (Y), zirconium (Zr), molybdenum (Mo), ruthenium (Ru), silver (Ag), tantalum (Ta), and tungsten (W). Alternatively, the gate electrode layer 160 can also employ a stacked structure. For example, as... FIG. 15A - FIG. 15C The gate electrode layer 162 shown can also use the above-described material, and the gate electrode layer 161 and the gate electrode layer 163 can be conductive films containing nitrogen, such as nitrides of the above-described material.

[0228] Insulation Layer 170

[0229] As the insulating layer 170, oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge), yttrium (Y), zirconium (Zr), lanthanum (La), neodymium (Nd), hafnium (Hf), tantalum (Ta), titanium (Ti), etc., can be used. For example, aluminum oxide (AlO) can be used. x ), magnesium oxide (MgO) x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y ), silicon oxynitride (SiN) x O y ), silicon nitride (SiN) x Gallium oxide (GaO) x germanium oxide (GeO) x ), Yttrium oxide (YO) x Zirconium oxide (ZrO) x ), Lanthanum oxide (LaO) x ), neodymium oxide (NdO) x ), Hafnium oxide (HfO) x ) and tantalum oxide (TaO) x One or more of the above-mentioned insulating films. In addition, the insulating layer 170 may also be a stack of the above-mentioned materials.

[0230] The insulating layer 170 preferably comprises an aluminum oxide film. The aluminum oxide film can have a barrier effect that prevents impurities such as hydrogen and moisture, as well as oxygen, from permeating through the film. Therefore, during and after the transistor manufacturing process, the aluminum oxide film is suitable as a protective film with the following effects: preventing impurities such as hydrogen and moisture that cause changes in the electrical characteristics of the transistor from mixing into the oxide semiconductor layer 121 and the oxide semiconductor layer 122; preventing oxygen, the main component of the oxide semiconductor layer 121 and the oxide semiconductor layer 122, from being released from the oxide semiconductor layer 121 and the oxide semiconductor layer 122; and preventing unnecessary release of oxygen from the insulating layer 110.

[0231] The insulating layer 170 is preferably a film with oxygen supply capability. When forming the second insulating film that becomes the insulating layer 170, a mixed layer is formed, which or the insulating layer 110 is added with oxygen. Due to subsequent heat treatment, the oxygen diffuses into the oxide semiconductor, which can supply oxygen defects in the oxide semiconductor, thereby improving transistor characteristics (e.g., threshold, reliability, etc.).

[0232] In addition, other insulating layers may be provided on the upper or lower side of the insulating layer 170. For example, the insulating layer 170 may use an insulating film containing one or more of magnesium oxide, silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. It may also contain oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge), yttrium (Y), zirconium (Zr), lanthanum (La), neodymium (Nd), hafnium (Hf), tantalum (Ta), titanium (Ti), etc. For example, an insulating film containing aluminum oxide (AlO) may be used. x ), magnesium oxide (MgO) x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y ), silicon oxynitride (SiN) x O y ), silicon nitride (SiN) x Gallium oxide (GaO) x germanium oxide (GeO) x ), Yttrium oxide (YO) x Zirconium oxide (ZrO) x ), Lanthanum oxide (LaO) x ), neodymium oxide (NdO) x ), Hafnium oxide (HfO) x ) and tantalum oxide (TaO) x The insulating layer 170 may be one or more of the above-mentioned materials. Alternatively, the insulating layer 170 may be a stack of the aforementioned materials. The insulating layer 170 preferably contains more oxygen than its stoichiometric composition. Oxygen released from this insulating layer can diffuse through the gate insulating layer 150 to the channel formation region of the oxide semiconductor layer 120, thus filling oxygen defects formed in the channel formation region. Therefore, stable transistor electrical characteristics can be obtained.

[0233] Insulation Layer 175

[0234] The insulating layer 175 can be made of elements including oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge), yttrium (Y), zirconium (Zr), lanthanum (La), neodymium (Nd), hafnium (Hf), tantalum (Ta), and titanium (Ti). For example, the insulating layer 175 can be made of elements including magnesium oxide (MgO). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x Nx), silicon oxynitride (SiN) x Ox), silicon nitride (SiN) x Gallium oxide (GaO) x germanium oxide (GeO) x ), Yttrium oxide (YO) x Zirconium oxide (ZrO) x ), Lanthanum oxide (LaO) x ), neodymium oxide (NdO) x ), Hafnium oxide (HfO) x ) and tantalum oxide (TaO) x ), aluminum oxide (AlO) x One or more insulating films of the above-mentioned materials. The insulating layer 175 may also be a stack of the above-mentioned materials. The insulating layer preferably contains more oxygen than the stoichiometric composition.

[0235] The insulating layer 175 can be made of a low-k material. For example, it can be silicon oxide (SiOF) with a few percent fluorine (F), silicon oxide (SiOC) with a few percent carbon (C), fluorosilicate glass (FSG), organosilicon glass (OSG), silsesquioxane (HSQ), methylsilsesquioxane (MSQ), organic polymers, polyimides, fluoropolymers (such as polytetrafluoroethylene), and amorphous carbon with added fluorine. By using a low-k material for the insulating layer 175, the capacitance of the transistor 10 can be further reduced.

[0236] <Transistor Manufacturing Methods>

[0237] Next, use FIG. 5A - FIG. 5C to FIG. 13A - FIG. 13C This describes a method for manufacturing the semiconductor device according to this embodiment. Note that parts that are repeated in the description of the transistor structure described above are omitted. Sometimes... FIG. 7A - FIG. 7C to FIG. 13A - FIG. 13C The direction shown as A1-A2 is called FIG. 1A and FIG. 1B The direction of the channel length is shown. Sometimes... FIG. 7A - FIG. 7C to FIG. 13A - FIG. 13C The direction shown as A3-A4 is called FIG. 1A and FIG. 1C The width direction of the channel is shown.

[0238] In this embodiment, each layer (insulating layer, oxide semiconductor layer, conductive layer, etc.) constituting the transistor can be formed by sputtering, chemical vapor deposition (CVD), vacuum evaporation, pulsed laser deposition (PLD). Alternatively, it can be formed by coating or printing. As typical film formation methods, there are sputtering and plasma-enhanced chemical vapor deposition (PECVD), but thermal CVD can also be used. As an example of thermal CVD, metalorganic chemical vapor deposition (MOCVD) or atomic layer deposition (ALD) can be used.

[0239] <Thermal CVD method>

[0240] Since the thermal CVD method is a film formation method that does not use plasma, it has the advantage of not generating defects caused by plasma damage.

[0241] Film formation using the thermal CVD method can be carried out as follows: the source gas and the oxidant are simultaneously supplied into the processing chamber, the pressure in the processing chamber is set to atmospheric pressure or reduced pressure, and they react near or on the substrate to be deposited on the substrate.

[0242] Using thermal CVD methods such as MOCVD or ALD, various films such as metal films, semiconductor films, and inorganic insulating films disclosed in the above embodiments can be formed. For example, when forming an In-Ga-Zn-O film, trimethylindium, trimethylgallium, and dimethylzinc can be used. The chemical formula of trimethylindium is In(CH3)3. The chemical formula of trimethylgallium is Ga(CH3)3. The chemical formula of dimethylzinc is Zn(CH3)2. However, it is not limited to the above combination, and triethylgallium (chemical formula: Ga(C2H5)3) can be used instead of trimethylgallium, and diethylzinc (chemical formula: Zn(C2H5)2) can be used instead of dimethylzinc.

[0243] <ALD method>

[0244] In existing film formation apparatuses using the CVD method, one or more source gases (precursors) for reaction are simultaneously supplied into the processing chamber during film formation. In a film formation apparatus using the ALD method, the precursors for reaction are sequentially introduced into the processing chamber, and the gases are repeatedly introduced in that order to perform film formation. For example, by switching each switching valve (also called a high-speed valve), two or more precursors are sequentially supplied into the processing chamber. To prevent mixing of multiple precursors, an inert gas (argon or nitrogen, etc.) is introduced after introducing the first precursor, and then the second precursor is introduced. Alternatively, the first precursor can be exhausted by vacuum pumping instead of introducing an inert gas, and then the second precursor is introduced.

[0245] FIG. 5A - FIG. 5DThe ALD film formation process is illustrated. The first precursor 601 is attached to the substrate surface (see reference). FIG. 5A This forms the first single layer (refer to...). FIG. 5B At this point, the metal atoms contained in the precursor can bond to hydroxyl groups present on the substrate surface. The metal atoms can also bond to alkyl groups such as methyl and ethyl groups. The second precursor 602, introduced after the first precursor 601 is degassed, reacts with the first monolayer (see reference). FIG. 5C Thus, the second monolayer is stacked on the first monolayer to form a thin film (see reference). FIG. 5D For example, when the second precursor contains an oxidizing agent, the metal atoms present in the first precursor or the alkyl groups bonded to the metal atoms react chemically with the oxidizing agent to form an oxide film. Alternatively, when a hydrogen-containing gas is used as the second precursor, a metal film can be formed through a reduction reaction.

[0246] ALD (Alternating Layer Deposition) is a film-forming method based on surface chemical reactions. A precursor adheres to the surface to be formed, and a self-terminating mechanism acts to create a layer. For example, a precursor such as trimethylaluminum reacts with hydroxyl (OH) groups present on the surface to be formed. In this case, only a thermally induced surface reaction occurs, thus the precursor comes into contact with the surface, and metal atoms in the precursor can adhere to the surface using thermal energy. Precursors have the following characteristics: high vapor pressure; thermal stability without decomposition before film formation; and rapid chemical adhesion to the substrate. Because the precursor is introduced as a gas, sufficient diffusion time allows for high coverage film formation even in areas with high aspect ratios and uneven surfaces.

[0247] Furthermore, in the ALD process, by repeatedly introducing gas in this sequence until the desired thickness is achieved, a thin film with good step coverage can be formed. Since the film thickness can be adjusted according to the number of times the gas is introduced in sequence, the ALD process allows for precise thickness control. Increasing the venting capacity can improve the film formation rate and reduce the impurity concentration in the film.

[0248] ALD methods include thermal ALD (using heat) and plasma ALD (using plasma). Thermal ALD uses thermal energy to induce a reaction in precursors, while plasma ALD uses free radicals to induce a reaction between precursors.

[0249] The ALD method can accurately form extremely thin films. It can also form high-density films with high surface coverage even on uneven surfaces.

[0250] Plasma ALD

[0251] In addition, by using the plasma ALD method, film formation can be performed at a lower temperature than the ALD method using heat (thermal ALD method). For example, the plasma ALD method can perform film formation even at temperatures below 100°C without reducing the film formation rate. In addition, in the plasma ALD method, N2 can be radicalized by plasma, so that nitride films can be formed in addition to oxide films.

[0252] In the plasma ALD method, the oxidizing property of the oxidant can be enhanced. As a result, the precursors remaining in the film or the organic components detached from the precursors during film formation by plasma ALD can be reduced, and carbon, chlorine, hydrogen, etc. in the film can be reduced, so that a film with a low impurity concentration can be formed.

[0253] In addition, when performing plasma ALD, radical species are generated. Like ICP (Inductively Coupled Plasma), the plasma can be generated in a state separated from the substrate, thereby suppressing plasma damage to the substrate or the protective film formed thereon.

[0254] By using the plasma ALD method as described above, compared with other film formation methods, the process temperature can be reduced and the surface coverage can be increased, whereby the film can be formed. As a result, the entry of water and hydrogen from the outside can be suppressed. Therefore, the reliability of transistor characteristics can be improved.

[0255] <Description of ALD apparatus>

[0256] FIG. 6A An example of a film formation apparatus using the ALD method is shown. The film formation apparatus using the ALD method includes: a film formation chamber (processing chamber 1701); raw material supply units 1711a and 1711b; high-speed valves 1712a and 1712b serving as flow controllers; raw material inlets 1713a and 1713b; a raw material outlet 1714; and an exhaust device 1715. The raw material inlets 1713a and 1713b provided in the processing chamber 1701 are respectively connected to the raw material supply units 1711a and 1711b through supply pipes or valves, and the raw material outlet 1714 is connected to the exhaust device 1715 through a discharge pipe, a valve, or a pressure regulator.

[0257] Inside the processing chamber, a substrate holder 1716 equipped with a heater is provided, and the substrate 1700 to be film-formed is disposed on the substrate holder.

[0258] In raw material supply sections 1711a and 1711b, raw material gas is formed from solid or liquid raw materials using a vaporizer or heating unit. Alternatively, raw material supply sections 1711a and 1711b may also supply gaseous raw material gas.

[0259] An example of two raw material supply units 1711a and 1711b is shown here, but it is not limited to this; more than three raw material supply units can also be provided. Furthermore, high-speed valves 1712a and 1712b can be precisely controlled in time to supply either the raw material gas or the inert gas. High-speed valves 1712a and 1712b are flow controllers for the raw material gas, and can also be considered flow controllers for the inert gas.

[0260] exist FIG. 6A In the film-forming apparatus shown, the substrate 1700 to be formed is placed on the substrate support 1716, and the processing chamber 1701 is sealed. Then, the substrate support 1716 is heated by a heater to heat the substrate 1700 to a desired temperature (e.g., above 100°C or 150°C). The supply of source gas, the exhaust of gas using the exhaust device 1715, the supply of inert gas, and the exhaust of gas using the exhaust device 1715 are repeated, thereby forming a thin film on the substrate surface.

[0261] exist FIG. 6A In the film-forming apparatus shown, by appropriately selecting the raw materials (volatile organometallic compounds, etc.) prepared in the raw material supply section 1711a and raw material supply section 1711b, an insulating layer containing an oxide (including composite oxides) of one or more elements such as hafnium (Hf), aluminum (Al), tantalum (Ta), and zirconium (Zr) can be formed. Specifically, an insulating layer containing hafnium oxide, an insulating layer containing aluminum oxide, an insulating layer containing hafnium silicate, or an insulating layer containing aluminum silicate can be formed. Furthermore, by appropriately selecting the raw materials (volatile organometallic compounds, etc.) prepared in the raw material supply section 1711a and raw material supply section 1711b, thin films such as metal layers such as tungsten layers or titanium layers, and nitride layers such as titanium nitride layers can also be formed.

[0262] For example, when forming a hafnium oxide layer using an ALD (Alternating Discharge) film-forming apparatus, two gases are used: a feed gas obtained by vaporizing a liquid containing a solvent and a hafnium precursor compound (hafnium alkoxide, tetramethylammonium hafnium (TDMAH), etc.); and ozone (O3) as an oxidant. In this case, the first feed gas supplied from feed supply section 1711a is TDMAH, and the second feed gas supplied from feed supply section 1711b is ozone. Note that the chemical formula of tetramethylammonium hafnium is Hf[N(CH3)2]4. Other materials include tetra(ethylmethylammonium)hafnium. Note that nitrogen can cause the charge trapping energy level to disappear. Therefore, when the feed gas contains nitrogen, hafnium oxide with a low charge trapping energy level density can be formed.

[0263] For example, when forming an alumina layer using an ALD (Alternating Current Deposition) film-forming apparatus, two gases are used: a raw material gas obtained by vaporizing a liquid containing a solvent and an aluminum precursor compound (such as trimethylaluminum (TMA)); and H2O as an oxidant. In this case, the first raw material gas supplied from the raw material supply section 1711a is TMA, and the second raw material gas supplied from the raw material supply section 1711b is H2O. Note that the chemical formula of trimethylaluminum is Al(CH3)3. Other liquid materials include tris(dimethylammonium)aluminum, triisobutylaluminum, and aluminum tris(2,2,6,6-tetramethyl-3,5-heptadecyl)one.

[0264] For example, when forming a silicon oxide film using a film-forming apparatus employing the ALD method, hexachlorosilane is attached to the surface to be formed, removing the chlorine contained in the attached material, and supplying free radicals of oxidizing gases (O2, nitrous oxide) to react with the attached material.

[0265] For example, when forming a tungsten film using an ALD (Alternating Discharge) method, WF6 gas and B2H6 gas are introduced sequentially and repeatedly to form an initial tungsten film, and then WF6 gas and H2 gas are introduced simultaneously to form the final tungsten film. Note that SiH4 gas can also be used instead of B2H6 gas.

[0266] For example, when forming oxide semiconductor films such as In-Ga-Zn-O films using an ALD (Alternating Deposition) apparatus, In(CH3)3 gas and O3 gas are simultaneously introduced to form an In-O layer, then Ga(CH3)3 gas and O3 gas are simultaneously introduced to form a GaO layer, and then Zn(CH3)2 and O3 gas are introduced sequentially and repeatedly to form a ZnO layer. Note that the order of these layers is not limited to the example above. Furthermore, these gases can be mixed to form mixed compound layers such as In-Ga-O layers, In-Zn-O layers, Ga-Zn-O layers, etc. Note that although H2O gas obtained by bubbling with an inert gas such as Ar can be used instead of O3 gas, it is preferable to use O3 gas that does not contain H. Additionally, In(C2H5)3 gas can be used instead of In(CH3)3 gas. Furthermore, Ga(C2H5)3 gas can be used instead of Ga(CH3)3 gas. Additionally, Zn(CH3)2 gas can also be used.

[0267] Multi-chamber film-forming device

[0268] FIG. 6B It shows that it has at least one FIG. 6A An example of a multi-chamber manufacturing apparatus for the film-forming device shown.

[0269] FIG. 6B The manufacturing apparatus shown can continuously form laminated films without contact with the atmosphere, thereby preventing impurity contamination and increasing throughput.

[0270] FIG. 6B The manufacturing apparatus shown includes at least a loading chamber 1702, a transfer chamber 1720, a pretreatment chamber 1703, a processing chamber 1701 serving as a film-forming chamber, and an unloading chamber 1706. In the processing chamber of the manufacturing apparatus (which also includes the loading chamber, transfer chamber, film-forming chamber, unloading chamber, etc.), to prevent the adhesion of moisture, it is preferable to fill it with an inert gas (such as nitrogen gas) having a suitable dew point, and it is preferable to maintain a reduced pressure.

[0271] Alternatively, processing chambers 1704 and 1705 can be film-forming apparatuses using the ALD method, similar to processing chamber 1701, or they can be film-forming apparatuses using plasma CVD, sputtering, or metal-organic chemical vapor deposition (MOCVD).

[0272] For example, the following shows an example of forming a multilayer film by using a plasma CVD method as processing chamber 1704 and a MOCVD method as processing chamber 1705.

[0273] FIG. 6BThe top view of the transfer chamber 1720 is shown as an example of a hexagonal shape, but depending on the number of layers of the laminated film, a manufacturing apparatus with a polygonal top surface shape and connecting more processing chambers may also be used. FIG. 6B In this case, the top surface of the substrate is rectangular, but not limited to this. Furthermore, although... FIG. 6B An example of a single-wafer type film deposition apparatus is shown, but a batch-type film deposition apparatus that deposits films on multiple substrates simultaneously can also be used.

[0274] <Form of Insulation Layer 110>

[0275] First, an insulating layer 110 is formed on the substrate 100. The insulating layer 110 can be formed using oxide insulating films such as aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, nitride insulating films such as silicon nitride, silicon oxynitride, aluminum nitride, and aluminum oxynitride, or a mixture of the above materials, via plasma CVD, thermal CVD (MOCVD, ALD), or sputtering. Furthermore, the insulating layer 110 can also be a stack of the above materials, wherein preferably, the upper layer of the stack that contacts the first oxide semiconductor film subsequently used as the oxide semiconductor layer 121 is formed using at least a material containing excess oxygen to supply oxygen to the oxide semiconductor layer 122.

[0276] For example, as the insulating layer 110, a silicon oxynitride film with a thickness of 100 nm formed by plasma CVD can be used.

[0277] Next, a heat treatment can be performed to remove water, hydrogen, and the like contained in the insulating layer 110. As a result, the concentration of water, hydrogen, and the like contained in the insulating layer 110 can be reduced, and the amount of water, hydrogen, and the like diffused into the first oxide semiconductor film formed subsequently can be reduced through the heat treatment.

[0278] <Formation of the first oxide semiconductor film and the second oxide semiconductor film>

[0279] Next, a first oxide semiconductor film, which will later be used as an oxide semiconductor layer 121, and a second oxide semiconductor film, which will later be used as an oxide semiconductor layer 122, are formed on the insulating layer 110. The first oxide semiconductor film and the second oxide semiconductor film can be formed by sputtering, MOCVD, PLD, etc., and sputtering is preferred. As a sputtering method, RF sputtering, DC sputtering, AC sputtering, etc. can be used. When using sputtering, the film is formed using a facing target method (also known as a facing electrode method, vapor phase sputtering method, VDSP (Vapor Deposition Spattering)), which can reduce plasma damage during film formation.

[0280] For example, when forming a first oxide semiconductor film using sputtering, it is preferable that each processing chamber in the sputtering apparatus be evacuated to a high vacuum (5 × 10⁻⁶) using an adsorption vacuum pump such as a cryogenic pump. -7 Pa to 1×10 -4 The substrate on which the film is formed is heated to 100°C or higher, preferably 400°C or higher, to remove as much water or other impurities as possible from the oxide semiconductor. Alternatively, a turbomolecular pump and a cold trap are preferably combined to prevent gases containing carbon or moisture from flowing back from the exhaust system into the processing chamber. Alternatively, an exhaust system combining a turbomolecular pump and a cryogenic pump may also be used.

[0281] To obtain high-purity intrinsic oxide semiconductors, it is necessary not only to evacuate the processing chamber under high vacuum, but also to purify the sputtering gas. By using a high-purity gas with a dew point of -40°C or below, preferably -80°C or below, and more preferably -100°C or below, as the oxygen or argon gas used as the sputtering gas, it is possible to prevent moisture and other contaminants from entering the oxide semiconductor film as much as possible.

[0282] As the sputtering gas, a rare gas (typically argon), oxygen, or a mixture of rare gas and oxygen is appropriately used. Furthermore, when using a mixture of rare gas and oxygen, it is preferable to increase the proportion of oxygen relative to the rare gas.

[0283] When forming an oxide semiconductor film, for example, by using a sputtering method, the oxide semiconductor film can also be formed by setting the substrate temperature to 150°C or higher and 750°C or lower, preferably 150°C or higher and 450°C or lower, and more preferably 200°C or higher and 420°C or lower. This can form a CAAC-OS film.

[0284] The material of the first oxide semiconductor film can be selected in such a way that its electron affinity is less than that of the second oxide semiconductor film.

[0285] The indium content of the second oxide semiconductor film can also be higher than that of the first and third oxide semiconductor films. In oxide semiconductors, the s-orbitals of heavy metals mainly contribute to carrier conduction, and the overlap of s-orbitals is increased by increasing the In ratio. Therefore, oxides with an In ratio higher than Ga have higher mobility than oxides with an In ratio equal to or less than Ga. Thus, by using an oxide with a higher indium content in the oxide semiconductor layer 122, high-mobility transistors can be achieved.

[0286] Furthermore, when forming the first and second oxide semiconductor films using sputtering, a multi-chamber sputtering apparatus can be used to continuously form the first and second oxide semiconductor films without exposing them to the atmosphere. This suppresses unwanted impurities from entering the interface between the first and second oxide semiconductor films, thus lowering the interface energy level. As a result, the electrical characteristics of the transistor can be stabilized, especially its characteristics during reliability testing.

[0287] When oxygen is added to the first oxide semiconductor film, and the oxide semiconductor film is damaged, the presence of the oxide semiconductor layer 122 allows the oxide semiconductor layer 123, which is used as the main electrical path, to be kept away from the damaged area. As a result, the electrical characteristics of the transistor can be stabilized, especially the characteristics in reliability testing.

[0288] For example, as the first oxide semiconductor film, an oxide semiconductor film with a thickness of 20 nm can be formed by sputtering using a target with an In:Ga:Zn ratio of 1:3:4 (atomic ratio). As the second oxide semiconductor film, an oxide semiconductor film with a thickness of 15 nm can be formed using a target with an In:Ga:Zn ratio of 1:1:1 (atomic ratio).

[0289] By performing heat treatment after forming the first oxide semiconductor film and the second oxide semiconductor film, the amount of oxygen defects in the second oxide semiconductor film can be reduced.

[0290] Next, a first heat treatment is performed to move some of the oxygen into the second oxide semiconductor film, thereby reducing oxygen defects in the second oxide semiconductor film. This second oxide semiconductor film with reduced oxygen defects is called the second oxide semiconductor film. Additionally, oxygen defects in the first oxide semiconductor film are also reduced at this time. Furthermore, the first heat treatment can remove hydrogen, water, and other substances contained in both the oxygen-added first oxide semiconductor film and the second oxide semiconductor film. As a result, the impurity content in both the oxygen-added first oxide semiconductor film and the second oxide semiconductor film can be reduced.

[0291] The temperature of the first heat treatment is above 250°C and below the substrate strain point, preferably above 300°C and below 650°C, and more preferably above 350°C and below 550°C.

[0292] The first heating treatment is performed in an atmosphere containing rare gases such as helium, neon, argon, xenon, and krypton, or an inert gas atmosphere containing nitrogen. Alternatively, after heating in an inert gas atmosphere, heating can be performed in an oxygen atmosphere or a dry air atmosphere (air with a dew point below -80°C, preferably below -100°C, more preferably below -120°C). Heating can also be performed under reduced pressure. Note that, except for the aforementioned dry air, the inert gas and oxygen gas preferably do not contain hydrogen, water, etc., and typically have a dew point below -80°C, preferably below -100°C. The treatment time is from 3 minutes to 24 hours.

[0293] Note that in the first heat treatment, a device that uses heat conduction or thermal radiation generated by a heating element such as a resistance heating element to heat the workpiece can replace an electric furnace. For example, an RTA (Rapid Thermal Anneal) device such as a GRTA (Gas Rapid Thermal Anneal) device or an LRTA (Lamp Rapid Thermal Anneal) device can be used. An LRTA device heats the workpiece using radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, or high-pressure mercury lamp. A GRTA device uses a high-temperature gas for the first heat treatment. Rare gases such as argon or inert gases such as nitrogen are used as the high-temperature gas.

[0294] The first heat treatment can also be performed after the etching that forms the oxide semiconductor layer 121 and oxide semiconductor layer 22, as described later.

[0295] For example, after a heat treatment at 450°C for 1 hour in a nitrogen atmosphere, a heat treatment at 450°C for 1 hour in an oxygen atmosphere can be performed.

[0296] The above processes can reduce oxygen defects in oxide semiconductor films and reduce impurities such as hydrogen and water. Furthermore, oxide semiconductor films with reduced local energy level density can be formed.

[0297] <Formation of the first conductive film>

[0298] Next, a first conductive film, which serves as the source electrode layer 130 and the drain electrode layer 140, is formed on the oxide semiconductor layer 123. The first conductive film can be formed by sputtering, chemical vapor deposition (CVD) (including metal-organic chemical vapor deposition (MOCVD), metal chemical vapor deposition, atomic layer deposition (ALD), or plasma chemical vapor deposition (PECVD)), evaporation, pulsed laser deposition (PLD), etc.

[0299] The material of the first conductive film is preferably a single layer or a stack of conductive films containing materials selected from copper (Cu), tungsten (W), molybdenum (Mo), gold (Au), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), nickel (Ni), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt (Co), ruthenium (Ru), platinum (Pt), iridium (Ir), strontium (Sr), alloys of the above-mentioned low-resistance materials, or compounds with the above-mentioned materials as the main component. For example, in the case of a stack, the lower conductive layer in contact with the oxide semiconductor layer 122 may contain a material that easily bonds with oxygen, and the upper conductive layer may contain a material with high oxidation resistance. In addition, high-melting-point materials such as tungsten (W) or molybdenum (Mo), which have heat resistance and conductivity, are preferably used. Furthermore, the first conductive film is preferably formed using a low-resistance conductive material such as aluminum (Al) or copper (Cu). Furthermore, when using Cu-Mn alloys, a film containing manganese oxide is formed at the interface with the oxygen-containing insulator, which can inhibit the diffusion of Cu, so it is preferred.

[0300] For example, a tungsten film with a thickness of 20 to 100 nm can be formed by sputtering as the first conductive film.

[0301] The conductive layer 130b formed by processing the first conductive film in subsequent processes can function as a hard mask and as a source electrode layer and drain electrode layer in subsequent processes, so no additional processes are required, thus shortening the semiconductor manufacturing process.

[0302] <Forming of oxide semiconductor layer 121 and oxide semiconductor layer 122>

[0303] Next, a photoresist mask is formed through a photolithography process. Using this photoresist mask, the first conductive film is selectively etched, thereby forming a conductive layer 130b. Then, after removing the photoresist from the conductive layer 130b, the conductive layer 130b is used as a hard mask to selectively etch the second oxide semiconductor film and the first oxide semiconductor film, forming island-shaped oxide semiconductor layers 122 and 121 (see Figure 7). Dry etching can be used as the etching method. Furthermore, by using the conductive layer 130b as a hard mask to etch the oxide semiconductor layers, the edge roughness of the oxide semiconductor layers can be reduced compared to using a photoresist mask.

[0304] For example, by using methane or argon as the etching gas and using a resist mask and a hard mask, the first oxide semiconductor film and the second oxide semiconductor film can be selectively etched to form oxide semiconductor layer 121 and oxide semiconductor layer 122.

[0305] <Formation of the Second Insulating Film>

[0306] Next, a second insulating film is formed on the insulating layer 110 and the conductive layer 130b.

[0307] The second and third insulating films can be produced using plasma CVD, thermal CVD (MOCVD, ALD), sputtering, etc., for example, using alumina (SiO2). x ), magnesium oxide (MgO) x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y Gallium oxide (GaO) x germanium oxide (GeO) x ), Yttrium oxide (YO) x Zirconium oxide (ZrO) x ), Lanthanum oxide (LaO) x ), neodymium oxide (NdO) x ), Hafnium oxide (HfO) x ) and tantalum oxide (TaO) x Oxide insulating films such as silicon nitride (SiN) x ), silicon oxynitride (SiN) x O y ), aluminum nitride (AlN) x ), aluminum oxynitride (AlN) x O y It is formed by nitride insulating films, or mixtures of these materials.

[0308] Furthermore, as the second insulating film, an alumina film is preferably formed by sputtering. Alumina is also preferably used as the sputtering target. Additionally, the gas used during film formation preferably contains an oxygen gas.

[0309] When the alumina film is formed, the mixed layer 171 is formed at the interface between it and the insulating layer 110.

[0310] For example, due to the influence of voltage, power, plasma, substrate temperature, etc. applied during film formation by sputtering, the oxygen gas used to form the second insulating film exists in various states such as oxygen free radicals, oxygen ions, and oxygen atoms, and this oxygen gas has a higher energy than the stable state. At this time, oxygen (also called excess oxygen, exO) 172 is added to the insulating layer 110 or the mixed layer 171 (see reference). FIG. 8A - FIG. 8C ).

[0311] Next, a second heat treatment may be performed. The temperature of the second heat treatment is typically 150°C or higher and below the strain point of the substrate, preferably 250°C or higher and 500°C or lower, more preferably 300°C or higher and 450°C or lower. Due to this heat treatment, the oxygen 172 added to the insulating layer 110 diffuses and migrates into the oxide semiconductor layer 122, thereby supplying oxygen to oxygen defects present in the oxide semiconductor layer 122 (see reference). FIG. 9A - FIG. 9C ).

[0312] For example, alumina (AlO) can be used by sputtering. x The target material is sputtered using a gas containing 50% by volume of oxygen to form a second insulating film. The thickness of this insulating layer can be from 20 nm to 40 nm. Additionally, as a second heat treatment, the material can be heated at 400°C for 1 hour in an oxygen atmosphere.

[0313] <Addition of Oxygen>

[0314] Alternatively, oxygen addition can be performed separately during the fabrication of transistor 10, and is not limited to the methods described above. This oxygen addition process can be performed on insulating layer 110, on the first oxide semiconductor film, or on the third insulating film 123a described later. As the added oxygen, any one or more of oxygen free radicals, oxygen atoms, oxygen atom ions, and oxygen molecular ions can be used. Examples of methods for adding oxygen include ion doping, ion implantation, and plasma immersion ion implantation.

[0315] When ion implantation is used as a method for adding oxygen, both oxygen atomic ions and oxygen molecular ions can be used. Using oxygen molecular ions reduces damage to the membrane to which oxygen is being added. Oxygen molecular ions separate on the surface of the membrane and are added as oxygen atomic ions. Since energy is consumed in separating oxygen molecules into oxygen atoms, the energy per oxygen atom when adding oxygen molecular ions to the oxygen-supplying membrane is lower than when adding oxygen atomic ions. Therefore, damage to the oxygen-supplying membrane can be reduced.

[0316] Furthermore, the energy of each oxygen atom ion is lower than that of the injected oxygen molecular ions. Therefore, by injecting oxygen molecular ions, the accelerating voltage can be increased, thereby increasing the throughput. Additionally, by injecting oxygen molecular ions, the dosage required to add the same amount of oxygen atom ions can be reduced to half that required by injecting oxygen atom ions. As a result, the throughput of the manufacturing process can be increased.

[0317] Furthermore, when adding oxygen to the membrane to which oxygen is to be added, it is preferable to add oxygen to the membrane in such a way that the peak of the oxygen atom ion concentration distribution is located in the membrane to which oxygen is to be added. As a result, compared with the case of implanting oxygen atom ions, the accelerating voltage during implantation can be reduced, thereby reducing damage to the membrane to which oxygen is supplied. In other words, the amount of defects in the membrane to which oxygen is added can be reduced, thereby suppressing variations in the electrical characteristics of the transistor.

[0318] Alternatively, oxygen can be added to the oxygen-added membrane by plasma treatment (plasma immersion ion implantation) in which the membrane to be oxygenated is exposed to plasma generated in an oxygen-containing atmosphere. Examples of oxygen-containing atmospheres include atmospheres containing oxidizing gases such as oxygen, ozone, nitrous oxide, and nitrogen dioxide. Furthermore, by exposing the oxygen-added membrane to plasma generated while a bias voltage is applied to one side of the substrate 100, the amount of oxygen added to the membrane can be increased, which is therefore preferred. An example of an apparatus for performing this plasma treatment is an ashing apparatus.

[0319] For example, the accelerating voltage can be set to 5kV, and an ion implantation method can be used to deliver a dose of 1×10⁻⁶. 16 Oxygen molecules per cm² are added to the first oxide semiconductor film.

[0320] By combining the above steps with subsequent heat treatment, the amount of oxygen defects in the oxide semiconductor layer 122 can be reduced. Note that the film density of the film with added oxygen is lower than that of the film before adding oxygen.

[0321] <Formation of the Third Insulating Film>

[0322] Next, a third insulating film is formed on the second insulating film. The third insulating film can be formed using plasma CVD, thermal CVD (MOCVD, ALD), sputtering, or spin coating methods, for example, using alumina (SiO2). x ), magnesium oxide (MgO) x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y Gallium oxide (GaO) x germanium oxide (GeO) x ), Yttrium oxide (YO) x Zirconium oxide (ZrO) x ), Lanthanum oxide (LaO) x ), neodymium oxide (NdO) x ), Hafnium oxide (HfO) x ) and tantalum oxide (TaO) x Oxide insulating films such as silicon nitride (SiN) x ), silicon oxynitride (SiN) x O y ), aluminum nitride (AlN) x ), aluminum oxynitride (AlN) x O y It can be formed from nitride insulating films, or mixtures of these materials. Alternatively, a laminate of the above materials can also be used.

[0323] In addition, low-dielectric-constant materials (Low-k materials) can be used as the third insulating film. For example, silicon oxide (SiOF) with a few percent fluorine (F), silicon oxide (SiOC) with a few percent carbon (C), fluorosilicate glass (FSG), organosilicon glass (OSG), hydrosilsesquioxane (HSQ), methylsilsesquioxane (MSQ), organic polymers, fluoropolymers (such as polytetrafluoroethylene), polyimide, and amorphous carbon with added fluorine can be used.

[0324] Alternatively, a second heat treatment can be performed after the third insulating film is formed.

[0325] <Planarization of the Third Insulating Film>

[0326] Next, the third insulating film is planarized to form the insulating layer 175b. Planarization can be performed using methods such as CMP (Chemical Mechanical Polishing), dry etching, or reflow. When planarizing using CMP, a film with a different composition than the third insulating film is formed on top of it, which can increase the thickness of the insulating layer 175b on the substrate surface after CMP treatment.

[0327] Alternatively, a second heat treatment can be performed after the third insulating film has been planarized.

[0328] <Forming of the trench, source electrode layer 130, and gate insulating layer 150>

[0329] Next, a photoresist mask 176 is formed on the insulating layer 175b using a photolithography process (see reference). FIG. 10A - FIG. 10C Alternatively, an organic film can be coated on the insulating layer 175b or the resist, followed by a photolithography process. This organic film contains propylene glycol methyl ether, ethyl lactate, etc., and functions as a bottom anti-reflective coating (BARC). Furthermore, it can improve the adhesion between the resist and the film, and enhance resolution.

[0330] Note that when forming transistors with extremely short channel lengths, at least the area where the conductive layer 130b used as the source electrode layer 130 and drain electrode layer 140 is cut off can be processed using a resist mask with methods suitable for fine-line processing, such as electron beam lithography, immersion lithography, or EUV lithography, and then etched in this area. Furthermore, when forming the resist mask using electron beam lithography, if a positive resist is used as the resist mask, the exposure area can be minimized, thereby increasing throughput. Using this method, transistors with channel lengths of 100 nm or less, and further, 30 nm or less, can be formed. Alternatively, fine processing can be performed using exposure techniques with extremely short wavelengths of light (e.g., extreme ultraviolet (EUV), X-rays, etc.).

[0331] Using the aforementioned resist mask, the insulating layer 175b is grooved using a dry etching method. By selectively etching, grooves 174 are formed in the insulating layer 175.

[0332] Next, selective etching is performed to cut off the exposed conductive layer 130b, thereby forming the source electrode layer 130 and the drain electrode layer 140 (see reference). FIG. 11A - FIG. 11C ).

[0333] Alternatively, a washing process can be performed after the formation of the source electrode layer 130 and the drain electrode layer 140 to remove etching residues. This washing process can suppress short circuits between the source electrode layer 130 and the drain electrode layer 140. This washing process can be performed using alkaline solutions such as TMAH (Tetramethylammonium Hydroxide) solution, or acidic solutions such as diluted hydrofluoric acid, oxalic acid, or phosphoric acid. Due to the washing process, a portion of the oxide semiconductor layer 122 is etched, forming a recess in the oxide semiconductor layer 122.

[0334] Furthermore, the formation order of oxide semiconductor layer 121, oxide semiconductor layer 122, source electrode layer 130, and drain electrode layer 140 can be changed. For example, the trench portion 174 for forming the source electrode layer 130 and drain electrode can be formed first, and then the oxide semiconductor layer 121 and oxide semiconductor layer 122 can be formed.

[0335] For example, after planarizing the silicon oxynitride film formed as the second insulating film, a photoresist mask is formed on the silicon oxynitride film, and an opening in the silicon oxynitride is formed by dry etching using the photoresist mask and a gas containing carbon or fluorine. The source electrode layer 130 and the drain electrode layer 140 can be formed by dry etching the conductive layer 130b using a chlorine gas or a fluorine gas.

[0336] <Forming of the third oxide semiconductor film 123a>

[0337] Next, a third oxide semiconductor film 123a, which serves as the oxide semiconductor layer 123, is formed on the oxide semiconductor layer 122 and the insulating layer 175. The third oxide semiconductor film 123a can be formed using the same method as the first oxide semiconductor film, and the material of the third oxide semiconductor film 123a can be selected in such a way that its electron affinity is smaller than that of the second oxide semiconductor film.

[0338] For example, as the third oxide semiconductor film 123a, an oxide semiconductor film with a thickness of 5 nm can be formed by sputtering using a target material with an In:Ga:Zn ratio of 1:3:2 (atomic number ratio).

[0339] <Forming of insulating film 150a>

[0340] Next, a fourth insulating film 150a, which serves as the gate insulating layer 150, is formed on the oxide semiconductor film 123a. The fourth insulating film 150a can be, for example, aluminum oxide (Al₂O₃). x ), magnesium oxide (MgO) x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N yThe fourth insulating film 150a can be a stack of the above materials, including silicon oxynitride, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Sputtering, CVD (plasma CVD, MOCVD, ALD, etc.), and MBE methods can be used to form the fourth insulating film 150a. The same method used for insulating layer 110 can be appropriately used to form the fourth insulating film 150a.

[0341] For example, as the fourth insulating film 150a, a silicon oxynitride film with a thickness of 10 nm can be formed by plasma CVD.

[0342] <Formation of conductive film 160a>

[0343] Next, a second conductive film 160a, which serves as the gate electrode layer 160, is formed on the fourth insulating film 150a (see reference). FIG. 12A - FIG. 12C The second conductive film 160a can be made of, for example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), copper (Cu), yttrium (Y), zirconium (Zr), molybdenum (Mo), ruthenium (Ru), silver (Ag), gold (Au), platinum (Pt), tantalum (Ta), tungsten (W), or alloys thereof. The second conductive film 160a can be formed using sputtering, CVD (plasma CVD, MOCVD, ALD, etc.), MBE, vapor deposition, or plating. The second conductive film 160a can be a nitrogen-containing conductive film, or a stack of the aforementioned conductive films and a nitrogen-containing conductive film. Furthermore, the second conductive film 160a can be a single layer or a stack.

[0344] For example, the conductive film 160a can be a stacked structure formed by forming 10 nm of titanium nitride using the ALD method and 150 nm of tungsten using the metal CVD method.

[0345] <flattening process>

[0346] Next, planarization is performed. Planarization can be performed using methods such as CMP or dry etching. The planarization process can end when the third insulating film 150a is exposed, when the third oxide semiconductor film 123a is exposed, or when the insulating layer 175 is exposed. Thus, the gate electrode layer 160, the gate insulating layer 150, and the oxide semiconductor layer 123 (see reference) can be formed. FIG. 13A - FIG. 13C ).

[0347] When the planarized insulating layer 175 includes an oxide semiconductor film 123a or an insulating film 150a, the resist mask can be reused for processing. A resist mask is formed on the oxide semiconductor film 123a or the insulating film 150a using a photolithography process. The area of ​​this mask is larger than the top surface area of ​​the gate electrode layer 160, allowing selective etching of the insulating film 150a and the oxide semiconductor film 123a to form the gate insulating layer 150 and the oxide semiconductor layer 123.

[0348] By providing an oxide semiconductor layer 123 in the transistor 10 that is less prone to oxygen defects, oxygen can be suppressed from escaping from the sides of the oxide semiconductor layer 123 in the channel width direction, thereby suppressing the generation of oxygen defects. As a result, a transistor with improved electrical characteristics and high reliability can be realized.

[0349] Next, a third heat treatment may be performed. The temperature of the heat treatment is typically 150°C or higher and below the strain point of the substrate, preferably 250°C or higher and 500°C or lower, more preferably 300°C or higher and 450°C or lower. Due to this heat treatment, the oxygen added to the insulating layer (e.g., insulating layer 175) diffuses and moves into the oxide semiconductor layer 122, thereby supplying oxygen to oxygen defects present in the oxide semiconductor layer 122.

[0350] For example, it can be heated at 400°C for 1 hour in an oxygen atmosphere.

[0351] Through the above processes, the local energy level density of the oxide semiconductor film is reduced, thereby enabling the fabrication of transistors with excellent electrical characteristics. Furthermore, it is possible to manufacture highly reliable transistors that exhibit minimal changes in electrical characteristics due to the passage of time or stress testing.

[0352] <Example 1 of a variation of transistor 10: transistor 11>

[0353] use FIG. 14A , FIG. 14B and FIG. 14C Its shape and FIG. 1A The transistor 10 shown is illustrated with different transistors 11.

[0354] FIG. 14A , FIG. 14B and FIG. 14C These are the top view and cross-sectional view of transistor 11. FIG. 14A This is a top view of transistor 11. FIG. 14B It is along FIG. 14A A cross-sectional view of the dotted-dash line A1-A2. FIG. 14C It is a cross-sectional view along the dotted-dash line A3-A4.

[0355] The difference between transistor 11 and transistor 10 is that transistor 11 has a conductive layer 135 that contacts the sides (excluding the channel region) of oxide semiconductor layer 121 and oxide semiconductor layer 122, the sides of source electrode layer 130, the sides of drain electrode layer 140, the sides and top surface of insulating layer 110, and the bottom surface of insulating layer 170. The conductive layer 135 is as follows... FIG. 14B The diagram shows a sidewall shape.

[0356] Conductive Layer 135

[0357] The conductive layer 135 is preferably a single layer or a stack of materials selected from copper (Cu), tungsten (W), molybdenum (Mo), gold (Au), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), nickel (Ni), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt (Co), ruthenium (Ru), platinum (Pt), iridium (Ir), strontium (Sr), alloys of the above materials, or a conductive layer containing compounds such as oxygen, nitrogen, fluorine, and silicon with the above materials as the main components. For example, in the case of a stack, the lower conductive layer in contact with the oxide semiconductor layer 122 may contain a material that easily bonds with oxygen, and the upper conductive layer may contain a material with high oxidation resistance. In addition, high-melting-point materials such as tungsten or molybdenum, which have heat resistance and conductivity, are preferred. In addition, low-resistance conductive materials such as aluminum or copper are preferred. Furthermore, when a Cu-Mn alloy is used, manganese oxide is formed at the interface with the oxygen-containing insulator, which can suppress the diffusion of Cu, so it is preferred.

[0358] By having a conductive layer 135, the area of ​​the conductive layer in contact with the oxide semiconductor layer 121 and the oxide semiconductor layer 122 can be increased, thereby increasing the on-state current.

[0359] <Example 2 of a variation of transistor 10: transistor 12>

[0360] use FIG. 15A - FIG. 15C and FIG. 16A - FIG. 16C Its shape and FIG. 1A The transistor 10 shown is illustrated with different transistors 12.

[0361] FIG. 15A , FIG. 15B and FIG. 15C These are the top view and cross-sectional view of transistor 12. FIG. 15A This is a top view of transistor 12. FIG. 15B It is along FIG. 15A A cross-sectional view of the dotted-dash line A1-A2. FIG. 15C It is a cross-sectional view along the dotted-dash line A3-A4.

[0362] The difference between transistor 12 and transistor 10 is that transistor 12 also has a conductive layer 165 located on the underside of insulating layer 110 and an insulating layer 177 located on the top surface of insulating layer 175, oxide semiconductor layer 123, gate insulating layer 150 and gate electrode layer 160.

[0363] Conductive Layer 165

[0364] The conductive layer 165 can function as a bottom gate. The conductive layer 165 can be provided with the same potential as the gate electrode layer 160, or it can be provided with a different potential. The conductive layer 165 is preferably a single layer or stack of conductive layers containing materials such as copper (Cu), tungsten (W), molybdenum (Mo), gold (Au), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), nickel (Ni), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt (Co), ruthenium (Ru), platinum (Pt), iridium (Ir), strontium (Sr), etc.; alloys thereof; or compounds containing oxygen, nitrogen, fluorine, silicon, etc., with the above materials as the main components. For example, the conductive layer 166 can contain a material with strong oxidation resistance. Furthermore, the conductive layer 167 preferably uses a high-melting-point material such as tungsten or molybdenum, which has both heat resistance and conductivity. Additionally, a low-resistance conductive material such as aluminum or copper is preferred.

[0365] Insulation Layer 177

[0366] The insulating layer 177 may contain oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge), yttrium (Y), zirconium (Zr), lanthanum (La), neodymium (Nd), hafnium (Hf), tantalum (Ta), titanium (Ti), etc. For example, aluminum oxide (AlO) may be used. x ), magnesium oxide (MgO) x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y ), silicon oxynitride (SiN) x O y ), silicon nitride (SiN) x Gallium oxide (GaO) x germanium oxide (GeO) x ), Yttrium oxide (YO) x Zirconium oxide (ZrO) x ), Lanthanum oxide (LaO) x ), neodymium oxide (NdO) x ), Hafnium oxide (HfO) x ) and tantalum oxide (TaO) x One or more of the above-mentioned insulating films. The insulating layer 177 may also be a stack of the above-mentioned materials.

[0367] The insulating layer 177 preferably comprises an aluminum oxide film. The aluminum oxide film can have a barrier effect that prevents impurities such as hydrogen and moisture, as well as oxygen, from permeating through the film. Therefore, during and after the transistor manufacturing process, the aluminum oxide film is suitable as a protective film that has the following effects: prevents impurities such as hydrogen and moisture that cause changes in the electrical characteristics of the transistor from mixing into the oxide semiconductor layer 121 and the oxide semiconductor layer 122; prevents oxygen, which is a major component, from being released from the oxide semiconductor layer 121 and the oxide semiconductor layer 122; and prevents unnecessary release of oxygen from the insulating layer 175.

[0368] Furthermore, the insulating layer 177 is preferably a film with oxygen supply capability. For example, the insulating layer 177 is preferably formed by sputtering. When forming the insulating layer 177, a hybrid layer is formed at the interface with the insulating layer 175, and oxygen 172 can be added to the hybrid layer or the insulating layer 175.

[0369] A third heat treatment can be performed on the transistor 12 after the insulating layer 177 is formed. Typically, this third heat treatment can be above 150°C and below the substrate strain point, preferably above 250°C and below 500°C, and more preferably above 300°C and below 450°C. The oxygen added to the insulating layer 175 by the third heat treatment diffuses into the oxide semiconductor layer 121 and oxide semiconductor layer 122, filling oxygen defects in the oxide semiconductor layer 122.

[0370] Furthermore, the third heat treatment can also be used as the second heat treatment. This allows oxygen 172 added to insulating layers 110 and 175 to move through gate insulating layer 150, oxide semiconductor layer 123, and oxide semiconductor layer 121 to oxide semiconductor layer 122, thereby filling oxygen defects in oxide semiconductor layer 122 (see reference). FIG. 16A - FIG. 16C ).

[0371] This improves the transistor characteristics of transistor 12 (such as threshold and reliability).

[0372] In addition, transistor 12 can be as follows FIG. 17A - FIG. 17C The structure shown uses transistors connected in parallel (transistor 13) (see reference). FIG. 17A - FIG. 17C Furthermore, transistor 13 can be as follows: FIG. 18 The structure shown is as follows: an insulating layer 180 is provided on the insulating layer 170, and a conductive layer 190 (conductive layer 191, conductive layer 192) is provided on the gate electrode layer 160, with the gate electrode layer 160 and the conductive layer 190 being electrically connected.

[0373] The insulating layer 180 can be formed using the same material as the insulating layer 175. The conductive layer 190 can be formed using the same material as the gate electrode layer 160.

[0374] Transistor 13 can increase the on-state current while exhibiting good transistor characteristics.

[0375] This embodiment can be appropriately combined with other embodiments and examples shown in this specification.

[0376] Implementation Method 2

[0377] In this embodiment, a transistor 14 with a structure different from that of the transistor 10 described in Embodiment 1 and a method for manufacturing the transistor 14 will be described.

[0378] <Transistor 14>

[0379] FIG. 19A , FIG. 19B and FIG. 19C This is a top view and a cross-sectional view of a transistor 14 according to one embodiment of the present invention. FIG. 19A It is a top view. FIG. 19B It is along FIG. 19A The cross-sectional view shown is the dotted-dash line A1-A2. FIG. 19C It is along FIG. 19A The cross-sectional view shown is along the dashed-dot line A3-A4. FIG. 19A In Chinese, for clarity, sometimes a part of the constituent elements is enlarged, reduced, or omitted. Additionally, the direction of the dashed line A1-A2 is sometimes referred to as the channel length direction, and the direction of the dashed line A3-A4 is sometimes referred to as the channel width direction.

[0380] The difference between transistor 14 and transistor 10 is that transistor 14, as FIG. 19A , FIG. 19B , FIG. 19C As shown, an insulating layer 185 is provided on the top surface of the source electrode layer 130 and the drain electrode layer 140 in the trench portion 174. The insulating layer 185 is in contact with the insulating layer 170 and the side surface of the insulating layer 175, and an oxide semiconductor layer 123 is provided on the upper side of the insulating layer 185.

[0381] Insulation Layer 185

[0382] As the insulating layer 185, elements including oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge), yttrium (Y), zirconium (Zr), lanthanum (La), neodymium (Nd), hafnium (Hf), tantalum (Ta), and titanium (Ti) can be used. For example, elements including magnesium oxide (MgO) can be used. x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) xNx), silicon oxynitride (SiN) x Ox), silicon nitride (SiN) x Gallium oxide (GaO) x germanium oxide (GeO) x ), Yttrium oxide (YO) x Zirconium oxide (ZrO) x ), Lanthanum oxide (LaO) x ), neodymium oxide (NdO) x ), Hafnium oxide (HfO) x ) and tantalum oxide (TaO) x ), aluminum oxide (AlO) x One or more insulating films of the above-mentioned materials. The insulating layer 185 may also be a stack of the above-mentioned materials. The insulating layer preferably contains more oxygen than the stoichiometric composition.

[0383] The insulating layer 185 can be made of a low-k material. For example, it can be silicon oxide (SiOF) with a few percent fluorine (F), silicon oxide (SiOC) with a few percent carbon (C), fluorosilicate glass (FSG), organosilicon glass (OSG), silsesquioxane (HSQ), methylsilsesquioxane (MSQ), organic polymers, polyimides, fluoropolymers (polytetrafluoroethylene), and fluorinated amorphous carbon. By using a low-k material for the insulating layer 185, the capacitance of the transistor 14 can be further reduced.

[0384] Transistor 14, by having an insulating layer 185, can be processed below the resolution limit of the device, and can be processed in a finer manner, thereby suppressing development costs such as the introduction of new equipment.

[0385] <Manufacturing Method of Transistor 14>

[0386] The manufacturing method of transistor 14 will be described below. Note that the process identical to that of transistor 10 described in Embodiment 1 will be referenced from the description of Embodiment 1.

[0387] like FIG. 20A , FIG. 20B As shown, after forming insulating layers 170 and 175b, a resist mask 176 for forming the trench is formed. Compared to the case of manufacturing transistor 10, the resist mask 176 allows for a wider trench size (more flexible design rules).

[0388] Next, the insulating layer 175b is selectively etched using a resist mask 176 to form the insulating layer 175.

[0389] Next, a fourth insulating film, which will become the insulating layer 185, is formed. The fourth insulating film can be formed using plasma CVD, thermal CVD (MOCVD, ALD), sputtering, or spin coating.

[0390] Next, an insulating layer 185 is formed by dry etching.

[0391] Next, the insulating layer 185 is used as a hard mask to selectively etch the conductive layer 130b until the oxide semiconductor layer 122 is exposed, thereby forming the source electrode layer 130 and the drain electrode layer 140 (see reference). FIG. 21A - FIG. 21C ).

[0392] Next, a third oxide semiconductor film 123a, a third insulating film 150a, and a conductive film 160a are formed sequentially (see reference). FIG. 22A - FIG. 22C Transistor 14 is manufactured by performing planarization (see reference). FIG. 23A - FIG. 23C ).

[0393] This embodiment can be appropriately combined with other embodiments and examples shown in this specification.

[0394] Implementation Method 3

[0395] <Structure of Oxide Semiconductors>

[0396] In this embodiment, the structure of the oxide semiconductor will be described.

[0397] Oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. Non-single-crystal oxide semiconductors include CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor), polycrystalline oxide semiconductors, nc-OS (nanocrystalline Oxide Semiconductor), a-likeOS (amorphous like Oxide Semiconductor), and amorphous oxide semiconductors.

[0398] From another perspective, oxide semiconductors are divided into amorphous oxide semiconductors and crystalline oxide semiconductors. Crystalline oxide semiconductors include single-crystal oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, and nc-OS, among others.

[0399] As a definition of amorphous structure, it is generally known that it is in a metastable state and not fixed, and is isotropic without inhomogeneous structure. Alternatively, it can be described as having non-fixed bond angles and exhibiting short-range order but not long-range order.

[0400] Conversely, a substantially stable oxide semiconductor cannot be called a completely amorphous oxide semiconductor. Furthermore, an oxide semiconductor that lacks isotropy (e.g., has a periodic structure in tiny regions) cannot be called a completely amorphous oxide semiconductor. Note that a-like OS has a periodic structure in tiny regions, but also contains voids and exhibits an unstable structure. Therefore, a-like OS is physically close to an amorphous oxide semiconductor.

[0401] <CAAC-OS>

[0402] First, let's explain CAAC-OS.

[0403] CAAC-OS is one of the oxide semiconductors that contains multiple c-axis oriented crystalline regions (also known as particles).

[0404] In the composite analysis image of the bright-field image and diffraction pattern of CAAC-OS obtained by transmission electron microscopy (TEM) (also known as a high-resolution TEM image), multiple particles were observed. However, in the high-resolution TEM image, no clear boundaries, i.e., grain boundaries, were observed between the particles. Therefore, it can be said that in CAAC-OS, a decrease in electron mobility caused by grain boundaries is not likely to occur.

[0405] The following section describes the CAAC-OS observed using TEM. FIG. 24A This shows a high-resolution TEM image of the CAAC-OS cross-section obtained by viewing from a direction approximately parallel to the sample plane. The high-resolution TEM image was obtained using the Spherical Aberration Corrector function. This high-resolution TEM image obtained using the Spherical Aberration Corrector function is specifically referred to as a Cs-corrected high-resolution TEM image. For example, a Cs-corrected high-resolution TEM image can be obtained using an atomic resolution analytical electron microscope such as the JEM-ARM200F manufactured by Nippon Electron Ltd.

[0406] FIG. 24B Showing will FIG. 24A (1) A magnified Cs-corrected high-resolution TEM image of region (1). (By...) FIG. 24BIt can be confirmed that the metal atoms in the particles are arranged in layers. Each layer of metal atoms has a concave-convex configuration that reflects the surface (also called the formed surface) or the top surface of the CAAC-OS film and is arranged in a manner parallel to the formed surface or the top surface of the CAAC-OS.

[0407] like FIG. 24B As shown, CAAC-OS has a unique atomic arrangement. FIG. 24C It is a diagram that uses auxiliary lines to show the unique atomic arrangement. (From...) FIG. 24B and FIG. 24C It is known that the size of a single particle is greater than 1 nm or 3 nm, and the size of the gaps created by the tilt between particles is about 0.8 nm. Therefore, the particles can also be called nanocrystals (nc). Note that CAAC-OS can also be called an oxide semiconductor with CANC (C-Axis Aligned nanocrystals).

[0408] Here, based on Cs-corrected high-resolution TEM images, the configuration of CAAC-OS particles 5100 on substrate 5120 is schematically represented as a structure of stacked bricks or blocks (see reference). FIG. 24D ).exist FIG. 24C The portion observed to tilt between particles corresponds to FIG. 24D The area shown is 5161.

[0409] also, FIG. 25A This shows a Cs-corrected high-resolution TEM image of the CAAC-OS plane obtained by viewing from a direction approximately perpendicular to the sample surface. FIG. 25B , FIG. 25C and FIG. 25D Show respectively FIG. 25A Cs-corrected high-resolution TEM images magnified from regions (1), (2), and (3) in the image. FIG. 25B , FIG. 25C and FIG. 25D It can be seen that the metal atoms in the particles are arranged in triangular, square, or hexagonal shapes. However, there is no regularity in the arrangement of metal atoms between different particles.

[0410] Next, the analysis of CAAC-OS using X-ray diffraction (XRD) will be explained. For example, when analyzing the structure of CAAC-OS containing InGaZnO4 crystals using the out-of-plane method, such as... FIG. 26AAs shown, a peak often appears around the diffraction angle (2θ) of 31°. Since this peak originates from the (009) plane of the InGaZnO4 crystal, it can be inferred that the crystals in CAAC-OS have a c-axis orientation, and the c-axis is oriented approximately perpendicular to the surface or top surface to which it is formed.

[0411] Note that when analyzing the structure of CAAC-OS using the out-of-plane method, in addition to the peak near 2θ 31°, a peak sometimes also appears near 2θ 36°. The peak near 2θ 36° indicates that a portion of the CAAC-OS contains crystals without c-axis orientation. Preferably, in the CAAC-OS structure analyzed using the out-of-plane method, a peak appears near 2θ 31° but no peak appears near 2θ 36°.

[0412] On the other hand, when analyzing the structure of CAAC-OS using the in-plane method, where X-rays are incident on the sample from a direction approximately perpendicular to the c-axis, a peak appears around 2θ = 56°. This peak originates from the (110) plane of the InGaZnO4 crystal. In CAAC-OS, even when 2θ is fixed at around 56° and the sample is rotated about the normal vector of the sample plane (φ-axis) for analysis (φ-scan), the peak value remains the same. FIG. 26B As shown, no clear peak is observed. In contrast, in single-crystal oxide semiconductors of InGaZnO4, when performing a φ scan with 2θ fixed at around 56°, as shown... Figure 26C As shown, six peaks originating from the crystal plane equivalent to (110) were observed. Therefore, structural analysis using XRD confirmed that the orientations of the a-axis and b-axis in CAAC-OS are irregular.

[0413] Next, CAAC-OS analysis using electron diffraction will be explained. For example, when an electron beam with a diameter of 300 nm is incident on a CAAC-OS containing InGaZnO4 crystals in a direction parallel to the sample plane, it is possible to obtain... Figure 27A The diffraction pattern shown is also known as a selected area transmission electron diffraction pattern. This diffraction pattern contains spots originating from the (009) plane of InGaZnO4 crystallization. Therefore, electron diffraction also reveals that the particles contained in CAAC-OS have a c-axis orientation, and the c-axis is oriented approximately perpendicular to the formed surface or top surface. On the other hand, Figure 27B The diffraction pattern is shown when an electron beam with a diameter of 300 nm is incident on the same sample in a direction perpendicular to the sample plane. Figure 27B A ring-shaped diffraction pattern was observed. Therefore, electron diffraction also indicates that the a-axis and b-axis of the particles contained in CAAC-OS are not oriented. It can be considered that... Figure 27BThe first ring in the crystal originates from the (010) and (100) planes of InGaZnO4 crystals. Furthermore, it can be considered that... Figure 27B The second ring in the middle is caused by (110) surface, etc.

[0414] As mentioned above, CAAC-OS is a highly crystalline oxide semiconductor. Since the crystallinity of oxide semiconductors can sometimes be reduced due to the introduction of impurities or the formation of defects, from the opposite perspective, CAAC-OS can be said to be an oxide semiconductor with fewer impurities or defects (such as oxygen defects).

[0415] In addition, impurities refer to elements other than the main components of oxide semiconductors, such as hydrogen, carbon, silicon, and transition metals. For example, elements such as silicon, which have a stronger bonding force with oxygen than the metal elements constituting the oxide semiconductor, can remove oxygen from the oxide semiconductor, thereby disrupting the atomic arrangement and leading to a decrease in crystallinity. Furthermore, because heavy metals such as iron or nickel, argon, carbon dioxide, etc., have large atomic radii (or molecular radii), they can also disrupt the atomic arrangement of oxide semiconductors, leading to a decrease in crystallinity.

[0416] When oxide semiconductors contain impurities or defects, their properties can sometimes change due to light or heat. For example, impurities in oxide semiconductors can sometimes act as carrier traps or carrier sources. In addition, oxygen defects in oxide semiconductors can sometimes act as carrier traps or carrier sources by trapping hydrogen.

[0417] CAAC-OS, with fewer impurities and oxygen vacancies, is an oxide semiconductor with low carrier density. Specifically, it can be used with carrier densities below 8 × 10⁻⁶. 11 / cm 3 Preferably less than 1×10 11 / cm 3 More preferably, less than 1×10 10 / cm 3 And it is 1×10 -9 / cm 3 The above describes oxide semiconductors. Such oxide semiconductors are called high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors. CAAC-OS has low impurity concentration and defect state density. That is, it can be said that CAAC-OS is an oxide semiconductor with stable properties.

[0418] <nc-OS>

[0419] Next, we will explain nc-OS.

[0420] In high-resolution TEM images of nc-OS, there are regions where crystalline regions are observable and regions where clear crystalline regions are not observed. The crystalline regions in nc-OS are mostly 1 nm or larger than 10 nm and smaller than 3 nm. Note that oxide semiconductors with crystalline regions larger than 10 nm but smaller than 100 nm are sometimes referred to as microcrystalline oxide semiconductors. For example, grain boundaries are sometimes not clearly observable in high-resolution TEM images of nc-OS. Note that the origin of nanocrystals may be the same as that of particles in CAAC-OS. Therefore, the crystalline regions of nc-OS are sometimes referred to as particles below.

[0421] In nc-OS, the atomic arrangement in tiny regions (e.g., regions larger than 1 nm and smaller than 10 nm, particularly regions larger than 1 nm and smaller than 3 nm) exhibits periodicity. Furthermore, no regularity in crystal orientation is observed between different particles in nc-OS. Therefore, no orientation is observed in the overall film. Thus, sometimes nc-OS is indistinguishable from a-like OS or amorphous oxide semiconductors in certain analytical methods. For example, when performing structural analysis of nc-OS using out-of-plane X-rays with a beam diameter larger than the particle size, no peaks representing crystal planes are detected. When electron diffraction is performed on nc-OS using electron beams with a beam diameter larger than the particle size (e.g., 50 nm or larger), a halo-like diffraction pattern is observed. On the other hand, when nanobeam electron diffraction is performed on nc-OS using electron beams with a beam diameter close to or smaller than the particle size, spots are observed. Additionally, in the nanobeam electron diffraction pattern of nc-OS, sometimes high-brightness regions resembling circles (rings) are observed. Moreover, in the nanobeam electron diffraction pattern of nc-OS, multiple spots are sometimes observed in the annular region.

[0422] Thus, since there is no regularity in the crystallization orientation between particles (nanocrystals), nc-OS can also be called an oxide semiconductor containing RANC (Random Aligned nanocrystals) or an oxide semiconductor containing NANC (Non-Aligned nanocrystals).

[0423] nc-OS is an oxide semiconductor with higher regularity than amorphous oxide semiconductors. Therefore, the defect state density of nc-OS is lower than that of a-like OS or amorphous oxide semiconductors. However, no regularity in crystal orientation is observed between different particles in nc-OS. Therefore, the defect state density of nc-OS is higher than that of CAAC-OS.

[0424] <a-like OS>

[0425] a-like OS is an oxide semiconductor with a structure between nc-OS and amorphous oxide semiconductor.

[0426] Voids are sometimes observed in high-resolution TEM images of a-like OS. Additionally, in high-resolution TEM images, there are areas where crystallization is clearly visible and areas where crystallization is not visible.

[0427] Because a-like OS contains voids, its structure is unstable. To demonstrate that a-like OS has an unstable structure compared to CAAC-OS and nc-OS, the structural changes caused by electron irradiation are shown below.

[0428] As samples for electron irradiation, a-like OS (referred to as sample A), nc-OS (referred to as sample B), and CAAC-OS (referred to as sample C) were prepared. Each sample was an In-Ga-Zn oxide.

[0429] First, high-resolution cross-sectional TEM images of each sample were obtained. The high-resolution cross-sectional TEM images show that each sample has a crystalline structure.

[0430] Note that the determination of which part is considered a crystalline region is as follows. For example, the unit lattice of InGaZnO4 is known to have a structure in which nine layers, comprising three In-O layers and six Ga-Zn-O layers, are stacked in a layered manner along the c-axis. The spacing between these layers that are close to each other is almost equal to the lattice surface spacing (also known as the d-value) of the (009) plane, which is determined to be 0.29 nm by crystal structure analysis. Therefore, the portion with a lattice fringe spacing of 0.28 nm or more and 0.30 nm or less can be considered as an InGaZnO4 crystalline region. Each lattice fringe corresponds to the ab plane of the InGaZnO4 crystal.

[0431] Figure 28 Examples are shown where the average size of the crystalline portions (22 to 45 portions) of various samples was investigated. Note that the crystalline portion size corresponds to the length of the lattice fringes described above. Figure 28 It can be seen that in a-like OS, the crystal portion gradually increases in size according to the cumulative amount of electron irradiation. Specifically, as... Figure 28 As shown in (1), it can be seen that in the initial observation using TEM, the crystal part with a size of about 1.2 nm (also called the initial crystal nucleus) has a cumulative irradiation dose of 4.2 × 10⁻⁶. 8 e - / nm 2 The growth rate reached approximately 2.6 nm. On the other hand, it was found that the cumulative electron irradiation dose for both nc-OS and CAAC-OS from the start of electron irradiation to the present was 4.2 × 10⁻⁶.8 e - / nm 2 Within this range, the size of the crystallized portion remained unchanged. Specifically, such as Figure 28 As shown in (2) and (3) in the figure, regardless of the cumulative irradiation of electrons, the average crystal size of nc-OS and CAAC-OS is about 1.4 nm and about 2.1 nm, respectively.

[0432] Thus, electron irradiation can sometimes induce the growth of crystalline regions in a-like OS. On the other hand, it is known that electron irradiation-induced crystalline region growth is almost nonexistent in nc-OS and CAAC-OS. In other words, a-like OS has an unstable structure compared to CAAC-OS and nc-OS.

[0433] Furthermore, because a-like OS contains voids, its density is lower than that of nc-OS and CAAC-OS. Specifically, the density of a-like OS is more than 78.6% and less than 92.3% of that of single-crystal oxide semiconductors with the same composition. The densities of nc-OS and CAAC-OS are more than 92.3% and less than 100% of those of single-crystal oxide semiconductors with the same composition. Note that it is difficult to form oxide semiconductors with densities less than 78% of those of single-crystal oxide semiconductors.

[0434] For example, in oxide semiconductors with an atomic ratio of In:Ga:Zn = 1:1:1, the density of a single-crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm³. 3 Therefore, for example, in an oxide semiconductor with an atomic ratio of In:Ga:Zn = 1:1:1, the density of a-like OS is 5.0 g / cm³. 3 Above and less than 5.9 g / cm 3 Additionally, for example, in oxide semiconductors with an atomic ratio of In:Ga:Zn = 1:1:1, the densities of nc-OS and CAAC-OS are 5.9 g / cm³. 3 Above and less than 6.3 g / cm 3 .

[0435] Note that sometimes single-crystal oxide semiconductors with identical compositions do not exist. In such cases, by combining different single-crystal oxide semiconductors in arbitrary proportions, the density of single-crystal oxide semiconductors corresponding to the desired composition can be estimated. The density of single-crystal oxide semiconductors corresponding to the desired composition can be calculated using a weighted average based on the combination proportions of the different single-crystal oxide semiconductors. Note that it is preferable to minimize the number of types of single-crystal oxide semiconductors used in the density calculation.

[0436] As described above, oxide semiconductors have various structures and properties. Note that oxide semiconductors can be, for example, stacked films of two or more types, including amorphous oxide semiconductors, a-like OS, nc-OS, and CAAC-OS.

[0437] Implementation Method 4

[0438] In this embodiment, an example of a circuit utilizing a transistor according to one aspect of the present invention will be described with reference to the accompanying drawings.

[0439] <Cross-section Structure>

[0440] Figure 29A A cross-sectional view of a semiconductor device according to one embodiment of the present invention is shown. Figure 29A In the diagram, the X1-X2 direction indicates the channel length direction, and the Y1-Y2 direction indicates the channel width direction. Figure 29A The semiconductor device shown includes a transistor 2200 using a first semiconductor material in the lower part and a transistor 2100 using a second semiconductor material in the upper part. Figure 29A An example of the transistor shown in the above embodiment is illustrated as a transistor 2100 using the second semiconductor material. Note that the left side of the dotted line represents a cross-section in the channel length direction of the transistor, while the right side of the dotted line represents a cross-section in the channel width direction of the transistor.

[0441] The first semiconductor material and the second semiconductor material are preferably materials having different band gaps. For example, a semiconductor material other than an oxide semiconductor (silicon (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, organic semiconductors, etc.) can be used as the first semiconductor material, and an oxide semiconductor can be used as the second semiconductor material. Transistors using single-crystal silicon, etc., as materials other than oxide semiconductors are easy to operate at high speeds. On the other hand, by applying the transistor illustrated in the above embodiment to a transistor using an oxide semiconductor, good subthreshold characteristics can be obtained, and a miniature transistor can be realized. Furthermore, this transistor has a fast switching speed, so it can operate at high speeds, and its off-state current is small, so the leakage current is small.

[0442] Transistor 2200 can be either an n-channel transistor or a p-channel transistor; the appropriate transistor can be used depending on the circuit. Furthermore, the specific structure of the semiconductor device, including materials and structure, is not limited to the structure shown herein, except for the transistor of one embodiment of the present invention that incorporates oxide semiconductors.

[0443] exist Figure 29AIn the structure shown, transistor 2100 is disposed on transistor 2200 with insulators 2201 and 2207 in between. Multiple wirings 2202 are disposed between transistors 2200 and 2100. Furthermore, multiple plugs 2203 embedded in various insulators are electrically connected to the wirings or electrodes disposed on and under the insulators. In addition, an insulator 2204 covering transistor 2100 and wirings 2205 on the insulator 2204 are also provided.

[0444] In this way, by stacking two types of transistors, the area occupied by the circuit can be reduced, and multiple circuits can be arranged in high density.

[0445] Here, when a silicon-based semiconductor material is used in the transistor 2200 disposed in the lower layer, hydrogen in the insulator near the semiconductor film of the transistor 2200 has the effect of terminating the dangling bonds of silicon, thereby improving the reliability of the transistor 2200. On the other hand, when an oxide semiconductor is used in the transistor 2100 disposed in the upper layer, hydrogen in the insulator near the semiconductor film of the transistor 2100 may become one of the causes of carrier generation in the oxide semiconductor, thus sometimes causing a decrease in the reliability of the transistor 2100. Therefore, when an oxide semiconductor transistor 2100 is stacked on top of a silicon-based semiconductor transistor 2200, it is particularly effective to provide an insulator 2207 between them that has the function of preventing hydrogen diffusion. By using the insulator 2207 to confine hydrogen in the lower layer, the reliability of the transistor 2200 can be improved. Furthermore, since the diffusion of hydrogen from the lower layer to the upper layer is suppressed, the reliability of the transistor 2100 can also be improved.

[0446] Insulator 2207 can be made of aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttrium-stabilized zirconium oxide (YSZ), etc.

[0447] Furthermore, it is preferable to form a barrier film that prevents hydrogen diffusion on the transistor 2100, covering the transistor 2100 including the oxide semiconductor film. This barrier film can be made of the same material as the insulator 2207, and aluminum oxide film is particularly preferred. Aluminum oxide film has a high blocking effect, preventing impurities such as hydrogen and moisture, as well as oxygen, from permeating through the film. Therefore, by using an aluminum oxide film as the barrier film covering the transistor 2100, oxygen can be prevented from detaching from the oxide semiconductor film in the transistor 2100, and water and hydrogen can also be prevented from mixing into the oxide semiconductor film. Note that this barrier film can be either stacked on the insulator 2204 or disposed on the underside of the insulator 2204.

[0448] In addition, the transistor 2200 is not only a planar transistor, but can also be various types of transistors. For example, it can be a FIN (fin) type, TRI-GATE (tri-gate) type transistor, etc. Figure 29D An example of a cross-sectional view at this time is shown. An insulator 2212 is provided on the semiconductor substrate 2211. The semiconductor substrate 2211 has a convex portion (also referred to as a fin) with a thin tip. In addition, an insulator may also be provided on the convex portion. This insulator serves as a mask to prevent the semiconductor substrate 2211 from being etched when forming the convex portion. Additionally, the convex portion can be a shape with a non-thin tip. For example, the convex portion can also be a substantially rectangular parallelepiped or a shape with a thick tip. A gate insulator 2214 is provided on the convex portion of the semiconductor substrate 2211, and a gate electrode 2213 is provided on the gate insulator 2214. Active regions and drain regions 2215 are formed in the semiconductor substrate 2211. Although an example where the semiconductor substrate 2211 has a convex portion is shown here, the semiconductor device according to one aspect of the present invention is not limited to this. For example, an SOI substrate can also be processed to form a semiconductor region with a convex portion.

[0449] <Example of circuit structure>

[0450] In the above structure, various circuits can be constructed by appropriately connecting the electrodes of the transistor 2100 and the transistor 2200. An example of a circuit structure that can be achieved by using the semiconductor device according to one aspect of the present invention is described below.

[0451] <CMOS inverter>

[0452] Figure 29B The shown circuit diagram shows the structure of a so-called CMOS inverter, in which a p-channel transistor 2200 and an n-channel transistor 2100 are connected in series and their respective gates are connected.

[0453] <CMOS analog switch>

[0454] Figure 29C The shown circuit diagram shows a structure in which the respective sources and drains of the transistor 2100 and the transistor 2200 are connected. In Figure 29A it, the X1-X2 direction represents the channel length direction, and the Y1-Y2 direction represents the channel width direction. By adopting this structure, it can be used as a so-called CMOS analog switch.

[0455] <Example of storage device>

[0456] Figures 30A to 30C An example of a semiconductor device (storage device) is shown. This semiconductor device (storage device) uses a transistor according to one aspect of the present invention and can retain the stored content even without power supply, and there is no limit on the number of write operations.

[0457] Figure 30A The semiconductor device shown includes: a transistor 3200 using a first semiconductor material; a transistor 3300 using a second semiconductor material; and a capacitor 3400. The transistor 3300 can be the same as those described in Embodiments 1 and 2.

[0458] Figure 30B Show Figure 30A The diagram shows a cross-sectional view of a semiconductor device. The semiconductor device in this cross-sectional view employs a structure with a back gate in transistor 3300.

[0459] in addition, Figure 30A This is the structure when the intermediate layer 2210 is conductive; when the intermediate layer 2210 is insulating, it can be as follows: Figures 22A to 22C Transistor 2200 and transistor 2100 are connected by wiring 3005 as shown.

[0460] Transistor 3300 is a transistor whose channel is formed in a semiconductor layer containing oxide semiconductor. Because transistor 3300 has a small off-state current, stored content can be retained for a long time by using this transistor. In other words, because a semiconductor memory device that does not require refresh operation or has an extremely low refresh frequency can be formed, power consumption can be significantly reduced.

[0461] exist Figure 30A In this configuration, the first wiring 3001 is electrically connected to the source electrode of transistor 3200, and the second wiring 3002 is electrically connected to the drain electrode of transistor 3200. Furthermore, the third wiring 3003 is electrically connected to one of the source and drain electrodes of transistor 3300, and the fourth wiring 3004 is electrically connected to the gate electrode of transistor 3300. Additionally, the gate electrode of transistor 3200 is electrically connected to the other of the source and drain electrodes of transistor 3300 and one electrode of capacitor 3400, and the fifth wiring 3005 is electrically connected to the other electrode of capacitor 3400.

[0462] exist Figure 30A In the semiconductor device shown, by effectively utilizing the feature that can maintain the potential of the gate electrode of transistor 3200, data can be written, held, and read out as shown below.

[0463] The writing and holding of data are explained. First, the potential of the fourth wiring 3004 is set to the potential that turns on transistor 3300, thus turning on transistor 3300. Consequently, the potential of the third wiring 3003 is applied to the gate electrode of transistor 3200 and capacitor 3400. In other words, a predetermined charge is applied to the gate of transistor 3200 (writing). Here, either a charge with two different potential levels (hereinafter referred to as low-level charge and high-level charge) is applied. Then, by setting the potential of the fourth wiring 3004 to the potential that turns off transistor 3300, transistor 3300 is turned off, and the charge applied to the gate of transistor 3200 is held (holding).

[0464] Because the off-state current of transistor 3300 is extremely small, the gate charge of transistor 3200 is maintained for a long time.

[0465] Next, the data readout will be explained. When a predetermined potential (constant potential) is applied to the fifth wiring 3005 while a predetermined potential (readout potential) is applied to the first wiring 3001, the second wiring 3002 has a different potential depending on the amount of charge held in the gate of the transistor 3200. This is because, generally speaking, when the transistor 3200 is an n-channel transistor, the apparent threshold voltage V when a high-level charge is applied to the gate electrode of the transistor 3200 is... th_H The apparent threshold voltage V is lower than the voltage V when a low-level charge is applied to the gate electrode of transistor 3200. th_L Here, the apparent threshold voltage refers to the potential of the fifth wiring 3005 required to make transistor 3200 "on". Therefore, by setting the potential of the fifth wiring 3005 to V... th_L With V th_H The potential V0 between these values ​​can be used to identify the charge applied to the gate of transistor 3200. For example, when a high-level charge is supplied during writing, if the potential of the fifth wiring 3005 is V0 (>V0), then... th_H When transistor 3200 is supplied with a low-level charge, even if the potential of the fifth wiring 3005 is V0, transistor 3200 becomes "conducting". <V th_L Transistor 3200 remains in the "off state". Therefore, the held data can be read by identifying the potential of the second wiring 3002.

[0466] Note that when the memory cells are configured in an array, it is necessary to read only the data from the desired memory cells. Thus, when no data is being read, a potential less than V can be applied to the fifth wiring 3005 that keeps transistor 3200 in the "off" state regardless of the gate state. th_HAlternatively, a potential greater than V can be applied to the fifth wiring 3005 that makes transistor 3200 "on" regardless of the gate state. th_L The potential.

[0467] Figure 30C The semiconductor device shown is Figure 30A The difference between the semiconductor devices shown is that transistor 3200 is not present. In this case, data writing and retention can still be performed using the same methods as described above.

[0468] Next, the data readout will be explained. When transistor 3300 is in the ON state, the floating third wiring 3003 and capacitor 3400 are turned on, and charge is redistributed between the third wiring 3003 and capacitor 3400. As a result, the potential of the third wiring 3003 changes. The amount of change in the potential of the third wiring 3003 varies depending on the potential of the first terminal of capacitor 3400 (or the charge accumulated in capacitor 3400).

[0469] For example, if the potential of the first terminal of capacitor 3400 is V, the capacitance of capacitor 3400 is C, the capacitive component of the third wiring 3003 is CB, and the potential of the third wiring 3003 before charge redistribution is VB0, then the potential of the third wiring 3003 after charge redistribution is (CB×VB0+C×V) / (CB+C). Therefore, assuming that the potential of the first terminal of capacitor 3400 is in two states, namely V1 and V0 (V1>V0), it can be known that the potential of the third wiring 3003 when holding potential V1 (=(CB×VB0+C×V1) / (CB+C)) is higher than the potential of the third wiring 3003 when holding potential V0 (=(CB×VB0+C×V0) / (CB+C)).

[0470] Data can be read by comparing the potential of the third wiring 3003 with the specified potential.

[0471] In this case, the transistor using the first semiconductor material can be used in a drive circuit to drive the memory cell, and the transistor using the second semiconductor material can be stacked as transistor 3300 on the drive circuit.

[0472] In the semiconductor device shown in this embodiment, by using transistors whose channel formation region comprises oxide semiconductors with extremely low off-state current, stored content can be retained for an extremely long time. In other words, because refresh operations are not required, or the frequency of refresh operations can be made extremely low, power consumption can be significantly reduced. Furthermore, stored content can be retained for a long time even without a power supply (note that a fixed potential is preferred).

[0473] Furthermore, in the semiconductor device shown in this embodiment, data writing does not require high voltage, and there is no problem of component degradation. Since, for example, it is not necessary to inject or extract electrons from the floating gate as in conventional non-volatile memories, problems such as degradation of the gate insulating layer do not occur. In other words, in the semiconductor device according to one aspect of the disclosed invention, there is no limitation on the number of rewrites, a limitation inherent in conventional non-volatile memories, thus greatly improving reliability. Moreover, data writing is performed based on the transistor's on or off state, making high-speed operation easily achievable.

[0474] Furthermore, even if the connection objects of all terminals of active components (transistors, diodes, etc.) and passive components (capacitors, resistors, etc.) are not specified in this specification, those skilled in the art can sometimes still construct an inventive method. That is to say, it can be said that even if the connection objects are not specified, an inventive method is clearly defined. Moreover, when the content specifying the connection objects is described in this specification, it can sometimes be determined that an inventive method without specifying the connection objects is described in this specification. Especially when considering multiple terminal connection objects, the connection objects of the terminals need not be limited to a specified portion. Therefore, sometimes by specifying only a portion of the connection objects of terminals of active components (transistors, diodes, etc.) and passive components (capacitors, resistors, etc.), an inventive method can be constructed.

[0475] Furthermore, in this specification and other documents, as long as at least one circuit connection object is specified, a person skilled in the art can sometimes constitute an invention. Alternatively, as long as at least one circuit function is specified, a person skilled in the art can sometimes constitute an invention. That is to say, it can be said that as long as the function is specified, an inventive approach is clearly defined. Furthermore, it can sometimes be determined that an inventive approach with specified function is described in this specification and other documents. Therefore, even if the function of a particular circuit is not specified, specifying the connection object constitutes an inventive approach. Furthermore, even if the connection object of a particular circuit is not specified, specifying its function constitutes an inventive approach.

[0476] Note that in this specification and the like, a mode of the invention can be constituted by extracting a part from the drawings or articles shown in a certain embodiment. Therefore, in the case of a drawing or article describing a certain part, the content of the extracted part of the drawing or article is also regarded as a mode of the disclosed invention and can constitute a mode of the invention. Thus, for example, in a drawing or article describing one or more of active elements (such as transistors and diodes), wirings, passive elements (such as capacitors and resistors), conductive layers, insulating layers, semiconductor layers, organic materials, inorganic materials, components, devices, working methods, manufacturing methods, etc., a part can be extracted to constitute a mode of the invention. For example, M (M is an integer, M < N) circuit elements (such as transistors and capacitors) can be extracted from a circuit diagram composed of N (N is an integer) circuit elements (such as transistors and capacitors) to constitute a mode of the invention. As another example, M (M is an integer, M < N) layers can be extracted from a cross-sectional view composed of N (N is an integer) layers to constitute a mode of the invention. Furthermore, as another example, M (M is an integer, M < N) elements can be extracted from a flowchart composed of N (N is an integer) elements to constitute a mode of the invention.

[0477] <Imaging device>

[0478] An imaging device according to an embodiment of the present invention will be described below.

[0479] Figure 31A FIG. is a plan view showing an example of an imaging device 200 according to an embodiment of the present invention. The imaging device 200 includes a pixel section 210, an outer circuit 260 for driving the pixel section 210, an outer circuit 270, an outer circuit 280, and an outer circuit 290. The pixel section 210 includes a plurality of pixels 211 arranged in a matrix of p rows and q columns (p and q are integers of 2 or more). The outer circuits 260, 270, 280, and 290 are respectively connected to the plurality of pixels 211 and have a function of supplying signals for driving the plurality of pixels 211. In this specification and the like, the outer circuits 260, 270, 280, 290, etc. are sometimes collectively referred to as the "outer circuit" or the "driving circuit". For example, the outer circuit 260 can also be said to be a part of the outer circuit.

[0480] The imaging device 200 preferably includes a light source 291. The light source 291 can emit detection light P1.

[0481] The peripheral circuitry includes at least one of a logic circuit, a switch, a buffer, an amplifier circuit, or a conversion circuit. Alternatively, the peripheral circuitry may be formed on the substrate on which the pixel portion 210 is formed. Furthermore, semiconductor devices such as ICs may be used for part or all of the peripheral circuitry. Note that one or more of peripheral circuits 260, 270, 280, and 290 may be omitted.

[0482] like Figure 31B As shown, the pixel units 210 included in the imaging device 200 can also be arranged with the pixels 211 tilted. By arranging the pixels 211 in a tilted manner, the pixel spacing (interval) in the row direction and column direction can be shortened. As a result, the imaging quality of the imaging device 200 can be improved.

[0483] <Example 1 of pixel structure>

[0484] By making a pixel 211 included in the camera device 200 consist of a plurality of sub-pixels 212, and by combining each sub-pixel 212 with a filter (color filter) that allows light of a specific wavelength region to pass through, information for displaying a color image can be obtained.

[0485] Figure 32A This is a plan view showing an example of pixel 211 used to obtain a color image. Figure 32A The pixel 211 shown includes a sub-pixel 212 (hereinafter also referred to as "sub-pixel 212R") with a color filter that allows light in the red (R) wavelength region to pass through, a sub-pixel 212 (hereinafter also referred to as "sub-pixel 212G") with a color filter that allows light in the green (G) wavelength region to pass through, and a sub-pixel 212 (hereinafter also referred to as "sub-pixel 212B") with a color filter that allows light in the blue (B) wavelength region to pass through. The sub-pixel 212 can be used as a photoelectric sensor.

[0486] Sub-pixels 212 (sub-pixels 212R, 212G, and 212B) are electrically connected to wirings 231, 247, 248, 249, and 250. Furthermore, sub-pixels 212R, 212G, and 212B are each independently connected to wiring 253. In this specification, for example, wirings 248 and 249 connected to the pixel 211 in the nth row are referred to as wiring 248[n] and wiring 249[n], respectively. Furthermore, for example, wiring 253 connected to the pixel 211 in the mth column is referred to as wiring 253[m]. Furthermore, in... Figure 32AIn the diagram, the wiring 253 connecting the sub-pixel 212R included in the m-th column pixel 211 is called wiring 253[m]R, the wiring 253 connecting the sub-pixel 212G is called wiring 253[m]G, and the wiring 253 connecting the sub-pixel 212B is called wiring 253[m]B. The sub-pixel 212 is electrically connected to the peripheral circuit through the above wiring.

[0487] The camera device 200 has a structure in which adjacent pixels 211 are arranged and sub-pixels 212 with color filters that allow light of the same wavelength region to pass through are electrically connected to each other by a switch. Figure 32B This illustrates an example of the connection between a sub-pixel 212 included in pixel 211 located in row n and column m, and a sub-pixel 212 included in pixel 211 located in row n+1 and column m adjacent to pixel 211. Figure 32B In the diagram, sub-pixel 212R, located in the nth row (n is an integer greater than 1 and less than p) and in the mth column (m is an integer greater than 1 and less than q), is connected to sub-pixel 212R located in the (n+1)th row and in the mth column via switch 201. Furthermore, sub-pixel 212G, located in the nth row and in the mth column, is connected to sub-pixel 212G located in the (n+1)th row and in the mth column via switch 202. Additionally, sub-pixel 212B, located in the nth row and in the mth column, is connected to sub-pixel 212B located in the (n+1)th row and in the mth column via switch 203.

[0488] The color of the filter used for sub-pixel 212 is not limited to red (R), green (G), and blue (B); filters that allow cyan (C), yellow (Y), and magenta (M) light to pass through can also be used. By setting a sub-pixel 212 in a single pixel 211 that detects light in three different wavelength regions, a full-color image can be obtained.

[0489] Alternatively, in addition to sub-pixels 212 that are respectively provided with color filters that allow red (R), green (G), and blue (B) light to pass through, pixel 211 may also include sub-pixels 212 that are provided with color filters that allow yellow (Y) light to pass through. Alternatively, in addition to sub-pixels 212 that are respectively provided with color filters that allow cyan (C), yellow (Y), and magenta (M) light to pass through, pixel 211 may also include sub-pixels 212 that are provided with color filters that allow blue (B) light to pass through. By providing sub-pixels 212 that detect light in four different wavelength regions within a single pixel 211, the color reproduction of the obtained image can be further improved.

[0490] For example, in Figure 32AIn this design, the pixel ratio (or light-receiving area ratio) of the sub-pixels 212 detecting the red wavelength region, the green wavelength region, and the blue wavelength region is not limited to 1:1:1. For example, a Bayer arrangement with a pixel ratio (light-receiving area ratio) of red:green:blue = 1:2:1 can also be used. Alternatively, the pixel ratio (light-receiving area ratio) can also be red:green:blue = 1:6:1.

[0491] The number of sub-pixels 212 set in pixel 211 can be one, but preferably two or more. For example, by setting two or more sub-pixels 212 that detect the same wavelength region, redundancy can be improved, thereby improving the reliability of the imaging device 200.

[0492] Furthermore, an infrared light detection camera 200 can be realized by using an IR (Infrared) filter that reflects or absorbs visible light and allows infrared light to pass through.

[0493] By using ND (Neutral Density) filters, output saturation can be prevented when a large amount of light is incident on a photoelectric conversion element (light-receiving element). By combining ND filters with different light-reducing amounts, the dynamic range of the camera device can be increased.

[0494] In addition to the aforementioned filter, a lens can also be provided in pixel 211. Here, refer to... Figures 33A-33B The cross-sectional diagram illustrates an example of the configuration of pixel 211, filter 254, and lens 255. By configuring lens 255, the photoelectric conversion element can receive light efficiently. Specifically, as shown... Figure 33A As shown, light 256 can pass through the lens 255, filter 254 (filter 254R, filter 254G and filter 254B) and pixel circuit 230 formed in the pixel 211 and be incident on the photoelectric conversion element 220.

[0495] Note that, as shown in the area surrounded by the dotted line, sometimes a portion of the light 256 indicated by the arrow is obscured by a portion of the wiring 257. Therefore, as... Figure 33B As shown, a preferred structure is one in which a lens 255 and a filter 254 are arranged on one side of the photoelectric conversion element 220, thereby enabling the photoelectric conversion element 220 to efficiently receive light 256. By incident light 256 onto the photoelectric conversion element 220 from one side, a camera device 200 with high detection sensitivity can be provided.

[0496] As Figures 33A-33B The photoelectric conversion element 220 shown can also be a photoelectric conversion element with a pn junction or a pin junction.

[0497] The photoelectric conversion element 220 can also be formed using a material that has the function of absorbing radiation and generating electric charge. Examples of materials that have the function of absorbing radiation and generating electric charge include selenium, lead iodide, mercuric iodide, gallium arsenide, cadmium telluride, and cadmium-zinc alloy.

[0498] For example, when selenium is used in photoelectric conversion element 220, a photoelectric conversion element 220 with a light absorption coefficient in a wide wavelength range such as visible light, ultraviolet light, infrared light, X-rays, and gamma rays can be realized.

[0499] Here, the pixel 211 included in the camera device 200, in addition to Figures 32A-32B In addition to the sub-pixel 212 shown, it may also include a sub-pixel 212 having a first filter.

[0500] <Example 2 of pixel structure>

[0501] Below, an example of a pixel including transistors using silicon and transistors using oxide semiconductors will be described.

[0502] Figure 34A and Figure 34B It is a cross-sectional view of the components that make up the camera device.

[0503] Figure 34A The imaging device shown includes: a silicon-based transistor 351 disposed on a silicon substrate 300; transistors 352 and 353, formed of oxide semiconductor, stacked on the transistor 351; and a photodiode 360 ​​disposed in the silicon substrate 300, including an anode 361 and a cathode 362. Each transistor and photodiode 360 ​​is electrically connected to various connectors 370 and wiring 371. Furthermore, the anode 361 of the photodiode 360 ​​is electrically connected to the connector 370 through a low-resistance region 363.

[0504] The camera device includes: a layer 310 including a transistor 351 and a photodiode 360 ​​disposed on a silicon substrate 300; a layer 320 disposed in contact with the layer 310 and including wiring 371; a layer 330 disposed in contact with the layer 320 and including transistor 352 and transistor 353; and a layer 340 disposed in contact with the layer 330 and including wiring 372 and wiring 373.

[0505] exist Figure 34A In one example of a cross-sectional view, a light-receiving surface of a photodiode 360 ​​is provided on the silicon substrate 300 on the side opposite to the surface where the transistor 351 is formed. By employing this structure, the optical path can be ensured unaffected by various transistors or wiring. Therefore, a pixel with a high aperture ratio can be formed. Furthermore, the light-receiving surface of the photodiode 360 ​​can also be the same surface as the surface where the transistor 351 is formed.

[0506] When forming pixels using transistors, layer 310 may be a layer having transistors, or alternatively, pixels may be formed using only transistors and layer 310 may be omitted.

[0507] In Figure 34A the cross-sectional view, it may be formed such that the photodiode 360 provided in layer 310 overlaps with the transistors provided in layer 330. Therefore, the integration degree of the pixels can be increased. That is, the resolution of the imaging device can be increased.

[0508] As Figure 34B shown, the imaging device may also adopt a structure in which the photodiode 365 is disposed on the transistor on the side of layer 340. In Figure 34B for example, layer 310 includes transistors 351 and 352 using silicon, layer 320 includes wiring 371, layer 330 includes transistors 352 and 353 using an oxide semiconductor layer, layer 340 includes a photodiode 365, the photodiode 365 includes semiconductor layers 63, 64, and 65, and the wiring 373 is electrically connected to the wiring 374 through a plug 370.

[0509] By adopting the Figure 34B shown element structure, the aperture ratio can be increased.

[0510] As the photodiode 365, a pin junction diode element using an amorphous silicon film or a microcrystalline silicon film, etc. may also be adopted. The photodiode 365 has a structure in which an n-type semiconductor layer 368, an i-type semiconductor layer 367, and a p-type semiconductor layer 366 are stacked in sequence. The i-type semiconductor layer 367 preferably uses amorphous silicon. The p-type semiconductor layer 366 and the n-type semiconductor layer 368 may use amorphous silicon or microcrystalline silicon containing a dopant for imparting each conductivity type. The photodiode 365 having an amorphous silicon as the photoelectric conversion layer has high sensitivity in the visible light wavelength region and is easy to detect weak visible light.

[0511] This embodiment can be appropriately combined with other embodiments and examples shown in this specification.

[0512] Embodiment 5

[0513] <RF tag>

[0514] In this embodiment, an RF tag including the transistors or storage devices exemplified in the above embodiment will be described with reference to Figure 35 the following.

[0515] The RF tag of this embodiment includes a storage circuitry internally, in which necessary data is stored, and uses a contactless unit such as wireless communication to transmit and / or receive data from the outside. Due to these characteristics, the RF tag can be used in personal identification systems that identify items by reading their individual information. Note that, given these applications, extremely high reliability is required.

[0516] Reference Figure 35 Explain the structure of the RF tag. Figure 35 This is a block diagram showing a structural example of an RF tag.

[0517] like Figure 35 As shown, the RF tag 800 includes an antenna 804 that receives a wireless signal 803 transmitted from an antenna 802 connected to a communicator 801 (also called an interrogator, reader / writer, etc.). The RF tag 800 also includes a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 807, a modulation circuit 808, a logic circuit 809, a storage circuit 810, and a ROM 811. Furthermore, in the transistor with rectifier function included in the demodulation circuit 807, a material that sufficiently suppresses reverse current, such as an oxide semiconductor, can be used. This suppresses the reduction in rectification effect caused by reverse current and prevents output saturation of the demodulation circuit; that is, the relationship between the input and output of the demodulation circuit can be made close to a linear relationship. Note that data transmission methods are broadly classified into three types: electromagnetic coupling methods that use mutual inductance to communicate by arranging a pair of coils opposite each other; electromagnetic induction methods that use an induced field for communication; and radio wave methods that use radio waves for communication. Any of the above methods can be used in the RF tag 800 shown in this embodiment.

[0518] Next, the structure of each circuit will be explained. Antenna 804 transmits and receives wireless signals 803 via antenna 802 connected to communicator 801. In rectifier circuit 805, the input AC signal generated by receiving the wireless signal through antenna 804 is rectified, for example, by half-wave voltage doubler rectification, and the rectified signal is smoothed by a capacitor placed in the subsequent stage, thereby generating an input potential. Additionally, a limiting circuit can be provided on either the input or output side of rectifier circuit 805. The limiting circuit controls the input AC signal amplitude to prevent a certain amount of power from being input into the subsequent circuit when the internal generated voltage is large.

[0519] The constant voltage circuit 806 is a circuit that generates a stable power supply voltage from the input potential to supply various circuits. The constant voltage circuit 806 may also include a reset signal generation circuit internally. The reset signal generation circuit is a circuit that uses the rise of the stable power supply voltage to generate a reset signal for the logic circuit 809.

[0520] The demodulation circuit 807 is a circuit that demodulates an input AC signal by envelope detection and generates a demodulated signal. In addition, the modulation circuit 808 is a circuit that modulates data output from the antenna 804.

[0521] The logic circuit 809 is a circuit that analyzes the demodulated signal and performs processing. The storage circuit 810 is a circuit that holds the input data, and includes a row decoder, a column decoder, a storage area, etc. In addition, the ROM 811 is a circuit that holds an identification number (ID), etc. and outputs it according to the processing.

[0522] Note that each of the above circuits can be appropriately provided or omitted as needed.

[0523] Here, the storage circuit shown in the above embodiment can be used for the storage circuit 810. Since the storage circuit of one aspect of the present invention can hold data even in a power-off state, it is suitable for RF tags. Furthermore, since the power (voltage) required for data writing of the storage circuit of one aspect of the present invention is much lower than that of existing non-volatile memories, there is no difference in the maximum communication distance during data reading and writing. Furthermore, the storage device of one aspect of the present invention can suppress malfunction or miswriting due to insufficient power during data writing.

[0524] In addition, since the storage circuit of one aspect of the present invention can be used as a non-volatile memory, it can also be applied to the ROM 811. In this case, it is preferable that the producer separately prepares an instruction for writing data to the ROM 811 to prevent the user from freely rewriting. Since the producer writes the identification number before shipment, only the shipped good products can have the identification number and not all the manufactured RF tags, so that the identification numbers of the products after shipment are not discontinuous, and customer management can be easily performed based on the products after shipment.

[0525] This embodiment can be appropriately combined with other embodiments and examples shown in this specification.

[0526] Embodiment 6

[0527] In this embodiment, a CPU including the storage device described in the above embodiment will be described.

[0528] Figure 36 is a block diagram showing an example of the structure of a CPU in which the transistor described in the above embodiment is used for at least a part thereof.

[0529] <Circuit diagram of CPU> <00​​The CPU shown has the following components on substrate 1190: ALU 1191 (ALU: Arithmetic Logic Unit), ALU controller 1192, instruction decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface 1198, rewritable ROM 1199, and ROM interface 1189. The substrate 1190 can be a semiconductor substrate, SOI substrate, glass substrate, etc. The ROM 1199 and ROM interface 1189 can also be located on different chips. Of course, Figure 36 The CPU shown is merely a simplified example; actual CPUs have a wide variety of structures depending on their application. For instance, they can also include... Figure 36 The CPU or arithmetic circuit shown is the core structure, with multiple such cores configured to operate simultaneously. Furthermore, the number of bits that can be processed in the CPU's internal arithmetic circuitry or data bus can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0531] Instructions input to the CPU via bus interface 1198 are input to instruction decoder 1193 and decoded before being input to ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195.

[0532] The ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates signals to control the operation of the ALU 1191. Furthermore, the interrupt controller 1194, while executing the CPU's program, determines and processes interrupt requests from external input / output devices or peripheral circuits based on their priority or mask state. The register controller 1197 generates the address of register 1196 and reads or writes register 1196 according to the CPU's state.

[0533] Additionally, the timing controller 1195 generates signals to control the operating timing of the ALU 1191, ALU controller 1192, instruction decoder 1193, interrupt controller 1194, and register controller 1197. For example, the timing controller 1195 has an internal clock generator that generates an internal clock signal based on a reference clock signal and supplies the internal clock signal to the aforementioned circuits.

[0534] exist Figure 36 In the CPU shown, a storage unit is provided in register 1196. The transistors shown in Embodiments 1 to 3 can be used as the storage unit of register 1196.

[0535] exist Figure 36 In the CPU shown, the register controller 1197 selects the holding operation in register 1196 based on instructions from ALU 1191. In other words, the register controller 1197 selects whether data is held by flip-flops or by capacitors within the memory cells of register 1196. When flip-flops are selected, power supply voltage is supplied to the memory cells in register 1196. When capacitors are selected, the data is overwritten, and power supply voltage to the memory cells in register 1196 can be stopped.

[0536] <Storage Circuit>

[0537] Figure 37 This is an example of a circuit diagram that can be used as a storage element in register 1196. Storage element 1200 includes circuitry 1201 (data is lost when power is off), circuitry 1202 (data is not lost when power is off), switches 1203 and 1204, logic element 1206, capacitor 1207, and circuitry 1220 with selection functionality. Circuitry 1202 includes capacitor 1208, transistor 1209, and transistor 1210. Additionally, storage element 1200 may include other components such as diodes, resistors, or inductors as needed.

[0538] Here, circuit 1202 can use the storage device shown in the above embodiment. When the power supply voltage to the storage element 1200 is stopped, a ground potential (0V) or a potential that turns off transistor 1209 continues to be input to the gate of transistor 1209 in circuit 1202. For example, the first gate of transistor 1209 is grounded through a load such as a resistor.

[0539] This example illustrates a transistor 1213 with a conductivity type (e.g., n-channel) as switch 1203, and a transistor 1214 with the opposite conductivity type (e.g., p-channel) as switch 1204. Here, the first terminal of switch 1203 corresponds to one of the source and drain terminals of transistor 1213, and the second terminal of switch 1203 corresponds to the other of the source and drain terminals of transistor 1213. The on / off state (i.e., the state of transistor 1213 being turned on or off) between the first and second terminals of switch 1203 is selected by a control signal RD input to the gate of transistor 1213. Similarly, the first terminal of switch 1204 corresponds to one of the source and drain terminals of transistor 1214, and the second terminal of switch 1204 corresponds to the other of the source and drain terminals of transistor 1214. The on / off state (i.e., the state of transistor 1214 being turned on or off) between the first and second terminals of switch 1204 is selected by a control signal RD input to the gate of transistor 1214.

[0540] One of the source and drain of transistor 1209 is electrically connected to one of the pairs of electrodes of capacitor 1208 and the gate of transistor 1210. This connection is referred to here as node M2. One of the source and drain of transistor 1210 is electrically connected to a wiring capable of supplying a low power supply potential (e.g., GND), while the other is electrically connected to the first terminal of switch 1203 (one of the source and drain of transistor 1213). The second terminal of switch 1203 (the other of the source and drain of transistor 1213) is electrically connected to the first terminal of switch 1204 (one of the source and drain of transistor 1214). The second terminal of switch 1204 (the other of the source and drain of transistor 1214) is electrically connected to a wiring capable of supplying the power supply potential VDD. The second terminal of switch 1203 (the other of the source and drain of transistor 1213), the first terminal of switch 1204 (one of the source and drain of transistor 1214), the input terminal of logic element 1206, and one of the pairs of electrodes of capacitor 1207 are electrically connected to each other. Here, the connection portion is referred to as node M1. The other input of one of the pairs of electrodes of capacitor 1207 can be fixed at a potential. For example, a low power supply potential (GND, etc.) or a high power supply potential (VDD, etc.) can be input. The other input of the pair of electrodes of capacitor 1207 is electrically connected to a wiring capable of supplying a low power supply potential (e.g., a GND line). The other input of the other of the pairs of electrodes of capacitor 1208 can be fixed at a potential. For example, a low power supply potential (GND, etc.) or a high power supply potential (VDD, etc.) can be input. The other input of the pair of electrodes of capacitor 1208 is electrically connected to a wiring capable of supplying a low power supply potential (e.g., a GND line).

[0541] When actively utilizing the parasitic capacitance of transistors or wiring, capacitors 1207 and 1208 may not be required.

[0542] The control signal WE is input to the first gate (first gate electrode) of transistor 1209. The conduction or non-conducting state between the first and second terminals of switches 1203 and 1204 is selected by a control signal RD, which is different from the control signal WE. When the first and second terminals of one switch are in a conduction state, the first and second terminals of the other switch are in a non-conducting state.

[0543] Figure 37 The transistor 1209 shown has a structure including a second gate (second gate electrode: back gate). A control signal WE can be input to the first gate and a control signal WE2 can be input to the second gate. The control signal WE2 can be a signal with a fixed potential. This fixed potential could be, for example, ground potential GND or a potential lower than the source potential of transistor 1209. In this case, the control signal WE2 is a signal with a potential used to control the threshold voltage of transistor 1209, and can further reduce the current when the gate voltage VG of transistor 1209 is 0V. The control signal WE2 can also be a signal with the same potential as the control signal WE. Alternatively, transistor 1209 can also be a transistor without a second gate.

[0544] The signal corresponding to the data held in circuit 1201 is input to another of the source and drain of transistor 1209. Figure 36 This illustrates an example where a signal output from circuit 1201 is input to the other of the source and drain of transistor 1209. Logic element 1206 inverts the logic value of the signal output from the second terminal of switch 1203 (the other of the source and drain of transistor 1213) to create an inverted signal, which is then input to circuit 1201 via circuit 1220.

[0545] In addition, although Figure 37 An example is shown where a signal output from the second terminal of switch 1203 (the other of the source and drain of transistor 1213) is input to circuit 1201 via logic element 1206 and circuit 1220, but this is not a limitation. Alternatively, the signal output from the second terminal of switch 1203 (the other of the source and drain of transistor 1213) can be input to circuit 1201 without inverting its logic value. For example, when there is a node in circuit 1201 containing a signal that inverts the logic value of a signal input from an input terminal, the signal output from the second terminal of switch 1203 (the other of the source and drain of transistor 1213) can be input to that node.

[0546] exist Figure 37Of the transistors shown for the storage element 1200, transistors other than transistor 1209 may use transistors whose channels are formed in a layer of semiconductor material other than oxide semiconductor or in the substrate 1190. For example, transistors whose channels are formed in a silicon layer or a silicon substrate may be used. Alternatively, all transistors for the storage element 1200 may use transistors whose channels are formed in an oxide semiconductor layer. Or, the storage element 1200 may also include transistors other than transistor 1209 whose channels are formed in an oxide semiconductor layer, and the remaining transistors may use transistors whose channels are formed in a layer of semiconductor material other than oxide semiconductor or in the substrate 1190.

[0547] Figure 37 The circuit 1201 shown can be, for example, a flip-flop circuit. Alternatively, the logic element 1206 can be, for example, an inverter or a clock inverter.

[0548] In a semiconductor device according to one aspect of the present invention, data stored in circuit 1201 can be retained by capacitor 1208 disposed in circuit 1202 during periods when no power supply voltage is supplied to storage element 1200.

[0549] Furthermore, the off-state current of the transistor whose channel is formed in an oxide semiconductor layer is extremely small. For example, the off-state current of the transistor whose channel is formed in an oxide semiconductor layer is much smaller than that of the transistor whose channel is formed in crystalline silicon. Therefore, by using this transistor as transistor 1209, the signal held by capacitor 1208 can be maintained for a long period of time, even when no power supply voltage is supplied to storage element 1200. Therefore, storage element 1200 can retain its stored contents (data) even when the power supply voltage is stopped.

[0550] In addition, since the storage element is characterized by pre-charging operation by setting switches 1203 and 1204, it can shorten the time until the circuit 1201 retains the original data after the power supply voltage is restarted.

[0551] Furthermore, in circuit 1202, the signal held by capacitor 1208 is input to the gate of transistor 1210. Therefore, after the power supply voltage to the storage element 1200 is resumed, the signal held by capacitor 1208 can be converted into the state of transistor 1210 (on or off state) and read out from circuit 1202. Thus, even if there are some changes in the potential corresponding to the signal held in capacitor 1208, the original signal can be read accurately.

[0552] By using this storage element 1200 in storage devices such as registers or cache memories in the processor, data in the storage device can be prevented from being lost due to a interruption of the power supply voltage. Furthermore, the storage device can be restored to its state before the power supply was interrupted within a short period after the power supply voltage is resumed. Therefore, power can be interrupted for a short time in the entire processor or one or more logic circuits constituting the processor, thereby suppressing power consumption.

[0553] In this embodiment, although the example of using the storage element 1200 for a CPU is described, the storage element 1200 can also be applied to LSIs such as DSP (Digital Signal Processor), custom LSIs, PLDs (Programmable Logic Devices), and RF (Radio Frequency) tags.

[0554] This embodiment can be appropriately combined with other embodiments and examples shown in this specification.

[0555] Implementation Method 7

[0556] In this embodiment, an example of the structure of a display device using a transistor according to one aspect of the present invention will be described.

[0557] <Example of circuit structure for a display device>

[0558] Figure 38A This is a top view of a display device according to one aspect of the present invention. Figure 38B This is a circuit diagram illustrating a pixel circuit that can be used when a liquid crystal element is used as a pixel in a display device according to one aspect of the present invention. Additionally, Figure 38C This is a circuit diagram illustrating a pixel circuit that can be used when organic EL elements are used in the pixels of a display device according to one aspect of the present invention.

[0559] Transistors disposed in the pixel section can be formed according to Embodiments 1 to 3. Furthermore, since these transistors are easily formed as n-channel transistors, a portion of the drive circuit, which can be composed of n-channel transistors, is formed on the same substrate as the transistors in the pixel section. As described above, by using the transistors shown in the above embodiments in the pixel section or drive circuit, a highly reliable display device can be provided.

[0560] Figure 38AAn example of a top view of an active matrix display device is shown. The substrate 700 of the display device includes: a pixel section 701; a first scan line driving circuit 702; a second scan line driving circuit 703; and a signal line driving circuit 704. The pixel section 701 is provided with a plurality of signal lines extending from the signal line driving circuit 704 and a plurality of scan lines extending from the first scan line driving circuit 702 and the second scan line driving circuit 703. Furthermore, pixels, each having a display element, are arranged in a matrix at the intersection regions of the scan lines and signal lines. Additionally, the substrate 700 of the display device is connected to a timing control circuit (also called a controller or control IC) via a connection portion such as an FPC (Flexible Printed Circuit).

[0561] exist Figure 38A In this design, a first scan line driving circuit 702, a second scan line driving circuit 703, and a signal line driving circuit 704 are formed on the same substrate 700 as the pixel unit 701. This reduces the number of externally located components such as driving circuits, thereby lowering costs. Furthermore, when driving circuits are located outside the substrate 700, wiring needs to be extended, and the number of connections between wirings increases. When driving circuits are located on the substrate 700, the number of connections between wirings can be reduced, thereby improving reliability or yield. Alternatively, a structure can be used where any one of the first scan line driving circuit 702, the second scan line driving circuit 703, and the signal line driving circuit 704 is mounted on the substrate 700, or a structure where they are located outside the substrate 700.

[0562] Liquid crystal display device

[0563] in addition, Figure 38B An example of a pixel circuit structure is shown. Here, as an example, a pixel circuit that can be used in a VA-type liquid crystal display device is shown.

[0564] This pixel circuit can be applied to a structure where a pixel has multiple pixel electrode layers. Each pixel electrode layer is connected to a different transistor, allowing each transistor to be driven by a different gate signal. Therefore, the signals applied to each pixel electrode layer in a multi-domain pixel can be controlled independently.

[0565] The scan line 712 of transistor 716 and the scan line 713 of transistor 717 are separated from each other so that different gate signals can be provided. On the other hand, transistors 716 and 717 share signal line 714. The transistors shown in Embodiments 1 to 3 can be used as transistors 716 and 717. This provides a highly reliable liquid crystal display device.

[0566] Additionally, transistor 716 is electrically connected to the first pixel electrode, and transistor 717 is electrically connected to the second pixel electrode. The first pixel electrode and the second pixel electrode are separate. Note that there are no particular restrictions on the shape of the first pixel electrode and the second pixel electrode. For example, the first pixel electrode can be V-shaped.

[0567] The gate electrode of transistor 716 is connected to scan line 712, while the gate electrode of transistor 717 is connected to scan line 713. By applying different gate signals to scan line 712 and scan line 713, the operating timing of transistors 716 and 717 can be made different to control the liquid crystal alignment.

[0568] Alternatively, a storage capacitor can be formed from capacitor wiring 710, a gate insulating layer used as a dielectric, and capacitor electrodes electrically connected to the first pixel electrode layer or the second pixel electrode layer.

[0569] In a multi-domain design, a first liquid crystal element 718 and a second liquid crystal element 719 are disposed in a pixel. The first liquid crystal element 718 is composed of a first pixel electrode layer, a counter electrode layer and a liquid crystal layer therebetween, while the second liquid crystal element 719 is composed of a second pixel electrode layer, a counter electrode layer and a liquid crystal layer therebetween.

[0570] also, Figure 38B The pixel circuit shown is not limited to this. For example, it can also be used in... Figure 38B Add switches, resistors, capacitors, transistors, sensors, or logic circuits to the pixel circuit shown.

[0571] Organic EL Display Device

[0572] Figure 38C Other examples of pixel circuitry are shown. Here, the pixel structure of a display device using organic EL elements is shown.

[0573] In organic light-emitting diodes (EL) devices, an electric current is generated by applying a voltage to the light-emitting element, which allows electrons and holes to be injected from a pair of electrodes into a layer containing a luminescent organic compound. The luminescent organic compound then reaches an excited state by recombination of the electrons and holes, and emits light when this excited state returns to its ground state. Based on this mechanism, the light-emitting element is called a current-excited light-emitting element (LEE).

[0574] Figure 38C This diagram illustrates an example of a pixel circuit that can be applied. An example using two n-channel transistors in a single pixel is shown here. Furthermore, this pixel circuit can employ digital temporal grayscale driving.

[0575] The following describes the structure of the applicable pixel circuits and the operation of pixels when using digital time grayscale driving.

[0576] Pixel 720 includes a switching transistor 721, a driving transistor 722, a light-emitting element 724, and a capacitor 723. In the switching transistor 721, the gate electrode layer is connected to the scan line 726, the first electrode (one of the source electrode layer and drain electrode layer) is connected to the signal line 725, and the second electrode (the other of the source electrode layer and drain electrode layer) is connected to the gate electrode layer of the driving transistor 722. In the driving transistor 722, the gate electrode layer is connected to the power line 727 via the capacitor 723, the first electrode is connected to the power line 727, and the second electrode is connected to the first electrode (pixel electrode) of the light-emitting element 724. The second electrode of the light-emitting element 724 corresponds to a common electrode 728. The common electrode 728 is electrically connected to a common potential line formed on the same substrate.

[0577] The transistors described in Embodiments 1 to 3 can be appropriately used as the switching transistor 721 and the driving transistor 722. This provides a highly reliable organic EL display device.

[0578] The potential of the second electrode (common electrode 728) of the light-emitting element 724 is set to a low power supply potential. Note that a low power supply potential refers to a potential lower than the high power supply potential supplied to the power line 727, such as GND, 0V, etc. The high and low power supply potentials are set above the positive threshold voltage of the light-emitting element 724, and the potential difference is applied to the light-emitting element 724 to allow current to flow through it, thereby causing the light-emitting element 724 to emit light. The positive voltage of the light-emitting element 724 is the voltage required to achieve the desired brightness, and at least includes the positive threshold voltage.

[0579] Alternatively, the gate capacitor of the driving transistor 722 can be used instead of the capacitor 723, thus omitting the capacitor 723.

[0580] Next, the signals input to the driving transistor 722 will be explained. When using a voltage input voltage drive mode, a video signal is input to the driving transistor 722 in two states: either fully on or fully off. To ensure the driving transistor 722 operates in the linear region, a voltage higher than the voltage of the power supply line 727 is applied to the gate electrode layer of the driving transistor 722. Additionally, a voltage greater than or equal to the sum of the power supply line voltage and the threshold voltage Vth of the driving transistor 722 is applied to the signal line 725.

[0581] When performing analog grayscale driving, a voltage greater than or equal to the sum of the forward voltage of the light-emitting element 724 and the threshold voltage Vth of the driving transistor 722 is applied to the gate electrode layer of the driving transistor 722. Additionally, a video signal that causes the driving transistor 722 to operate in the saturation region is input, causing current to flow through the light-emitting element 724. To ensure the driving transistor 722 operates in the saturation region, the potential of the power supply line 727 is set higher than the gate potential of the driving transistor 722. By employing an analog video signal, a current corresponding to the video signal can flow through the light-emitting element 724, thus performing analog grayscale driving.

[0582] Note that the structure of pixel circuits is not limited to Figure 38C The pixel structure shown. For example, it can also be found in... Figure 38C Add switches, resistors, capacitors, sensors, transistors, or logic circuits to the pixel circuit shown.

[0583] When the transistors illustrated in the above embodiments are applied... Figures 38A-38C In the illustrated circuit, the source electrode (first electrode) and drain electrode (second electrode) are electrically connected to a low potential side and a high potential side, respectively. Furthermore, a structure capable of inputting the aforementioned potential can be adopted: the potential of the first gate electrode is controlled by a control circuit or the like, and a potential lower than that supplied to the source electrode can be supplied to the second gate electrode via wiring not shown.

[0584] For example, in this specification, the display element, the display device including the display element, the light-emitting element, and the light-emitting device including the light-emitting element can take various forms or include various elements. The display element, display device, light-emitting element, or light-emitting device may include, for example, at least one of the following: EL (electroluminescent) element (EL element containing organic and inorganic materials, organic EL element, or inorganic EL element), LED (white LED, red LED, green LED, blue LED, etc.), transistor (transistor that emits light according to current), electron emission element, liquid crystal element, electronic ink, electrophoretic element, grating light valve (GLV), plasma display panel (PDP), micro-electromechanical system (MEMS), digital micromirror device (DMD), digital micro shutter (DMS), MIRASOL (a registered trademark in Japan), IMOD (interferometry modulation) element, electrowetting element, piezoelectric ceramic display, and display element using carbon nanotubes. Additionally, it may include display media whose contrast, brightness, reflectivity, and transmittance change due to electrical or magnetic effects. As an example of a display device using an EL element, an EL display is included. Examples of display devices using electron emission elements include field emission displays (FEDs) or surface-conduction electron-emitter displays (SEDs). Examples of display devices using liquid crystal elements include liquid crystal displays (transmissive liquid crystal displays, transflective liquid crystal displays, reflective liquid crystal displays, intuitive liquid crystal displays, and projective liquid crystal displays). Examples of display devices using electronic ink or electrophoretic elements include electronic paper.

[0585] Note that this implementation method can be appropriately combined with other implementation methods and examples shown in this specification.

[0586] Implementation Method 8

[0587] In this embodiment, refer to Figures 29A to 29D This describes a display module using a semiconductor device according to one aspect of the present invention.

[0588] <Display Module>

[0589] exist Figure 39 In the display module 6000 shown, a touch panel 6004 connected to FPC 6003, a display panel 6006 connected to FPC 6005, a backlight unit 6007, a frame 6009, a printed circuit board 6010, and a battery 6011 are disposed between the upper cover 6001 and the lower cover 6002. Note that sometimes the backlight unit 6007, battery 6011, touch panel 6004, etc., are not provided.

[0590] The semiconductor device of one aspect of the present invention can be used, for example, in a display panel 6006 or an integrated circuit mounted on a printed circuit board.

[0591] The shape and size of the upper cover 6001 and the lower cover 6002 can be appropriately changed according to the size of the touch panel 6004 and the display panel 6006.

[0592] The touch panel 6004 can be a resistive or capacitive touch panel and can overlap with the display panel 6006. The opposing substrate (sealed substrate) of the display panel 6006 can have touch panel functionality. Alternatively, a light sensor can be provided within each pixel of the display panel 6006, adding optical touch panel functionality to the display panel 6006. Alternatively, touch sensor electrodes can be provided within each pixel of the display panel 6006, adding capacitive touch panel functionality to the display panel 6006.

[0593] The backlight unit 6007 includes a light source 6008. The light source 6008 can be disposed at the end of the backlight unit 6007, and a light diffusion plate can be used.

[0594] In addition to protecting the display panel 6006, the frame 6009 also functions as an electromagnetic shield, blocking electromagnetic waves generated from the printed circuit board 6010. The frame 6009 can also function as a heat sink.

[0595] The printed circuit board 6010 includes a power supply circuit and signal processing circuitry for outputting video and clock signals. An external commercial power supply or a separately supplied battery 6011 can be used to power the power supply circuit. When using a commercial power supply, the battery 6011 can be omitted.

[0596] The display module 6000 may be additionally equipped with components such as polarizers, phase difference plates, prism sheets, etc.

[0597] Note that this implementation method can be appropriately combined with other implementation methods and examples shown in this specification.

[0598] Implementation Method 9

[0599] In this embodiment, an example of the use of a semiconductor device according to one aspect of the present invention will be described.

[0600] <Packaging using leadframe type through-hole board>

[0601] Figure 40A This is a perspective view showing the cross-sectional structure of a package using a leadframe type interposer. Figure 40AIn the package shown, a chip 1751, corresponding to a semiconductor device according to one aspect of the invention, is legally connected to terminals 1752 on a connector plate 1750 via wire bonding. Terminals 1752 are disposed on the surface of the connector plate 1750 on which the chip 1751 is located. The chip 1751 may also be sealed with molding resin 1753, wherein the sealing is performed with a portion of each terminal 1752 exposed.

[0602] Figure 40B This illustrates the structure of a module in which an electronic device (mobile phone) is packaged and mounted within a circuit substrate. Figure 40B In the module of the mobile phone shown, the printed circuit board 1801 houses the package 1802 and the battery 1804. Additionally, the panel 1800, which includes display elements, is mounted with the printed circuit board 1801 via an FPC 1803.

[0603] Note that this implementation method can be appropriately combined with other implementation methods and examples shown in this specification.

[0604] Implementation Method 10

[0605] In this embodiment, an electronic device and lighting apparatus according to one aspect of the present invention will be described with reference to the accompanying drawings.

[0606] <Electronic Devices>

[0607] Electronic devices or lighting devices can be manufactured using a semiconductor device according to one aspect of the present invention. Furthermore, highly reliable electronic devices or lighting devices can be manufactured using a semiconductor device according to one aspect of the present invention. Additionally, electronic devices or lighting devices with improved touch sensor detection sensitivity can be manufactured using a semiconductor device according to one aspect of the present invention.

[0608] Examples of electronic devices include: television sets (also known as televisions or television receivers); displays for computers, etc.; cameras such as digital cameras and digital camcorders; digital photo frames; mobile phones (also known as mobile phones or mobile phone devices); portable game consoles; portable information terminals; sound reproduction devices; and large game machines such as pinball machines.

[0609] Furthermore, in cases where the electronic device or lighting device of one aspect of the present invention is flexible, the electronic device or lighting device may also be assembled along the curved surface of the inner or outer wall of a house or high-rise building, or the interior or exterior decoration of a car.

[0610] Furthermore, an electronic device according to one aspect of the present invention may also include a secondary battery, which is preferably charged by contactless power transmission.

[0611] Examples of secondary batteries include lithium-ion secondary batteries such as lithium polymer batteries (lithium-ion polymer batteries) that utilize gel-like electrolytes, lithium-ion batteries, nickel-metal hydride batteries, nickel-cadmium batteries, organic free radical batteries, lead-acid batteries, air secondary batteries, nickel-zinc batteries, and silver-zinc batteries.

[0612] An electronic device according to one aspect of the present invention may also include an antenna. By receiving signals through the antenna, images or information can be displayed on a display unit. Furthermore, in the case where the electronic device includes a secondary battery, the antenna can be used for contactless power transmission.

[0613] Figure 41A A portable game console is shown, comprising a housing 7101, a housing 7102, a display unit 7103, a display unit 7104, a microphone 7105, a speaker 7106, operation keys 7107, and a stylus 7108, etc. A semiconductor device according to one aspect of the present invention can be used in integrated circuits, CPUs, etc., built into the housing 7101. By using a light-emitting device according to one aspect of the present invention on the display unit 7103 or the display unit 7104, a user-friendly portable game console less prone to quality issues can be provided. Note that although... Figure 41A The portable game console shown includes two display units, namely display unit 7103 and display unit 7104, but the number of display units included in the portable game console is not limited to two.

[0614] Figure 41B A smartwatch is shown, including a frame 7302, a display 7304, operation buttons 7311 and 7312, a connection terminal 7313, a wristband 7321, a strap buckle 7322, etc. A semiconductor device according to one aspect of the present invention can be used for a memory, CPU, etc., built into the frame 7302.

[0615] Figure 41C A portable information terminal is shown, including a display unit 7502, operation buttons 7503, an external connection port 7504, a speaker 7505, a microphone 7506, etc., installed in a housing 7501. The semiconductor device of one aspect of the present invention can be used in mobile memory, CPU, etc., built into the housing 7501. Because the display unit 7502 can achieve very high resolution, although the display unit 7502 is small to medium-sized, it can perform various displays such as 4K or 8K, and obtain very clear images.

[0616] Figure 41DA camera is shown, including a first frame 7701, a second frame 7702, a display unit 7703, operation keys 7704, a lens 7705, and a connecting part 7706. The operation keys 7704 and the lens 7705 are disposed in the first frame 7701, and the display unit 7703 is disposed in the second frame 7702. The first frame 7701 and the second frame 7702 are connected by the connecting part 7706, and the angle between the first frame 7701 and the second frame 7702 can be changed by the connecting part 7706. The image displayed on the display unit 7703 can also be switched according to the angle between the first frame 7701 and the second frame 7702 formed by the connecting part 7706. The imaging device of one aspect of the present invention can be positioned at the focal point of the lens 7705. The semiconductor device of one aspect of the present invention can be used in integrated circuits, CPUs, etc., built into the first frame 7701.

[0617] Figure 41E A digital signboard is shown, which includes a display unit 7902 mounted on a utility pole 7901. A display device according to one aspect of the present invention can be used in the control circuit of the display unit 7902.

[0618] Figure 42A A notebook computer is shown, comprising a chassis 8121, a display unit 8122, a keyboard 8123, and a pointing device 8124, etc. A semiconductor device according to one aspect of the present invention can be used in a CPU, memory, etc., built into the chassis 8121. Because the display unit 8122 can achieve very high resolution, although the display unit 8122 is small to medium-sized, it can perform 8K display and obtain very clear images.

[0619] Figure 42B Showing the exterior of the car 9700. Figure 42C The image shows the driver's seat of a car 9700. The car 9700 includes a body 9701, wheels 9702, an instrument panel 9703, lights 9704, etc. A semiconductor device according to one aspect of the present invention can be used in the display section and control integrated circuit of the car 9700. For example, it can be used... Figure 42C A semiconductor device according to one aspect of the present invention is provided in the display units 9710 to 9715 shown.

[0620] Display units 9710 and 9711 are display devices or input / output devices installed on the windshield of an automobile. By using a conductive material with light transmittance to manufacture the electrodes in the display device or input / output device, the display device or input / output device of one aspect of the present invention can be made into a so-called transparent display device or input / output device that allows visibility to the other side. The transparent display device or input / output device will not obstruct the view even when driving the automobile 9700. Therefore, the display device or input / output device of one aspect of the present invention can be installed on the windshield of the automobile 9700. In addition, when transistors or the like used to drive the display device or input / output device are provided in the display device or input / output device, it is preferable to use transparent transistors such as organic transistors using organic semiconductor materials or transistors using oxide semiconductor materials.

[0621] Display unit 9712 is a display device installed on the pillar. For example, by displaying an image from an imaging unit installed on the vehicle body on display unit 9712, the field of vision obstructed by the pillar can be supplemented. Display unit 9713 is a display device installed on the dashboard. For example, by displaying an image from an imaging unit installed on the vehicle body on display unit 9713, the field of vision obstructed by the dashboard can be supplemented. In other words, by displaying an image from an imaging unit installed on the exterior of the vehicle, blind spots can be filled, thereby improving safety. In addition, by displaying images that supplement areas that cannot be seen, safety can be confirmed more naturally and comfortably.

[0622] Figure 42D The illustration shows a car interior with a bench seat serving as both the driver's and passenger's seats. Display unit 9721 is a display device or input / output device installed in the door section. For example, by displaying images from an imaging unit installed in the vehicle body on display unit 9721, the view obstructed by the door can be supplemented. Display unit 9722 is a display device installed on the steering wheel. Display unit 9723 is a display device installed in the center of the bench seat. Furthermore, by installing the display device on the seat surface or backrest, it can also be used as a seat heater with the display device as its heat source.

[0623] Display units 9714, 9715, or 9722 can provide navigation information, speedometer, tachometer, driving distance, fuel level, gear position, air conditioning settings, and other various information. Furthermore, the user can appropriately change the displayed content and layout. Display units 9710 to 9713, 9721, and 9723 can also display the aforementioned information. Display units 9710 to 9715, 9721 to 9723 can also be used as lighting devices. Additionally, display units 9710 to 9715, 9721 to 9723 can also be used as heating devices.

[0624] in addition, Figure 43A The appearance of the camera 8000 is shown. The camera 8000 includes a frame 8001, a display unit 8002, operation buttons 8003, a shutter button 8004, and a connecting part 8005, etc. In addition, the camera 8000 may also be equipped with a lens 8006.

[0625] The connector 8005 includes electrodes and can be connected to a flash unit or the like, in addition to the viewfinder 8100 described later.

[0626] This camera 8000 includes a structure that allows the lens 8006 to be detached from the frame 8001 and exchanged, and the lens 8006 and the frame can also be formed as one unit.

[0627] Video recording can be performed by pressing the shutter button 8004. Alternatively, the display unit 8002 is used as a touchscreen, allowing video recording also to be performed by touching the display unit 8002.

[0628] A display device or input / output device according to one aspect of the present invention can be applied to the display unit 8002.

[0629] Figure 43B An example is shown where the camera 8000 is equipped with a viewfinder 8100.

[0630] The viewfinder 8100 includes a frame 8101, a display 8102, and buttons 8103, etc.

[0631] The frame 8101 includes a connecting portion 8005 that fits into the camera 8000, allowing the viewfinder 8100 to be mounted onto the camera 8000. Additionally, this connecting portion includes electrodes that can display images received from the camera 8000 via these electrodes on the display unit 8102.

[0632] Button 8103 is used as a power button. By using button 8103, the display unit 8102 can be switched between displaying and not displaying.

[0633] A semiconductor device according to one aspect of the present invention can be applied to integrated circuits and image sensors in the housing 8101.

[0634] In addition, Figure 43A and Figure 43B In this invention, the camera 8000 and the viewfinder 8100 are separate and detachable electronic devices, but the viewfinder, which has a display device or input / output device according to one aspect of the present invention, can also be built into the frame 8001 of the camera 8000.

[0635] Figure 43C This shows the appearance of the head-mounted display 8200.

[0636] The head-mounted display 8200 includes a mounting section 8201, a lens 8202, a main body 8203, a display section 8204, and a cable 8205. Additionally, a battery 8206 is built into the mounting section 8201.

[0637] Power is supplied from battery 8206 to main body 8203 via cable 8205. Main body 8203 is equipped with a wireless receiver and can display image information such as received image data on display unit 8204. In addition, by using a camera installed in main body 8203 to capture the user's eyeballs and eyelid movements, and calculating the coordinates of the user's viewpoint based on this information, the user's viewpoint can be used as an input method.

[0638] Alternatively, multiple electrodes can be provided at the user-contacted location of the mounting section 8201. The main body 8203 can also have the function of identifying the user's gaze point by detecting the current flowing through the electrodes in response to the user's eye movements. Furthermore, the main body 8203 can have the function of monitoring the user's pulse by detecting the current flowing through the electrodes. The mounting section 8201 can have various sensors such as temperature sensors, pressure sensors, and acceleration sensors, and can also have the function of displaying the user's biometric information on the display section 8204. Additionally, the main body 8203 can detect movements of the user's head, etc., and synchronously change the image displayed on the display section 8204 in sync with the user's head movements.

[0639] A semiconductor device of one aspect of the present invention can be applied to the integrated circuit in the main body 8203.

[0640] At least a portion of this embodiment can be implemented in combination with other embodiments described in this specification.

[0641] Implementation Method 11

[0642] In this embodiment, refer to Figures 44A to 44F This section describes an example of the use of an RF tag in a semiconductor device employing one aspect of the present invention.

[0643] <Examples of the use of RF tags>

[0644] RF tags have a wide range of uses. For example, they can be set on items such as banknotes, coins, securities, bearer bonds, certificates (driver's licenses, resident cards, etc., refer to Figure 44A ), vehicles (bicycles, etc., refer to Figure 44B ), packaging containers (wrapping paper, bottles, etc., refer to Figure 44C ), recording media (DVDs, videotapes, etc.), personal items (bags, glasses, etc., refer to Figure 44D ), food items, plants, animals, the human body, clothing items, daily necessities, medical products including drugs or pharmaceuticals, electronic devices (liquid crystal display devices, EL display devices, television devices or mobile phones), etc. or shipping labels for each item (refer to Figure 44E and Figure 44F ), etc.

[0645] The RF tag 4000 of one embodiment of the present invention is fixed in a manner of being attached to the surface of an item or embedded in the item. For example, when the item is a book, the RF tag 4000 is fixed in the book by being embedded in the paper of the book, and when the item is a packaging of an organic resin, the RF tag 4000 is fixed in the packaging of the organic resin by being embedded in the organic resin. The RF tag 4000 of one embodiment of the present invention is small, thin and lightweight, so it does not affect the design of the item even when fixed in the item. In addition, by setting the RF tag 4000 of one embodiment of the present invention on banknotes, coins, securities, bearer bonds or certificates, etc., an identification function can be given. By utilizing this identification function, forgery can be prevented. In addition, by setting the RF tag 4000 of one embodiment of the present invention in packaging containers, recording media, personal items, food items, clothing items, daily necessities or electronic devices, etc., the operating efficiency of systems such as inspection systems can be improved. In addition, by installing the RF tag 4000 of one embodiment of the present invention in vehicles, theft can be prevented and the safety can be improved.

[0646] As described above, by applying the RF tag using the semiconductor device of one embodiment of the present invention to each of the uses listed in this embodiment, the power consumption including operations such as data writing or reading can be reduced, and thus the maximum communication distance can be made long. In addition, even in a state where power is not supplied, data can be retained for an extremely long period, so the above RF tag is suitable for uses with a low frequency of writing or reading.

[0647] Note that this embodiment can be appropriately combined with other embodiments and examples shown in this specification.

[0648] Symbol description

[0649] 10 transistors

[0650] 11 transistors

[0651] 12 transistors

[0652] 13 transistors

[0653] 14 transistors

[0654] 63 Semiconductor layer

[0655] 64 Semiconductor Layer

[0656] 65 Semiconductor layer

[0657] 100 substrate

[0658] 110 Insulation Layer

[0659] 120 Oxide Semiconductor Layer

[0660] 121 Oxide Semiconductor Layer

[0661] 122 Oxide Semiconductor Layer

[0662] 123 Oxide semiconductor layer

[0663] 123a Oxide Semiconductor Film

[0664] 124 Oxide Semiconductor Layer

[0665] 130 source electrode layer

[0666] 130b conductive layer

[0667] 131 Source electrode layer

[0668] 132 Source Electrode Layer

[0669] 135 conductive layer

[0670] 140 Drain electrode layer

[0671] 141 Drain electrode layer

[0672] 142 Drain electrode layer

[0673] 150 gate insulating layer

[0674] 150a insulating film

[0675] 160 gate electrode layer

[0676] 160a conductive film

[0677] 161 Gate electrode layer

[0678] 162 gate electrode layer

[0679] 163 Gate electrode layer

[0680] 165 conductive layer

[0681] 166 conductive layer

[0682] 167 Conductive Layer

[0683] 170 hybrid layer

[0684] 171 Oxygen

[0685] Area 172

[0686] 174 Groove

[0687] 175 Insulation Layer

[0688] 175b Insulation Layer

[0689] 176 Resist Mask

[0690] 177 Insulation layer

[0691] 180 insulation layer

[0692] 185 Insulation Layer

[0693] 190 conductive layer

[0694] 191 Conductive layer

[0695] 192 Conductive layer

[0696] 200 camera devices

[0697] 201 switch

[0698] 202 Switch

[0699] 203 Switch

[0700] 210 pixels

[0701] 211 pixels

[0702] 212 subpixels

[0703] 212B subpixel

[0704] 212G subpixels

[0705] 212R subpixel

[0706] 220 Photoelectric Conversion Element

[0707] 230 pixel circuit

[0708] 231 Wiring

[0709] 247 Wiring

[0710] 248 Wiring

[0711] 249 Wiring

[0712] 250 wiring

[0713] 253 Wiring

[0714] 254 filter

[0715] 254B filter

[0716] 254G filter

[0717] 254R filter

[0718] 255 lens

[0719] 256 Light

[0720] 257 Wiring

[0721] 260 Peripheral Circuits

[0722] 270 Peripheral Circuit

[0723] 280 peripheral circuit

[0724] 290 Peripheral Circuit

[0725] 291 Light Source

[0726] 300 silicon substrate

[0727] 310th floor

[0728] 320 floors

[0729] 330th floor

[0730] 340th floor

[0731] 351 transistors

[0732] 352 transistors

[0733] 353 transistors

[0734] 360° photodiode

[0735] 361 Anode

[0736] 362 Cathode

[0737] 363 Low Resistance Region

[0738] 365 photodiode

[0739] 366 Semiconductor Layer

[0740] 367 Semiconductor Layer

[0741] 368 Semiconductor Layer

[0742] 370 plug

[0743] 371 Wiring

[0744] 372 Wiring

[0745] 373 Wiring

[0746] 374 Wiring

[0747] 601 Precursor

[0748] 602 Precursor

[0749] 700 substrate

[0750] 701 pixels

[0751] 702 Scan Line Drive Circuit

[0752] 703 Scan Line Drive Circuit

[0753] 704 signal line driver circuit

[0754] 710 Capacitor Wiring

[0755] 712 scan lines

[0756] 713 scan lines

[0757] 714 signal line

[0758] 716 transistors

[0759] 717 transistor

[0760] 718 Liquid Crystal Components

[0761] 719 Liquid Crystal Components

[0762] 720 pixels

[0763] 721 Switching Transistor

[0764] 722 drive transistor

[0765] 723 capacitor

[0766] 724 Light Emitting Element

[0767] 725 signal line

[0768] 726 scan lines

[0769] 727 power cord

[0770] 728 Common Electrode

[0771] 800 RF Tag

[0772] 801 Communicator

[0773] 802 antenna

[0774] 803 wireless signal

[0775] 804 antenna

[0776] 805 rectifier circuit

[0777] 806 Constant Voltage Circuit

[0778] 807 demodulation circuit

[0779] 808 modulation circuit

[0780] 809 Logic Circuits

[0781] 810 storage circuit

[0782] 811 ROM

[0783] 1189 ROM interface

[0784] 1190 substrate

[0785] 1191 ALU

[0786] 1192 ALU controller

[0787] 1193 Instruction Decoder

[0788] 1194 Interrupt Controller

[0789] 1195 timing controller

[0790] 1196 Register

[0791] 1197 Register Controller

[0792] 1198 bus interface

[0793] 1199 ROM

[0794] 1200 storage elements

[0795] 1201 Circuit

[0796] 1202 circuit

[0797] 1203 switch

[0798] 1204 switch

[0799] 1206 Logic Element

[0800] 1207 capacitor

[0801] 1208 capacitor

[0802] 1209 transistor

[0803] 1210 transistor

[0804] 1213 Transistor

[0805] 1214 transistors

[0806] 1220 circuit

[0807] 1223 Oxide Semiconductor Layer

[0808] 1700 film-forming substrate

[0809] Processing Room 1701

[0810] 1702 Loading Room

[0811] 1703 Pre-treatment Room

[0812] Processing Room 1704

[0813] Processing Room 1705

[0814] 1706 Unloading Room

[0815] 1711a Raw Material Supply Department

[0816] 1711b Raw Material Supply Department

[0817] 1712a High-speed valve

[0818] 1712b High-speed valve

[0819] 1713a Raw material inlet

[0820] 1713b Raw material inlet

[0821] 1714 Raw material discharge outlet

[0822] 1715 Exhaust System

[0823] 1716 Substrate Support

[0824] 1720 Teleportation Room

[0825] 1750 plug-in board

[0826] 1751 chip

[0827] 1752 terminal

[0828] 1753 Molding Resin

[0829] 1800 panel

[0830] 1801 Printed Circuit Board

[0831] 1802 package

[0832] 1803 FPC

[0833] 1804 battery

[0834] 2100 transistors

[0835] 2200 transistors

[0836] 2201 Insulator

[0837] 2202 cabling

[0838] 2203 plug

[0839] 2204 Insulator

[0840] 2205 Wiring

[0841] 2207 Insulator

[0842] 2210 Intermediate Layer

[0843] 2211 Semiconductor substrate

[0844] 2212 Insulator

[0845] 2213 Gate electrode

[0846] 2214 Gate Insulator

[0847] 2215 Leakage Area

[0848] 3001 Wiring

[0849] 3002 wiring

[0850] 3003 wiring

[0851] 3004 wiring

[0852] 3005 wiring

[0853] 3200 transistors

[0854] 3300 transistors

[0855] 3400 capacitor

[0856] 4000 RF tags

[0857] 5100 particles

[0858] 5120 substrate

[0859] Area 5161

[0860] 6000 Display Module

[0861] 6001 Top Cover

[0862] 6002 bottom cover

[0863] 6003 FPC

[0864] 6004 Touch Panel

[0865] 6005 FPC

[0866] 6006 Display Panel

[0867] 6007 Backlight Unit

[0868] 6008 Light Source

[0869] 6009 Framework

[0870] 6010 Printed Circuit Board

[0871] 6011 battery

[0872] 7101 frame

[0873] 7102 Frame

[0874] 7103 Display Section

[0875] 7104 Display Section

[0876] 7105 Microphone

[0877] 7106 speaker

[0878] 7107 Operation Keys

[0879] 7108 Stylus

[0880] 7302 frame

[0881] 7304 Display Section

[0882] 7311 Operation Button

[0883] 7312 Operation Button

[0884] 7313 Connecting Terminal

[0885] 7321 Wristband

[0886] 7322 gold

[0887] 7501 frame

[0888] 7502 Display Section

[0889] 7503 Operation Button

[0890] 7504 External Connection Port

[0891] 7505 speaker

[0892] 7506 Microphone

[0893] 7701 frame

[0894] 7702 frame

[0895] 7703 Display Section

[0896] 7704 Operation Keys

[0897] 7705 Lens

[0898] 7706 Connecting Part

[0899] 7901 utility pole

[0900] 7902 Display Section

[0901] 8000 camera

[0902] 8001 frame

[0903] 8002 Display Section

[0904] 8003 Operation Button

[0905] 8004 shutter button

[0906] 8005 Connecting Part

[0907] 8006 lens

[0908] 8100 Viewfinder

[0909] 8101 frame

[0910] 8102 Display Section

[0911] 8103 button

[0912] 8121 frame

[0913] 8122 Display Section

[0914] 8123 Keyboard

[0915] 8124 Pointing Device

[0916] 8200 Head-Mounted Display

[0917] 8201 Installation Department

[0918] 8202 Lens

[0919] 8203 Main Body

[0920] 8204 Display Section

[0921] 8205 cable

[0922] 8206 battery

[0923] 9700 car

[0924] 9701 vehicle body

[0925] 9702 Wheel

[0926] 9703 Dashboard

[0927] 9704 lamp

[0928] 9710 Display Section

[0929] 9711 Display Section

[0930] 9712 Display Section

[0931] 9713 Display Section

[0932] 9714 Display Unit

[0933] 9715 Display Section

[0934] 9721 Display Section

[0935] 9722 Display Unit

[0936] 9723 Display Department

Claims

1. A semiconductor device, comprising: First oxide semiconductor layer; The source electrode layer and drain electrode layer are located on the first oxide semiconductor layer; An insulating layer that contacts the top surface of the source electrode layer, the top surface of the drain electrode layer, and the side surface of the first oxide semiconductor layer; A second oxide semiconductor layer located on the insulating layer and in contact with the side surfaces of the source electrode layer and the drain electrode layer; A gate electrode layer located on the first oxide semiconductor layer, separated by the second oxide semiconductor layer; as well as The gate insulating layer located between the second oxide semiconductor layer and the gate electrode layer, The first oxide semiconductor layer has a first region in contact with the source electrode layer, a second region in contact with the drain electrode layer, and a third region located between the first region and the second region and in contact with the second oxide semiconductor layer. The thickness of the third region is less than the thickness of the first region and the thickness of the second region.

2. A semiconductor device, comprising: First oxide semiconductor layer; The source electrode layer and drain electrode layer are located on the first oxide semiconductor layer; An insulating layer that contacts the top surface of the source electrode layer, the top surface of the drain electrode layer, and the side surface of the first oxide semiconductor layer; A second oxide semiconductor layer located on the insulating layer and in contact with the side surfaces of the source electrode layer and the drain electrode layer; A gate electrode layer located on the first oxide semiconductor layer, separated by the second oxide semiconductor layer; as well as The second insulating layer is located between the second oxide semiconductor layer and the gate electrode layer. The first oxide semiconductor layer has a first region in contact with the source electrode layer, a second region in contact with the drain electrode layer, and a third region located between the first region and the second region and in contact with the second oxide semiconductor layer. The thickness of the third region is less than the thickness of the first region and the thickness of the second region.

3. A semiconductor device, comprising: First oxide semiconductor layer; Electrically connected to the source electrode layer and drain electrode layer of the first oxide semiconductor layer; An insulating layer that is in contact with the first surface of the source electrode layer, the first surface of the drain electrode layer, and the first surface of the first oxide semiconductor layer; as well as A second oxide semiconductor layer that overlaps with the insulating layer and contacts the second surface of the source electrode layer and the second surface of the drain electrode layer. The first oxide semiconductor layer has a first region in contact with the source electrode layer, a second region in contact with the drain electrode layer, and a third region located between the first region and the second region and in contact with the second oxide semiconductor layer.

4. A semiconductor device, comprising: First oxide semiconductor layer; The source electrode layer and drain electrode layer are located on the first oxide semiconductor layer; A first insulating layer that contacts the top surface of the source electrode layer, the top surface of the drain electrode layer, and the side surface of the first oxide semiconductor layer; A second insulating layer having a groove and located on the first insulating layer; A second oxide semiconductor layer that contacts the inner surface of the trench and the side surfaces of the source electrode layer and the drain electrode layer; A gate electrode layer, which is located in the trench and is situated on the first oxide semiconductor layer with the second oxide semiconductor layer in between; as well as The gate insulating layer located between the second oxide semiconductor layer and the gate electrode layer, The first oxide semiconductor layer has a first region in contact with the source electrode layer, a second region in contact with the drain electrode layer, and a third region located between the first region and the second region and in contact with the second oxide semiconductor layer. The thickness of the third region is less than the thickness of the first region and the thickness of the second region.

5. A semiconductor device, comprising: First oxide semiconductor layer; The source electrode layer and drain electrode layer are located on the first oxide semiconductor layer; A first insulating layer that contacts the top surface of the source electrode layer, the top surface of the drain electrode layer, and the side surface of the first oxide semiconductor layer; A second insulating layer having a groove and located on the first insulating layer; A second oxide semiconductor layer located in the trench and in contact with the side surfaces of the source electrode layer and the drain electrode layer; A gate electrode layer, which is located in the trench and is situated on the first oxide semiconductor layer with the second oxide semiconductor layer in between; as well as The gate insulation layer located in the groove, The first oxide semiconductor layer has a first region in contact with the source electrode layer, a second region in contact with the drain electrode layer, and a third region located between the first region and the second region and in contact with the second oxide semiconductor layer. The thickness of the third region is less than the thickness of the first region and the thickness of the second region.

6. The semiconductor device according to any one of claims 1 to 5, further comprising an insulator located beneath the first oxide semiconductor layer.

7. The semiconductor device of claim 6, wherein the insulator includes a protrusion overlapping the first oxide semiconductor layer.

8. A method for manufacturing a semiconductor device, comprising the following steps: Forming a first oxide semiconductor film; A first heat treatment is performed after the formation of the first oxide semiconductor film; A first conductive film is formed on the first oxide semiconductor film; The first oxide semiconductor film is selectively etched using a first mask and the first conductive film to form a first oxide semiconductor layer with an island-like shape; A first insulating film and a second insulating film are formed on the first conductive film; Grooves are formed in the first insulating film, the second insulating film, and the first conductive film; as well as A second oxide semiconductor film is formed in the groove.

9. A method for manufacturing a semiconductor device, comprising the following steps: Forming a first oxide semiconductor layer; A source electrode layer and a drain electrode layer are formed on the first oxide semiconductor layer; An insulating layer is formed that contacts the top surface of the source electrode layer, the top surface of the drain electrode layer, and the side surface of the first oxide semiconductor layer; A second oxide semiconductor layer is formed on the insulating layer, and the second oxide semiconductor layer is in contact with the side surface of the source electrode layer and the side surface of the drain electrode layer; A gate electrode layer is formed on the first oxide semiconductor layer, with the second oxide semiconductor layer in between; as well as A gate insulating layer is formed between the second oxide semiconductor layer and the gate electrode layer. The first oxide semiconductor layer has a first region in contact with the source electrode layer, a second region in contact with the drain electrode layer, and a third region located between the first region and the second region and in contact with the second oxide semiconductor layer. The thickness of the third region is less than the thickness of the first region and the thickness of the second region.

10. A method for manufacturing a semiconductor device, comprising the following steps: Forming a first oxide semiconductor layer; A source electrode layer and a drain electrode layer are formed on the first oxide semiconductor layer; A first insulating layer is formed that contacts the top surface of the source electrode layer, the top surface of the drain electrode layer, and the side surface of the first oxide semiconductor layer; A second insulating layer is formed on the first insulating layer; A groove is formed in the second insulating layer; A second oxide semiconductor layer is formed in the trench, and the second oxide semiconductor layer is in contact with the side surface of the source electrode layer and the side surface of the drain electrode layer; A gate electrode layer is formed in the trench, and the gate electrode layer is located on the first oxide semiconductor layer with the second oxide semiconductor layer in between; as well as A gate insulating layer is formed in the groove.

Images