A circuit for generating a pulse signal and a method for generating a pulse signal

Abstract

The present invention relates to the field of high-voltage pulse signals, and specifically to a circuit for generating pulse signals and a method for generating pulse signals. The circuit includes a first switch component, a second switch component and a charge-discharge capacitor connected in series, a power supply for powering the charge-discharge capacitor, and a load resistor connected in parallel with the second switch component; the first switch component and the second switch component are both controlled by a trigger signal to control the on-off state; the voltage across the load resistor is used to generate a pulse signal. The present invention connects the load resistor in parallel with the IGBT transistor, which can remove the interference of the charge on the IGBT transistor on the load resistor. Therefore, the rising edge and the falling edge of the high-voltage pulse signal generated by the charge-discharge capacitor on the load resistor in the present invention have a large steepness, which is closer to a rectangular high-voltage pulse signal, so as to be better applied to the treatment of tumors.

Description

Technical Field

[0001] The present invention relates to the field of high voltage pulse signals, and in particular to a circuit for generating pulse signals and a method for generating pulse signals. Background Art

[0002] High-voltage pulse signals are widely used in the fields of secondary ion mass spectrometry, electromagnetic pulse technology research, harmful waste gas treatment, pulse-excited plasma jet sterilization, biomedical treatment, etc. Taking the field of biomedical treatment as an example, high-voltage pulse signals act on tumor tissues through treatment probes, releasing high-voltage pulses to "break" tumor cells, and finally the cells undergo apoptosis to complete the entire process of tumor treatment. Since cell tissues can be equivalent to a series-parallel system of resistors and capacitors, the high-voltage pulse acting on cell tissues is actually a process of charging them, so the biomedical field has strict requirements on pulse steepness.

[0003] The pulse signal generated by the existing circuit for generating pulse signals has a rising edge and a falling edge that change slowly, resulting in the pulse signal not being the required rectangular pulse signal, thereby causing the generated pulse signal to reduce the therapeutic effect on tumor cells. Summary of the invention

[0004] In order to solve the above technical problems, one of the objects of the present invention is to provide a circuit for generating a pulse signal, which can increase the steepness of the rising edge and the falling edge of the generated pulse signal, so that the pulse signal is closer to a rectangular pulse signal, so that the generated pulse signal can be better applied to the treatment of tumor cells.

[0005] To achieve the above object, the present invention adopts the following technical solutions:

[0006] A circuit for generating a pulse signal, the circuit comprising a first switch component, a second switch component and a charge-discharge capacitor connected in series, a power supply for supplying power to the charge-discharge capacitor, and a load resistor connected in parallel with the second switch component;

[0007] The first switch component and the second switch component are both controlled in on and off states by a trigger signal; the voltage across the load resistor is used to generate a pulse signal.

[0008] Further, the first switch component includes a first switch unit, the first switch unit includes a first transistor, and a first protection component connected in parallel with the first transistor for preventing the first transistor from being broken down;

[0009] The second switch component comprises a second switch unit, the second switch unit comprises a second transistor, and a second protection component connected in parallel with the second transistor for preventing the second transistor from being broken down;

[0010] The first transistor, the second transistor and the charge and discharge capacitor are connected in series, and the load resistor is connected in parallel with the second transistor.

[0011] Further preferably, the electrical parameters of the first transistor are the same as the electrical parameters of the second transistor, and the electrical parameters of the first transistor and the electrical parameters of the second transistor both include withstand voltage, maximum current, turn-on voltage, input and output capacitance, turn-on and turn-off time, and the electrical parameters of the first protection component are the same as the electrical parameters of the second protection component.

[0012] Further preferably, the number of the first switch units is equal to the number of the second switch units, and each first transistor in the first switch unit and each second transistor in the second switch unit form a series circuit.

[0013] Further preferably, the first protection component includes a second resistor and a first capacitor connected in series, and a first resistor connected in parallel with the second resistor and the first capacitor; the first transistor is a first IGBT transistor, the C pole of the first IGBT transistor is connected to one end of the first resistor and one end of the second resistor, the other end of the second resistor is connected to one end of the first capacitor, the other end of the first resistor and the other end of the first capacitor are connected to the E pole of the first IGBT transistor, and the G pole of the first IGBT transistor is connected to the trigger signal trig_1;

[0014] The second protection component includes a fourth resistor and a second capacitor connected in series, and a third resistor connected in parallel with the fourth resistor and the second capacitor; the second transistor is a second IGBT transistor, the C pole of the second IGBT transistor is connected to one end of the fourth resistor and one end of the third resistor, the other end of the fourth resistor is connected to one end of the second capacitor, the other end of the third resistor and the other end of the second capacitor are both connected to the E pole of the second IGBT transistor, and the G pole of the second IGBT transistor is connected to the trigger signal trig_2;

[0015] The E pole of the first IGBT transistor is connected to the C pole of the second IGBT transistor.

[0016] Further, the circuit also includes an actual circuit, in which: the load resistor is a braking ripple resistor, and the braking ripple resistor includes a load stray inductance and a load pure resistance connected in series, and a load distributed capacitor connected in parallel with a circuit branch where the load stray inductance and the load pure resistance are located;

[0017] The circuit branch where the load stray inductance and the load pure resistance are located is also connected in parallel with the second transistor.

[0018] Further preferably, in an actual circuit: the first transistor includes a first pure IGBT tube, a first source capacitor, a first depletion layer capacitor, a first oxide layer capacitor and a first gate capacitor, the first depletion layer capacitor, the first oxide layer capacitor and the first gate capacitor are connected in series, the circuit branch where the first depletion layer capacitor, the first oxide layer capacitor and the first gate capacitor are located is connected between the E pole and the C pole of the first pure IGBT tube, one end of the first source capacitor is connected to the C pole of the first pure IGBT tube, and the other end of the first source capacitor is connected to the E pole of the first pure IGBT tube;

[0019] The second transistor includes a second pure IGBT tube, a second source capacitor, a second depletion layer capacitor, a second oxide layer capacitor and a second gate capacitor, the second depletion layer capacitor, the second oxide layer capacitor and the second gate capacitor are connected in series, the circuit branch where the second depletion layer capacitor, the second oxide layer capacitor and the second gate capacitor are located is connected between the E pole and the C pole of the second pure IGBT tube, one end of the second source capacitor is connected to the C pole of the second pure IGBT tube, and the other end of the second source capacitor is connected to the E pole of the second pure IGBT tube;

[0020] The E pole of the first pure IGBT tube is connected to the C pole of the second pure IGBT tube;

[0021] One end of the charging and discharging capacitor is connected to the C pole of the first pure IGBT tube, and the other end of the charging and discharging capacitor is connected to the E pole of the second pure IGBT tube.

[0022] Furthermore, the actual circuit also includes a current limiting inductor, one end of which is connected to the E pole of the first pure IGBT tube, and the other end of which is connected to the load stray inductance and the C pole of the second pure IGBT tube.

[0023] The second object of the present invention is to provide a method for generating a pulse signal, wherein the first switch component includes a first switch unit, which is a first IGBT transistor; the second switch component includes a second switch unit, which is a second IGBT transistor; the G pole of the first IGBT transistor is connected to a trigger signal trig_1, and the G pole of the second IGBT transistor is connected to a trigger signal trig_2; the trigger signal trig_1 and the trigger signal trig_2 are both binary signals, and are both composed of a high potential and a low potential;

[0024] When the trigger signal trig_1 is at a high potential, the first IGBT transistor is in an on state, and when the trigger signal trig_1 is at a low potential, the first IGBT transistor is in an off state;

[0025] When the trigger signal trig_2 is at a high potential, the second IGBT transistor is in an on state, and when the trigger signal trig_2 is at a low potential, the second IGBT transistor is in an off state;

[0026] The method for generating a pulse signal includes generating a voltage pulse signal at both ends of a load resistor by discharging a charge-discharge capacitor, and includes the following steps:

[0027] S1, the trigger signal trig_1 changes from a low potential to a high potential at time t1; the trigger signal trig_2 changes from a high potential to a low potential at time t2, at which time the charge-discharge capacitor begins to discharge; time t2 is after time t1;

[0028] S2, after reaching the set time, the trigger signal trig_1 changes from high potential to low potential at time t3; the trigger signal trig_2 changes from low potential to high potential at time t4, at which time the charge and discharge capacitors stop discharging; time t4 is after time t3.

[0029] Furthermore, the charging and discharging capacitors are energy storage capacitors with a withstand voltage of 6KV and a capacitance value of 2uf; the first resistor and the third resistor are both high-voltage glass glaze resistors, and the resistance values ​​are both 5MΩ; the second resistor and the fourth resistor are both metal film resistors, with a power of 5W and a resistance value of 22Ω; the first capacitor and the second capacitor are both high-voltage ceramic capacitors, and the capacitance values ​​are both 47nf; the time difference between moment t2 and moment t1 is 0~100ns, and the time difference between moment t4 and moment t3 is 0~100ns.

[0030] The beneficial effects of the present invention are as follows:

[0031] (1) At the initial moment of the discharge of the charging and discharging capacitors, the present invention places all IGBT transistors in the on state (conducting state), and at this time all IGBT transistors form a series circuit. Since the load resistor of the present invention is connected in parallel with one group of IGBT transistors, the load resistor is short-circuited at this time, that is, the voltage released by the charging and discharging capacitors does not act on the load resistor, but releases the charge stored in the IGBT. Thereafter, the IGBT transistor connected in parallel with the load resistor is turned off (off state), and at this time the charge released by the charging and discharging capacitors acts on the load resistor, and a high-voltage pulse signal begins to be formed. Similarly, when the generation of the high-voltage pulse signal is terminated, the series-connected IGBT transistors are first turned off, and then the parallel-connected IGBT transistors are turned on to release the charge stored in the IGBT transistors.

[0032] In summary, the present invention connects the load resistor in parallel with one group of IGBT transistors, which can remove the interference of the capacitor on the IGBT transistor on the signal carried by the load resistor. Therefore, the rising edge and falling edge of the high-voltage pulse signal generated on the load resistor by charging and discharging the capacitor in the present invention have a large steepness, which is closer to a rectangular high-voltage pulse signal, so as to be better applied to the treatment of tumors.

[0033] (2) The present invention does not require the construction of a complex load signal steepening circuit. It only requires all IGBT transistors to be the same to achieve the generation of nanosecond-level rising and falling edges of high-voltage pulse signals on the load resistor, thereby meeting the requirements for pulse steepness of high-voltage pulse signals in biomedicine and other fields. At the same time, it can effectively steepen the falling edge of the pulse signal under large load conditions, meeting the requirements for high-voltage pulse steepness in different fields.

[0034] (3) Since the IGBT actually used is not an ideal IGBT, but an IGBT with stray capacitance. The load resistor actually used is a brake ripple resistor, which has a large power and will generate stray capacitance and inductance during use. Therefore, the present invention converts the ideal IGBT into an IGBT with stray capacitance, and also converts the ideal load resistor into a load resistor with stray capacitance and stray inductance, so that the circuit designed by the present invention is closer to the actual use state, so that the circuit parameters can be adjusted according to actual needs to obtain the required high-voltage pulse signal.

[0035] In the actual circuit, at the initial moment of the discharge of the charging and discharging capacitors, the present invention puts all IGBT transistors in the on state (conducting state), and at this time all IGBT transistors form a series circuit. Since the load resistor of the stray capacitance and stray inductance of the present invention is connected in parallel with one group of IGBT transistors, the load resistor is short-circuited at this time, that is, the voltage released by the charging and discharging capacitors does not act on the load resistor, but releases the charge stored on the four capacitors contained in the IGBT transistors. Thereafter, the IGBT transistor connected in parallel with the load resistor is closed (cut-off state), and the charge released by the charging and discharging capacitors acts on the load resistor, and a high-voltage pulse signal begins to be formed. Similarly, when the generation of the high-voltage pulse signal is terminated, the series-connected IGBT transistors are first closed, and then the parallel-connected IGBT transistors are opened to release the charge stored on the four capacitors contained in the IGBT transistors.

[0036] (4) If the IGBT transistor is in a short-circuit state for a long time, it will be damaged. If each IGBT transistor performs a high-low potential conversion at the same time, the steepness of the rising and falling edges of the generated high-voltage pulse signal will be reduced. Therefore, the present invention designs the time difference between time t2 and time t1 to be 0-100ns, and the time difference between time t4 and time t3 to be 0-100ns, which can not only increase the steepness of the rising and falling edges of the generated high-voltage pulse signal, making the high-voltage pulse signal closer to a rectangular pulse signal, but also prevent damage to the IGBT transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 The ideal circuit diagram for generating pulse signals of the present invention;

[0038] Figure 2 A practical circuit diagram of generating a pulse signal with only one first switch unit and one second switch component of the present invention;

[0039] Figure 3a To invent a trigger signal for an IGBT tube corresponding to the initial moment of generating a high-voltage pulse signal;

[0040] Figure 3b For the present invention Figure 3a The waveform corresponding to the rising edge of the high-voltage pulse signal in the minimum time unit of 20us under the action of the trigger signal;

[0041] Figure 3c For the present invention Figure 3a The waveform corresponding to the rising edge of the high-voltage pulse signal in the minimum time unit of 40ns under the action of the trigger signal;

[0042] Figure 4a The trigger signal of the IGBT tube corresponding to the moment when the high-voltage pulse signal is stopped in the present invention;

[0043] Figure 4b For the present invention Figure 4a The waveform of the high voltage pulse signal corresponding to the minimum time unit of 4us under the action of the trigger signal;

[0044] Figure 4c For the present invention Figure 4b The falling edge waveform diagram of the high voltage pulse signal in the figure corresponds to the minimum time of 40ns;

[0045] Figure 4d For the present invention Figure 4b The rising edge waveform diagram of the high voltage pulse signal in the figure corresponds to the minimum time of 40ns.

[0046] The meanings of the symbols in the figure are as follows:

[0047] 1-first switch component 11-first switch unit Q1-first transistor Q11-first pure IGBT tube C11-first source capacitor C12-first depletion layer capacitor C13-first oxide layer capacitor C14-first gate capacitor 2-second switch component 21-second switch unit Q2-second transistor Q21-second pure IGBT tube C21-second source capacitor C22-second depletion layer capacitor C23-second oxide layer capacitor C24-second gate capacitor 3-host computer 4-controller 5-isolation component R0-load resistor R01-load pure resistor L01-load stray inductance C01-load distributed capacitor C0-charge and discharge capacitors R1~R4-first resistor~fourth resistor C1-first capacitor C2-second capacitor L1-current limiting inductor DETAILED DESCRIPTION

[0048] The following is a clear and complete description of the technical solution of the present invention in combination with the embodiments and the accompanying drawings. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0049] Example 1

[0050] A circuit for generating a pulse signal. In this embodiment, the pulse signal generated is a high-voltage pulse signal. The circuit for generating the pulse signal is as follows Figure 1 The ideal circuit shown in FIG. 1 is an ideal circuit in which the transistors and resistors included in the circuit are not doped with any inductors and capacitors. The ideal circuit in this embodiment is as follows: Figure 1 As shown, it includes a first switch component 1, a second switch component 2 and a charge-discharge capacitor C0 connected in series, a power source VCC for supplying power to the charge-discharge capacitor C0, and a load resistor R0 connected in parallel with the second switch component 2.

[0051] like Figure 1 As shown, the output end of the host computer 3 is connected to the input end of the controller 4, the output end of the controller 4 is connected to the input end of the isolation component 5, and the output end of the isolation component 5 is used to output the trigger signal trig_1 and the trigger signal trig_2.

[0052] like Figure 1As shown, the first switch component 1 includes two groups of first switch units 11, and each group of the first switch units 11 includes a first transistor Q1, and a first protection component connected in parallel with the first transistor Q1 for preventing the first transistor Q1 from being broken down. The first protection component includes a second resistor R2 and a first capacitor C1 connected in series, and a first resistor R1 connected in parallel with the circuit branch where the second resistor R2 and the first capacitor C1 are located; the first transistor Q1 is a first IGBT transistor, the C pole of the first IGBT transistor is connected to one end of the first resistor R1 and one end of the second resistor R2, the other end of the second resistor R2 is connected to one end of the first capacitor C1, the other end of the first resistor R1 and the other end of the first capacitor C1 are connected to the E pole of the first IGBT transistor, and the G pole of the first IGBT transistor is used to connect the trigger signal trig_1. The C pole of the first IGBT transistor of one group in the first switch component 1 is connected to the E pole of the other group, and the C pole of the first IGBT transistor of the other group is also connected to the power supply VCC, and the model of the first IGBT transistor and the second IGBT transistor are both STGW40H120DF2, and the manufacturer is STMicroelectronics.

[0053] like Figure 1 As shown, the second switch component 2 includes two groups of second switch units 21, each group of second switch units 21 includes a second transistor Q2, and a second protection component connected in parallel with the second transistor Q2 for preventing the second transistor Q2 from being broken down. The second protection component includes a fourth resistor R4 and a second capacitor C2 connected in series, and a third resistor R3 connected in parallel with the circuit branch where the fourth resistor R4 and the second capacitor C2 are located; the second transistor Q2 is a second IGBT transistor, the C pole of the second IGBT transistor is connected to one end of the fourth resistor R4 and one end of the third resistor R3, the other end of the fourth resistor R4 is connected to one end of the second capacitor C2, the other end of the third resistor R3 and the other end of the second capacitor C2 are both connected to the E pole of the second IGBT transistor, and the G pole of the second IGBT transistor is used to access the trigger signal trig_2.

[0054] like Figure 1 As shown, two groups of first IGBT transistors, two groups of second IGBT transistors and the charge-discharge capacitor C0 form a series circuit, and the load resistor R0 and the circuit branch where the two groups of second IGBT transistors are located form a parallel circuit.

[0055] The resistance value of the first resistor R1 is the same as the resistance value of the third resistor R3, the resistance value of the second resistor R2 is the same as the resistance value of the fourth resistor R4, the value of the first capacitor C1 is the same as the value of the second capacitor C2, and the parameters of the first IGBT transistor and the second IGBT transistor are the same. This design makes the electrical parameters of the second switch component 2 and the first switch component 1 the same, so that the circuit of the present invention can generate a high-voltage pulse signal with a large steepness on both the rising edge and the falling edge.

[0056] Example 2

[0057] On the basis of Example 1, the ideal circuit in Example 1 is converted into an actual circuit. In the actual circuit, the IGBT transistor is an insulated gate transistor. Due to the limited manufacturing process, there will always be capacitance between the gate (G pole) and the emitter (E pole) of the IGBT transistor, oxide layer capacitance, depletion layer capacitance, and capacitance between the source (C pole) and the emitter (E pole). Therefore, Figure 2 As shown, each IGBT transistor is surrounded by four capacitors.

[0058] Because the circuit uses wires or copper sheets, there is more or less inductance. When working at high frequencies, it has a serious impact on the leading and trailing edges of the nanosecond load signal, slowing down the leading and trailing edges of the load signal, which is equivalent to the existence of a current-limiting inductor L1 in the actual circuit.

[0059] The load resistor R0 is the brake ripple resistor, which is not a pure resistive load. It also has capacitance and stray inductance, which will also affect the steepness of the rising and falling edges of the high-voltage pulse signal generated by the circuit. Based on the above analysis, the following Figure 2 In the actual circuit shown, the load resistor R0 is a braking ripple resistor, which includes a load stray inductance L01 and a load pure resistance R01 connected in series, and a load distributed capacitor C01 connected in parallel with the circuit branch where the load stray inductance L01 and the load pure resistance R01 are located. The circuit branch where the load stray inductance L01 and the load pure resistance R01 are located is also connected in parallel with the second transistor Q2.

[0060] In the actual circuit: the first transistor Q1 includes a first pure IGBT tube Q11, a first source capacitor C11 (a capacitor between the source and the emitter of the IGBT transistor), a first depletion layer capacitor C12, a first oxide layer capacitor C13 and a first gate capacitor C14 (a capacitor between the gate and the emitter of the IGBT transistor), the first depletion layer capacitor C12, the first oxide layer capacitor C13 and the first gate capacitor C14 are connected in series, the circuit branch where the first depletion layer capacitor C12, the first oxide layer capacitor C13 and the first gate capacitor C14 are located is connected between the E pole and the C pole of the first pure IGBT tube Q11, one end of the first source capacitor C11 is connected to the C pole of the first pure IGBT tube Q11, and the other end of the first source capacitor C11 is connected to the E pole of the first pure IGBT tube Q11;

[0061] The second transistor Q2 includes a second pure IGBT tube Q21, a second source capacitor C21, a second depletion layer capacitor C22, a second oxide layer capacitor C23 and a second gate capacitor C24, the second depletion layer capacitor C32, the second oxide layer capacitor C23 and the second gate capacitor C24 are connected in series, the circuit branch where the second depletion layer capacitor C22, the second oxide layer capacitor C23 and the second gate capacitor C24 are located is connected between the E pole and the C pole of the second pure IGBT tube Q21, one end of the second source capacitor C21 is connected to the C pole of the second pure IGBT tube Q21, and the other end of the second source capacitor C21 is connected to the E pole of the second pure IGBT tube Q21;

[0062] The E pole of the first pure IGBT tube Q11 is connected to the C pole of the second pure IGBT tube Q21; one end of the charge and discharge capacitor C0 is connected to the C pole of the first pure IGBT tube Q11, and the other end of the charge and discharge capacitor C0 is connected to the E pole of the second pure IGBT tube Q21.

[0063] The actual circuit also includes a current limiting inductor L1, one end of which is connected to the E pole of the first pure IGBT tube Q11, and the other end of which is connected to the load stray inductance L01 and the C pole of the second pure IGBT tube Q21.

[0064] In this embodiment, the pure resistor is a pure resistive resistor (having only the characteristics of a resistor without being mixed with the characteristics of other circuit components), and the distributed capacitor is a capacitor having only the characteristics of a capacitor without being mixed with the characteristics of other circuit components.

[0065] The working principle of this embodiment is as follows

[0066] (1) Before the charging and discharging capacitor C0 is discharged, the second pure IGBT tube Q21 is always in the on state.

[0067] (2) The first pure IGBT tube Q11 is turned on, and the second pure IGBT tube Q21 is still in the on state. The structure is as follows Figure 2 The nanosecond short circuit shown by the arrow I in the figure, at this time the charge and discharge capacitor C0 will Figure 2 In mode I, discharge is performed to release the energy stored in the energy storage element in the circuit in advance, effectively steepening the rising edge of the high-voltage pulse signal carried by the load pure resistance R01.

[0068] (3) The first pure IGBT tube Q11 is turned off, and the second pure IGBT tube Q21 is turned off after a delay of nanoseconds. At this time, the charge and discharge capacitor C0 will be Figure 2 In mode II, the discharge is performed, and the energy stored in the load stray inductance L01 and the load distributed capacitance C01 is released rapidly, effectively steepening the falling edge of the high-voltage pulse signal carried by the load pure resistance R01.

[0069] Example 3

[0070] Based on Example 1, a method for generating a pulse signal is provided, wherein the trigger signal trig_1 and the trigger signal trig_2 are both binary signals, both consisting of a high potential and a low potential; when the trigger signal trig_1 is at a high potential, the first IGBT transistor (the first transistor Q1) is in an on state, and when the trigger signal trig_1 is at a low potential, the first IGBT transistor is in an off state.

[0071] When the trigger signal trig_2 is at a high level, the second IGBT transistor (the second transistor Q2 ) is in an on state, and when the trigger signal trig_2 is at a low level, the second IGBT transistor is in an off state.

[0072] The method for generating a pulse signal includes generating a high-voltage pulse signal at both ends of a load resistor R0 by discharging a charge-discharge capacitor C0, and includes the following steps:

[0073] S1, the trigger signal trig_1 changes from a low potential to a high potential at time t1; the trigger signal trig_2 changes from a high potential to a low potential at time t2, at which time the charge-discharge capacitor C0 starts to discharge; time t2 is after time t1;

[0074] S2, after reaching the set time, the trigger signal trig_1 changes from high potential to low potential at time t3; the trigger signal trig_2 changes from low potential to high potential at time t4, at which time the charge-discharge capacitor C0 stops discharging; time t4 is after time t3.

[0075] In this embodiment, the time difference between time t2 and time t1 is 20 ns to 100 ns, and the time difference between time t4 and time t3 is 50 ns to 100 ns.

[0076] Example 4

[0077] On the basis of implementation 2 and example 3, embodiment 3 is applied to the circuit of implementation 2. In this embodiment, there is only one group of first switch units 11 and one group of second switch units 21. Figure 3a , 3b In FIG. 3c, A represents the trigger signal trig_1 connected to the first transistor Q1 and the first pure IGBT tube Q11, B represents the trigger signal trig_2 connected to the second transistor Q2 and the second pure IGBT tube Q21, and C represents the high-voltage pulse signal carried by the load pure resistor R01.

[0078] The rising edge of the trigger signal trig_1 and the falling edge of the trigger signal trig_2 are as follows: Figure 3a As shown, in this embodiment, the time difference between time t2 and time t1 is 20ns, and the pulse widths of the two trigger signals are both 10us.

[0079] like Figure 3b and Figure 3c As shown in the C waveform in FIG, the rising edge of the high-voltage pulse signal is very fast, which is 54 ns. Therefore, the circuit and method of the present invention can effectively improve the steepness of the rising edge of the high-voltage pulse signal.

[0080] Example 5

[0081] On the basis of implementation 2 and example 3, embodiment 3 is applied to the circuit of implementation 2. In this embodiment, there is only one group of first switch units 11 and one group of second switch units 21. Figure 4a , 4b In Figures 4c and 4d, A represents the trigger signal trig_1 connected to the first transistor Q1 and the first pure IGBT tube Q11, B represents the trigger signal trig_2 connected to the second transistor Q2 and the second pure IGBT tube Q21, and C represents the high-voltage pulse signal carried by the load pure resistor R01.

[0082] The falling edge of the trigger signal trig_1 and the rising edge of the trigger signal trig_2 are as follows: Figure 4a As shown, in this embodiment, the time difference between time t4 and time t2 is 100ns, and the pulse widths of the two trigger signals are both 10us.

[0083] Figure 4b The C waveform in the figure is a rectangular high voltage pulse signal generated by this embodiment. Figure 4c From the waveform C in FIG. 1 , it can be known that the time required for the falling edge of the high-voltage pulse signal in this embodiment is 70 ns. However, since this embodiment does not control the time difference between the falling edge of the trigger signal trig_1 and the rising edge of the trigger signal trig_2, Figure 4dIt can be seen that the time required for the rising edge of the high-voltage pulse signal in this embodiment is 101ns, which is much longer than the time required for the rising edge of the high-voltage pulse signal in Example 4. Therefore, it is proved again that the circuit and method of the present invention can effectively improve the steepness of the rising edge and falling edge of the generated high-voltage pulse signal.

Claims

1. A circuit for generating a pulse signal, characterized in that: The circuit comprises a first switch component (1), a second switch component (2) and a charge-discharge capacitor (C0) connected in series, a power supply for supplying power to the charge-discharge capacitor (C0), and a load resistor (R0) connected in parallel with the second switch component (2); The first switch component (1) and the second switch component (2) are both controlled in on / off state by a trigger signal; the voltage across the load resistor (R0) is used to generate a pulse signal; The first switch component (1) comprises a first switch unit (11), the first switch unit (11) comprises a first transistor (Q1), and a first protection component connected in parallel with the first transistor (Q1) for preventing the first transistor (Q1) from being broken down; The second switch component (2) comprises a second switch unit (21), the second switch unit (21) comprises a second transistor (Q2), and a second protection component connected in parallel with the second transistor (Q2) for preventing the second transistor (Q2) from being broken down; The first transistor (Q1), the second transistor (Q2) and the charge and discharge capacitor (C0) are connected in series, and the load resistor (R0) is connected in parallel with the second transistor (Q2); The electrical parameters of the first transistor (Q1) are the same as the electrical parameters of the second transistor (Q2), and the electrical parameters of the first protection component are the same as the electrical parameters of the second protection component; The number of the first switch units (11) is equal to the number of the second switch units (21), and each first transistor (Q1) in the first switch unit (11) and each second transistor (Q2) in the second switch unit (21) form a series circuit; The first protection component comprises a second resistor (R2) and a first capacitor (C1) connected in series, and a first resistor (R1) connected in parallel with the second resistor (R2) and the first capacitor (C1); the first transistor (Q1) is a first IGBT transistor, the C pole of the first IGBT transistor is connected to one end of the first resistor (R1) and one end of the second resistor (R2), the other end of the second resistor (R2) is connected to one end of the first capacitor (C1), the other end of the first resistor (R1) and the other end of the first capacitor (C1) are connected to the E pole of the first IGBT transistor, and the G pole of the first IGBT transistor is used to access the trigger signal trig_1; The second protection component comprises a fourth resistor (R4) and a second capacitor (C2) connected in series, and a third resistor (R3) connected in parallel with the fourth resistor (R4) and the second capacitor (C2); the second transistor (Q2) is a second IGBT transistor, the C pole of the second IGBT transistor is connected to one end of the fourth resistor (R4) and one end of the third resistor (R3), the other end of the fourth resistor (R4) is connected to one end of the second capacitor (C2), the other end of the third resistor (R3) and the other end of the second capacitor (C2) are both connected to the E pole of the second IGBT transistor, and the G pole of the second IGBT transistor is used to access the trigger signal trig_2; The E pole of the first IGBT transistor is connected to the C pole of the second IGBT transistor.

2. The circuit for generating a pulse signal as claimed in claim 1, characterized in that: The circuit also includes an actual circuit, in which: the load resistor (R0) is a braking ripple resistor, and the braking ripple resistor includes a load stray inductance (L01) and a load pure resistance (R01) connected in series, and a load distributed capacitor (C01) connected in parallel with a circuit branch where the load stray inductance (L01) and the load pure resistance (R01) are located; The circuit branch where the load stray inductance (L01) and the load pure resistance (R01) are located is also connected in parallel with the second transistor (Q2).

3. The circuit for generating a pulse signal as claimed in claim 2, characterized in that: In an actual circuit: the first transistor (Q1) comprises a first pure IGBT tube (Q11), a first source capacitor (C11), a first depletion layer capacitor (C12), a first oxide layer capacitor (C13) and a first gate capacitor (C14); the first depletion layer capacitor (C12), the first oxide layer capacitor (C13) and the first gate capacitor (C14) are connected in series; a circuit branch where the first depletion layer capacitor (C12), the first oxide layer capacitor (C13) and the first gate capacitor (C14) are located is connected between the E pole and the C pole of the first pure IGBT tube (Q11); one end of the first source capacitor (C11) is connected to the C pole of the first pure IGBT tube (Q11); and the other end of the first source capacitor (C11) is connected to the E pole of the first pure IGBT tube (Q11); The second transistor (Q2) comprises a second pure IGBT tube (Q21), a second source capacitor (C21), a second depletion layer capacitor (C22), a second oxide layer capacitor (C23) and a second gate capacitor (C24); the second depletion layer capacitor (C32), the second oxide layer capacitor (C23) and the second gate capacitor (C24) are connected in series; a circuit branch where the second depletion layer capacitor (C22), the second oxide layer capacitor (C23) and the second gate capacitor (C24) are located is connected between the E pole and the C pole of the second pure IGBT tube (Q21); one end of the second source capacitor (C21) is connected to the C pole of the second pure IGBT tube (Q21); and the other end of the second source capacitor (C21) is connected to the E pole of the second pure IGBT tube (Q21); The E pole of the first pure IGBT tube (Q11) is connected to the C pole of the second pure IGBT tube (Q21); One end of the charging and discharging capacitor (C0) is connected to the C pole of the first pure IGBT tube (Q11), and the other end of the charging and discharging capacitor (C0) is connected to the E pole of the second pure IGBT tube (Q21).

4. The circuit for generating a pulse signal as claimed in claim 3, characterized in that: The actual circuit also includes a current limiting inductor (L1), one end of which is connected to the E pole of the first pure IGBT tube (Q11), and the other end of which is connected to the load stray inductance (L01) and the C pole of the second pure IGBT tube (Q21).

5. A method for generating a pulse signal based on the circuit for generating a pulse signal according to claim 1, characterized in that: The first switch component (1) comprises a first switch unit (11), the first switch unit (11) is a first IGBT transistor; the second switch component (2) comprises a second switch unit (21), the second switch unit (21) is a second IGBT transistor; the G pole of the first IGBT transistor is connected to a trigger signal trig_1, and the G pole of the second IGBT transistor is connected to a trigger signal trig_2; the trigger signal trig_1 and the trigger signal trig_2 are both binary signals, both consisting of a high potential and a low potential; When the trigger signal trig_1 is at a high potential, the first IGBT transistor is in an on state, and when the trigger signal trig_1 is at a low potential, the first IGBT transistor is in an off state; When the trigger signal trig_2 is at a high potential, the second IGBT transistor is in an on state, and when the trigger signal trig_2 is at a low potential, the second IGBT transistor is in an off state; The method for generating a pulse signal includes generating a voltage pulse signal at both ends of a load resistor (R0) by discharging a charge-discharge capacitor (C0), and includes the following steps: S1, the trigger signal trig_1 changes from a low potential to a high potential at time t1; the trigger signal trig_2 changes from a high potential to a low potential at time t2, at which time the charge-discharge capacitor (C0) starts to discharge; time t2 is after time t1; S2, after reaching the set time, the trigger signal trig_1 changes from high potential to low potential at time t3; the trigger signal trig_2 changes from low potential to high potential at time t4, at which time the charge-discharge capacitor (C0) stops discharging; time t4 is after time t3.

6. The method for generating a pulse signal as claimed in claim 5, characterized in that: The charging and discharging capacitor (C0) is a storage capacitor with a withstand voltage of 6KV and a capacitance value of 2uf; the first resistor (R1) and the third resistor (R3) are both high-voltage glass glaze resistors, and the resistance values ​​are both 5MΩ; the second resistor (R2) and the fourth resistor (R4) are both metal film resistors, the power is both 5W, and the resistance value is both 22Ω; the first capacitor (C1) and the second capacitor (C2) are both high-voltage ceramic capacitors, and the capacitance value is both 47nf; the time difference between time t2 and time t1 is 0~100ns, and the time difference between time t4 and time t3 is 0~100ns.

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