Apparatus and method for generating circuit clock signals

Abstract

Embodiments of this disclosure provide an apparatus and method for generating a circuit clock signal. The apparatus includes: a clock buffer configured to buffer an original clock signal to obtain a buffered clock signal; a clock delay unit configured to delay the original clock signal to obtain a plurality of delayed clock signals, the plurality of delayed clock signals being delayed by different amounts of time relative to the original clock signal; a broadened clock generator configured to generate a broadened clock signal based on the original clock signal and the plurality of delayed clock signals, the frequency of the broadened clock signal being lower than the frequency of the original clock signal; and a clock selector configured to select one of the buffered clock signal and the broadened clock signal as the circuit clock signal based on the selection signal.

Description

Technical Field

[0001] The exemplary embodiments disclosed herein generally relate to the field of electronic circuits, and particularly to apparatus and methods for generating circuit clock signals. Background Technology

[0002] In the field of electronic circuits, clock signals are used to coordinate the operation of various electronic components, ensuring that they run synchronously. In integrated circuits, especially large digital chips such as central processing units (CPUs) and graphics processing units (GPUs), digital circuits may encounter power fluctuations during operation. Power fluctuations can cause some electronic components to fail to meet timing requirements, resulting in timing errors. In such cases, the clock needs to be able to adaptively adjust to avoid timing errors, ensure the correctness of data transmission, and achieve better performance. Summary of the Invention

[0003] The purpose of this disclosure is to provide an apparatus and method for generating circuit clock signals to at least partially solve the above-mentioned problems and other potential problems.

[0004] In a first aspect of this disclosure, an apparatus for generating a circuit clock signal is provided, comprising: a clock buffer configured to buffer an original clock signal to obtain a buffered clock signal; a clock delay unit configured to delay the original clock signal to obtain a plurality of delayed clock signals, the plurality of delayed clock signals being delayed by different amounts of time relative to the original clock signal; a broadened clock generator configured to generate a broadened clock signal based on the original clock signal and the plurality of delayed clock signals, the frequency of the broadened clock signal being lower than the frequency of the original clock signal; and a clock selector configured to select one of the buffered clock signal and the broadened clock signal as the circuit clock signal based on the selection signal.

[0005] In a second aspect of this disclosure, a method for generating a circuit clock signal is provided, comprising: buffering an original clock signal to obtain a buffered clock signal; delaying the original clock signal to obtain a plurality of delayed clock signals, the plurality of delayed clock signals being delayed by different amounts of time relative to the original clock signal; generating a broadened clock signal from the original clock signal and the plurality of delayed clock signals, the frequency of the broadened clock signal being lower than the frequency of the original clock signal; and selecting one of the buffered clock signal and the broadened clock signal as the circuit clock signal based on a selection signal.

[0006] It should be understood that the content described in this content section is not intended to limit the key or essential features of the embodiments of this disclosure, nor is it intended to restrict the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0007] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. In the drawings, the same or similar reference numerals denote the same or similar elements, wherein:

[0008] Figure 1 A circuit schematic diagram of an apparatus for generating a circuit clock signal according to an embodiment of the present disclosure is shown;

[0009] Figure 2 A timing diagram of the original clock signal, a plurality of delayed clock signals, and a stretched clock signal according to an embodiment of the present disclosure is shown.

[0010] Figure 3 A predetermined order for cyclically selecting clock signals from a raw clock signal and a plurality of delayed clock signals is shown according to an embodiment of the present disclosure;

[0011] Figure 4 A circuit schematic of a stretched clock generator according to an embodiment of the present disclosure is shown;

[0012] Figure 5 A timing diagram of a circuit clock signal according to an embodiment of the present disclosure is shown;

[0013] Figure 6 A flowchart of a method for generating a circuit clock signal according to an embodiment of the present disclosure is shown. Detailed Implementation

[0014] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0015] In the description of embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The term "some embodiments" should be understood as "at least some embodiments". Other explicit and implicit definitions may also be included below.

[0016] As mentioned above, in integrated circuits, digital circuits may encounter power fluctuations during operation. Power fluctuations can cause timing requirements of some electronic components to be unmet, resulting in timing errors. In this case, the clock needs to be adaptively adjusted to avoid timing errors and ensure the correctness of data transmission. One clock adjustment method is to use a phase-locked loop (PLL) to adjust the clock; however, the adjustment speed of a PLL is slow and cannot meet the need for rapid adaptive adjustment. In some cases, two PLLs can be used to generate two clock frequencies, thereby dynamically providing different clock signals; however, setting up two PLLs results in significant resource waste. Embodiments of this disclosure provide a scheme for generating circuit clock signals. In this scheme, multiple delayed clock signals are obtained by delaying the original clock signal. Then, a broadened clock signal is generated based on the original clock signal and the multiple delayed clock signals. In the event of power fluctuations, the broadened clock signal can be dynamically selected as the circuit clock signal. In this way, rapid adaptive clock adjustment can be achieved, avoiding timing errors and ensuring the correctness of data transmission, thereby achieving better circuit performance. The following will combine... Figures 1 to 6 The principles of this disclosure will be described in detail below.

[0017] Figure 1 A circuit schematic diagram of an apparatus for generating a circuit clock signal according to an embodiment of the present disclosure is shown. Figure 1 As shown, the apparatus described herein generally includes a clock buffer 10, a clock delay unit 20, a widened clock generator 30, a clock selector 40, and a control unit 50.

[0018] Clock buffer 10 is used to buffer the original clock signal clk0 to obtain the buffered clock signal clk_buf. The original clock signal clk0 is the clock signal used by the circuit under normal operating conditions, and it has a predetermined clock frequency, such as having a predetermined frequency value or being within a predetermined frequency range. Clock buffer 10 can employ any suitable clock buffering technique to buffer the original clock signal clk0. In some embodiments, clock buffer 10 may include a multi-stage inverter, which can invert the original clock signal clk0 multiple times, thereby buffering and enhancing the original clock signal clk0, and improving the driving capability of the clock signal.

[0019] It should be understood that the clock buffering methods described above are merely examples and are not intended to limit the embodiments of this disclosure in any way. Any clock buffering techniques currently known or developed in the future may be used in conjunction with the embodiments of this disclosure.

[0020] The clock delay unit 20 is used to delay the original clock signal clk0 to obtain multiple delayed clock signals clk1-clk7. The delayed clock signals clk1-clk7 are delayed by different amounts of time relative to the original clock signal clk0. Figure 1 Seven delayed clock signals clk1-clk7 generated by clock delay unit 20 are shown to illustrate the principles of this disclosure. Clock delay unit 20 can use any suitable clock delay technique to delay the original clock signal clk0. It should be noted that the numbers, values, etc. mentioned above and elsewhere in this disclosure are exemplary and are not intended to limit the scope of this disclosure in any way. Any other suitable numbers or values ​​are possible.

[0021] In some embodiments, such as Figure 1 As shown, the clock delay unit 20 includes a plurality of delay components 21 connected in sequence. The number of delay components 21 is equal to the number of delayed clock signals clk1-clk7. For example, Figure 1 The clock delay unit 20 shown includes seven delay components 21 for generating seven delayed clock signals clk1-clk7. In other embodiments, the clock delay unit 20 may include more or fewer delay components 21 for generating a corresponding number of delayed clock signals.

[0022] like Figure 1As shown, the original clock signal clk0 is provided to the first delay component among a plurality of delay components 21. Each delay component 21 provides a corresponding delayed clock signal among the delayed clock signals clk1-clk7. For example, the first delay component 21 may delay the original clock signal clk0 to provide the delayed clock signal clk1. The second delay component may delay the delayed clock signal clk1 to provide the delayed clock signal clk2. The third delay component may delay the delayed clock signal clk2 to provide the delayed clock signal clk3. The fourth delay component may delay the delayed clock signal clk3 to provide the delayed clock signal clk4. The fifth delay component may delay the delayed clock signal clk4 to provide the delayed clock signal clk5. The sixth delay component may delay the delayed clock signal clk5 to provide the delayed clock signal clk6. The seventh delay component can delay the delayed clock signal clk6 to provide a delayed clock signal clk7. In this way, multiple delayed clock signals can be reliably generated sequentially, and such a clock delay unit 20 has a simple structure and low cost.

[0023] Each of the multiple delay components 21 can employ any suitable clock delay technique to delay the clock signal. For example, in some embodiments, delay component 21 can employ a buffer to delay the clock signal. In other embodiments, delay component 21 can employ a multi-stage inverter to delay the clock signal. In still other embodiments, delay component 21 can employ a resistor-capacitor (RC) delay component to delay the clock signal. It should be understood that the above-described structure of delay component 21 is merely illustrative and is not intended to limit the embodiments of this disclosure in any way. Any clock delay technique currently known or developed in the future can be used in conjunction with the embodiments of this disclosure.

[0024] In some embodiments, each of the plurality of delay components 21 can provide the same amount of delay. For example, Figure 1 Each delay component 21 shown can provide a delay of 12.5% ​​of clock cycles. Figure 2 The timing diagram shows the original clock signal clk0 and multiple delayed clock signals clk1-clk7. (See diagram for example.) Figure 2As shown, clock signal clk1 is delayed by 12.5% ​​of clock cycles relative to the original clock signal clk0, clock signal clk2 is delayed by 25% of clock cycles relative to the original clock signal clk0, clock signal clk3 is delayed by 37.5% of clock cycles relative to the original clock signal clk0, clock signal clk4 is delayed by 50% of clock cycles relative to the original clock signal clk0, clock signal clk5 is delayed by 62.5% of clock cycles relative to the original clock signal clk0, clock signal clk6 is delayed by 75% of clock cycles relative to the original clock signal clk0, and clock signal clk7 is delayed by 87.5% of clock cycles relative to the original clock signal clk0. It should be understood that when the clock delay unit 20 includes more or fewer delay components 21, each delay component 21 can provide a different value of delay.

[0025] Alternatively, in some embodiments, the multiple delay components 21 may provide different delay amounts, which may be selected according to circuit design and actual needs, and the embodiments of this disclosure are not limited in this regard.

[0026] In some embodiments, the clock delay unit 20 may include multiple individual delay components, rather than as shown in the figure. Figure 1 The multiple delay components shown are connected in sequence to provide corresponding delayed clock signals. This arrangement can also provide multiple delayed clock signals, but... Figure 1 Compared to the structure shown, the structure is more complex and more expensive.

[0027] It should be understood that the above-described structure of the clock delay unit 20 is merely an example and is not intended to limit the embodiments of this disclosure in any way. Any clock delay technology currently known or developed in the future may be used in conjunction with the embodiments of this disclosure.

[0028] The extended clock generator 30 is used to generate an extended clock signal clk_bro based on the original clock signal clk0 and multiple delayed clock signals clk1-clk7. The frequency of the extended clock signal clk_bro is lower than the frequency of the original clock signal clk0. An exemplary timing diagram of the extended clock signal clk_bro is shown in [the diagram]. Figure 2 It is shown in the middle. For example... Figure 2 As shown, the frequency of the stretched clock signal clk_bro is lower than that of the original clock signal clk0, and the duration of a single clock cycle of the stretched clock signal clk_bro is longer than that of a single clock cycle of the original clock signal clk0. The stretched clock generator 30 can use any suitable clock stretching technique to generate the stretched clock signal clk_bro based on the original clock signal clk0 and multiple delayed clock signals clk1-clk7.

[0029] For example, in some embodiments, such as Figure 1 As shown, the clock widening generator 30 includes a signal selection unit 31 and a clock widening unit 32. The signal selection unit 31 is used to cyclically select a clock signal from the original clock signal clk0 and a plurality of delayed clock signals clk1-clk7 in a predetermined order. The clock widening unit 32 is used to generate a widened clock signal clk_bro based on the clock signal clk_sel selected by the signal selection unit 31.

[0030] Figure 3 A predetermined order for cyclically selecting clock signals from a raw clock signal clk0 and a plurality of delayed clock signals clk1-clk7, according to an embodiment of the present disclosure, is illustrated. Figure 3 As shown, the signal selection unit 31 cyclically selects a clock signal from the original clock signal clk0 and multiple delayed clock signals clk1-clk7 in a counter-clockwise sequence indicated by the arrow. Specifically, the signal selection unit 31 first selects the original clock signal clk0, and then sequentially selects the delayed clock signals clk5, clk2, clk7, clk4, clk1, clk6, and clk3. Subsequently, the signal selection unit 31 selects the original clock signal clk0 again, thus entering the next selection cycle.

[0031] The signal selection unit 31 can be implemented in various ways to cyclically select a clock signal from the original clock signal clk0 and multiple delayed clock signals clk1-clk7. As an example, Figure 4 An example implementation of the signal selection unit 31 is shown. For example... Figure 4 As shown, the signal selection unit 31 includes a switch matrix 33 and a switch matrix control unit 34. The switch matrix 33 includes multiple switches, such as the first switch 331 to the eighth switch 338. Combined with... Figure 1One end of each of the first switches 331 to the eighth switch 338 is coupled to the clock delay unit 20 to receive the original clock signal clk0 and a corresponding clock signal from a plurality of delayed clock signals clk1-clk7. Specifically, one end of the first switch 331 is used to receive the original clock signal clk0, one end of the second switch 332 is used to receive the delayed clock signal clk5, one end of the third switch 333 is used to receive the delayed clock signal clk2, one end of the fourth switch 334 is used to receive the delayed clock signal clk7, one end of the fifth switch 335 is used to receive the delayed clock signal clk4, one end of the sixth switch 336 is used to receive the delayed clock signal clk1, one end of the seventh switch 337 is used to receive the delayed clock signal clk6, and one end of the eighth switch 338 is used to receive the delayed clock signal clk3. The other end of each switch is coupled to the clock widening unit 32 to provide the clock signal clk_sel selected by the signal selection unit 31 to the clock widening unit 32. Using this arrangement, the clock signal can be reliably and stably selected from the original clock signal clk0 and multiple delayed clock signals clk1-clk7 in a cyclic manner, and its circuit structure is simple and its implementation cost is low.

[0032] In some embodiments, a clock signal can be cyclically selected from the original clock signal clk0 and a plurality of delayed clock signals clk1-clk7 by cyclically controlling the on / off states of switches 331-338. The on / off states of the first switch 331 to the eighth switch 338 can be controlled by corresponding control signals S1 to S8. For example, the on / off state of the first switch 331 can be controlled by control signal S1. As an example, when control signal S1 is 0 (low level), the first switch 331 is off, and when control signal S1 is 1 (high level), the first switch 331 is on. As another example, when control signal S1 is 1, the first switch 331 can be off, and when control signal S1 is 0, the first switch 331 can be on. Similarly, by changing the levels of control signals S2-S8, the on / off states of the corresponding switches in the second switch 332 to the eighth switch 338 can be changed.

[0033] Control signals S1 to S8 can be provided by the switch matrix control unit 34. For example... Figure 4 As shown, the switch matrix control unit 34 can generate control signals S1 to S8 based on the enable signal EN, to control the first switch 331 to the eighth switch 338 to be cyclically turned on in sequence, thereby causing the original clock signal clk0 and multiple delayed clock signals clk1-clk7 to be turned on as follows: Figure 3 The predetermined sequence shown is cyclically selected by the signal selection unit 31. The switch matrix control unit 34 can generate control signals S1 to S8 in any suitable manner.

[0034] The enable signal EN can be provided in various ways. For example, returning... Figure 1 The enable signal EN can be provided by the control unit 50. In some embodiments, when an adaptive clock signal needs to be adjusted in the integrated circuit, such as during power fluctuations or due to power consumption requirements or functional requirements of the integrated circuit, the control unit 50 can provide a high-level enable signal EN to the switch matrix control unit 34 to initiate the generation of control signals S1 to S8. When no adaptive clock signal needs to be adjusted in the integrated circuit, the control unit 50 can provide a low-level enable signal EN to the switch matrix control unit 34. An exemplary level logic for the enable signal EN is described in... Figure 2 It is shown in the figure. It should be understood that in other embodiments, the control unit 50 may provide the enable signal EN with the opposite level logic.

[0035] For example, in some embodiments, such as Figure 4 As shown, the switch matrix control unit 34 includes a startup unit 341 and a switch signal generation unit 342. The startup unit 341 generates a broadened startup signal START based on an enable signal EN. The broadened startup signal START controls the switch signal generation unit 342 to begin generating control signals S1 to S8. The switch signal generation unit 342 generates corresponding control signals S1 to S8 based on the broadened startup signal START to control the on / off states of the first switch 331 to the eighth switch 338, thereby causing the first switch 331 to the eighth switch 338 to be cyclically turned on sequentially. Using this arrangement, the on / off states of multiple switches in the switch matrix 33 can be precisely controlled, and this circuit structure is simple and low-cost.

[0036] In some embodiments, such as Figure 4 As shown, the start unit 341 includes a pulse generator 3411, an OR gate 3412, and a set-reset (SR) latch 3413. The pulse generator 3411 generates a pulse signal EN_PULSE based on an enable signal EN. One input of the OR gate 3412 is connected to the output of the pulse generator 3411 to receive the pulse signal EN_PULSE. The other input of the pulse generator 3411 receives the control signal S8 of the last switch (e.g., the eighth switch 338) among the multiple switches of the switch matrix 33. The S input (i.e., the set input) of the SR latch 3413 is connected to the output of the OR gate 3412. The R input (i.e., the reset input) of the SR latch 3413 receives the control signal S1 of the first switch (i.e., the first switch 331) among the multiple switches of the switch matrix 33. The output of the SR latch 3413 provides a broadened start signal START.

[0037] Upon receiving the broadened start signal START, the switch signal generation unit 342 begins generating control signals, such as control signals S1 to S8, for the plurality of switches included in the switch matrix 33. In one embodiment, as... Figure 4 As shown, the switch signal generation unit 342 includes a multiplexer 3421, a plurality of D flip-flops 3422 connected in series, and a first additional D flip-flop 3423.

[0038] One input of multiplexer 3421 receives the broadened clock signal clk_bro, and the other input receives the original clock signal clk0. Multiplexer 3421 is used to select one of the broadened clock signal clk_bro and the original clock signal clk0 based on the selection control signal on the selection control terminal S, and provides the selection result at its output clk_out. In some embodiments, when the selection control signal on the selection control terminal S is 1, multiplexer 3421 selects the broadened clock signal clk_bro, and when the selection control signal on the selection control terminal S is 0, multiplexer 3421 selects the original clock signal clk0. It should be understood that the reverse selection logic is also possible.

[0039] The D input of the first D flip-flop in a series-connected plurality of D flip-flops 3422 is connected to the output of the SR latch 3413 to receive the broadened start signal START. The other D flip-flops in the plurality of D flip-flops 3422, excluding the first one, are sequentially connected after the first D flip-flop. That is, the D inputs of the other D flip-flops in the plurality of D flip-flops 3422, excluding the first one, are connected to the Q output of the preceding D flip-flop. The clock input CLK of the plurality of D flip-flops 3422 is connected to the output clk_out of the multiplexer 3421. The Q outputs of the plurality of D flip-flops 3422 respectively provide control signals, such as control signals S1 to S8, for the multiple switches included in the switch matrix 33.

[0040] The clock input of the first additional D flip-flop 3423 is connected to the Q output of the first D flip-flop among the plurality of D flip-flops 3422. The D input of the first additional D flip-flop 3423 receives the enable signal EN. The Q output of the first additional D flip-flop 3423 is connected to the selection control terminal S of the multiplexer 3421.

[0041] The switch signal generation unit 342 described above employs specially designed control logic, thereby providing accurate switch control signals to ensure that multiple switches in the switch matrix 33 are turned on sequentially in a predetermined order. Furthermore, this circuit structure is simple and easy to implement.

[0042] As described above, the clock stretching unit 32 is used to generate a stretched clock signal clk_bro based on the clock signal clk_sel selected by the signal selection unit 31. The clock stretching unit 32 can use any suitable clock stretching technique to stretch the clock signal.

[0043] For example, in some embodiments, such as Figure 4 As shown, the clock stretching unit 32 includes a second additional D flip-flop 321 and an inverter 322. The clock input terminal CLK of the second additional D flip-flop 321 is connected to the output terminal of the signal selection unit 31 to receive the clock signal clk_sel selected by the signal selection unit 31. The input terminal of the inverter 322 is connected to the Q output terminal of the second additional D flip-flop 321. The output terminal of the inverter 322 is connected to the D input terminal of the second additional D flip-flop 321. The output terminal of the inverter 322 provides the stretched clock signal clk_bro.

[0044] The following will combine Figure 4 An exemplary operation of the extended clock generator 30 is described.

[0045] like Figure 4As shown, when the enable signal EN, which is at a high level (logic 1), is provided to the pulse generator 3411, the pulse generator 3411 generates a pulse signal EN_PULSE. The pulse signal EN_PULSE is applied to the SR latch 3413 via the OR gate 3412, causing the SR latch 3413 to be set to 1, thereby making the widening start signal START 1. At this time, since the selection control signal on the selection control terminal S of the multiplexer 3421 is 0, the multiplexer 3421 provides the original clock signal clk0 to the clock input terminal CLK of the multiple D flip-flops 3422. When the rising edge of the original clock signal clk0 arrives, the first D flip-flop among the multiple D flip-flops 3422 makes the control signal S1 become 1, while the control signals S2-S8 remain 0, thereby turning on the first switch 331, while the second switch 332 to the eighth switch 338 remain open. When control signal S1 becomes 1, the selection control signal on the selection control terminal S of multiplexer 3421 also becomes 1, causing multiplexer 3421 to provide the broadened clock signal clk_bro to the clock input terminal CLK of multiple D flip-flops 3422. At the rising edge of the broadened clock signal clk_bro, the multiple D flip-flops 3422 change control signal S1 to 0, control signal S2 to 1, while control signals S3-S8 remain 0, thus turning on the second switch 332 and turning off the remaining switches. At the next rising edge of the broadened clock signal clk_bro, the multiple D flip-flops 3422 change control signal S2 to 0, control signal S3 to 1, while control signals S1 and S4-S8 remain 0, thus turning on the third switch 333 and turning off the remaining switches. In this way, control signals S1-S8 can sequentially cycle to 1, thus sequentially turning on the first switch 331 to the eighth switch 338.

[0046] In addition, such as Figure 4 As shown, when the first switch 331 is turned on, the original clock signal clk0 is provided to the clock input terminal CLK of the second additional D flip-flop 321. Combined with... Figure 2 When the rising edge of the original clock signal clk0 arrives, the second additional D flip-flop 321 and inverter 322 cause the broadened clock signal clk_bro to become 1. When the second switch 332 is turned on, the delayed clock signal clk5 is provided to the clock input CLK of the second additional D flip-flop 321. Figure 2 When the rising edge of the delayed clock signal clk5 arrives, the second additional D flip-flop 321 and inverter 322 cause the stretched clock signal clk_bro to become 0. When the third switch 333 is turned on, the delayed clock signal clk2 is provided to the clock input CLK of the second additional D flip-flop 321. Figure 2When the rising edge of the delayed clock signal clk2 arrives, the second additional D flip-flop 321 and inverter 322 cause the stretched clock signal clk_bro to become 1. When the fourth switch 334 is turned on, the delayed clock signal clk7 is provided to the clock input CLK of the second additional D flip-flop 321. Figure 2 When the rising edge of the delayed clock signal clk7 arrives, the second additional D flip-flop 321 and inverter 322 cause the broadened clock signal clk_bro to become 0. In this way, by sequentially turning on the first switch 331 to the eighth switch 338, the second additional D flip-flop 321 and inverter 322 can switch the level of the broadened clock signal clk_bro between 1 and 0. Figure 2 As shown, the frequency of the broadened clock signal clk_bro is lower than that of the original clock signal clk0, and the duration of a single clock cycle of the broadened clock signal clk_bro is longer than that of a single clock cycle of the original clock signal clk0.

[0047] return Figure 1 Clock selector 40 is connected to clock buffer 10 and extended clock generator 30 to select one of the buffered clock signal clk_buf and the extended clock signal clk_bro as the circuit clock signal clk_adap based on the select signal SELECT.

[0048] The select signal can be provided in various ways. For example, returning... Figure 1The selection signal SELECT can be provided by the control unit 50. In some embodiments, when an adaptive clock signal adjustment is required in the integrated circuit, such as during power fluctuations or due to power consumption requirements or functional requirements of the integrated circuit, the control unit 50 can provide a high-level selection signal SELECT to the clock selector 40, causing the clock selector 40 to select the broadened clock signal clk_bro as the circuit clock signal clk_adap. When no adaptive clock signal adjustment is required in the integrated circuit, the control unit 50 can provide a low-level selection signal SELECT to the clock selector 40, causing the clock selector 40 to select the buffered clock signal clk_buf as the circuit clock signal clk_adap. It should be understood that in other embodiments, the control unit 50 can also provide the selection signal SELECT with the opposite level logic. In this case, the clock selector 40 can select the broadened clock signal clk_bro as the circuit clock signal clk_adap when the control unit 50 provides a low-level selection signal SELECT, and select the buffered clock signal clk_buf as the circuit clock signal clk_adap when the control unit 50 provides a high-level selection signal SELECT.

[0049] In one embodiment, clock selector 40 may include a glitch-free multiplexer. In other embodiments, clock selector 40 may also be implemented in other ways, which are not limited by the embodiments disclosed herein.

[0050] Figure 5 A timing diagram of a circuit clock signal according to an embodiment of the present disclosure is shown. Figure 5 As shown, when the enable signal EN is low, the original clock signal clk0 is used as the circuit clock signal clk_adap, with a clock period of approximately 499.468 picoseconds (ps). When the enable signal EN goes high, the broadened clock signal clk_bro is used as the circuit clock signal clk_adap, with a stable clock period of approximately 598.032 ps. Therefore, in the embodiments according to this disclosure, when adaptive clock signal adjustment is required in an integrated circuit, the clock signal can be quickly broadened to process data at a slower clock frequency, avoiding timing errors and ensuring the correctness of data transmission. Furthermore, compared to the conventional approach of using two PLLs to generate two clock frequencies, the embodiments of this disclosure can achieve adaptive clock signal adjustment at a lower cost.

[0051] Embodiments of this disclosure also provide a method 600 for generating a circuit clock signal, such as... Figure 6 As shown. Method 600 can be derived from the above combined with Figures 1 to 5 The described apparatus for generating a circuit clock signal is executed. For example... Figure 6 As shown, method 600 includes: in block 610, buffering the original clock signal clk0 to obtain a buffered clock signal clk_buf; in block 620, delaying the original clock signal clk0 to obtain a plurality of delayed clock signals clk1-clk7, wherein the plurality of delayed clock signals clk1-clk7 are delayed by different amounts of time relative to the original clock signal clk0; in block 630, generating a broadened clock signal clk_bro based on the original clock signal clk0 and the plurality of delayed clock signals clk1-clk7, wherein the frequency of the broadened clock signal clk_bro is lower than the frequency of the original clock signal clk0; and in block 640, selecting one of the buffered clock signal clk_buf and the broadened clock signal clk_bro as the circuit clock signal clk_adap based on the selection signal SELECT.

[0052] In some embodiments, delaying the original clock signal clk0 includes: delaying the original clock signal clk0 by a plurality of delay components 21 connected in sequence, wherein the number of delay components 21 is equal to the number of delayed clock signals, the original clock signal clk0 is provided to the first delay component among the plurality of delay components 21, and each delay component among the plurality of delay components 21 provides a corresponding delayed clock signal among the plurality of delayed clock signals clk1-clk7.

[0053] In some embodiments, generating a broadened clock signal clk_bro based on the original clock signal clk0 and a plurality of delayed clock signals clk1-clk7 includes: a signal selection unit 31 cyclically selecting clock signals from the original clock signal clk0 and the plurality of delayed clock signals clk1-clk7 in a predetermined order; and a clock broadening unit 32 generating the broadened clock signal clk_bro based on the clock signal clk_sel selected by the signal selection unit 31.

[0054] In some embodiments, the signal selection unit 31 cyclically selects clock signals from the original clock signal clk0 and a plurality of delayed clock signals clk1-clk7 in a predetermined order, which includes: the switch matrix control unit 34 controlling a plurality of switches of the switch matrix 33 to be cyclically turned on in sequence based on the enable signal EN, so that the original clock signal clk0 and the plurality of delayed clock signals clk1-clk7 are selected by the signal selection unit 31 in a predetermined order, wherein one end of each of the plurality of switches is coupled to the clock delay unit 20 to receive the corresponding clock signal from the original clock signal clk0 and the plurality of delayed clock signals clk1-clk7, and the other end of each of the plurality of switches is coupled to the clock stretching unit 32 to provide the clock signal selected by the signal selection unit 31 to the clock stretching unit 32.

[0055] In some embodiments, the switch matrix control unit 34 controls multiple switches of the switch matrix 33 to be turned on sequentially and cyclically based on the enable signal EN, which includes: the start unit 341 generating a broadened start signal START based on the enable signal EN; and the switch signal generation unit 342 generating a corresponding control signal for controlling multiple switches based on the broadened start signal START, so that the multiple switches are turned on sequentially and cyclically.

[0056] Embodiments of this disclosure are also embodied in the following examples.

[0057] Example 1. An apparatus for generating a circuit clock signal, comprising:

[0058] A clock buffer is configured to buffer the original clock signal to obtain a buffered clock signal.

[0059] A clock delay unit is configured to delay the original clock signal to obtain a plurality of delayed clock signals, wherein the plurality of delayed clock signals are delayed by different amounts of time relative to the original clock signal;

[0060] A broadened clock generator is configured to generate a broadened clock signal based on the original clock signal and the plurality of delayed clock signals, wherein the frequency of the broadened clock signal is lower than the frequency of the original clock signal; and

[0061] A clock selector is configured to select one of the buffered clock signal and the stretched clock signal as the circuit clock signal based on a selection signal.

[0062] Example 2. The apparatus according to Example 1, wherein the clock delay unit comprises a plurality of delay components connected in sequence, the number of delay components being equal to the number of delayed clock signals, the original clock signal being provided to a first delay component of the plurality of delay components, and each delay component of the plurality of delay components providing a corresponding delayed clock signal among the plurality of delayed clock signals.

[0063] Example 3. The apparatus according to Example 2, wherein each of the plurality of delay components is configured to provide the same amount of delay.

[0064] Example 4. The apparatus according to Example 1, wherein the stretched clock generator comprises:

[0065] A signal selection unit is configured to cyclically select clock signals from the original clock signal and the plurality of delayed clock signals in a predetermined order; and

[0066] The clock stretching unit is configured to generate the stretched clock signal based on the clock signal selected by the signal selection unit.

[0067] Example 5. The apparatus according to Example 4, wherein the signal selection unit comprises:

[0068] A switch matrix, comprising a plurality of switches, wherein one end of each switch is coupled to the clock delay unit to receive the original clock signal and a corresponding clock signal from the plurality of delayed clock signals, and the other end of each switch is coupled to the clock stretching unit to provide the clock signal selected by the signal selection unit to the clock stretching unit; and

[0069] The switch matrix control unit is configured to control the plurality of switches to be turned on sequentially and cyclically based on an enable signal, so that the original clock signal and the plurality of delayed clock signals are selected by the signal selection unit in the predetermined order.

[0070] Example 6. The apparatus according to Example 5, wherein the switch matrix control unit comprises:

[0071] The startup unit is configured to generate a broadened startup signal based on the enable signal; and

[0072] The switch signal generation unit is configured to generate corresponding control signals for controlling the plurality of switches based on the broadened start signal, so that the plurality of switches are turned on sequentially in a cyclic manner.

[0073] Example 7. The apparatus according to Example 6, wherein the activation unit comprises:

[0074] A pulse generator is configured to generate a pulse signal based on the enable signal;

[0075] An OR gate, one input of which receives the pulse signal, and the other input of which receives the control signal of the last of the plurality of switches; and

[0076] The SR latch has its S input connected to the output of the OR gate, its R input receiving the control signal of the first switch among the plurality of switches, and its output providing the widening start signal.

[0077] Example 8. The apparatus according to Example 6, wherein the switch signal generation unit comprises:

[0078] A multiplexer, one input of which receives the broadened clock signal, and the other input of which receives the original clock signal;

[0079] A plurality of D flip-flops are connected in series. The D input of the first D flip-flop receives the widening start signal. The D inputs of the other D flip-flops (excluding the first one) are connected to the Q output of the preceding D flip-flop. The clock inputs of the D flip-flops are connected to the output of the multiplexer. The Q outputs of the D flip-flops respectively provide the control signals for the plurality of switches.

[0080] The first additional D flip-flop has its clock input connected to the Q output of the first D flip-flop, its D input receiving the enable signal, and its Q output connected to the selection control terminal of the multiplexer.

[0081] Example 9. The apparatus according to Example 4, wherein the clock stretching unit comprises:

[0082] The second additional D flip-flop receives a clock signal selected by the signal selection unit at its clock input; and

[0083] An inverter, the input of which is connected to the Q output of the second additional D flip-flop, the output of which is connected to the D input of the second additional D flip-flop, and the output of which provides the stretched clock signal.

[0084] Example 10. A method for generating a circuit clock signal, comprising:

[0085] The original clock signal is buffered to obtain a buffered clock signal;

[0086] The original clock signal is delayed to obtain multiple delayed clock signals, each of which is delayed by a different amount of time relative to the original clock signal.

[0087] A broadened clock signal is generated based on the original clock signal and the plurality of delayed clock signals, wherein the frequency of the broadened clock signal is lower than the frequency of the original clock signal; and

[0088] The circuit clock signal is selected from either the buffered clock signal or the stretched clock signal based on a selection signal.

[0089] Example 11. The method according to Example 10, wherein delaying the original clock signal includes:

[0090] The original clock signal is delayed by a plurality of delay components connected in sequence, the number of delay components being equal to the number of delayed clock signals. The original clock signal is provided to the first delay component among the plurality of delay components, and each delay component among the plurality of delay components provides a corresponding delayed clock signal among the plurality of delayed clock signals.

[0091] Example 12. The method according to Example 10, wherein generating the broadened clock signal based on the original clock signal and the plurality of delayed clock signals comprises:

[0092] The signal selection unit cyclically selects a clock signal from the original clock signal and the plurality of delayed clock signals in a predetermined order; and

[0093] The clock stretching unit generates the stretched clock signal based on the clock signal selected by the signal selection unit.

[0094] Example 13. The method according to Example 12, wherein the signal selection unit cyclically selects clock signals from the original clock signal and the plurality of delayed clock signals in a predetermined order, comprising:

[0095] The switch matrix control unit controls multiple switches of the switch matrix to be turned on sequentially and cyclically based on an enable signal, so that the original clock signal and the multiple delayed clock signals are selected by the signal selection unit in the predetermined order. One end of each of the multiple switches is coupled to the clock delay unit to receive the corresponding clock signal from the original clock signal and the multiple delayed clock signals, and the other end of each of the multiple switches is coupled to the clock stretching unit to provide the clock signal selected by the signal selection unit to the clock stretching unit.

[0096] Example 14. The method according to Example 13, wherein controlling multiple switches of the switch matrix by the switch matrix control unit based on an enable signal to sequentially and cyclically turn on includes:

[0097] The startup unit generates a broadened startup signal based on the enable signal; and

[0098] The switch signal generation unit generates corresponding control signals for controlling the plurality of switches based on the broadened start signal, so that the plurality of switches are turned on in sequence.

[0099] Various implementations of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed implementations. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described implementations. The terminology used herein is chosen to best explain the principles, practical applications, or improvements to technology in the market, or to enable others skilled in the art to understand the various implementations disclosed herein.

Claims

1. An apparatus for generating a circuit clock signal, comprising: A clock buffer (10) is configured to buffer the original clock signal to obtain a buffered clock signal; The clock delay unit (20) is configured to delay the original clock signal to obtain a plurality of delayed clock signals, wherein the plurality of delayed clock signals are delayed by different amounts of time relative to the original clock signal; A clock stretching generator (30) is configured to generate a stretched clock signal based on the original clock signal and the plurality of delayed clock signals, wherein the frequency of the stretched clock signal is lower than the frequency of the original clock signal, wherein the clock stretching generator (30) includes: a signal selection unit (31) configured to cyclically select clock signals from the original clock signal and the plurality of delayed clock signals in a predetermined order; and a clock stretching unit (32) configured to generate the stretched clock signal based on the clock signal selected by the signal selection unit (31); wherein the signal selection unit (31) includes: a switch matrix (33) containing... The system includes multiple switches, one end of each of which is coupled to the clock delay unit (20) to receive the original clock signal and a corresponding clock signal from the plurality of delayed clock signals, and the other end of each of which is coupled to the clock stretching unit (32) to provide the clock signal selected by the signal selection unit (31) to the clock stretching unit (32); and a switch matrix control unit (34) configured to control the plurality of switches to be cyclically turned on sequentially based on an enable signal, such that the original clock signal and the plurality of delayed clock signals are selected by the signal selection unit (31) in the predetermined order; and A clock selector (40) is configured to select one of the buffered clock signal and the stretched clock signal as the circuit clock signal based on a selection signal.

2. The apparatus according to claim 1, wherein the clock delay unit (20) comprises a plurality of delay components (21) connected in sequence, the number of delay components (21) being equal to the number of delayed clock signals, the original clock signal being provided to the first delay component among the plurality of delay components (21), and each delay component among the plurality of delay components (21) providing a corresponding delayed clock signal among the plurality of delayed clock signals.

3. The apparatus of claim 2, wherein each of the plurality of delay components (21) is configured to provide the same amount of delay.

4. The apparatus according to claim 1, wherein the switch matrix control unit (34) comprises: The startup unit (341) is configured to generate a broadened startup signal based on the enable signal; as well as The switch signal generation unit (342) is configured to generate corresponding control signals for controlling the plurality of switches based on the broadened start signal, so that the plurality of switches are turned on in sequence.

5. The apparatus according to claim 4, wherein the starting unit (341) comprises: A pulse generator (3411) is configured to generate a pulse signal based on the enable signal; OR gate (3412), one of its inputs receives the pulse signal, and the other of its inputs receives the control signal of the last of the plurality of switches; as well as The SR latch (3413) has its S input connected to the output of the OR gate (3412), its R input receiving the control signal of the first of the plurality of switches, and its output providing the widening start signal.

6. The apparatus according to claim 4, wherein the switch signal generation unit (342) comprises: A multiplexer (3421) has one input receiving the widened clock signal and the other input receiving the original clock signal; A plurality of D flip-flops (3422) are connected in series. The D input of the first D flip-flop (3422) receives the widening start signal. The D inputs of the other D flip-flops (3422) are connected to the Q output of the preceding D flip-flop. The clock inputs of the plurality of D flip-flops (3422) are connected to the output of the multiplexer (3421). The Q outputs of the plurality of D flip-flops (3422) respectively provide the control signals for the plurality of switches. as well as The first additional D flip-flop (3423) has its clock input connected to the Q output of the first D flip-flop, its D input receiving the enable signal, and its Q output connected to the selection control terminal of the multiplexer (3421).

7. The apparatus of claim 1, wherein the clock stretching unit (32) comprises: The second additional D flip-flop (321) receives the clock signal selected by the signal selection unit (31) at its clock input terminal; as well as An inverter (322) is connected to the Q output of the second additional D flip-flop (321), and its output is connected to the D input of the second additional D flip-flop (321). The output of the inverter (322) provides the stretched clock signal.

8. A method for generating a circuit clock signal, comprising: The original clock signal is buffered to obtain a buffered clock signal; The original clock signal is delayed to obtain multiple delayed clock signals, each of which is delayed by a different amount of time relative to the original clock signal. A broadened clock signal is generated based on the original clock signal and the plurality of delayed clock signals, wherein the frequency of the broadened clock signal is lower than the frequency of the original clock signal. Generating the broadened clock signal includes: a signal selection unit cyclically selecting clock signals from the original clock signal and the plurality of delayed clock signals in a predetermined order; and a clock broadening unit generating the broadened clock signal based on the clock signals selected by the signal selection unit. The cyclic selection of clock signals includes: a switch matrix control unit controlling a plurality of switches of a switch matrix to be cyclically turned on sequentially based on an enable signal, such that the original clock signal and the plurality of delayed clock signals are selected by the signal selection unit in the predetermined order. One end of each of the plurality of switches is coupled to a clock delay unit to receive a corresponding clock signal from the original clock signal and the plurality of delayed clock signals, and the other end of each of the plurality of switches is coupled to the clock broadening unit to provide the clock signal selected by the signal selection unit to the clock broadening unit. The circuit clock signal is selected from either the buffered clock signal or the stretched clock signal based on a selection signal.

9. The method of claim 8, wherein delaying the original clock signal comprises: The original clock signal is delayed by a plurality of delay components connected in sequence, the number of delay components being equal to the number of delayed clock signals. The original clock signal is provided to the first delay component among the plurality of delay components, and each delay component among the plurality of delay components provides a corresponding delayed clock signal among the plurality of delayed clock signals.

10. The method of claim 8, wherein controlling a plurality of switches of the switch matrix to be cyclically turned on sequentially based on an enable signal by the switch matrix control unit comprises: The startup unit generates a broadened startup signal based on the enable signal; as well as The switch signal generation unit generates corresponding control signals for controlling the plurality of switches based on the broadened start signal, so that the plurality of switches are turned on in sequence.

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