Secure device comprising a physically unclonable function unit, and puf unit device operating method

Abstract

A security device includes: a physical unclonable function (PUF) cell array including a plurality of PUF cells connected with a first word line; a controller selecting a target PUF cell among the plurality of PUF cells and outputting a control signal based on the target PUF cell; a decoder applying a first voltage to the first word line in response to the control signal; a bit line selection circuit outputting a target current passing through a bit line connected with the target PUF cell and a sum current corresponding to a sum of currents passing through remaining bit lines connected with other PUF cells; and a bit determiner outputting a target bit of the target PUF cell based on the target current and the sum current, and the security device generating a security key based on the target bit for responding to an authentication request.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0138808, filed on November 1, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The embodiments of the inventive concept disclosed herein relate to security devices, and more specifically, to security devices including physically unclonable function (PUF) units and methods of operating such devices. Background Technology

[0004] Technologies associated with security and encryption are crucial for communication and mobile devices. In cryptography, a key is a piece of information that determines the functional output of a cryptographic algorithm. When keys are generated using software on a system connected to a network, unauthorized users can obtain them by intruding into the system. Therefore, hardware-based security technologies are being developed.

[0005] Security devices based on Physically Unclonable Function (PUF) randomly generate unique keys based on the device's process, voltage, and temperature (PVT). However, errors may occur in the keys due to various environmental factors. This error reduces the reliability of the PUF device. Summary of the Invention

[0006] At least one exemplary embodiment of the present invention provides a security device including a physically unclonable function (PUF) unit with improved reliability and reduced circuit complexity, a method of operating the security device, and a method of operating the physically unclonable function unit device.

[0007] According to an exemplary embodiment, a security device includes: a Physically Unclonable Function (PUF) cell array including a plurality of first PUF cells connected to a first word line; a controller that selects a target PUF cell among the plurality of first PUF cells and outputs a control signal indicating the selected target PUF cell; a decoder that applies a first voltage to the first word line in response to the control signal; a bit line selection circuit connected to a plurality of first bit lines and outputting a first target current and a first sum current, the first target current passing through a bit line among the plurality of first bit lines connected to the target PUF cell, and the first sum current corresponding to the sum of currents passing through the remaining bit lines connected to other PUF cells among the plurality of first PUF cells; and a bit determiner that outputs a target bit of the target PUF cell based on the first target current and the first sum current, and the security device generates a security key based on the target bit for responding to an authentication request.

[0008] According to an exemplary embodiment, an operating method of a physical unclonable function (PUF) cell device including a plurality of PUF cells includes selecting a target PUF cell among the plurality of PUF cells, applying a first voltage to a first word line connected with the target PUF cell, generating a target value based on a target current corresponding to the target PUF cell and a center value based on a sum current corresponding to a sum of currents output from other PUF cells connected with the first word line, determining a target bit of the target PUF cell based on the target value and the center value, and generating a security key based on the target bit for responding to an authentication request.

[0009] According to an exemplary embodiment, an operating method of a security device including first to N-th physical unclonable function (PUF) cells includes applying a first voltage to a first word line connected with the first to N-th PUF cells, obtaining first information from the first PUF cell and second information from the second to N-th PUF cells, determining a first bit of the first PUF cell from the obtained first information and the obtained second information, applying the first voltage to the first word line connected with the first to N-th PUF cells, obtaining third information from the second PUF cell and fourth information from the first PUF cell and the third to N-th PUF cells, determining a second bit of the second PUF cell based on the obtained third information and the fourth information, and generating a security key based on the first bit and the second bit for responding to an authentication request, where N is a positive integer. BRIEF DESCRIPTION OF DRAWINGS

[0010] The inventive concept will become apparent by reference to exemplary embodiments thereof as described in detail hereinafter.

[0011] FIG. 1 is a block diagram illustrating a security device according to an exemplary embodiment of the inventive concept.

[0012] FIG. 2 is a diagram for describing a method of determining a target bit of a PUF cell.

[0013] FIG. 3 is a block diagram of a PUF cell device according to an exemplary embodiment of the inventive concept. FIG. 1

[0014] FIG. 4 is a diagram illustrating an exemplary structure of a plurality of PUF cells of FIG. 3

[0015] FIG. 5 is a diagram illustrating a configuration of a PUF cell device of FIG. 3

[0016] ​​​FIG. 6 is a flowchart illustrating FIG. 3 and FIG. 5 operation of a PUF cell device.

[0017] FIG. 7 is a diagram for describing FIG. 3 operation of a PUF cell device.

[0018] FIG. 8 is a diagram for describing a target bit determination method of a PUF cell device according to an exemplary embodiment of the inventive concept. FIG. 3

[0019] FIG. 9 is a diagram illustrating a PUF cell array according to an exemplary embodiment of the inventive concept.

[0020] FIG. 10A is a diagram illustrating FIG. 9 an exemplary PUF cell device to which a PUF cell array of

[0021] FIG. 10B to FIG. 10D is a diagram for describing operation of a PUF cell device according to an exemplary embodiment of the inventive concept. FIG. 10A

[0022] FIG. 11 is a diagram for describing a way to improve reliability of a PUF cell device.

[0023] FIG. 12A is a flowchart for describing operation of a stable PUF cell or an effective PUF cell of a PUF cell device according to an exemplary embodiment of the inventive concept. FIG. 1

[0024] FIG. 12B is a diagram for describing operation of a stable PUF cell or an effective PUF cell of a PUF cell device. FIG. 1

[0025] FIG. 13A and FIG. 13B are diagrams for describing operation of a flowchart according to FIG. 12A

[0026] FIG. 14 is a block diagram illustrating a controller of FIG. 1 according to an exemplary embodiment of the inventive concept.

[0027] FIG. 15 is a diagram for describing operation of a PUF cell device according to an exemplary embodiment of the inventive concept.

[0028] FIG. 16A ​​​​​is a block diagram for describing an operation of a security device according to an exemplary embodiment of the present inventive concept.

[0029] FIG. 16B and FIG. 16C is a flowchart for describing an operation of a security device according to an exemplary embodiment of the present inventive concept.

[0030] FIG. 17 is a block diagram illustrating an electronic system to which a security device according to an exemplary embodiment of the present inventive concept is applied.

[0031] FIG. 18 is a block diagram illustrating an electronic device to which a security device according to an exemplary embodiment of the present inventive concept is applied. DETAILED DESCRIPTION

[0032] Hereinafter, embodiments of the present inventive concept will be described in detail with reference to the accompanying drawings, so that the present inventive concept can be easily implemented by those skilled in the art.

[0033] The components described in the detailed description with reference to the terms "component", "unit", "module", "layer", etc. and the functional blocks shown in the drawings can be implemented in the form of software, hardware, or a combination thereof. For example, the software can be machine code, firmware, embedded code, and application software. For example, the hardware can include a circuit, an electronic circuit, a processor, a computer, an integrated circuit, an integrated circuit core, a pressure sensor, an inertial sensor, a micro electro mechanical system (MEMS), a passive element, or a combination thereof.

[0034] Further, unless differently defined, all terms used herein, including technical or scientific terms or terminologies, have the same meanings as those that are generally understood by those skilled in the art to which the present inventive concept pertains. Terms defined in a dictionary should be interpreted as having a same meaning as the relevant technical terms used in the related art, and should not be interpreted to have ideal or over formal meanings unless explicitly defined in the specification.

[0035] Hereinafter, in order to describe the present inventive concept, a plurality of exemplary components or exemplary numerical values are provided, but the present inventive concept is not limited thereto. For example, in the following drawings, an example of eight PUF cells connected to one word line is shown for the sake of simplicity of illustration. However, the present inventive concept is not limited thereto, because the example is used only for describing the present inventive concept.

[0036] FIG. 1 is a block diagram of a security device according to an exemplary embodiment of the present inventive concept. FIG. 2 is a diagram for describing a method of determining a target bit of a PUF cell. FIG. 2 A horizontal axis of the distribution of indicates information (e.g., mismatch information or current amount) obtained from the PUF cell. Referring toFIG. 1 and FIG. 2 The security device 10 includes an array-based physically unclonable function (PUF) cell device 100 (e.g., a semiconductor device) and a controller 101 (e.g., a control circuit).

[0037] The array-based PUF cell device 100 can include a plurality of PUF cells. The plurality of PUF cells can be arranged in the form of an array. Hereinafter, for the convenience of description, the array-based PUF cell device 100 will be simply referred to as a "PUF cell device 100".

[0038] In an exemplary embodiment, each of the plurality of PUF cells can be implemented with at least one of various kinds of PUFs, such as a transistor-based threshold voltage PUF cell, an arbiter-based PUF cell (e.g., a feed-forward PUF cell, an XOR PUF cell in which arbiter PUF cells are arranged in parallel, or a lightweight PUF cell), a ring oscillator-based PUF cell, a memory-based PUF cell (e.g., a static random access memory (SRAM) PUF cell, a latch PUF cell, a flash PUF cell, or a memristor PUF cell), and a PUF cell that can be reconfigured according to a laser beam or heat variation.

[0039] Hereinafter, for the convenience of describing the inventive concept, it is assumed that each of the plurality of PUF cells is a transistor-based threshold voltage PUF cell. However, the inventive concept is not limited thereto. For example, each of the plurality of PUF cells can be implemented with various types of PUF cells.

[0040] The PUF cell device 100 is configured to output a target bit TB under the control of the controller 101. The controller 101 controls the PUF cell device 100. For example, the controller 101 provides a control signal CTRL to the PUF cell device 100. The control signal CTRL can include information or an address for selecting a target PUF cell among the plurality of PUF cells included in the PUF cell device 100. For example, the control signal can uniquely identify the target PUF cell.

[0041] The PUF cell device 100 can select the target PUF cell among the plurality of PUF cells in response to the control signal CTRL received from the controller 101, and can output a target bit TB corresponding to the selected target PUF cell.

[0042] The controller 101 can receive target bits TB associated with all or some of the plurality of PUF cells included in the PUF cell device 100, and can generate and output a security key KEY based on the received target bits TB.

[0043] In an exemplary embodiment, the plurality of PUF cells can have different process, voltage, and temperature (PVT) variations. Each of the plurality of PUF cells can output different information depending on the corresponding PVT variation even if the same bias (e.g., bias current, bias voltage, etc.) is provided to the plurality of PUF cells. For example, the plurality of PUF cells can have different PVT variations due to various factors (e.g., doping concentration, thickness and geometry of gate oxide layer) even if the plurality of PUF cells are fabricated by the same semiconductor process or on the same wafer.

[0044] That is, even if the first PUF cell and the second PUF cell are fabricated by the same semiconductor process or on the same wafer, the information output from the first PUF cell can have a positive polarity while the information output from the second PUF cell can have a negative polarity. Alternatively, the magnitude or value of the information output from the first PUF cell and the magnitude or value of the information output from the second PUF cell can be different.

[0045] A target bit TB associated with each of the plurality of PUF cells can be determined based on the information of each PUF cell. For example, the plurality of pieces of information output from the plurality of PUF cells included in the PUF cell device 100 can form a first distribution DB1 as illustrated. In an exemplary embodiment, the first distribution DB1 can be a Gaussian distribution or a normal distribution. A center value (e.g., peak value) of the first distribution DB1 can be used as a reference value REF0 for determining the polarity of each of the plurality of PUF cells. For example, a PUF cell having information less than the center value can be considered to have a negative polarity, and a PUF cell having information greater than or equal to the center value can be considered to have a positive polarity. FIG. 2

[0046] The exemplary PUF cell device determines the target bit of the target PUF cell by collecting analog information of the target PUF cell, converting the collected analog information into digital data via an analog-to-digital converter, and comparing the converted digital data with reference data (i.e., the reference value REF0).

[0047] However, the PUF cell device 100 according to an exemplary embodiment of the inventive concept determines the target bit TB of the target PUF cell without using a separate analog-to-digital converter and separate reference data. For example, the PUF cell device 100 according to an exemplary embodiment of the inventive concept can determine the target bit TB by generating or calculating a center value based on other PUF cells corresponding to the target PUF cell among the plurality of PUF cells, and comparing a target value corresponding to the target PUF cell with the center value. The structure and operation of the PUF cell device 100 according to an exemplary embodiment of the inventive concept will be described below with reference to the accompanying drawings.

[0048] ​FIG. 3 is a block diagram of a PUF cell device according to an example embodiment of the inventive concept. FIG. 1 is a block diagram of a PUF cell device according to an example embodiment of the inventive concept. For simplicity of illustration, an example is shown as a plurality of PUF cells PC arranged in an 8x8 matrix, but the inventive concept is not limited thereto. The PUF cell array 110 can further include additional PUF cells, and thus, the number of word lines and the number of bit lines can increase. In an example embodiment, the number of PUF cells PC connected to one word line is at least "N". In this case, "N" indicates a minimum number of PUF cells, the value of which forms a normal distribution or a Gaussian distribution. In an example embodiment, "N" can be in the range of 4 to 256.

[0049] For convenience of description, it is assumed that information obtained from each of the plurality of PUF cells PC is a current generated according to a word line bias of each of the plurality of PUF cells PC. However, the inventive concept is not limited thereto. For example, information obtained from a PUF cell can be variously changed or modified depending on the type of the PUF cell.

[0050] Referring to FIG. 1 and FIG. 3 , the PUF cell device 100 includes a PUF cell array 110, a decoder 120 (e.g., a decoder circuit), a bit line selection circuit 130, a bit determiner 140 (e.g., a circuit), and a voltage regulator 150.

[0051] The PUF cell array 110 includes a plurality of PUF cells PC. The plurality of PUF cells PC can be arranged in a row direction and a column direction to form an array. The plurality of PUF cells PC can be connected with a plurality of word lines WL1 to WL8 and a plurality of bit lines BL1 to BL8. Each of the plurality of PUF cells PC can be configured to output a current depending on a bias (e.g., a bias current, a bias voltage, etc.) of a corresponding word line among the plurality of word lines WL1 to WL8. As described above, the current output from each of the plurality of PUF cells PC can have a value that varies depending on physical characteristics or environmental conditions of each of the plurality of PUF cells PC.

[0052] The decoder 120 receives and decodes a control signal CTRL from the controller 101. For example, the control signal CTRL can include address information corresponding to a target PUF cell among the plurality of PUF cells PC, which is to determine its target bit TB. The decoder 120 decodes the address information corresponding to the target PUF cell and controls the plurality of word lines WL1 to WL8 based on a decoding result. The decoder 120 provides a bit line selection signal BS to the bit line selection circuit 130 based on the decoding result. The bit line selection signal BS can be a signal for selecting a bit line corresponding to the target PUF cell from among the plurality of bit lines BL1 to BL8.

[0053] The bit line selection circuit 130 receives a bit line selection signal BS from the decoder 120 and controls a plurality of bit lines BL1 to BL8 based on the received bit line selection signal BS. For example, assume that the bit line selection signal BS corresponds to the third bit line BL3. In this case, the bit line selection circuit 130 outputs a signal (e.g., a current) received through the third bit line BL3 as a target current I_tg and outputs a sum of signals (e.g., currents) received from the remaining bit lines BL1, BL2, and BL4 to BL8 as a sum current I_sum.

[0054] The bit determiner 140 receives the target current I_tg and the sum current I_sum. The bit determiner 140 determines a target bit TB of a target PUF cell based on the target current I_tg and the sum current I_sum. For example, the bit determiner 140 can divide the sum current I_sum by a given value. In an exemplary embodiment, the given value is a value obtained by subtracting "1" from the number of PUF cells PC connected to one bit line (e.g., N-1). That is, as described above, in a case where the target current I_tg is provided from one of the PUF cells PC connected to the third bit line BL3 and the sum current I_sum is provided from the PUF cells PC connected to the first bit line BL1, the second bit line BL2, and the fourth bit line BL4 to the eighth bit line BL8 (i.e., 7 PUF cells PC), the sum current I_sum is divided by "7". That is, the bit determiner 140 calculates an average current of a unit PUF cell based on the sum current I_sum.

[0055] The bit determiner 140 compares the magnitude of the calculated average current with the magnitude of the target current I_tg and determines the target bit TB of the target PUF cell depending on the result of the comparison.

[0056] The voltage regulator 150 provides a voltage "V" to be applied to a plurality of word lines WL1 to WL8 to the decoder 120. In an exemplary embodiment, bias voltages or active voltages (or bias currents) to be respectively provided to the plurality of word lines WL1 to WL8 have the same level. Alternatively, the bias voltages or active voltages to be respectively provided to the plurality of word lines WL1 to WL8 vary depending on physical characteristics of the plurality of PUF cells PC. Alternatively, the bias voltages or active voltages to be respectively provided to the plurality of word lines WL1 to WL8 can have different levels such that information collected from the plurality of PUF cells PC forms a normal distribution or a Gaussian distribution.

[0057] FIG. 4 is a diagram illustrating an exemplary structure of a plurality of PUF cells of FIG. 3 Referring to FIG. 3 and FIG. 4Any one of the multiple PUF cells PC, PCa, includes a first transistor TR1. The gate of the first transistor TR1 is connected to the word line WL, its drain is connected to the bit line BL, and its source is connected to receive a specific voltage level. The first transistor TR1 can control the magnitude of the current output to the bit line BL depending on the level of the word line WL. In this case, the magnitude of the current can vary depending on the physical characteristics of the first transistor TR1. That is, even if the multiple PUF cells PC are formed with the same structure as “PCa” and the same word line bias is applied to each of the multiple PUF cells PC, the current flowing through the bit line BL can vary depending on the physical characteristics of each PUF cell.

[0058] Alternatively, any one of the plurality of PUF cells PC includes a first transistor TR1 and a second transistor TR2. The first transistor TR1 and the second transistor TR2 are connected in series between a node providing a specific voltage level and the bit line BL, and can operate depending on the level of the word line WL. As described above, even if the plurality of PUF cells PC are formed with the same structure as “PCb” and the same word line bias is applied to each of the plurality of PUF cells PC, the current flowing through the bit line BL can vary depending on the physical characteristics of each PUF cell.

[0059] Reference FIG. 4 The transistor-based PUF units PCa and PCb described are for illustrative purposes only and are not intended to limit the scope of the invention. Multiple PUF units PC can be implemented in a variety of ways using the various structures described above.

[0060] FIG. 5 This illustrates an exemplary embodiment based on the concept of the present invention. FIG. 3 A diagram illustrating the configuration of the PUF unit device. For the sake of simplicity, an example is shown where the PUF unit array 110 includes first PUF units PC1 to eighth PUF units PC8 connected to the first word line WL1, but the inventive concept is not limited thereto. For example, the PUF unit array 110 may further include additional PUF units connected to multiple word lines and multiple bit lines. For the sake of simplicity, some components (such as decoder 120 and voltage regulator 150) are omitted.

[0061] Reference FIG. 3 and FIG. 5The PUF cell device 100 includes a PUF cell array 110, a bit line selection circuit 130, and a bit determiner 140. The PUF cell array 110 can include first to eighth PUF cells PC1 to PC8. The first to eighth PUF cells PC1 to PC8 are connected with a first word line WL1. The first to eighth PUF cells PC1 to PC8 are connected with first to eighth bit lines BL1 to BL8, respectively. The first to eighth PUF cells PC1 to PC8 output first to eighth currents I1 to I8 through the first to eighth bit lines BL1 to BL8, respectively, in response to a first voltage V1 provided to the first word line WL1. The first voltage V1 can be provided by a voltage regulator 150.

[0062] The bit line selection circuit 130 includes first to eighth selectors SEL1 to SEL8. The first to eighth selectors SEL1 to SEL8 are connected with the first to eighth bit lines BL1 to BL8, respectively. The first to eighth selectors SEL1 to SEL8 operate in response to bit line selection signals BS1 to BS8 and inverted bit line selection signals / BS1 to / BS8.

[0063] For example, the first selector SEL1 includes a first transistor configured to provide the first current I1 output from the first bit line BL1 to a second converter 142 of the bit determiner 140 in response to the first bit line selection signal BS1, and a second transistor configured to provide the first current I1 output from the first bit line BL1 to a first converter 141 of the bit determiner 140 in response to the inverted bit line selection signal / BS1. Similarly to the above description, the remaining selectors SEL2 to SEL8 can also operate in response to corresponding bit line selection signals BS2 to BS8 and corresponding inverted bit line selection signals / BS2 to / BS8, and thus, additional description is omitted to avoid repetition.

[0064] In an exemplary embodiment, each of the bit line selection signals BS1 to BS8 is a signal for selecting a bit line corresponding to a target PUF cell, and each of the inverted bit line selection signals / BS1 to / BS8 is a signal for selecting a bit line corresponding to each of the remaining PUF cells. For example, assume that the target PUF cell is the third PUF cell PC3. In this case, the third bit line selection signal BS3 is activated, and the first inverted bit line selection signal / BS1, the second inverted bit line selection signal / BS2, and the fourth inverted bit line selection signal / BS4 to the eighth inverted bit line selection signal / BS8 are activated. In this way, the third current I3 output through the third bit line BL3 is supplied to the second converter 142, and the first current I1, the second current I2, and the fourth current I4 to the eighth current I8 output from the first bit line BL1, the second bit line BL2, and the fourth bit line BL4 to the eighth bit line BL8 are supplied to the first converter 141 as the sum current I_sum.

[0065] The bit determiner 140 includes the first converter 141, the second converter 142, and a comparator COMP (e.g., an operational amplifier or other comparison circuit). The first converter 141 can be connected with transistors included in the plurality of selectors SEL1 to SEL8 and operated in response to the inverted bit line selection signals / BS1 to / BS8. The second converter 142 can be connected with transistors included in the plurality of selectors SEL1 to SEL8 and operated in response to the bit line selection signals BS1 to BS8.

[0066] That is, as described above, the first converter 141 receives the sum current I_sum corresponding to the sum of the currents output from the remaining PUF cells except for the target PUF cell, and the second converter 142 receives the target current I_tg output from the target PUF cell. The first converter 141 converts the received sum current I_sum to output the center value CV, and the second converter 142 converts the target current I_tg to output the target value TV.

[0067] In an exemplary embodiment, the center value CV and the target value TV are voltage levels corresponding to the sum current I_sum and the target current I_tg, respectively. That is, the first converter 141 and the second converter 142 can be current-voltage converters. However, the inventive concept is not limited thereto. For example, each of the first converter 141 and the second converter 142 can be implemented with a current mirror configured to replicate a received current at a given ratio.

[0068] In an exemplary embodiment, the first converter 141 determines the center value CV by dividing the sum current I_sum by a given value. That is, the first converter 141 can provide a function of a divider DIV configured to divide the sum current I_sum by the given value. For example, the first converter 141 can include a divider or a divider circuit to divide the sum current I_sum by the given value. For example, as described above, in a case where the target PUF cell is the third PUF cell PC3, the sum current I_sum can be a sum of currents (e.g., I1, I2, and I4 to I8) output from 7 PUF cells (e.g., PC1, PC2, and PC4 to PC8). That is, the first converter 141 can calculate a current value corresponding to the center value CV by dividing the sum current I_sum by "7". In an exemplary embodiment, the center value CV indicates a center value of a normal distribution or a Gaussian distribution formed by information obtained from a plurality of PUF cells PC1 to PC8 connected to the first word line WL1 (however, the number of PUF cells is greater than 8). That is, in a case where the number of the plurality of PUF cells is a certain number or more (e.g., 4 to 256 or more), the remaining PUF cells except for the target PUF cell among the plurality of PUF cells can form a normal distribution or a Gaussian distribution, and thus the center value CV can be calculated by using the remaining PUF cells.

[0069] In an exemplary embodiment, a division ratio of the first converter 141 is determined based on the number of PUF cells corresponding to the sum current I_sum. In an exemplary embodiment, the division ratio of the first converter 141 can be greater or less than the number of PUF cells corresponding to the sum current I_sum by a given value.

[0070] In an exemplary embodiment, the second converter 142 determines the target value TV without performing a separate division operation on the target current I_tg. Alternatively, the second converter 142 determines the target value TV by dividing the target current I_tg based on a given ratio. In an exemplary embodiment, a second division ratio of the second converter 142 is based on a first division ratio of the first converter 141. In an exemplary embodiment, the second division ratio of the second converter 142 is less than the first division ratio of the first converter 141.

[0071] The comparator COMP receives the center value CV from the first converter 141 and receives the target value TV from the second converter 142. The comparator COMP compares the center value CV and the target value TV and outputs the target bit TB as a comparison result.

[0072] As described above, the PUF cell device 100 according to an exemplary embodiment of the present invention determines the target bit TB of the target PUF cell by using some of the calculated center values ​​CV in a plurality of PUF cells PCs without separate analog-to-digital converters and separate reference data, and by comparing the calculated center value CV with the target value TV of the target PUF cell. Therefore, the circuit complexity of the PUF device 100 is reduced, and a PUF cell device 100 with improved reliability can be implemented.

[0073] FIG. 6 This illustrates an exemplary embodiment based on the concept of the present invention. FIG. 3 and FIG. 5 The flowchart for the operation of the PUF unit device is shown below. (Refer to...) FIG. 3 , FIG. 5 and FIG. 6 In operation S110, PUF unit device 100 selects a target PUF unit. For example, PUF unit device 100 can receive a control signal CTRL from controller 101 and can select a target PUF unit from multiple PUF unit PCs based on the received control signal CTRL.

[0074] In operation S120, the PUF cell device 100 provides a first voltage V1 to the word line corresponding to the selected target PUF cell. In an exemplary embodiment, the first voltage V1 may have a level for obtaining different magnitudes of current from a plurality of PUF cells connected to the first word line WL1.

[0075] In operation S130, PUF unit device 100 generates a center value CV. For example, as shown in reference... FIG. 5 The PUF unit device 100 can obtain a sum current I_sum corresponding to the sum of currents of the remaining PUF units (excluding the target PUF unit) among the plurality of PUF units connected to the word line, and can generate a center value CV based on the obtained sum current I_sum.

[0076] In operation S140, the PUF unit device 100 compares the target value TV and the center value CV. For example, as shown in reference... FIG. 5 The target value TV can be a value corresponding to the target current I_tg obtained from the target PUF cell, and the center value CV can be a value generated based on the sum of currents I_sum obtained from the other PUF cells. The PUF cell device 100 can determine whether the target value TV is greater than the center value CV.

[0077] When the target value TV is greater than the center value CV, in operation S151, the PUF cell device 100 sets the target bit TB to a first value (e.g., "bit 1"). When the target value TV is less than the center value CV, in operation S152, the PUF cell device 100 sets the target bit TB to a second value (e.g., "bit 0") different from the first value. In an exemplary embodiment, when the target value is greater than or equal to the center CV, the target bit is set to the first value. In an alternative embodiment, when the target value is less than or equal to the center value, the target bit is set to the second value.

[0078] In operation S160, the PUF cell device 100 outputs the determined target bit TB.

[0079] FIG. 7 is a graph for describing the operation of the PUF cell device. FIG. 3 The horizontal axis of the distribution of FIG. 7 indicates information (e.g., mismatch information or current amount) obtained from the PUF cell.

[0080] Referring to FIG. 3 and FIG. 7 , information obtained from the plurality of PUF cells PC included in the PUF cell device 100 can form a first distribution DB1. Referring to FIG. 2 , a center value of the first distribution DB1, i.e., a reference value REF0, is described, and thus additional description is omitted to avoid repetition.

[0081] In an exemplary embodiment, information obtained from the plurality of PUF cells PC connected to the first word line WL1 forms a first sub-distribution sDB1, and information obtained from the plurality of PUF cells PC connected to the second word line WL2 forms a second sub-distribution sDB2. As FIG. 7 indicated, each of the first sub-distribution sDB1 and the second sub-distribution sDB2 can have a shape of a normal distribution or a Gaussian distribution.

[0082] That is, in the case of selecting a first target PUF cell from among the plurality of PUF cells PC connected to the first word line WL1, an average value of information obtained from the remaining PUF cells other than the target PUF cell among the plurality of PUF cells PC connected to the first word line WL1 has a first center value CVa. As such, it is possible to determine whether the first target PUF cell is a positive PUF cell +PC having a positive polarity or a negative PUF cell -PC having a negative polarity by comparing a first target value based on information obtained from the first target PUF cell with the first center value CVa.

[0083] Similarly, when selecting a second target PUF unit from among the multiple PUF units PC connected to the second word line WL2, the average value of the information obtained from the remaining PUF units (excluding the target PUF unit) among the multiple PUF units PC connected to the second word line WL2 has a second center value CVb. Thus, by comparing the second target value based on the information obtained from the second target PUF unit with the second center value CVb, it can be determined whether the second target PUF unit is a positive PUF unit +PC with positive polarity or a negative PUF unit -PC with negative polarity.

[0084] As described above, the plurality of PUF cells PCs included in the PUF cell device 100 of the present invention can form a normal distribution or a Gaussian distribution that varies depending on the word line offset. Therefore, the PUF cell device 100 of the present invention can calculate the center value by using PUF cells connected to the same word line as the target PUF cell, and can determine the target bit of the target PUF cell based on the calculated center value.

[0085] FIG. 8 This is for describing an exemplary embodiment of the concept according to the present invention. FIG. 3 A diagram illustrating the target bit determination method for the PUF unit device. (Refer to...) FIG. 3 and FIG. 8 The PUF unit device 100 includes a PUF unit array 110, a bit line selection circuit 130, and a bit determiner 140. The PUF unit array 110 includes multiple PUF units PC1 to PC8 connected to a first word line WL1 and multiple bit lines BL1 to BL8. The bit line selection circuit 130 includes multiple selectors SEL1 to SEL8. The bit determiner 140 includes a first converter 141, a second converter 142, and a comparator COMP. The components have already been described above; therefore, additional descriptions are omitted to avoid repetition. Furthermore, it is assumed that a third PUF unit PC3 is the target PUF unit.

[0086] When the third PUF unit PC3 is selected as the target PUF unit, a first voltage V1 is provided to the first word line WL1 connected to the third PUF unit PC3. In response to the first voltage V1 of the first word line WL1, the multiple PUF units PC1 to PC8 respectively output multiple currents I1 to I8 through multiple bit lines BL1 to BL8.

[0087] Because the third PUF unit PC3 is the target PUF unit, the third bit line selection signal BS3, used to select the third bit line BL3 connected to the third PUF unit PC3, is activated, and the inverse phase line selection signals / BS1, / BS2, and / BS4 to / BS8, used for the remaining bit lines BL1, BL2, and BL4 to BL8, are activated. That is, in response to the third bit line selection signal BS3, the third selector SEL3 provides the third current I3 of the third bit line BL3 to the second converter 142 as the target current I_tg. In response to the first anti-phase line selection signal / BS1, the second anti-phase line selection signal / BS2, and the fourth to eighth anti-phase line selection signals / BS4 to / BS8, the first selector SEL1, the second selector SEL2, and the fourth to eighth selectors SEL4 provide the first current I1, the second current I2, and the fourth to eighth current I8 of the first bit line BL1, the second bit line BL2, the fourth bit line BL4, and the eighth bit line BL8 to the first converter 141 as the sum current I_sum.

[0088] The first converter 141 outputs a center value CV based on the sum of currents I_sum, and the second converter 142 outputs a target value TV based on the third current I3 (i.e., the target current). The comparator COMP compares the center value CV and the target value TV to generate the target bit TB, and outputs the target bit TB in the third PUF unit PC3.

[0089] FIG. 9 This is a diagram illustrating a PUF cell array according to an exemplary embodiment of the concept of the present invention. (Refer to...) FIG. 9 The PUF cell array 110A includes multiple PUF cells PCs, and the multiple PUF cell PCs are connected to multiple word lines WL1 to WL6 and multiple bit lines BL11 to BL18 and BL21 to BL28. In an exemplary embodiment, the number of PUF cells, the number of word lines, or the number of bit lines in the PUF cell array 110A are not limited to... FIG. 9 The configuration shown.

[0090] With reference FIG. 2 The described PUF cell array 110 is different. FIG. 9The plurality of PUF cells PC of the PUF cell array 110A is connected with the bit lines BL11 to BL18 of the first group and the bit lines BL21 to BL28 of the second group. For example, the PUF cells PC connected with the first word line WL1, the third word line WL3, and the fifth word line WL5 are connected with the bit lines BL11 to BL18 of the first group, and the PUF cells PC connected with the second word line WL2, the fourth word line WL4, and the sixth word line WL6 are connected with the bit lines BL21 to BL28 of the second group. That is, the PUF cells PC connected with the first word line WL1, the third word line WL3, and the fifth word line WL5 and the PUF cells PC connected with the second word line WL2, the fourth word line WL4, and the sixth word line WL6 are connected with the bit lines of different groups, and can be operated independently from each other.

[0091] FIG. 10A is a diagram illustrating FIG. 9 a PUF cell device to which the PUF cell array 110A is applied. FIG. 10B to FIG. 10D is a diagram for describing FIG. 10A operation of the PUF cell device. For simplicity of description, the same components as those described above are not described.

[0092] Referring to FIG. 10A to FIG. 10D , the PUF cell device includes the PUF cell array 110A, the first bit line selection circuit 131 and the second bit line selection circuit 132, and a bit determiner (e.g., a comparator COMP). The PUF cell array 110A includes a plurality of PUF cells PC11 to PC18 and PC21 to PC28. The plurality of PUF cells PC11 to PC18 and PC21 to PC28 can be connected with the first word line WL1 and the second word line WL2. The PUF cells PC PC11 to PC18 connected with the first word line WL1 are connected with the bit lines BL11 to BL18 of the first group, and the PUF cells PC21 to PC28 connected with the second word line WL2 are connected with the bit lines BL21 to BL28 of the second group.

[0093] The first bit line selection circuit 131 is connected with the bit lines BL11 to BL18 of the first group. In an exemplary embodiment, the first bit line selection circuit 131 includes selectors described with reference to FIG. 5 and FIG. 8 The selectors included in the first bit line selection circuit 131 are respectively connected with the bit lines BL11 to BL18 of the first group and are operated in response to a corresponding bit line selection signal or a corresponding inverted bit line selection signal. The second bit line selection circuit 132 is connected with the bit lines BL21 to BL28 of the second group. In an exemplary embodiment, the second bit line selection circuit 132 includes selectors described with reference to FIG. 5 and FIG. 8The selectors described herein are connected to the bit lines BL21 to BL28 of the second group, respectively, and operate in response to the corresponding bit line selection signal or the corresponding inverse phase line selection signal. For the sake of simplicity and ease of description, the detailed configuration and operation of the selectors have been described above, and therefore additional descriptions are omitted to avoid repetition.

[0094] The first converter 141 outputs a target value TV or a center value CV based on information (e.g., current) received from the second bit line selection circuit 132. The second converter 142 outputs a center value CV or a target value TV based on information (e.g., current) received from the first bit line selection circuit 131.

[0095] In one exemplary embodiment, the first bit selection circuit 131 provides the target current or sum current to the second converter 142, and the second bit selection circuit 132 provides the sum current or target current to the first converter 141.

[0096] For example, such as FIG. 10B As shown, assume that PUF unit PC13 connected to the first word line WL1 is the target PUF unit. In this case, a first voltage V1 is applied to the first word line WL1 and the second word line WL2. In an exemplary embodiment, the voltage applied to the first word line WL1 and the second word line WL2 can be set differently depending on the physical characteristics of the plurality of PUF units PC11 to PC18 and PC21 to PC28 connected to the first word line WL1 and the second word line WL2. In response to the first voltage V1 applied to the first word line WL1 and the second word line WL2, each of the plurality of PUF units PC11 to PC18 and PC21 to PC28 outputs a corresponding current.

[0097] The first bit selection circuit 131, in response to the third bit selection signal BS3, provides the second converter 142 with a current I13 output from the PUF unit PC13, which is connected to the first word line WL1 and the third bit line BL13 of the first group. In this case, the current I13 is the target current I_tg. The second converter 142 outputs a target value TV based on the target current I_tg.

[0098] In response to the inverse phase line selection signals / BS1, / BS2, and / BS4 to / BS8, the second bit line selection circuit 132 provides the first converter 141 with a sum current I_sum2 corresponding to the sum of the currents provided through some bit lines BL21, BL22, and BL24 to BL28 of the second group. The first converter 141 outputs a center value CV based on the sum current I_sum2 provided from the second bit line selection circuit 132. The comparator COMP compares the center value CV with the target value TV to generate the target bit TB and outputs the target bit TB of the third PUF unit PC3 as the comparison result.

[0099] As described above, the PUF cell device according to an example embodiment of the present inventive concept calculates a center value CV based on sum currents obtained from some PUF cells connected to a second word line different from a first word line corresponding to a target PUF cell. In this case, the some PUF cells can refer to PUF cells connected to the remaining bit lines except for the bit line corresponding to the target PUF cell among the PUF cells connected to the different word line. That is, in the embodiment of FIG. 10, in the case where the target PUF cell PC13 is connected to the first word line WL1, the PUF cells PC21, PC22, and PC24 to PC28 connected to the second word line WL2 and the first bit line BL21, the second bit line BL22, and the fourth bit line BL24 to the eighth bit line BL28 of the second group are used to calculate the center value CV. FIG. 10B

[0100] However, the present inventive concept is not limited thereto. For example, as shown in FIG. 11, in the case where the target PUF cell (for example, PC13) is connected to the first word line WL1, all of the PUF cells PC21 to PC28 connected to the second word line WL2 can be used to calculate the center value CV. In this case, except that the second bit line selection circuit 132 receives the first inverted bit line selection signal / BS1 to the eighth inverted bit line selection signal / BS8 and all of the PUF cells PC21 to PC28 connected to the second word line WL2 are used to calculate the center value CV, the target bit determination operation is similar to the above-described operation, and thus an additional description is omitted to avoid redundancy. FIG. 10C

[0101] However, the present inventive concept is not limited thereto. For example, as shown in FIG. 11, in the case where the target PUF cell (for example, PC13) is connected to the first word line WL1, all of the PUF cells PC21 to PC28 connected to the second word line WL2 can be used to calculate the center value CV. In this case, except that the second bit line selection circuit 132 receives the first inverted bit line selection signal / BS1 to the eighth inverted bit line selection signal / BS8 and all of the PUF cells PC21 to PC28 connected to the second word line WL2 are used to calculate the center value CV, the target bit determination operation is similar to the above-described operation, and thus an additional description is omitted to avoid redundancy. FIG. 10D ​​As shown, in the case where the target PUF cell (e.g., PC13) is connected with the first word line WL1, all the remaining PUF cells PC11, PC12, PC14 to PC18, and PC21 to PC28 except for the target PUF cell PC13 among the plurality of PUF cells PC11 to PC18 and PC21 to PC28 connected with the first word line WL1 and the second word line WL2 are used to calculate the center value CV. In this case, the second bit line selection circuit 132 provides the second sum current I_sum2 corresponding to the sum of the currents from the PUF cells PC21 to PC28 connected with the second word line WL2 to the first converter 141, and the first bit line selection circuit 131 provides the first sum current I_sum1 corresponding to the sum of the currents from the remaining PUF cells PC11, PC12, and PC14 to PC18 among the PUF cells PC11 to PC18 connected with the first word line WL1 except for the target PUF cell PC3 to the first converter 141. The first converter 141 outputs the center value CV based on both the first sum current I_sum1 and the second sum current I_sum2.

[0102] In an exemplary embodiment, the division ratio of the first converter 141 or the second converter 142 can vary depending on the number of PUF cells to be used to calculate the center value CV.

[0103] The above exemplary embodiments are provided to describe the inventive concept, and are not intended to limit the inventive concept. For example, in the PUF cell device, the number of PUF cells, the number of word lines, or the number of bit lines can be variously changed or modified. Further, the PUF cells used to calculate the center value CV can be variously configured depending on the structure of the PUF cell array. For example, referring to FIG. 10A to FIG. 10D Embodiments of calculating the center value by using PUF cells of word lines adjacent to the word line of the target PUF cell are described, but PUF cells of word lines physically spaced apart from the word line of the target PUF cell can be used to calculate the center value. Alternatively, a plurality of PUF cells connected with a plurality of word lines can be used to calculate the center value.

[0104] FIG. 11 is a diagram for describing a way to improve the reliability of a PUF cell device. Referring to FIG. 11As described above, information obtained from the plurality of PUF cells of the PUF cell device can form a normal distribution or a Gaussian distribution like the first distribution DB1, and a target bit TB or a polarity of the PUF cell can be determined based on the reference value REF0. The information output from the PUF cell can vary depending on various conditions (e.g., operating temperature and operating voltage). That is, in the PUF cell outputting information close to the reference value REF0, the output information can vary depending on various factors, and thus, the polarity of the PUF cell or the determined bit can change. This results in a decrease in reliability of the PUF cell device.

[0105] As such, the exemplary PUF cell device can collect information of each of the plurality of PUF cells included in the PUF cell device through a separate test operation, can convert the collected information into digital data through an analog-to-digital converter, and can discard the PUF cell having information between the reference value REF0 and "-a" or "+a". For example, the PUF cell having information in the range of REF0-a to REF0+a can be discarded (ignored). Discarding a specific PUF cell means that the specific PUF cell is not selected as a target PUF cell in the next PUF cell operation. That is, the overall reliability of the PUF cell device can be improved by discarding (or ignoring) the PUF cell PC having relatively low reliability.

[0106] However, as described above, in order to discard the PUF cell PC having relatively low reliability, operations such as converting information of all PUF cells into digital data through an analog-to-digital converter and setting a separate reference value REF0 are required.

[0107] The PUF cell device 100 according to an exemplary embodiment of the inventive concept determines and discards unstable PUF cells by adjusting a division ratio with respect to a center value CV and determining a target bit based on the adjusted division ratio.

[0108] FIG. 12A is a flowchart for describing an operation of a stable PUF cell or an effective PUF cell of the PUF cell device according to an exemplary embodiment of the inventive concept. FIG. 1 is a flowchart for describing an operation of a stable PUF cell or an effective PUF cell of the PUF cell device according to an exemplary embodiment of the inventive concept. FIG. 12B is a flowchart for describing an operation of a stable PUF cell or an effective PUF cell of the PUF cell device according to an exemplary embodiment of the inventive concept. FIG. 1 is a flowchart for describing an operation of a stable PUF cell or an effective PUF cell of the PUF cell device according to an exemplary embodiment of the inventive concept. FIG. 1 , FIG. 2 , FIG. 12A and FIG. 12B In operation S211, the PUF cell device 100 selects a target PUF cell. For example, the PUF cell device can select a target PUF cell based on a received control signal.

[0109] In operation S212, the PUF unit device 100 generates a target value TV and generates a first center value CV1 based on a first division ratio "N-a". In an exemplary embodiment, "N" is a positive integer and "a" is a real number. For example, the PUF unit device 100 can generate the target value TV and the first center value CV1 corresponding to the target PUF unit based on the operation method described above with reference to FIG. 2. FIG. 1 to FIG. 10D In this case, the division ratio for the first center value CV1 can be smaller than the given division ratio. For example, in the case where the center value is calculated by using "N" PUF units, in the above embodiment, the 0th center value CV0 is calculated based on the division ratio "N". However, in operation S212, in the case where the center value is calculated by using "N" PUF units, the center value is calculated based on the division ratio "N-a" (i.e., smaller than the division ratio in the above embodiment). In this case, as shown in FIG. 3, the first center value CV1 calculated based on the division ratio "N-a" is greater than the 0th center value CV0 calculated based on the division ratio "N". FIG. 12B

[0110] In operation S213, the PUF unit device 100 compares the target value TV and the first center value CV1. When the target value TV is not greater than the first center value CV1, the PUF unit device 100 proceeds to operation S215. When the target value TV is greater than the first center value CV1, in operation S214, the PUF unit device 100 determines the selected target PUF unit as a valid PUF unit. For example, as shown in FIG. 4, the target value TV being greater than the first center value CV1 can mean that the target value TV is spaced apart from the 0th center value CV0 by a certain distance (e.g., a logical distance). That is, even if the information output from the target PUF unit varies depending on various environmental conditions, the probability that the target value TV of the target PUF unit is lower than the 0th center value CV0 can be very low. That is, the target PUF unit having the target value TV greater than the first center value CV1 is a stable (or valid) PUF unit. FIG. 12B

[0111] When after operation S214 or in operation S213 it is determined that the target value TV is not greater than the first center value CV1, in operation S215, the PUF unit device 100 determines whether the above operations have been completely performed for all PUF units. When it is determined that the above operations have not been completely performed for all PUF units, in operation S216, the PUF unit device 100 selects a next target PUF unit. Thereafter, the PUF unit device 100 can repeat operations S212 to S216.

[0112] ​​As described above, by performing operations S211 to S216, the PUF unit device 100 of the present invention calculates a first center value CV1 (i.e., greater than the 0th center value) by using a division ratio smaller than a given division ratio, and determines a PUF unit having a target value greater than the first center value CV1 as a valid PUF unit.

[0113] In operation S221, PUF unit device 100 selects a target PUF unit. In operation S222, PUF unit device 100 generates a target value TV and generates a second center value CV2 based on a second division ratio "N+a". For example, PUF unit device 100 based on a reference... FIG. 1 to FIG. 10D The described operation method generates a target value TV and a second center value CV2 corresponding to the target PUF unit. In this case, as described above, when calculating the center value using "N" PUF units, the 0th center value CV0 is calculated based on a division ratio "N". In contrast, in operation S222, the second center value CV2 is calculated based on a division ratio "N+a" which is greater than the division ratio "N". In this case, the second center value CV2 is less than... FIG. 12B The zeroth center value CV0 is shown.

[0114] In operation S223, PUF unit device 100 determines whether the target value TV is less than the second center value CV2.

[0115] When the target value TV is not less than the second center value CV2, the PUF unit device 100 proceeds to operation S225. When the target value TV is less than the second center value CV2, in operation S224, the PUF unit device 100 determines the selected target PUF unit as a valid PUF unit. For example, as... FIG. 12B As shown, a target value TV less than the second center value CV2 means that the target value TV is separated from the 0th center value CV0 by a certain distance (e.g., logical distance). That is, even if the information output from the target PUF unit varies depending on various environmental conditions, the probability that the target value TV of the target PUF unit is higher than the 0th center value CV0 can be very low. In other words, a target PUF unit with a target value TV less than the second center value CV2 can be a stable (e.g., effective) PUF unit.

[0116] Subsequently, the PUF unit device 100 can perform operations S225 and S226. Operations S225 and S226 are similar to operations S215 and S216 described above, therefore, additional descriptions are omitted to avoid repetition.

[0117] As described above, by performing operations S221 to S226, the PUF cell device 100 according to the present inventive concept calculates the second center value CV2 (i.e., smaller than the 0th center value) by using a division ratio larger than a given division ratio, and can determine a PUF cell having a target value smaller than the second center value CV2 as a valid PUF cell.

[0118] Thereafter, in operation S230, the PUF cell device 100 stores information about the valid PUF cell. For example, the PUF cell device 100 can store address information about the valid PUF cell. In this case, because the stored information is only the address information of the valid PUF cell, and other information (i.e., information capable of determining a bit value) about the polarity or the target value of the valid PUF cell is not separately stored, it is not possible to restore the target value or the security key even if the address information is leaked or illegally intruded.

[0119] For the sake of simplicity of illustration and convenience of description, operation S230 is separately shown, but the present inventive concept is not limited thereto. For example, operation S230 can be separately performed in operation S214 or operation S224. Alternatively, operation S230 can be performed by the controller 101. For example, depending on the result of operation S213, the first value or the second value can be output as the target bit TB of the target PUF cell. The controller 101 can determine the target PUF cell as a valid PUF cell upon receiving the first value indicating that the target value TV is greater than the first center value CV1, and not perform a separate determination on the target PUF cell upon receiving the second value indicating that the target value TV is smaller than the first center value CV1. In an exemplary embodiment, information (e.g., address information) about the target PUF cell for determining the target PUF cell as a valid PUF cell is stored in a separate memory of the controller 101.

[0120] In an exemplary embodiment, as FIG. 12B indicated, PUF cells among the plurality of PUF cells that are not determined as valid PUF cells can be managed as invalid PUF cells. In an exemplary embodiment, the invalid PUF cells can refer to PUF cells that are not selected as target PUF cells in a target bit determination operation of the PUF cell device 100 later.

[0121] FIG. 13A and 13B are diagrams for describing operations of flowcharts according to FIG. 12A . Referring to FIG. 1 , FIG. 2 , FIG. 13A and FIG. 13BThe PUF cell device 100 includes a PUF cell array 110, a bit line selector 130, and a bit determiner 140. The PUF cell array 110 includes a plurality of PUF cells PC1 to PC8 connected to a first word line WL1 and a plurality of bit lines BL1 to BL8. The bit line selector 130 includes a plurality of selectors SEL1 to SEL8. The bit determiner 140 includes a first converter 141, a second converter 142, and a comparator COMP. Each component is described above, and thus additional description is omitted to avoid repetition.

[0122] First, referring to FIG. 13A the operation S211 to the operation S214 of FIG. 2 are described. FIG. 12A As shown in the operation S212, the first converter 141 outputs the first center value CV1 based on the first division ratio (e.g., "N-a"). The second converter 142 outputs the target value TV based on the third current I3. The comparator COMP compares the first center value CV1 and the target value TV to generate the first classification result CR1 and outputs the first classification result CR1. FIG. 13A FIG. 8 As shown in the operation S212, the first converter 141 outputs the first center value CV1 based on the first division ratio (e.g., "N-a"). The second converter 142 outputs the target value TV based on the third current I3. The comparator COMP compares the first center value CV1 and the target value TV to generate the first classification result CR1 and outputs the first classification result CR1.

[0123] As shown in the operation S212, the first converter 141 outputs the first center value CV1 based on the first division ratio (e.g., "N-a"). The second converter 142 outputs the target value TV based on the third current I3. The comparator COMP compares the first center value CV1 and the target value TV to generate the first classification result CR1 and outputs the first classification result CR1. FIG. 12A When the value of the first classification result CR1 is the first value (i.e., when the target value TV is greater than the first center value CV1), the third PUF cell PC3 is decided as a valid PUF cell. In this case, in the distribution of

[0124] the third PUF cell PC3 can be understood as having a value greater than the first center value CV1. FIG. 12B When the value of the first classification result CR1 is the second value (i.e., when the target value TV is not greater than the first center value CV1), the third PUF cell PC3 can be decided as a valid PUF cell or an invalid / instable PUF cell. For example, as from

[0125] FIG. 12B ​​distribution, the third PUF cell PC3 can be understood as having a value smaller than the first center value CV1 when the target value TV is smaller than the first center value CV1.

[0126] The operations described with reference to FIG. 13A may be performed on each of the plurality of PUF cells PC1 to PC8 to decide valid PUF cells having a target value larger than the first center value CV1 among the plurality of PUF cells PC1 to PC8.

[0127] Next, the operations S221 to S224 described with reference to FIG. 13B may be performed. FIG. 12A As shown in FIG. 13B , the fourth PUF cell PC4 can be selected as the target PUF cell. In this case, each of the plurality of selectors SEL1 to SEL8 can operate in response to the corresponding bit line selection signal or the corresponding inverted bit line selection signal. The operations of the plurality of selectors SEL1 to SEL8 are similar to the above-described operations, and thus additional description will be omitted to avoid repetition.

[0128] Through the operations of the plurality of selectors SEL1 to SEL8, a sum current I_sum corresponding to the sum of the remaining currents among the plurality of currents I1 to I8 except for the fourth current I4 is provided to the first converter 141, and the fourth current I4 is provided to the second converter 142. The second converter 142 outputs the target value TV based on the fourth current I4.

[0129] Unlike the above description with respect to FIG. 13A , the first converter 141 outputs the second center value CV2 based on a second division ratio (e.g., "N+a"). The comparator COMP compares the second center value CV2 and the target value TV to generate and output the second classification result CR2.

[0130] When the value of the second classification result CR2 is the second value (i.e., when the target value TV is smaller than the second center value CV2), the fourth PUF cell PC4 is decided as a valid PUF cell. In this case, in the distribution of FIG. 12B , the fourth PUF cell PC4 can be understood as having a value smaller than the second center value CV2.

[0131] In an exemplary embodiment, the operations described with reference to FIG. 13B may be performed on each of the plurality of PUF cells PC1 to PC8 to decide valid PUF cells having a target value smaller than the second center value CV2 among the plurality of PUF cells PC1 to PC8.

[0132] In an exemplary embodiment, the operation of referring to FIG. 13A described above can be selectively performed depending on a result of the operation of referring to FIG. 13A described above. For example, the operation of referring to FIG. 13B described above can be performed only for a PUF cell which is not decided as a valid PUF cell in the operation of referring to FIG. 13A described above. Alternatively, in a case where the operation of referring to FIG. 13B described above is first performed, the operation of referring to FIG. 13B described above can be performed only for a PUF cell which is not decided as a valid PUF cell in the operation of referring to FIG. 13B described above. FIG. 13A

[0133] Although the operation of deciding a valid PUF cell having a target value greater than a first center value CV1 and the operation of deciding a valid PUF cell having a target value less than a second center value CV2 are separately shown and described, the inventive concept is not limited thereto. For example, the first converter 141 can simultaneously calculate the first center value CV1 based on a first division ratio and the second center value CV2 based on a second division ratio through one conversion operation, and the comparator COMP can simultaneously compare the first center value CV1 and the second center value CV2 with the target value TV. In this case, whether the target PUF cell is a valid PUF cell can be determined through one sensing operation.

[0134] In an exemplary embodiment, whether the target PUF cell is a valid PUF cell can be determined by the controller 101. For example, the controller 101 can perform the operation of referring to FIG. 13A described above for each of a plurality of PUF cells of the PUF cell device 100, and can receive a first comparison result (or a first target bit) for each of the plurality of PUF cells. Thereafter, the controller 101 can perform the operation of referring to FIG. 13B described above for each of the plurality of PUF cells of the PUF cell device 100, and can receive a second comparison result (or a second target bit) for each of the plurality of PUF cells. The controller 101 can decide a valid PUF cell by combining the first comparison result (or the first target bit) and the second comparison result (or the second target bit), and can store address information of the decided valid PUF cell.

[0135] FIG. 14 is a block diagram of a controller according to an exemplary embodiment of the inventive concept. The operation of referring to FIG. 1 and FIG. 1 and FIG. 14 ​The controller 101 includes a target PUF cell selection circuit 101a, a memory 101b, a secure key generator 101c (e.g., a circuit), and a control circuit 101d.

[0136] The target PUF cell selection circuit 101a selects a target PUF cell among a plurality of PUF cells included in the PUF cell device 100. The target PUF cell selection circuit 101a can output a control signal CTRL based on the selected target PUF cell. In an exemplary embodiment, the target PUF cell selection circuit 101a is configured to select a target PUF cell among the valid PUF cells described with reference to FIG. 12A to FIG. 13B The memory 101b can include information (e.g., address information) about the valid PUF cells generated through the operations described with reference to FIG. 12A to FIG. 13B The target PUF cell selection circuit 101a can select a target PUF cell among the valid PUF cells based on the information stored in the memory 101b.

[0137] The secure key generator 101c receives target bits TB from the PUF cell device 100. In an exemplary embodiment, the secure key generator 101c generates a secure key KEY by combining a plurality of target bits TB received from the PUF cell device 100. The generated secure key KEY can be provided to an external electronic device or an integrated circuit. The control circuit 101d can be configured to control the overall operation of the controller 101. The secure key KEY can be used to authenticate the PUF cell device 100.

[0138] FIG. 15 is a diagram for describing an operation of a PUF cell device according to an exemplary embodiment of the inventive concept. For the convenience of description, the PUF cell device 100 of FIG. 3 and the controller 101 of FIG. 14 will be described based on the operations described with reference to FIG. 15 . In addition, it is assumed that the third PUF cell PC3, the fifth PUF cell PC5, and the eighth PUF cell PC8 among the plurality of PUF cells PC1 to PC8 are determined as valid PUF cells through the operations described with reference to FIG. 12A to FIG. 13B . That is, the controller 101 of FIG. 14 may include information about the valid PUF cells PC3, PC5, and PC8.

[0139] The PUF cell device 100 of FIG. 1 , FIG. 14 and FIG. 15The PUF unit device 100 includes a PUF unit array 110, a bit line selection circuit 130, and a bit determiner 140. The PUF unit array 110 includes multiple PUF units PC1 to PC8 connected to a first word line WL1 and multiple bit lines BL1 to BL8. The bit line selection circuit 130 includes multiple selectors SEL1 to SEL8. The bit determiner 140 includes a first converter 141, a second converter 142, and a comparator COMP. These components have been described above, therefore additional descriptions are omitted to avoid repetition.

[0140] Unlike the embodiments described above, in FIG. 15 In this embodiment, the center value CV is calculated using some of a plurality of PUF cells connected to the word line of the target PUF cell. For example, if the target PUF cell is the third PUF cell PC3, PUF cells that are not valid PUF cells (i.e., invalid / unstable PUF cells) among the plurality of PUF cells PC1 to PC8 connected to the first word line WL1 are used as PUF cells to calculate the center value CV. See reference FIG. 12B The invalid PUF cell is the PUF cell adjacent to the 0th center value CV0. That is, by using invalid PUF cells to calculate the center value CV, a value closer to the 0th center value CV0 can be obtained. Furthermore, by reducing the number of PUF cells used to calculate the center value CV, the total power consumption of the PUF cell device 100 can be reduced. For example, in... FIG. 15 In the diagram, PUF cells PC1, PC2, PC4, PC6, and PC7 are invalid PUF cells used to generate current I_sum.

[0141] FIG. 16A This is a block diagram illustrating the operation of a security device according to an exemplary embodiment of the present invention. FIG. 16B and FIG. 16C This is a flowchart describing the operation of a security device according to an exemplary embodiment of the present invention. (Refer to...) FIG. 16A and FIG. 16B The security device 200 includes a PUF cell array 210, an analog-to-digital converter 220, and a memory 230. In an exemplary embodiment, the PUF cell array 210 is referenced to... FIG. 1 to FIG. 15 Describe a PUF unit device or PUF unit array.

[0142] Reference FIG. 16B describe FIG. 16A The operation of safety equipment 200. In FIG. 16B In operation S310, the security device 200 obtains the sensed value of each of the plurality of PUF cells included in the PUF cell array 210. The sensed value may be analog information obtained from each of the plurality of PUF cells.

[0143] In operation S320, the security device 200 converts the sensed value SV into a digital value DV, and stores the converted digital value DV in the memory 230.

[0144] In operation S330, the security device 200 decides valid PUF cells based on the digital values DV stored in the memory 230. For example, as described with reference to FIG. 11 , the security device 200 can decide PUF cells corresponding to digital values greater than or less than the reference value REF0 by a given size among the digital values DV as valid PUF cells. In an exemplary embodiment, information about valid PUF cells can be stored in the memory 230.

[0145] In operation S340, the security device 200 performs a bit determination operation on each valid PUF cell by using a center value based on invalid PUF cells. For example, the security device 200 can perform the operation described with reference to FIG. 15 based on information about invalid PUF cells.

[0146] In an exemplary embodiment, the security device 200 performs the target bit determination operation described with reference to FIG. 1 to FIG. 5 by using the analog-to-digital converter 220. For example, with reference to FIG. 16A and FIG. 16C , in operation S410, the security device 200 obtains sensed values from each PUF cell. In an exemplary embodiment, the security device 200 obtains sensed values about all PUF cells. Alternatively, the security device 200 can obtain sensed values from target PUF cells and PUF cells associated with the target PUF cells (e.g., PUF cells used to calculate the center value as described with reference to FIG. 1 to FIG. 15 ).

[0147] In operation S420, the security device 200 converts the obtained sensed values into digital values.

[0148] In operation S430, the security device 200 can calculate a center value CV. For example, as in the above description, the security device 200 calculates the center value based on digital values corresponding to other PUF cells associated with the target PUF cell. That is, unlike the above embodiment, the security device 200 uses the analog-to-digital converter 220 to obtain digital values of other PUF cells associated with the target PUF cell and calculates the center value based on the obtained digital values.

[0149] Thereafter, the security device 200 performs operations S440 to S460. In an exemplary embodiment, the basic operation principle can be similar to that of operations S440 to S460 except that the operations of calculating the center value CV and determining the target bit are performed after analog-to-digital conversion using the analog-to-digital converter 220.FIG. 6 the above embodiment. For example, operation S440 is performed after operation S430 and can be implemented by operation S141 of the above embodiment. Operation S450 can be performed after operation S440 determines that the target value is not greater than the center value CV and can be implemented by operation S142 of the above embodiment. Operation S460 can be performed after operation S450 determines that the target value is not less than the center value CV and can be implemented by operation S143 of the above embodiment. FIG. 6 the above embodiment. For example, operation S451 is performed when operation S440 determines that the target value is greater than the center value CV and can be implemented by operation S151 of the above embodiment. Operation S452 is performed when operation S440 determines that the target value is not greater than the center value CV and can be implemented by operation S152 of the above embodiment. Operation S460 can be performed after operation S452 and can be implemented by operation S160 of the above embodiment. FIG. 6 the above embodiment. For example, operation S451 is performed when operation S440 determines that the target value is greater than the center value CV and can be implemented by operation S151 of the above embodiment. Operation S452 is performed when operation S440 determines that the target value is not greater than the center value CV and can be implemented by operation S152 of the above embodiment. Operation S460 can be performed after operation S452 and can be implemented by operation S160 of the above embodiment.

[0150] As described above, the security device 200 receives the sensing values SV of the plurality of PUF cells from the PUF cell array 210. The security device 200 can convert the sensing values SV of the plurality of PUF cells into digital values DV through the analog-to-digital converter 220. The digital values DV can be stored in the memory 230 or a separate storage circuit. The security device 200 can calculate the center value CV based on the digital values corresponding to at least two or more of the remaining PUF cells other than the target PUF cell among the digital values DV. In an exemplary embodiment, whenever the target bit is determined, the security device 200 can perform the following operations on the associated other PUF cells: the operation of obtaining the sensing values and the operation of converting the sensing values into digital values. Alternatively, the digital values of each of the plurality of PUF cells can be stored in the memory 230, and the security device 200 can calculate the center value by using the digital values stored in the memory 230.

[0151] FIG. 17 is a block diagram illustrating an electronic system to which a security device according to an embodiment of the present inventive concept is applied. Referring to FIG. 17 , the electronic system 1000 includes a host 1100 (e.g., a host device) and a security device 1200. The electronic system 1000 can be an electronic device such as a portable communication terminal, a personal digital assistant (PDA), a portable multimedia player (PMP), a smart phone, a digital camera, or a wearable device.

[0152] The host 1100 can be configured to control the security device 1200. The security device 1200 includes a PUF cell array 1210 and can be configured to operate under the control of the host 1100. In an exemplary embodiment, the security device 1200 is a smart card such as an integrated circuit (IC) card or chip, or can be a hardware component separately provided to generate a security key.

[0153] For example, the host 1100 can receive a device identifier (ID) from the security device 1200. The host 1100 can transmit a challenge to the security device 1200 based on the received device identifier ID. The security device 1200 can transmit a response to the host 1100 in response to the challenge from the host 1100. In an exemplary embodiment, the response includes the security key KEY described with reference to FIG. 1 to FIG. 1 6. That is, depending on the operation method described with reference to FIG. 1 to FIG. 1 6, the security device 1200 can obtain data based on the challenge from the host 1100 from a plurality of PUF cells included in the PUF cell array 1210, can generate a response (i.e., the security key) based on the obtained data, and can transmit the response to the host 1100. The host 1100 can perform an authentication operation on the security device 1200 or any other device based on the received response (e.g., based on the security key).

[0154] FIG. 18 FIG. 1 is a block diagram illustrating an electronic device to which a security device according to an exemplary embodiment of the present inventive concept is applied. Referring to FIG. 1, the electronic device 1000 includes a main processor 1010, a touch panel 1020, a touch driver integrated circuit 1022, a display panel 1030, a display driver integrated circuit 1032, a system memory 1040, a storage device 1050, an image processor 1080, a communication block 1070, an audio processor 1060, and a security chip 1090. In an exemplary embodiment, the electronic device 1000 can be one of various electronic devices such as a portable communication terminal, a personal digital assistant (PDA), a portable media player (PMP), a digital camera, a smartphone, a tablet computer, a notebook computer, and a wearable device. FIG. 18

[0155] The main processor 1010 can control overall operations of the electronic device 1000. The main processor 1010 can control / manage operations of components of the electronic device 1000. The main processor 1010 can process various operations for the purpose of operating the electronic device 1000.

[0156] The touch panel 1020 can be configured to sense a touch input from a user under the control of the touch driver integrated circuit 1022. The display panel 1030 can be configured to display image information under the control of the display driver integrated circuit 1032.

[0157] ​The system memory 3400 can store data for the operation of the electronic device 3000. For example, the system memory 3400 can include volatile memory such as static random access memory (SRAM), dynamic RAM (DRAM), or synchronous DRAM (SDRAM), and / or non-volatile memory such as phase-change RAM (PRAM), magnetoresistive RAM (MRAM), resistive RAM (ReRAM), or ferroelectric RAM (FRAM).

[0158] The storage 3500 can store data regardless of whether power is supplied. For example, the storage 3500 can include at least one of various non-volatile memories such as flash memory, PRAM, MRAM, ReRAM, and FRAM. For example, the storage 3500 can include embedded memory and / or removable memory of the electronic device 3000.

[0159] The audio processor 3600 can process an audio signal by using an audio signal processor 3610. The audio processor 3600 can receive an audio input through a microphone 3620, or can provide an audio output through a speaker 3630.

[0160] The communication block 3700 can exchange signals with external devices / systems through an antenna 3710. A transceiver 3720 and a modulator / demodulator (MODEM) 3730 of the communication block 3700 can process signals exchanged with external devices / systems in at least one of various wireless communication protocols such as long term evolution (LTE), worldwide interoperability for microwave access (WiMax), global system for mobile communications (GSM), code division multiple access (CDMA), Bluetooth, near field communication (NFC), wireless fidelity (Wi-Fi), and radio frequency identification (RFID).

[0161] The image processor 3800 can receive light through a lens 3810. An image device 3820 and an image signal processor 3830 included in the image processor 3800 can generate image information about an external object based on the received light.

[0162] The security chip 3900 can be implemented to manage a security operation or an authentication operation associated with the electronic device 3000. In an exemplary embodiment, the security chip 3900 includes a PUF unit device or a security device described with reference to FIG. 1 to FIG. 1 6.

[0163] In an exemplary embodiment, FIG. 18 A part of components of the electronic device 3000 can be implemented in the form of a system on chip (SoC), and can be provided as an application processor (AP) of the electronic device 3000.

[0164] According to at least one embodiment of the inventive concept, the center value is calculated by using other PUF cells associated with the target PUF cell without separate reference data, and the target bit of the target PUF cell is decided based on the calculated center value. Thus, an analog-to-digital converter or reference data is not separately required. This means that the circuit complexity of the security device is reduced. Furthermore, because the center value optimized for each PUF cell is decided, the reliability of the security device can be improved.

[0165] Thus, a security device including a physically unclonable function (PUF) cell having improved reliability and reduced cost, an operation method of the security device, and an operation method of a physically unclonable function cell device are provided.

[0166] Although the inventive concept has been described with reference to the exemplary embodiments, it will be apparent to those having ordinary skill in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the inventive concept.

Claims

1. A security device comprising: an array of physically unclonable function (PUF) cells including a plurality of first PUF cells connected with a first word line; a controller configured to select a target PUF cell among the plurality of first PUF cells and output a control signal indicating the selected target PUF cell; a decoder configured to apply a first voltage to the first word line in response to the control signal; a bit line selection circuit connected with a plurality of first bit lines and configured to output a first target current passing through a bit line among the plurality of first bit lines connected with the target PUF cell and a first sum current corresponding to a sum of currents passing through remaining bit lines connected with other PUF cells among the plurality of first PUF cells; and a bit determiner configured to output a target bit of the target PUF cell based on the first target current and the first sum current, wherein the security device generates a security key based on the target bit in response to an authentication request. each of the plurality of first PUF cells includes:

2. The security device of claim 1, wherein, a first transistor connected between a power node and a corresponding bit line among the plurality of first bit lines and configured to output a corresponding current in response to the first voltage provided to the first word line. each of the plurality of first PUF cells includes a first transistor and a second transistor, and 3. The security apparatus of claim 1, wherein, wherein the first transistor and the second transistor are connected in series between the power node and the corresponding bit line among the plurality of first bit lines and configured to operate in response to the first voltage provided to the first word line. the bit line selection circuit includes a plurality of selectors connected with the plurality of first bit lines, respectively, and 4. The security apparatus of claim 1, wherein, wherein each of the selectors includes: a first transistor connected between a corresponding bit line among the plurality of first bit lines and a first node from which the first target current is output and configured to operate in response to a corresponding bit line selection signal; and a second transistor connected between the corresponding bit line and a second node from which the first sum current is output and configured to operate in response to a corresponding inverted bit line selection signal. the bit determiner includes:

5. The security apparatus of claim 1, wherein, a first converter configured to convert the first sum current into a center value based on a given ratio; a second converter configured to convert the first target current into a target value; and a comparator configured to compare the center value and the target value to generate the target bit based on a comparison result. the given ratio corresponds to a number of the other PUF cells.

6. The security device of claim 5, wherein, the number of the other PUF cells is less than a number of the plurality of first PUF cells.

7. The security apparatus of claim 1, wherein, the array of PUF cells further includes a plurality of second PUF cells connected with a second word line and connected with a plurality of second bit lines, 8. The security apparatus of claim 1, wherein, wherein the decoder is further configured to apply a second voltage to the second word line in response to the control signal, wherein the bit line selection circuit is further configured to output a second sum current passing through the plurality of second bit lines from the plurality of PUF cells as a second sum current, and wherein the bit determiner is further configured to compare the center value and the target value to output the target bit, the center value being determined from the first sum current and the second sum current, and the target value being determined from the target current. the controller includes:

9. The security apparatus of claim 1, wherein, ​ a memory including address information of the valid PUF cells among the plurality of first PUF cells; a target PUF cell selection circuit configured to select a target PUF cell among the valid PUF cells based on the address information and output a control signal indicating the selected target PUF cell; and a security key generator configured to receive the target bit and output a security key based on the received target bit. 10.An operating method of a physical unclonable function (PUF) cell device including a plurality of PUF cells, the method comprising: selecting a target PUF cell among the plurality of PUF cells; applying a first voltage to a first word line connected to the target PUF cell; generating a target value based on a target current corresponding to the target PUF cell and a center value based on a sum current corresponding to a sum of currents output from other PUF cells connected to the first word line; determining a target bit of the target PUF cell based on the target value and the center value; and generating a security key based on the target bit for responding to an authentication request. The center value is generated based on a given ratio and a size of the sum current. The given ratio corresponds to a number of the other PUF cells.

11. The method of claim 10, wherein, The plurality of PUF cells includes a plurality of valid PUF cells and a plurality of invalid PUF cells, and 12. The method of claim 11, wherein, wherein the target PUF cell is selected from the plurality of valid PUF cells.

13. The method of claim 10, wherein, The number of the other PUF cells is less than a number of PUF cells connected to the first word line among the plurality of PUF cells. The center value is generated based on a given ratio and a size of the sum current.

14. The method of claim 10, wherein, The given ratio corresponds to a number of the other PUF cells. The plurality of PUF cells includes a plurality of valid PUF cells and a plurality of invalid PUF cells, and wherein the target PUF cell is selected from the plurality of valid PUF cells. The number of the other PUF cells is less than a number of PUF cells connected to the first word line among the plurality of PUF cells.

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