Fast precharge for memory sensing

Abstract

The present application relates to fast precharge for memory sensing. An operating mode associated with a command sequence having a reduced duration relative to another operating mode may be configured at a memory device. The operating mode may be configured based on determining that a program does not attempt to save or is independent of saving the logical state of the accessed memory cell, as well as other conditions. When operating in the mode, the memory device may execute a received precharge command using a first set of operations having a first duration, rather than executing the received precharge command using a second set of operations having a longer second duration. The first set of operations may also use less current or introduce less interference into the memory device relative to the second set of operations.

Description

[0001] Cross-references

[0002] This patent application claims priority to U.S. patent application No. 16 / 675,065 filed by Majerus on November 5, 2019, entitled “QUICK PRECHARGE FOR MEMORY SENSING,” which is assigned to the present assignee and is expressly incorporated herein by reference in its entirety.

[0003] The technical field relates to fast pre-charge for memory sensing. Background Art

[0004] The following relates generally to a system including at least one memory device, and more particularly to executing a fast precharge command sequence.

[0005] Memory devices are widely used to store information in a variety of electronic devices, such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming different states in the memory device. For example, binary devices most often store one of two states, typically represented by a logic 1 or a logic 0. Other devices can store more than two states. To access the stored information, components of the device can read or sense at least one stored state in the memory device. To store information, components of the device can write or program states in the memory device.

[0006] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), and others. Memory devices can be volatile or non-volatile. Non-volatile memories, such as FeRAM, can retain their stored logic state for extended periods of time even in the absence of external power. Volatile memory devices, such as DRAM, can lose their stored state when disconnected from external power. FeRAM can achieve densities similar to volatile memories, but has non-volatile properties due to the use of ferroelectric capacitors as storage elements.

[0007] Before deploying a memory device, a test program may be performed on the memory device to identify defects and ensure the reliability of the memory device. The test program may also be performed to identify failures of the memory device that may occur when the memory device is deployed. Summary of the Invention

[0008] A method is described. The method may include configuring a memory device including a memory array to operate in a first mode associated with a command sequence having a reduced duration relative to a second mode; after configuring the memory device to operate in the first mode, receiving a precharge command associated with memory cells of the memory array; and performing a first set of operations for executing the precharge command based at least in part on configuring the memory array to operate in the first mode, wherein the first set of operations is performed for a shorter duration than a second set of operations for executing the precharge command when the memory device is configured in the second mode.

[0009] A device is described. The device may include a memory unit and a memory controller coupled to the memory unit and configurable to operate in a first mode associated with a command sequence having a reduced duration relative to a second mode. The memory controller is operable to, when configured in the first mode, perform a first set of operations associated with the first mode to execute a first command for accessing the memory unit, or, when configured in the second mode, perform a second set of operations associated with the second mode to execute the first command for accessing the memory unit, wherein a duration for executing the first set of operations is shorter than a duration for executing the second set of operations.

[0010] A device is described. The device may include a memory array comprising memory cells and a memory controller coupled to the memory array. The memory controller is operable to configure a first mode associated with one or more command sequences having a reduced duration relative to a second mode; receive a precharge command associated with the memory cells after configuring the first mode; and perform a first set of operations for executing the precharge command based at least in part on configuring the memory array to operate in the first mode, wherein the first set of operations is performed within a shorter duration than a second set of operations for executing the precharge command when the second mode is configured. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 An example of a system that supports execution of the Fast Precharge command sequence disclosed herein is shown.

[0012] Figure 2 An example of a memory die that supports execution of the Fast Precharge command sequence disclosed herein is shown.

[0013] Figure 3 An example of a method for executing the Fast Precharge command sequence disclosed herein is shown.

[0014] Figure 4 A block diagram of a memory device that supports execution of the Fast Precharge command sequence disclosed herein is shown.

[0015] Figure 5 and 6 A flow chart illustrating one or more methods that support execution of the Fast Precharge command sequences disclosed herein is shown. DETAILED DESCRIPTION

[0016] Information can be stored in and read from a memory device using an access command that triggers, at the memory device, the performance of a sequence of operations for accessing (e.g., reading from or writing to) a memory cell addressed by the access command. In some instances, the sequence of operations (or "access command sequence") used to execute a received access command differs based on the technology used by the memory device. For example, an access command sequence (e.g., a precharge (PRE) command sequence) for accessing a ferroelectric memory cell may include additional operations and have a longer duration than a corresponding access command sequence (e.g., a PRE command sequence) for accessing a dynamic random access memory (DRAM) cell.

[0017] In some instances, access commands are also used to implement a test program for a memory device. That is, a test program can apply a series of voltages to specific components of a memory device in a specific order by providing a specific series of access commands to the memory device. However, as the capacity of memory devices increases, the duration of the test program also increases. This increase in test program duration can be exacerbated for memory devices that use access commands to implement test programs and techniques associated with longer duration access command sequences. In addition to the increased test program duration, using access command sequences to implement the test program can result in increased current (and therefore increased power) usage and inadvertent interference that can adversely affect the test program—for example, when the access command sequence causes the memory device to perform unnecessary operations that modify the voltages of one or more memory components.

[0018] To reduce test duration, reduce current draw during a test procedure, and mitigate the adverse effects of unintentional interference, a new access command sequence may be used when testing memory devices. For example, when executing a test procedure, a modified set of operations may be used to execute a PRE command. In some instances, a PRE command may be executed using a set of operations that omits operations that would otherwise be performed to execute the PRE command—for example, operations associated with writing a logic state back to a memory cell may be omitted. By omitting certain operations from the modified set of operations, the duration of the PRE command sequence may be reduced, the amount of current drawn by the memory device during the PRE command sequence may be reduced, or the amount of interference caused by the PRE command sequence may be reduced, or any combination thereof. In some instances, the modified set of operations used to execute the PRE command is referred to as a fast PRE command sequence, and the unmodified set of operations may be referred to as a PRE command sequence.

[0019] In some instances, a fast PRE command can be used when a test program executed on a memory device is not concerned with the logic state of the memory cells, for example, when the test program does not care whether the correct logic state is read from and written back to the memory cells during the test program. Additionally or alternatively, a fast PRE command can be used when the duration of the PRE command sequence exceeds a threshold duration, the amount of current drawn by the PRE command sequence exceeds a threshold current, or the amount of perturbation caused by the PRE command sequence exceeds a threshold amount, or any combination thereof. Additionally or alternatively, a fast PRE command sequence can be used to support test programs that attempt to test components without accommodating the additional voltages that will be applied to or removed from the components during the PRE command sequence.

[0020] As reference Figure 1 and 2 As described, the features of the present disclosure are first described in the context of a storage system and a die. Figure 3 Features of the present disclosure are described in the context of an exemplary method for executing a fast precharge command sequence in FIG. Figures 4 to 6 These and other features of the present disclosure are further illustrated and described with reference to device diagrams and flow charts relating to a fast precharge command sequence in FIG.

[0021] Figure 1 An example of a system 100 that supports execution of the Fast Precharge command sequence disclosed herein is shown.

[0022] The system 100 may include a host device 105, a memory device 110, and a plurality of channels 115 coupling the host device 105 with the memory device 110. The system 100 may include one or more memory devices 110, but aspects of the one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110). The system 100 may include part of an electronic device, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a vehicle, or other system. For example, the system 100 may illustrate aspects of a computer, a laptop computer, a tablet computer, a smartphone, a cellular phone, a wearable device, an internet-connected device, a vehicle controller, etc. The memory device 110 may be a component of the system that is operable to store data for one or more other components of the system 100.

[0023] At least a portion of system 100 can be an example of a host device 105. Host device 105 can be an example of a processor or other circuitry in a device that uses memory to execute processes, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop computer, a tablet computer, a smartphone, a cellular phone, a wearable device, an Internet-connected device, or some other fixed or portable electronic device, among other examples. In some examples, host device 105 can refer to hardware, firmware, software, or a combination thereof that implements the functionality of external memory controller 120. In some examples, external memory controller 120 can be referred to as a host or host device 105.

[0024] The memory device 110 can be a standalone device or a component operable to provide a physical memory address / space that can be used or referenced by the system 100. In some examples, the memory device 110 can be configured to operate with one or more different types of host devices. The signaling between the host device 105 and the memory device 110 can be operable to support one or more of the following: a modulation scheme for modulating signals, various pin configurations for transmitting signals, various form factors for the physical packaging of the host device 105 and the memory device 110, clock signaling and synchronization between the host device 105 and the memory device 110, timing conventions, or other factors.

[0025] Memory device 110 is operable to store data of components of host device 105. In some examples, memory device 110 can act as a slave type device to host device 105 (e.g., responding to and executing commands provided by host device 105 via external memory controller 120). Such commands can include one or more of a write command for a write operation, a read command for a read operation, a refresh command for a refresh operation, or other commands.

[0026] Host device 105 may include one or more of an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or other components such as one or more peripheral components or one or more input / output controllers. The components of the host device may be coupled to each other using a bus 135.

[0027] The processor 125 is operable to provide control or other functionality for at least a portion of the system 100 or at least a portion of the host device 105. The processor 125 can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or a combination of these components. In such instances, the processor 125 can be an instance of a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose GPU (GPGPU), or a system on a chip (SoC), or other instances. In some instances, the external memory controller 120 can be implemented by or as part of the processor 125.

[0028] BIOS component 130 may be a software component including a BIOS operating as firmware that may initialize and run various hardware components of system 100 or host device 105. BIOS component 130 may also manage the flow of data between processor 125 and various components of system 100 or host device 105. BIOS component 130 may include a program or software stored in one or more of read-only memory (ROM), flash memory, or other non-volatile memory.

[0029] The memory device 110 may include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a desired capacity or specified capacity for data storage. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). The memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more groups, one or more tiles, one or more portions), where each memory cell is operable to store at least one data bit. A memory device 110 including two or more memory dies may be referred to as a multi-die memory or a multi-die package or a multi-chip memory or a multi-chip package.

[0030] The device memory controller 155 may include circuitry, logic, or components operable to control the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, or instructions that enable the memory device 110 to perform various operations, and may be operable to receive, send, or execute commands, data, or control information related to the components of the memory device 110. The device memory controller 155 may be used to communicate with one or more of the external memory controller 120, one or more memory die 160, or the processor 125. In some examples, the device memory controller 155 may, in conjunction with the local memory controller 165 of the memory die 160, control the operation of the memory device 110 described herein.

[0031] In some examples, memory device 110 can receive data or commands, or both, from host device 105. For example, memory device 110 can receive a write command indicating that memory device 110 will store data for host device 105 or a read command indicating that memory device 110 will provide data stored in memory die 160 to host device 105.

[0032] A local memory controller 165 (e.g., local to the memory die 160) may be used to control the operation of the memory die 160. In some examples, the local memory controller 165 may be operable to communicate with the device memory controller 155 (e.g., to receive or send data or commands or both). In some examples, the memory device 110 may not include a device memory controller 155 and a local memory controller 165, or the external memory controller 120 may perform the various functions described herein. Thus, the local memory controller 165 may be operable to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 120, or the processor 125, or a combination thereof. Examples of components that may be included in the device memory controller 155 or the local memory controller 165, or both, may include a receiver for receiving signals (e.g., from the external memory controller 120), a transmitter for sending signals (e.g., to the external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, or various other circuits or controllers operable to support the described operations of the device memory controller 155 or the local memory controller 165, or both.

[0033] The external memory controller 120 is operable to facilitate communication of one or more of information, data, or commands between components of the system 100 or host device 105 (e.g., processor 125) and the memory device 110. The external memory controller 120 can convert or translate communications exchanged between components of the host device 105 and the memory device 110. In some instances, the external memory controller 120 or other components of the system 100 or host device 105, or their functionality described herein, can be implemented by the processor 125. For example, the external memory controller 120 can be hardware, firmware, software, or some combination thereof implemented by the processor 125 or other components of the system 100 or host device 105. Although the external memory controller 120 is described as being external to the memory device 110, in some instances, the external memory controller 120 or its functionality described herein can be implemented by one or more components of the memory device 110 (e.g., device memory controller 155, local memory controller 165), or vice versa.

[0034] Components of the host device 105 can exchange information with the memory device 110 using one or more channels 115. The channels 115 are operable to support communication between the external memory controller 120 and the memory device 110. Each channel 115 can be an example of a transmission medium that carries signals between the host device 105 and the memory device. Each channel 115 can include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of the system 100. A signal path can be an example of a conductive path that is operable to carry a signal. For example, a channel 115 can include a first terminal that includes one or more pins or pads at the host device 105 and one or more pins or pads at the memory device 110. A pin can be an example of a conductive input or output point of a device of the system 100, and the pin can be operable to serve as part of a channel.

[0035] Channels 115 (and associated signal paths and terminals) can be dedicated to conveying one or more types of information. For example, channels 115 can include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or a combination thereof. In some examples, communication on channels 115 can be performed using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of a signal can be recorded for each clock cycle (e.g., on either the rising or falling edge of a clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of a signal can be recorded for each clock cycle (e.g., on both the rising and falling edges of a clock signal).

[0036] In some examples, the channels 115 can include one or more command and address (CA) channels 186. The CA channels 186 are operable to communicate commands between the host device 105 and the memory device 110, including control information associated with the commands (e.g., address information). For example, the CA channels 186 can include a read command with the address of the desired data. In some examples, the CA channels 186 can include any number of signal paths to decode one or more address or command data (e.g., eight or nine signal paths).

[0037] The memory device 110 may be tested for reliability and defects, for example, before or while the memory device 110 is deployed. In some examples, a test program running on the host device 105 provides a memory (or access) command sequence to the memory device 110—for example, via the channel 115—to execute the test program on the memory device 110. In some examples, the memory device 110 may be configured to execute a received access command using a modified access command sequence based on being configured in a particular operating mode (e.g., a test mode). For example, the memory device 110 may execute an access command sequence that omits one or more operations that would otherwise be used to execute the received access command when the memory device 110 is in a test mode configured to ignore data stored in accessed memory cells. The access command sequence that omits the operations may be shorter, use less current, or introduce less interference (or any combination thereof) than an access command sequence that includes the ommitted operations.

[0038] Figure 2 An example of a memory die 200 that supports execution of the Fast Precharge command sequence disclosed herein is shown.

[0039] Memory die 200 may be a reference Figure 1 1 . An example of a memory die 160 is depicted. In some examples, the memory die 200 may be referred to as a memory chip, a memory device, or an electronic memory device. The memory die 200 may include one or more memory cells 205, each of which may be programmed to store a different logic state (e.g., a programmed one of a set of two or more possible states). For example, the memory cell 205 may be operable to store one bit of information at a time (e.g., a logic 0 or a logic 1). In some examples, the memory cell 205 (e.g., a multi-level memory cell) may store more than one bit of information at a time (e.g., a logic 00, a logic 01, a logic 10, a logic 11).

[0040] Memory cell 205 may store a state (e.g., a polarization state or dielectric charge) in a capacitor representing a programmable state. In a FeRAM architecture, memory cell 205 may include capacitor 240, which includes a ferroelectric material to store a charge and / or polarization representing a programmable state. Memory cell 205 may include a logic storage component (such as capacitor 240) and a switching component 245. Capacitor 240 may be an example of a ferroelectric capacitor. A first node of capacitor 240 may be coupled to switching component 245, and a second node of capacitor 240 may be coupled to plate line 220. Switching component 245 may be an example of a transistor or any other type of switching device that selectively establishes or cancels electronic communication between two components.

[0041] Memory die 200 may include access lines (e.g., word lines 210, digit lines 215, and plate lines 220) arranged in a pattern such as a grid pattern. Access lines may be conductive lines coupled to memory cells 205 and may be used to perform access operations on memory cells 205. In some examples, word lines 210 may be referred to as row lines. In some examples, digit lines 215 may be referred to as column lines or bit lines. References to access lines, row lines, column lines, word lines, digit lines, bit lines, or plate lines, or similar representations thereof, may be interchanged without loss of understanding or operation. Memory cells 205 may be located at intersections of word lines 210, digit lines 215, and / or plate lines 220.

[0042] By activating or selecting access lines, such as word lines 210, digit lines 215, and / or plate lines 220, operations such as reading and writing can be performed on memory cells 205. By biasing word lines 210, digit lines 215, and plate lines 220 (e.g., applying a voltage to word lines 210, digit lines 215, or plate lines 220), individual memory cells 205 can be accessed at their intersections. Activating or selecting word lines 210, digit lines 215, or plate lines 220 can include applying a voltage to the corresponding lines.

[0043] Access to the memory cell 205 may be controlled by a row decoder 225, a column decoder 230, and a plate driver 235. For example, the row decoder 225 may receive a row address from the local memory controller 265 and activate the word line 210 based on the received row address. The column decoder 230 may receive a column address from the local memory controller 265 and activate the digit line 215 based on the received column address. The plate driver 235 may receive a plate address from the local memory controller 265 and activate the plate line 220 based on the received plate address.

[0044] Selecting or deselecting memory cell 205 can be accomplished by activating or deactivating switching element 245. Using switching element 245, capacitor 240 can be placed in electronic communication with digit line 215. For example, capacitor 240 can be isolated from digit line 215 when switching element 245 is deactivated and can be coupled to digit line 215 when switching element 245 is activated.

[0045] The word line 210 can be a conductive line in electronic communication with the memory cell 205 and is used to perform access operations on the memory cell 205. In some architectures, the word line 210 can be in electrical communication with the gate of the switching component 245 of the memory cell 205 and can be operable to control the switching component 245 of the memory cell. In some architectures, the word line 210 can be in electronic communication with a node of the capacitor of the memory cell 205, and the memory cell 205 may not include a switching component.

[0046] The digit line 215 can be a conductive line connecting the memory cell 205 and the sensing element 250. In some architectures, the memory cell 205 can be selectively coupled to the digit line 215 during portions of an access operation. For example, the word line 210 and the switching element 245 of the memory cell 205 can be operable to selectively couple and / or isolate the capacitor 240 of the memory cell 205 and the digit line 215. In some architectures, the memory cell 205 can be in electronic communication (e.g., constant) with the digit line 215.

[0047] Plateline 220 may be a conductive line in electronic communication with memory cell 205 and used to perform access operations on memory cell 205. Plateline 220 may be in electronic communication with a node (e.g., the bottom of the cell) of capacitor 240. Plateline 220 may cooperate with digit line 215 to bias capacitor 240 during access operations of memory cell 205.

[0048] The sensing component 250 can determine the state (e.g., polarization state or charge) stored on the capacitor 240 of the memory cell 205 and determine the logic state of the memory cell 205 based on the detected state. The sensing component 250 can include one or more sense amplifiers to amplify the signal output of the memory cell 205. The sensing component 250 can compare the signal received from the memory cell 205 across the digit line 215 with a reference line 255 (e.g., a reference voltage). The detected logic state of the memory cell 205 can be provided as an output of the sensing component 250 (e.g., to the input / output 260) and can indicate the detected logic state to another component of the memory device 110 including the memory die 200.

[0049] The local memory controller 265 may control the operation of the memory cell 205 through various components (eg, the row decoder 225, the column decoder 230, the plate driver 235, and the sensing component 250). The local memory controller 265 may be a reference Figure 1 1. An example of a local memory controller 165 is described. In some examples, one or more of the row decoder 225, column decoder 230, plate driver 235, and sensing component 250 can be co-located with the local memory controller 265. The local memory controller 265 is operable to receive one or more commands or data from one or more different memory controllers (e.g., an external memory controller 120 associated with the host device 105, another controller associated with the memory die 200), translate the commands or data (or both) into information usable by the memory die 200, perform one or more operations on the memory die 200, and transfer data from the memory die 200 to the host device 105 based on the one or more operations performed. The local memory controller 265 can generate row signals and column address signals to activate the target word lines 210, target digit lines 215, and target plate lines 220. The local memory controller 265 can also generate and control various voltages or currents used during operation of the memory die 200. In general, the magnitude, shape, or duration of applied voltages or currents discussed herein may vary and may be different for the various operations discussed in operating memory die 200 .

[0050] The local memory controller 265 is operable to perform one or more access operations on one or more memory cells 205 of the memory die 200. Examples of access operations may include a write operation, a read operation, a refresh operation, a precharge operation, or an activate operation, etc. The local memory controller 265 is operable to perform other access operations not listed here or other operations related to the operation of the memory die 200 that are not directly related to accessing the memory cells 205.

[0051] The local memory controller 265 is operable to perform write operations (e.g., programming operations) on one or more memory cells 205 of the memory die 200. During a write operation, the memory cells 200 of the memory die 205 can be programmed to store a desired logic state. The local memory controller 265 can identify the target memory cell 205 on which the write operation is to be performed. The local memory controller 265 can identify the target word line 210, target digit line 215, and target plate line 220 coupled to the target memory cell 205. The local memory controller 265 can activate the target word line 210, target digit line 215, and target plate line 220 (e.g., apply a voltage to the word line 210, digit line 215, or plate line 220) to access the target memory cell 205. During a write operation, the local memory controller 265 can apply a specific signal (e.g., a write pulse) to the digit line 215 during the write operation to store a specific state (e.g., charge) in the capacitor 240 of the memory cell 205. A pulse used as part of a write operation may include one or more voltage levels over a duration.

[0052] The local memory controller 265 is operable to perform a read operation (e.g., a sense operation) on one or more memory cells 205 of the memory die 200. During a read operation, the logic state stored in the memory cell 205 of the memory die 200 can be determined. The local memory controller 265 can identify the target memory cell 205 on which the read operation is to be performed. The local memory controller 265 can identify the target word line 210, target digit line 215, and target plate line 220 coupled to the target memory cell 205. The local memory controller 265 can activate the target word line 210, target digit line 215, and target plate line 220 (e.g., apply a voltage to the word line 210, digit line 215, or plate line 220) to access the target memory cell 205. The target memory cell 205 can pass a signal to the sense component 250 in response to biasing the access line. The sense component 250 can amplify the signal. Local memory controller 265 can activate sense component 250 (e.g., latch sense component) and thereby compare the signal received from memory cell 205 to reference line 255. Based on the comparison, sense component 250 can determine the logic state stored on memory cell 205.

[0053] Information can be stored in and read from the memory die 200 using access commands that trigger a set of operations to be performed at the memory die 200 (which may also be referred to as a command sequence or access command sequence). In some examples, the signal used to transmit the access command includes an indication of the type of access command—e.g., using two bits transmitted in the signal—and the address of the memory cell to which the access command is directed—e.g., using the remaining bits transmitted in the signal to indicate a memory bank, memory portion, or memory row, or any combination thereof. Types of access commands can include an activate (ACT) command and a precharge (PRE) command. The ACT command can be used to prepare (or open) an addressed row of memory cells 205 for a subsequent read operation or write operation. For example, the ACT command can be used to connect all memory cells 205 coupled to a word line 210 (e.g., WL_1) to coupled digit lines 215 (e.g., DL_1 to DL_N). In some examples, the ACT command may also be used to sense the logic state of a row of memory cells 205 , for example, by activating sensing elements 250 coupled to digit lines 215 after connecting the row of memory cells 205 to the digit lines 215 .

[0054] The PRE command can be used to close an open row of memory cells 205 before opening or accessing, or opening and accessing, another row of memory cells 205. In some examples, the PRE command can be used to close a memory portion or memory bank including a row of memory cells 205 so that a different row of memory cells 205 in the memory portion or memory bank can be opened. For example, the PRE command can be used to disconnect a row of memory cells 205 coupled to a word line 210 (e.g., WL_1) from the coupled digit lines 215 (e.g., DL_1 to DL_N). In some examples, the PRE command can also be used to write a previously sensed logic state (e.g., a logic state sensed by the sense component 250 during an ACT command) back to the row of memory cells 205. In some examples, the previously sensed logic state is written back to the row of memory cells 250 using the output of the sense component 205. In some examples, the local memory controller 265 at the memory die 200 can receive access commands from an external device (e.g., a host device). In other examples, the access command may be generated internally by the memory die 200 , for example, the local memory controller 265 may generate the access command based on a test program installed on the local memory controller 265 or another component on the memory die 200 .

[0055] The local memory controller 265 may execute the received or generated access command. To execute the access command, the local memory controller 265 may perform a set of operations (or an access command sequence) corresponding to the access command—for example, the local memory controller 265 may apply a series of voltages to specific components in a predetermined order. In some instances, the duration of executing an access command sequence for executing an access command for one technology may be longer than the duration of executing an access command sequence for executing the same access command for another technology. For example, an access command sequence for executing an access command for accessing memory cells of one technology may include longer timing intervals, additional operations, or both, relative to an access command sequence for executing the same access command for accessing memory cells of another technology. For example, executing an access command sequence to execute an ACT command (or an ACT command sequence) to open a row of ferroelectric memory cells may take longer than executing an ACT command sequence to open a row of DRAM cells. Similarly, executing a set of operations to execute a PRE command (or a PRE command sequence) to close a row of ferroelectric memory cells may take longer than executing a PRE command sequence to close a row of DRAM cells.

[0056] In some examples, executing an ACT command sequence for one or more ferroelectric memory cells 205 can include three sets of operations. That is, the ACT command sequence can include a first set of operations associated with connecting one or more digit lines 215 to the one or more ferroelectric memory cells 205. The ACT command sequence can also include a second set of operations associated with exchanging charge between the one or more ferroelectric memory cells 205 and the one or more digit lines 215, for example, based on the charge stored in the one or more ferroelectric memory cells 205. And the ACT command sequence can include a third set of operations associated with sensing the voltage of the one or more digit lines 215 to determine the logic state stored in the one or more ferroelectric memory cells 205, for example, based on the charge exchanged between the one or more digit lines 215 and the one or more ferroelectric memory cells 205.

[0057] The first set of operations in the ACT command sequence can include activating the memory bank or memory portion addressed by the ACT command while decoding the row address included in the ACT command. After the row address is decoded and the digit lines 215 are precharged, the word lines 210 coupled to a row of ferroelectric memory cells 205 located at the row address can be identified.

[0058] A second set of operations in the ACT command sequence can include precharging a digit line 215 coupled to a row of ferroelectric memory cells 205 in a memory bank or memory portion addressed by the ACT command. In some instances, the digit line 215 is precharged while the row address is being decoded. In other instances, the digit line 215 is precharged after the row address is decoded. In some instances, precharging the digit line 215 can include charging the digit line 215 to a non-zero voltage. In some instances, precharging the digit line 215 can include applying an additional "boost" voltage to the digit line 215 after charging the digit line 215 to an intermediate voltage—for example, to complete precharging the digit line to a sense voltage. In other instances, precharging the digit line 215 can include connecting the digit line 215 to ground or a virtual ground.

[0059] After decoding the row address and precharging the digit line 215, a second set of operations can include activating the word line 210 coupled to the row of ferroelectric memory cells 205. For example, an activation voltage can be applied to the word line 210 so that an access voltage is applied across the row of ferroelectric memory cells 205. After activating the word line 210 and applying the access voltage across the row of ferroelectric memory cells, the second set of operations can include waiting for a predetermined duration to generate a signal on the digit line 215 while charge is exchanged between the row of ferroelectric memory cells 205 and the digit line 215. In some examples, the voltage of the digit line 215 can be maintained at a sense voltage while the signal is generated, and an amplifying capacitor can be used to measure the amount of charge to maintain the sense voltage.

[0060] A third set of operations in the ACT command sequence may be performed after the second set of operations are performed. The third set of operations may include closing a gate (or "isolation gate") that isolates the sensing component 250 from the digit line 215, thereby connecting the sensing component 250 to the digit line 215. After connecting the sensing component 250 to the digit line 215, the sensing component 250 may be activated to sense the logic state stored by the row of ferroelectric memory cells 205 based on the exchange of charge between the row of ferroelectric memory cells 205 and the digit line 215. In some examples, the sensing is based on the amount of charge stored by the amplifying capacitor at the end of the signal generation wait period. In some examples, sensing the logic state may include latching the output of the sensing component 250 to store the sensed logic state.

[0061] After sensing and latching the logic states of the row of ferroelectric memory cells 205, a third set of operations may include removing the applied voltage across the row of ferroelectric memory cells 205—for example, zero volts may be applied across the row of ferroelectric memory cells 205—to complete the ACT command sequence. In some examples, when no voltage is applied across the ferroelectric memory cells 205, the ferroelectric memory cells 205 may be referred to as being in a zero-disturb state. In some examples, the duration for fully executing the ACT command sequence may extend to approximately 77.5 nanoseconds. In some examples, the word line 210 remains activated after completing the ACT command sequence. In some examples, removing the voltage across the row of ferroelectric memory cells 205 may cause a logic state initially stored at a portion of the row of ferroelectric memory cells 205 (e.g., ferroelectric memory cells storing a "0") to be rewritten to that portion of the ferroelectric memory cells, and an opposite logic state to be stored at another portion of the row of ferroelectric memory cells 205 (e.g., ferroelectric memory cells storing a "1," or vice versa). In some examples, removing the voltage applied across the row of ferroelectric memory cells 205 can include equalizing the voltages of plate line(s) 220 (eg, PL_1 ) and digit line 215 , for example, by discharging digit line 215 to virtual ground.

[0062] In some examples, executing a PRE command sequence for one or more ferroelectric memory cells 205 can include two sets of operations. That is, the PRE command sequence can include a first set of operations associated with writing a previously sensed logic state back to the one or more ferroelectric memory cells 205. And the PRE command sequence can include a second set of operations associated with disconnecting the one or more ferroelectric memory cells 205 from the one or more digit lines 215.

[0063] A first set of operations in the PRE command sequence can include, for example, closing an isolation gate that isolates the sense component 250 from a digit line 215 coupled to a row of ferroelectric memory cells 205 by applying an activation voltage to a transistor coupling the sense component 250 and the digit line 215. In some examples, during the first interval, after the sense component 250 is coupled to the digit line 215, a voltage is applied across a ferroelectric memory cell 205 in the row of ferroelectric memory cells 205—for example, if a latch at the sense component 250 and associated with the ferroelectric memory cell 205 outputs a high voltage and a low voltage is applied to the plate line 220 coupled to the ferroelectric memory cell 205.

[0064] After closing the isolation barrier and during the second interval, the first set of operations can include applying a voltage to the plate line(s) 220. In some examples, after applying the voltage to the plate line(s) 220, a voltage is applied across one of the ferroelectric memory cells 205 in the row of ferroelectric memory cells 205—for example, if the sensing component 250 outputs a low voltage and a high voltage is applied to the plate line 220 coupled to the ferroelectric memory cell 205. In some examples, such as the logic state sensed in response to an ACT command, the output(s) of the sensing component 250 are based on the logic state of the row of ferroelectric memory cells 205 sensed during a previous operation. By shifting the voltage of the plate line(s) 205 from a low voltage to a high voltage, or vice versa, the logic state of the row of ferroelectric memory cells 205 previously sensed by the sensing component 250 can be written back to the row of ferroelectric memory cells 205. Furthermore, by performing the first set of operations, the logic state of the row of ferroelectric memory cells 205 can be restored after the destructive sensing operation.

[0065] A second set of operations in the PRE command sequence can be performed after the first set of operations are performed. The second set of operations can include balancing the voltages of the digit line 215 and the plate line(s) 220 so that no voltage (i.e., 0V) is applied across the row of ferroelectric memory cells 205. In some examples, balancing the voltages of the digit line 215 and the plate line(s) 220 includes applying the same voltage (e.g., a low, medium, or high voltage) to the digit line 215 and the plate line(s) 220. In some examples, balancing the voltages of the digit line 215 and the plate line(s) 220 includes waiting for a duration associated with removing charge between the bottom of the row of ferroelectric memory cells 205 and the select components that couple the row of ferroelectric memory cells 205 to the digit line 215. That is, waiting for the duration can prevent residual charge from being trapped on the bottom of the ferroelectric memory cells 205 when the select components are deactivated. Once the voltages of the digit line 215 and the plate line(s) 220 have equalized or the duration has expired (or both), the ferroelectric memory cell 205 can be said to be in a zero-disturb state.

[0066] After equalizing the voltages of the plate line(s) 220 and the digit line 215, a second set of operations can include applying a disable voltage to the word line 210 coupled to the select component, which can disable the select component and isolate the row of ferroelectric memory cells 205 from the digit line 215. The second set of operations can include deactivating the sense component 250. In some examples, the sense component 250 is deactivated simultaneously with deactivating the word line 210. In other examples, the sense component is deactivated after deactivating the word line 210. After the sense component 250 is deactivated, the second set of operations can include equalizing nodes of the sense component 250 to complete the PRE command sequence. In some examples, the nodes of the sense component 250 can correspond to a first input node coupled to the digit line 215 and a second input node coupled to the reference line 255. In some examples, the duration for fully executing the PRE command sequence can extend to approximately 80 nanoseconds.

[0067] The memory die 200 can be tested to ensure reliability or to identify failures (or both) and other causes. To test the memory die 200, one or more test procedures can be performed on the memory die 200. Some test procedures include margin testing, burn-in testing, reliability testing, qualification testing, and bench characterization testing. Margin testing can include applying specific patterns to components within the memory die 200 while performing timing and voltage measurements on specific components within the memory die 200. In some examples, margin testing includes applying patterns that are likely to cause signal interference to the components of the memory die 200. Margin testing is used to identify areas within the memory die 200 that are susceptible to such interference—for example, by measuring voltages at certain components that exceed a threshold voltage. Burn-in testing can include operating the memory die 200 under extreme operating conditions (e.g., elevated temperature and / or voltage) for an extended period of time. During the initial stages of burn-in testing, less robust components may fail (e.g., disconnected access lines, shorted memory cells, etc.) and can therefore be identified prior to deployment. Burn-in testing can be used to induce early failures so that the memory die 200 can be configured to avoid failed components before the memory die 200 is deployed.

[0068] Qualification testing can include operating the memory die 200 within communicated specifications—for example, by executing a command sequence within specified timing parameters. Qualification testing can be used to confirm that the memory die 200 meets the communicated specifications. Similarly, bench characterization testing can include operating the memory device within certain parameters—for example, by executing a command sequence within experimental timing parameters. Bench characterization testing can be used to determine the specifications of the memory die 200.

[0069] In some examples, for example, to apply a specific voltage pattern to components within the memory die 200, a test procedure may be executed by providing a specific sequence of access commands to the memory die 200. For example, the test procedure may include applying a series of voltages across the memory die 200 or to certain components within the memory die 200 by providing a specific sequence of ACT and PRE commands to the local memory controller 265.

[0070] As the capacity of memory devices increases, the duration to complete a test procedure may also increase—e.g., as more memory cells, traces, sensing components, drivers, etc. are tested. Furthermore, for memory devices that use access command sequences to execute the test procedure, the increased duration of the test procedure associated with high-capacity memory devices may be more severe for memory devices that use technology associated with longer access command sequences, such as FeRAM memory devices.

[0071] Additionally, for memory devices that execute test procedures using sequences of access commands, certain operations performed to execute the access commands may unnecessarily draw current and / or interfere with other components in the memory device—for example, when the particular test procedure is not intended to draw high current and / or generate interference.

[0072] To avoid excessive cost and time, techniques for shortening the test program can be employed. In some examples, to reduce test duration and cost, the memory die 200 can be configured to execute the access command sequence using a modified set of operations (e.g., a shortened set of operations) when executing the test program. Additionally or alternatively, to avoid unnecessary current draw and interference that is detrimental to the test program, the memory die 200 can be configured to execute the access command sequence using a modified set of operations (e.g., a set of operations that excludes operations for applying and removing voltage) when executing the test program.

[0073] For example, when executing a test program, an ACT command may be executed using a modified set of operations. For example, a local memory controller 265 receiving an ACT command directed to (or addressing) a row of memory cells 205 may omit operations in the ACT command sequence associated with the exchange of charge between the row of memory cells 205 and the corresponding digit lines 215—for example, to set up a sensing operation. The local memory controller 265 may also omit operations for sensing the logic state stored by the row of memory cells 205. This command sequence may be referred to as a "fast ACT command sequence."

[0074] In some examples, the fast ACT command sequence can include two operations: a first operation for activating the memory portion including the row of memory cells 205 and a subsequent operation for activating the word line 210 coupled to the row of memory cells 205. In some examples, the fast ACT command sequence can include a third operation for activating the sense component 250 coupled to the row of memory cells 205, which occurs after the word line 210 is activated. In some examples, the duration for fully executing the fast ACT command sequence can extend to approximately 10 nanoseconds.

[0075] Thus, relative to a full ACT command sequence, a fast ACT command sequence can omit operations for precharging digit line 215 to a precharge voltage; delay operations to allow charge to be exchanged between the row of memory cells 205 and digit line 215; operations for connecting sense component 250 to digit line 215; operations for activating sense component 250; operations for storing a logic state sensed by sense component 250; and / or operations for returning the row of memory cells 205 to a zero-disturb state—for example, because the row of memory cells 205 can be maintained in a zero-disturb state by the fast ACT command sequence. In some examples, a fast ACT command or a series of fast ACT commands can be used to apply a series of voltage pulses to word line 210 in rapid succession without disturbing other components coupled to the word line (e.g., the row of memory cells 205). When a fast ACT command sequence includes a third operation for activating sense component 250, the ACT command or a series of ACT commands can be used to activate and deactivate sense component 250 in rapid succession without disturbing other components coupled to sense component 250 (e.g., the row of memory cells 205).

[0076] In some instances, a fast ACT command sequence may be used when the memory die 200 uses a technique associated with a duration for sensing a logic state that exceeds a threshold duration—for example, if the ACT command sequence exceeds 40 nanoseconds. In some instances, a fast ACT command sequence may be used when the current drawn during a test procedure exceeds a threshold current—for example, if one or more ACT commands are used to activate multiple memory segments. In some instances, a fast ACT command sequence may be used when the disturbance during the test procedure exceeds a threshold disturbance—for example, if the test procedure wants to make measurements independent of disturbances. Additionally, or alternatively, a fast ACT command sequence may be used when running a specific test—for example, when executing a test procedure that ignores the logic state stored in the memory cell 205.

[0077] By using a fast ACT command sequence, the duration of a test procedure using a command sequence including an ACT command can be significantly reduced—e.g., because the fast ACT command sequence has a shorter duration. Furthermore, by using a fast ACT command sequence, the amount of current used during the test procedure can be reduced—e.g., because the application and removal of voltage to access lines is reduced and / or the activation of components is reduced. Furthermore, by using a fast ACT command sequence, unintentional interference with other components can be reduced—e.g., because the application and removal of voltage to access lines is reduced and / or the activation of sensing components is reduced.

[0078] In another example, when executing a test program, a modified set of operations can be used to execute PRE commands. For example, a local memory controller 265 that receives a PRE command directed to (or addresses) a memory bank, memory portion, and / or row(s) of memory cells 205 can omit operations in the PRE command sequence associated with writing a previously sensed logic state back to the row of opened memory cells 205. Such a command sequence can be referred to as a "fast PRE command sequence."

[0079] In some examples, a fast PRE command sequence can include three operations. A first operation for deactivating the word line 210 coupled to the row of memory cells 205. A following operation for deactivating the sense component 250 coupled to the memory cell 205. And a final operation for balancing the nodes of the sense component 250. In some examples, a fast PRE command sequence can include four operations. In this case, the fast PRE command sequence can begin by balancing the digit line 215 and the plate line(s) 220 coupled to the row of memory cells 205, which occurs before the word line 210 is deactivated. In some examples, the duration for fully executing the fast PRE command sequence can extend to 15 nanoseconds.

[0080] Thus, relative to a complete PRE command sequence, a fast PRE command sequence can omit operations for balancing the digit line 215 and the plate line(s) 220 coupled to a row of memory cells 205; operations for connecting an activated sense element 250 (or a latch associated with the sense element 250) to the digit line 215; operations for applying a voltage (e.g., a write voltage) to the plate line(s) 220; a delay operation to allow a logic state to be written to the row of memory cells 205; and / or a delay operation (e.g., a delay operation) to allow charge to be removed from the bottom of the row of memory cells 205. In some examples, the fast PRE command can be used to shut down a row of memory cells 205 for a reduced duration so that a subsequent command (e.g., an ACT command) can be processed more quickly and to allow additional voltages to be applied to the row of memory cells 205, components associated with the row of memory cells 205, and / or another row of memory cells 205.

[0081] In some instances, a fast PRE command sequence can be used when the memory die 200 uses a technique associated with a write-back logic state duration exceeding a threshold duration—for example, if a PRE command sequence exceeds 40 nanoseconds. In some instances, a fast PRE command sequence can be used when the current drawn during a test routine exceeds a threshold current—for example, if one or more PRE commands are used to shut down multiple memory sections. In some instances, a fast PRE command sequence can be used when the disturbance during the test routine exceeds a threshold disturbance—for example, if the test routine wants to make measurements independent of disturbances. Additionally or alternatively, a fast PRE command sequence can be used when running specific tests, such as when executing a test routine that ignores the logic state stored in the memory cell 205 being accessed.

[0082] By using a fast PRE command sequence, the duration of a test procedure using a command sequence including a PRE command can be significantly reduced—for example, because the fast PRE command sequence has a shorter duration. Furthermore, by using a fast PRE command sequence, the amount of current used during the test procedure can be reduced—for example, because the application and removal of voltage to the access line is reduced. Furthermore, by using a fast PRE command sequence, unintentional interference with other components can be reduced—because the application and removal of voltage to the access line is reduced.

[0083] In some instances, a fast ACT command sequence can be used in conjunction with a fast PRE command sequence to further reduce the duration of a test procedure. Furthermore, using fast ACT and fast PRE command sequences can enable a specific operating mode (e.g., test mode) to execute a process (e.g., a test procedure) that is not suitable for certain operations included in the ACT and PRE command sequences.

[0084] Figure 3 An example of a method for executing the Fast Precharge command sequence disclosed herein is shown.

[0085] Flowchart 300 illustrates various aspects of executing a received PRE command by a memory device using a first set of operations associated with a shorter duration, less current consumption, and / or less interference (which may also be referred to as a fast PRE command sequence) relative to a second set of operations (which may also be referred to as a PRE command sequence). In some instances, a fast PRE command sequence may be used when a test program, or a portion of a test program, ignores the logic state stored in a memory cell. For such a test program, whether the logic state stored in the memory cell is correct / restored after performing an access operation may not be important for the overall test program. Thus, a fast PRE command sequence may be configured to execute PRE commands within a shortened duration and / or omit steps associated with reliably writing to or reading from a memory cell.

[0086] In some instances, a PRE command sequence can be used when executing a test program that monitors the logic state stored in a memory cell or when performing a data access procedure. For such test and data access procedures, it is preferred that the logic state stored in the memory cell is correct after the access operation is performed. Therefore, the PRE command sequence can be configured to reliably store the logic state in the memory cell and / or restore the logic state read from the memory cell.

[0087] At block 305, a test program may be selected for or by the memory device. In some instances, the test program is selected by an engineer—e.g., as part of pre-deployment testing or based on a problem identified during operation. In some instances, the test program is selected by the memory device—e.g., based on a portion within a larger test program loaded on the memory device or based on a problem identified during operation of the memory device. In some instances, the selected test program may be a test program that ignores the logic states stored by the memory cells before and after performing access operations. The test program that ignores the logic states may include stress testing, wafer-level margin testing, wafer-level burn-in testing, package burn-in testing, unit-level reliability testing, qualification testing, and / or characterization testing.

[0088] At block 310, the memory device may receive an indication of a selected test program. In some instances, receiving an indication of a selected test program may include receiving an indication of a specific test program or type of test program selected. In some instances, the indication of the selected test program is received from an external device. In other instances, the indication of the selected test program is received from an internal component programmed to run one or a series of test programs.

[0089] Additionally, or alternatively, the memory device may receive an indication that a particular set of operations is to be used to execute the received access command. In some instances, the memory device may receive an indication that a fast PRE command sequence is to be used. In some instances, the fast PRE command sequence is used to reduce the duration of a test procedure, for example, because the fast PRE command sequence can omit operations that would otherwise be used to execute the PRE command sequence, and subsequent operations can be executed more quickly. Similarly, the fast PRE command sequence can be used to reduce current draw and interference with other memory components, for example, because the fast PRE command sequence can omit operations that would otherwise be used to change the voltage of one or more access lines and / or activate and deactivate sensing components during the PRE command sequence. The fast PRE command sequence can also be used to reduce current consumption when the PRE command addresses multiple memory groups, memory portions, and / or memory rows.

[0090] In some instances, the fast PRE command sequence is used to support test programs designed to individually control specific memory components. For example, a test program seeking to control a cell board can use the fast PRE command sequence when the fast PRE command sequence omits operations related to applying voltage to the cell board. Thus, the test program can avoid considering board line upsets that would otherwise be caused by applying voltage to the cell board when executing the PRE command sequence. For example, a test program that applies voltage to a board line for a predetermined duration can use the fast PRE command sequence to prevent additional voltage from being applied to the board line after the voltage is removed when the memory cell is turned off—for example, because the additional voltage could defeat the purpose of the test program.

[0091] Similarly, a fast PRE command sequence can be used to support test programs that seek to control switching components used to connect sensing components to digit lines. In some instances, a fast PRE command sequence can also facilitate applying a specific voltage sequence to a specific memory component, regardless of the voltage that would otherwise be applied to shut down the memory cell when the PRE command sequence is executed. In some instances, a test program that applies (or cycles) a specific voltage sequence to a plate line or digit line can use a fast PRE command sequence to prevent additional voltage from being applied to the plate line or digit line when shutting down the memory cell. In some instances, a fast PRE command sequence can be used to discharge the bottom of a memory cell before deactivating the corresponding word line by maintaining electrical connection between the memory cell and the digit line without applying voltage to the digit line or plate line coupled to the memory cell.

[0092] In other examples, the memory device may receive an indication that a PRE command sequence is to be used. In some examples, the duration for executing the PRE command sequence may be longer than the duration for executing the fast PRE command sequence. In some examples, the PRE command sequence may include operations included in the fast PRE command sequence and additional operations. In some examples, the additional operations included in the PRE command sequence may be associated with writing back a logic state to a previously sensed memory cell.

[0093] At block 315, the memory device may be configured for a test mode corresponding to the selected test program. In some examples, the memory device is externally configured for a test mode—for example, by applying a voltage to a test pin to activate and / or deactivate certain components within the memory device to support the corresponding test mode. In some examples, after being configured for a test mode, the memory device may process received access commands according to the configured test mode.

[0094] For example, if activating the test pins results in a first test mode associated with a test procedure that ignores the logic states of memory cells configured at the memory device, the memory device may execute a fast PRE command sequence after receiving the PRE command. In other examples, if activating the test pins results in a second test mode that maintains the logic states of memory cells configured at the memory device, the memory device may execute a PRE command sequence after receiving the PRE command.

[0095] In some examples, activating the test pin can cause a first test component within the memory device that stores a first set of operations for executing an access command (e.g., storing a fast PRE command sequence) to be activated, and / or cause a second test component within the memory device that stores a second set of operations for executing an access command (e.g., storing a PRE command sequence) to be disabled. In some examples, activating the test pin can cause the sense component to refrain from performing actions associated with writing a logic state back to the memory cell or to be completely disabled.

[0096] In other examples, the memory device configures itself into a test mode—for example, the memory device may activate and deactivate certain components within the memory device based on receiving an indication of a test mode. In some examples, the memory device may configure a test module to execute a received memory command using a first set of operations (e.g., a fast PRE command sequence) after receiving an indication that a test program that ignores logic states is to be run. In another example, the memory device may configure a test module to execute a received memory command using the first set of operations after receiving an indication that the first set of operations is to be used. In some examples, the indication indicates a specific duration for using the indicated set of operations. In other examples, the memory device is configured to use the indicated set of operations until an indication to the contrary is received.

[0097] In some examples, configuring the test module to use the first set of operations can include activating a first test component that stores the first set of operations for executing access commands and / or deactivating a second test component that stores a second set of operations for executing access commands (e.g., a PRE command sequence). In some examples, the memory device can configure the sense component to refrain from performing actions associated with writing logic states back to the memory cells, or can disable the sense component entirely based on receiving an instruction from the test program.

[0098] In other examples, the memory device can configure the test module to execute the received memory command (e.g., a PRE command sequence) using the second set of operations after receiving an indication that a test program intended to preserve a logic state is to be run or an explicit indication that the second set of operations is to be used. In some examples, configuring the test module to use the second set of operations can include activating the second test component and / or deactivating the first test component that stores the first set of operations for executing the access command.

[0099] At block 320, the memory device may receive a PRE command as part of a test program. In some instances, the PRE command is used to shut down a memory bank, memory portion, and / or memory cell row. Shutting down a memory cell may include disabling components used to access the memory cell (e.g., word lines, sensing components, digit lines, etc.). In some instances, shutting down a memory cell may also include writing back a logic state to the memory cell based on a previous sensing operation performed on the memory cell. In some instances, the PRE command is received from an external device—e.g., a host device that is running a test program and generating commands (including the PRE command) to execute the test program. In some instances, the PRE command is generated within the memory device—e.g., by an embedded test module running the test program. In some instances, the received PRE command includes address information identifying one or more memory cells for which the received PRE command is intended. For example, the received PRE command may include a memory bank address, a memory portion address, and / or a memory row address associated with the one or more memory cells.

[0100] In some examples, a PRE command is received (e.g., serially or in parallel) with other access commands that are also used to execute a test program. In some examples, a PRE command is received after receiving an ACT command for one or more memory cells as part of a test program, and the PRE command can be used to shut down a row of memory cells. In some examples, the received PRE command is a PREALL command. The PREALL command can be used to shut down all memory banks (or activated memory banks) in a memory device, all memory sections in a memory bank, and / or all memory rows in a memory section or all memory banks.

[0101] At block 325, the memory device may select a set of operations (or access command sequences) for executing the received PRE command. In some instances, the memory device selects the fast PRE command sequence as a result of being configured in a first test mode associated with a fast PRE command sequence, i.e., the memory device may automatically execute the fast PRE command sequence based on having been previously configured in the first test mode. In other instances, the memory device selects the fast PRE command sequence after determining that the memory device has been configured in the first test mode. In some instances, the memory device selects the fast PRE command sequence based on determining that a particular test program or type of test program is being executed.

[0102] In some examples, a fast PRE command sequence omits operations associated with writing back previously sensed logic states to memory cells included in the PRE command sequence. By omitting operations associated with writing back logic states, the duration of executing a PRE command can be reduced. The omitted operations can include operations for connecting a sensing component to a digit line—e.g., applying an output of the sensing component to a memory cell, where the output is based on a previously sensed logic state from the memory cell. By omitting operations associated with applying a voltage to a digit line, the voltage of the digit line can remain fixed (e.g., at a ground reference) for all or an extended portion of the execution of the PRE command, thereby reducing current draw and interference with other memory components during the execution of the PRE command.

[0103] The omitted operations may also include operations for applying a voltage to the plate line—for example, to write back the logic state to a memory cell storing a particular logic state. By omitting operations for applying a voltage to the plate line, the voltage of the plate line may remain fixed (for example, at a ground reference) for all or a longer portion of the execution of the PRE command, thereby reducing current consumption and interference with other memory components during the execution of the PRE command. The omitted operations may also include wait operations that provide a duration for reliably writing back the logic state of the memory cell. Additionally, the omitted operations may include operations for equalizing the voltages of the digit line and the plate line—for example, because the voltages of the digit line and the plate line do not change during the fast PRE command sequence.

[0104] Similarly, by omitting the operation of connecting the output of the sense component to the digit line and the voltage to the plate line, the amount of current drawn during the PREALL command can be reduced. In some instances, the amount of current drawn can be reduced below a threshold, which can enable the PREALL command to address a greater number of memory banks and / or memory portions.

[0105] In other instances, a PRE command sequence may be selected—for example, if the memory device is configured in a second test mode associated with a PRE command sequence. In this case, the memory device may execute the received PRE command by executing the PRE command sequence including the omitted operations.

[0106] At block 330, the memory device may execute the received PRE command by executing a fast PRE command sequence—e.g., based on the first test mode being configured. When executing the fast PRE command sequence, the memory device may begin by equalizing the voltages of the digit line(s) and the plate line(s), e.g., if the voltages of the digit line(s) and the plate line(s) have not yet been equalized. In some examples, equalizing the voltages of the digit line(s) and the plate line(s) includes applying the same voltage (e.g., a high voltage or a low voltage) to the digit line(s) and the plate line(s). Next, the memory device may deactivate the word lines. In some examples, deactivating the word lines includes applying a high voltage or a low voltage to the word lines, which may deactivate select components used to couple and decouple a row of memory cells to the digit lines. In some examples, the first set of operations omits the equalization operation and initially deactivates the word lines—e.g., if the voltages of the digit line(s) and the plate line(s) have already been equalized.

[0107] After, simultaneously with, or before deactivating the word line, the sensing component may be deactivated. Deactivating the sensing component may include disconnecting the sensing component from a voltage source. After deactivating the sensing component, the nodes of the sensing component may be equalized. Equalizing the nodes of the sensing component may include applying the same voltage (e.g., a high voltage or a low voltage) to the input and / or output nodes of the sensing component. In some instances, the memory device uses a third set of operations that are identical to the first set of operations, except that the third set of operations may always omit the equalization operation. In some instances, after completing the fast PRE command sequence, a logic state may be written back to the memory cell that is different from the logic state stored by the memory cell before the immediately previous sensing operation. In some instances, after completing the fast PRE command sequence, a soft logic state (e.g., a logic state with reduced reliability) may be written back to the memory cell.

[0108] In some examples, a PRE command can address an entire memory group or memory portion (e.g., a PREALL command), and the memory device can equalize the voltages of all plate lines and digit lines included in the memory group or memory portion; disable all word lines; and disable all sensing components coupled to the memory group or memory portion, which may include equalizing the voltages of all nodes of the sensing components. In some cases, the memory device can omit operations for equalizing the voltages of all plate lines and digit lines included in the memory group or memory portion.

[0109] In block 335, the memory device may receive an ACT command as part of a test program. In some instances, the ACT command may open a memory bank, a memory portion, or a row of memory cells. Opening a memory cell may include connecting the memory cell to a bit line, accessing the memory cell, and / or sensing the output of the memory cell to determine the logic state stored by the memory cell. In some instances, the ACT command may be directed to a row of memory cells closed by the PRE command or a different row of memory cells. In some instances, the ACT command may be directed to all rows of memory cells opened in the memory device (e.g., if the ACT command is an ACTALL command). In some instances, the ACT command is received from an external device running the test program or from an internal device generating commands for the test program.

[0110] At block 340, the memory device may execute an ACT command. In some instances, executing the ACT command includes executing an ACT command sequence that includes a first set of operations for connecting the memory cell to a digit line, a second set of operations for accessing the memory cell, for example, by applying an access voltage across the memory cell, and a third set of operations for determining a logic state of the memory cell, for example, by sensing a voltage on the digit line after accessing the memory cell. In other instances, executing the ACT command includes executing a fast ACT command sequence that omits operations associated with accessing the memory cell and / or sensing an output of the memory cell—for example, based on the memory device being configured in a first test mode. Executing the received PRE and ACT commands using a fast PRE command sequence and / or a fast ACT command sequence can reduce a duration associated with a test procedure relative to using a PRE command sequence and / or an ACT command sequence. Additionally, using a fast PRE command sequence and / or a fast ACT command sequence can reduce current draw and disturbances during the test procedure.

[0111] In some instances, the memory device may receive another PRE command and may repeat the operations performed at block 320 via block 330. In some instances, the memory device may be reconfigured to a new test mode before receiving another PRE command. For example, the memory device may be configured for a second test mode. In this case, the other received PRE commands may be executed using a PRE command sequence that includes operations omitted from the fast PRE command sequence.

[0112] Figure 4 A block diagram of a memory device supporting execution of a fast precharge command sequence according to various examples of the present disclosure is shown.

[0113] Memory device 400 may be referred to as an electronic memory device and may include memory cells 405, word lines 410, digit lines 415, plate lines 420, sense components 450, reference lines 455, and a memory controller 465, which may be examples of memory cells, word lines, bit lines, plate lines, sense components, reference lines, and local memory controllers, such as those described in detail in the accompanying drawings. Figure 1 and 2 The memory device 400 may also include a latch 425 and a reference component 430. The components of the memory device 400 may be in electronic communication with each other and may perform reference Figures 1 to 3 The functionality described.

[0114] Memory cell(s) 405 can be configured to store logic information. In some examples, memory cell(s) 405 can be accessed using one or more access commands that trigger the sequential application of voltages to components coupled to memory cell(s) 405.

[0115] Reference component 430 can include various components to generate a reference signal for sensing component 450. Reference component 430 can include circuitry configured to generate a reference signal.

[0116] Sense component 450 can compare the signal from memory cell 405 (via digit line 415) to a reference signal from reference component 430. Once the logic state is determined, the sense component can store the output in latch 425 where it can be used according to the operation of the electronics of which memory device 400 is a part.

[0117] The memory controller 465 may be combined with other components to apply voltages across the memory device 400, write data to the memory cells 405, read data from the memory cells 405, and generally operate the memory device 400, such as Figures 1 to 3 As shown. Memory controller 465 can be in electronic communication with word lines 410, digit lines 415, plate lines 420, reference components 430, and sense components 450. Memory controller 465 can include bias components 470, timing components 475, and configuration components 480. In some examples, memory controller 465 can include a row decoder, a column decoder, or both, as shown in FIG. Figure 2 This may enable the memory controller 465 to access one or more memory cells 405 .

[0118] In some examples, the memory controller 465 can activate the access lines by applying voltages to those various nodes using a bias component 470. In some examples, the bias component 470 can be configured to apply voltages to operate the memory cell 405 to read from or write to the memory cell 405, as described above. In some examples, the bias component 470 can be configured to provide a voltage potential to the reference component 430 to generate a reference signal for the sensing component 450. Additionally, the bias component 470 can provide a voltage potential for the operation of the sensing component 450.

[0119] Timing component 475 can be configured to control the timing of various word line selections or plate biases, including the timing of voltage application for switching and for performing memory functions such as reading and writing discussed herein. In some examples, timing component 475 can control the operation of bias component 470. In some examples, memory controller 465 can also include reference component 430, sense component 450, and latch 425.

[0120] The configuration component 480 can be configured to configure the memory device 400 in an operating mode (e.g., a test mode). For example, the configuration component 480 can configure the memory array in a test mode in which a first set of operations is performed to execute a received PRE command (e.g., a fast PRE command sequence) or a second set of operations associated with a longer duration is performed to execute a received PRE command (e.g., a PRE command sequence). The configuration component 480 can include a first operating mode component 485, a second operating mode component 490, and a command processing component 495.

[0121] The first operating mode component 485 can be configured to store a first set of command sequences for the first set of commands. In some examples, the first operating mode component 485 is configured to store a fast PRE command sequence. In some examples, when the memory device 400 is configured in the first test mode, the first operating mode component 485 can be configured to execute received commands according to a corresponding command sequence of the stored first set of command sequences—for example, after receiving a PRE command at the memory controller 465, the first operating mode component 485 can execute the fast PRE command sequence.

[0122] The second operating mode component 490 can be configured to store a second set of command sequences for a second set of commands. In some instances, one or more command sequences in the second set of command sequences have a longer duration than corresponding command sequences in the first set of command sequences. In some instances, the second operating mode component 490 is configured to store a PRE command sequence. In some instances, when the memory device 400 is configured in the second test mode or the data access mode, the second operating mode component 490 can be configured to execute received commands according to corresponding command sequences in the stored second set of command sequences—for example, after the memory controller 465 receives a PRE command, the second operating mode component 490 can execute the PRE command sequence.

[0123] The command processing component 495 can be configured to receive access commands—e.g., access commands received from an external device or another component of the memory controller 465. In some examples, the command processing component 495 can be configured to buffer the received access commands and relay the access commands to other components within the memory controller 465, such as the first operating mode component 485 and the second operating mode component 490. In some examples, the command processing component 495 can be configured to generate access commands, such as based on a test program installed at the memory controller 465.

[0124] In some instances, the memory controller 465 may be configured to operate in a first mode (e.g., a first test mode) associated with a shorter command sequence than a second mode (e.g., a second test mode). The memory controller 465 may also be configured to execute a first set of operations associated with the first mode (e.g., a fast PRE command sequence) to execute a first access command (e.g., a PRE command) when configured in the first mode, or to execute a second set of operations associated with the second mode (e.g., a PRE command sequence) to execute the first access command when configured in the second mode. In some instances, the memory controller 465 may execute the first set of operations in a shorter duration than the second set of operations. In some instances, the memory controller 465 may use a configuration component 480 to identify a test mode requested by an external device. The memory controller 465 may also use the configuration component 480 to configure the memory device 400 for the identified test mode (e.g., the first test mode or the second test mode). In some examples, when the first mode is configured, the memory controller 465 uses the configuration component 480 to configure the sense component 450 to refrain from writing the logic state back to the memory cell after sensing the memory cell.

[0125] In some examples, memory controller 465 can receive and process access commands. In some examples, when executing the first test program, memory controller 465 uses first operating mode component 485 to process access commands. When first operating mode component 485 is activated, memory controller 465 can execute a fast PRE command sequence after receiving a PRE command. To execute the fast PRE command sequence, as an initial step, first operating mode component 485 can apply a deactivation voltage to word line 410 using bias component 470. Next, first operating mode component 485 can send a signal (e.g., via control line 440) to disconnect sensing component 450 from the voltage source, which can deactivate sensing component 450. And finally, first operating mode component 485 can equalize nodes of sensing component 450. In some examples, equalizing the nodes of the sensing component includes sending a control signal to a switching component that connects digit line 415 and reference line 455 to a virtual ground. In some examples, an initial step of the fast PRE command sequence includes equalizing the voltages of digit line 415 and plate line 420. In some examples, equalizing the voltages of plate line 420 and digit line 415 can include sending a control signal to a switching component that connects digit line 415 to a virtual ground.

[0126] Figure 5 A flowchart illustrating one or more methods 500 for supporting execution of a fast precharge command sequence according to aspects of the present disclosure is shown. The operations of the method 500 may be implemented by a memory array or components thereof as described herein. For example, the operations of the method 500 may be implemented by a memory array or components thereof as described herein. Figure 4 The memory array described herein can be used to perform the functions described herein. In some examples, the memory array can execute a set of instructions to control the functional elements of the memory array to perform the functions described herein. Additionally, or alternatively, the memory array can use dedicated hardware to perform various aspects of the functions described herein.

[0127] At 505, a memory array may configure a memory device including the memory array to operate in a first mode associated with a command sequence having a reduced duration relative to a second mode. The operations of 505 may be performed according to the methods described herein. In some examples, aspects of the operations of 505 may be described with reference to Figure 4 Describes the configuration components to execute.

[0128] At 510, after configuring the memory device to operate in the first mode, the memory array may receive a precharge command associated with a memory cell of the memory array. The operations of 510 may be performed according to the methods described herein. In some examples, aspects of the operations of 510 may be described with reference to Figure 4 Describes the command processing component to execute.

[0129] At 515, the memory array may perform a first set of operations for executing a precharge command based on configuring the memory array to operate in a first mode, wherein the first set of operations is performed for a shorter duration than a second set of operations for executing a precharge command when the memory array is configured in a second mode. The operations of 515 may be performed according to the methods described herein. In some examples, the memory array may be configured to operate in a first mode. Figure 4 The first operating mode components, biasing components, and / or timing components described herein may be used to perform various aspects of the operation of 515.

[0130] In some examples, an apparatus as described herein may perform one or more methods, such as method 500. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for configuring a memory device including a memory array to operate in a first mode associated with a command sequence having a reduced duration relative to a second mode, after configuring the memory device to operate in the first mode, receiving a precharge command associated with a memory cell of the memory array, and based on configuring the memory array to operate in the first mode, performing a first set of operations for executing the precharge command, wherein the first set of operations is performed within a shorter duration than a second set of operations for executing the precharge command when the memory device is configured in the second mode.

[0131] Some examples of the method 500 and apparatus described herein may also include operations, features, means, or instructions for selecting the first set of operations over the second set of operations for executing the precharge command based on configuring the memory array to operate in the first mode.

[0132] In some examples of the method 500 and apparatus described herein, performing the first set of operations may include operations, features, components, or instructions for equalizing a voltage of a plate line that may be coupled to a memory cell and a voltage of a digit line that may be coupled to the memory cell as a first operation of the first set of operations.

[0133] In some examples of the method 500 and apparatus described herein, after equalizing the voltage of the plate line with the voltage of the digit line, performing the first set of operations may include operations, features, components, or instructions for disabling a word line that may be coupled to a memory cell, disabling a sense component that may be coupled to the memory cell, and equalizing a voltage at a first node of the sense component with a voltage at a second node of the sense component.

[0134] In some examples of the method 500 and apparatus described herein, the sensing component may be disabled after the word line may be disabled, and wherein the voltage of the first node and the voltage of the second node may be equalized after the sensing component may be disabled.

[0135] In some examples of the method 500 and apparatus described herein, performing the first set of operations may include operations, features, means, or instructions for disabling a word line that may be coupled to a memory cell or a sensing component that may be coupled to a memory cell as a first operation of the first set of operations.

[0136] In some examples of the method 500 and apparatus described herein, performing the first set of operations may include operations, features, components, or instructions for, as a second operation of the first set of operations occurring after the first operation, disabling a word line or a sensing component based on whether the word line or sensing component could be disabled in the first operation, and, after disabling the word line or sensing component, equalizing a voltage at a first node of the sensing component with a voltage at a second node of the sensing component.

[0137] Some examples of the method 500 and apparatus described herein may also include operations, features, components, or instructions for configuring the memory device to operate in the second mode, receiving a second precharge command associated with the memory cell after configuring the memory device to operate in the second mode, and performing a second set of operations to execute the second precharge command based on configuring the memory array to operate in the second mode.

[0138] In some examples of the methods 500 and apparatus described herein, performing the second set of operations may include operations, features, components, or instructions for coupling an output of a sensing component to a digit line that may be coupled to a memory cell, wherein a voltage of the output corresponds to a logic state stored in the memory cell as sensed by the sensing component prior to coupling, applying a voltage to a plate line that may be coupled to the memory cell based on coupling the output of the sensing component to the digit line, equalizing a voltage of the plate line with a voltage of the digit line based on applying the voltage to the plate line, waiting for a duration associated with removing charge from a bottom of the memory cell after equalizing the voltage of the plate line with the voltage of the digit line, deactivating a word line that may be coupled to a select component, wherein the select component may be coupled to the memory cell, deactivating the sensing component based on deactivating the word line, and equalizing a voltage of a first node of the sensing component with a voltage of a second node of the sensing component based on deactivating the sensing component.

[0139] Some examples of the method 500 and apparatus described herein may also include operations, features, components, or instructions for executing an activate command associated with the memory cell prior to receiving the precharge command and sensing a logic state from the memory cell based on executing the activate command, wherein the logic state sensed from the memory cell may be discarded based on executing the first set of operations.

[0140] In some examples of the method 500 and apparatus described herein, performing the first set of operations may include operations, features, components, or instructions for refraining from writing a logic state sensed from a memory cell by a sensing component back to the memory cell.

[0141] In some examples of the method 500 and apparatus described herein, inhibiting a logic state sensed from a memory cell from being written back to the memory cell may include operations, features, means, or instructions for coupling an output of a sensing component to a digit line that may be coupled to the memory cell, applying a voltage to a plate line that may be coupled to the memory cell based on coupling the output of the sensing component to the digit line, equalizing a voltage of the plate line with a voltage of the digit line; or any combination thereof.

[0142] In some examples of the method 500 and apparatus described herein, a memory cell stores a logic state prior to receiving a precharge command and stores a different logic state after performing the first set of operations.

[0143] In some examples of the method 500 and apparatus described herein, a precharge command can be associated with a group of memory cells including a memory cell, and wherein a first set of operations can be performed on the group of memory cells.

[0144] In some examples of the method 500 and devices described herein, a memory array includes one or more ferroelectric memory cells, and wherein the memory cells can be ferroelectric memory cells.

[0145] In some examples of the method 500 and apparatus described herein, the first mode may be associated with one or more of wafer-level margin testing, wafer-level burn-in testing, wafer-level reliability testing, package burn-in testing, unit-level reliability testing, qualification testing, or bench characterization testing.

[0146] Some examples of the method 500 and apparatus described herein may also include operations, features, means, or instructions for performing a first set of operations associated with operating the second memory cell, wherein the current level remains below a threshold based on the first mode being configured.

[0147] Some examples of the method 500 and apparatus described herein may also include operations, features, means, or instructions for applying a sequence of voltages to a plate line coupled to a memory cell prior to receiving a precharge command while performing tests associated with the plate line, wherein no additional voltages may be applied to the plate line based on the first mode being configured.

[0148] In some examples of the method 500 and apparatus described herein, the first mode can be a first test mode and the second mode can be a second test mode.

[0149] Figure 6A flowchart illustrating one or more methods 600 for supporting execution of a fast precharge command sequence according to aspects of the present disclosure is shown. The operations of the method 600 may be implemented by a memory array or components thereof as described herein. For example, the operations of the method 600 may be implemented by a memory array or components thereof as described herein. Figure 4 The memory array described herein can be used to perform the functions described herein. In some examples, the memory array can execute a set of instructions to control the functional elements of the memory array to perform the functions described herein. Additionally, or alternatively, the memory array can use dedicated hardware to perform various aspects of the functions described herein.

[0150] At 605, a memory array may configure a memory device including the memory array to operate in a first mode associated with a command sequence having a reduced duration relative to a second mode. The operations of 605 may be performed according to the methods described herein. In some examples, aspects of the operations of 605 may be described with reference to Figure 4 Describes the configuration components to execute.

[0151] At 610, after configuring the memory device to operate in the first mode, the memory array may receive a precharge command associated with a memory cell of the memory array. The operations of 610 may be performed according to the methods described herein. In some examples, aspects of the operations of 610 may be described with reference to Figure 4 Describes the command processing component to execute.

[0152] At 615, the memory array may perform a first set of operations for executing a precharge command based on configuring the memory array to operate in a first mode, wherein the first set of operations is performed for a shorter duration than a second set of operations for executing a precharge command when the memory array is configured in a second mode. The operations of 615 may be performed according to the methods described herein. In some examples, the memory array may be configured to operate in a first mode. Figure 4 The first operating mode components, biasing components, and / or timing components described herein may be used to perform various aspects of the operations of 615 .

[0153] At 620, as a first operation in the first set of operations, the memory array may disable a word line coupled to a memory cell or a sensing component coupled to a memory cell. The operation of 620 may be performed according to the methods described herein. In some examples, aspects of operation 620 may be performed by a first operating mode component and a bias component, as described with reference to FIG. Figure 4 As stated.

[0154] At 625, as a second operation in the first set of operations occurring after the first operation, the memory array may disable the word line or sensing component based on whether the word line or sensing component was disabled in the first operation. The operation of 625 may be performed according to the methods described herein. In some examples, aspects of operation 625 may be performed by the first operating mode component (e.g., in combination with the bias component), as described with reference to FIG. Figure 4 As stated.

[0155] At 630, after deactivating the word line or sensing component, the memory array equalizes the voltage of the first node of the sensing component and the voltage of the second node of the sensing component. The operation of 630 can be performed according to the methods described herein. In some examples, aspects of operation 630 can be performed by the first operating mode component (e.g., in combination with the bias component), as described with reference to FIG. Figure 4 As stated.

[0156] It should be noted that the methods described herein are possible implementations, and that the operations and steps may be rearranged or otherwise modified, and that other implementations are possible. Furthermore, portions from two or more methods may be combined.

[0157] A device is described. The device may include a memory unit and a memory controller coupled to the memory unit and configurable to operate in a first mode associated with a command sequence having a reduced duration relative to a second mode, wherein the memory controller is operable to, when configured in the first mode, perform a first set of operations associated with the first mode to execute a first command for accessing the memory unit, or to, when configured in the second mode, perform a second set of operations associated with the second mode to execute the first command for accessing the memory unit, wherein a duration for executing the first set of operations is shorter than a duration for executing the second set of operations.

[0158] In some examples, the memory controller may include operations, features, components, or instructions for configuring the component to be operable to identify a mode requested by an external device and configure the device to the identified mode, including the first mode or the second mode.

[0159] In some instances, a memory controller may include operations, features, components, or instructions for a first operating mode component operable to store a first set of command sequences corresponding to a set of access commands, and a second operating mode component operable to store a second set of command sequences corresponding to the set of access commands, wherein at least one command sequence in the first set of command sequences can be executed in a shorter time period than a corresponding command sequence in the second set of command sequences.

[0160] Some examples of the apparatus may include a sensing component coupled with the memory cell and operable to refrain from writing a logic state back to the memory cell after sensing the memory cell when the first mode is configurable.

[0161] An apparatus is described. The apparatus may include a memory array including memory cells and a memory controller coupled to the memory array, the memory controller operable to configure a first mode associated with one or more command sequences having a reduced duration relative to a second mode, receive a precharge command associated with the memory cells after configuring the first mode, and perform a first set of operations for executing the precharge command based on configuring the memory array to operate in the first mode, wherein the first set of operations is performed within a shorter duration than a second set of operations for executing the precharge command when the second mode is configured.

[0162] Some examples may also include, as an initial operation of the first set of operations, equalizing a voltage of a plate line that may be coupled to the memory cell and a voltage of a digit line that may be coupled to the memory cell, and, as a next operation of the first set of operations, disabling a word line that may be coupled to the memory cell or a sensing element that may be coupled to the memory cell.

[0163] Some examples may also include disabling a word line that may be coupled to the memory cell or a sensing component that may be coupled to the memory cell as an initial operation of the first set of operations.

[0164] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof. Some figures may illustrate a signal as a single signal; however, one of ordinary skill in the art will understand that a signal may represent a signal bus, where the bus may have various bit widths.

[0165] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication (or conductive contact, connected, or coupled) with each other if there is any conductive path between the components that is capable of supporting the flow of signals between the components at any time. At any given time, based on the operation of the device including the connected components, the conductive path between the components that are in electronic communication (or conductive contact or connected or coupled) with each other may be an open circuit or a closed circuit. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include an intermediate component (such as a switch, transistor, or other component). In some instances, the flow of signals between the connected components may be interrupted for a period of time using, for example, one or more intermediate components such as a switch or transistor.

[0166] The term "coupling" refers to the situation of moving from an open-circuit relationship between components, in which signals cannot currently be passed between the components via the conductive paths, to a closed-circuit relationship between the components in which signals can be passed between the components via the conductive paths. When a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components via conductive paths that previously did not allow signal flow.

[0167] The term "isolation" refers to a relationship between components where signals cannot flow between them. Components are isolated from one another if an open circuit exists between them. For example, when a switch is open, two components separated by the switch are isolated from one another. When a controller isolates two components from one another, it uses the conductive path that previously allowed signal flow to cause a change that prevents signal flow between the components.

[0168] The devices discussed herein, including the memory array, can be formed on a semiconductor substrate such as silicon, germanium, a silicon-germanium alloy, gallium arsenide, gallium nitride, or the like. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOS), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a subregion of the substrate can be controlled by doping with various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed by ion implantation during the initial formation or growth of the substrate or by any other doping means.

[0169] The switching components or transistors discussed herein may represent field effect transistors (FETs) and include three-terminal devices including a source, a drain, and a gate. The terminals may be connected to other electronic components via conductive materials such as metals. The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be referred to as a p-type FET. The channel may be terminated by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "on" or "activated." When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "off" or "deactivated."

[0170] The description set forth herein, in conjunction with the accompanying drawings, describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration," rather than "preferred" or "superior to other examples." The detailed description includes specific details that provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0171] In the accompanying drawings, similar components or features may have the same reference number. In addition, various components of the same type may be distinguished by following the reference number with a dash and a second reference that distinguishes between the similar components. If only the first reference number is used in the specification, the description applies to any of the similar components having the same first reference number, regardless of the second reference number.

[0172] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips referenced throughout the description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0173] The various illustrative blocks and modules described in connection with the disclosure herein may be implemented or executed by a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0174] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored as one or more instructions or codes on a computer-readable medium or transmitted via the computer-readable medium. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the characteristics of software, it is possible to implement the above-mentioned functions using software executed by a processor, hardware, firmware, hardwiring, or a combination of any of these. The features that implement the functions can also be physically located in various locations, including being distributed so that part of the functions are implemented in different physical locations. In addition, as used herein, including in the claims, "or" as used in a list of items (e.g., a list of items beginning with a phrase such as "at least one of" or "one or more") indicates that a list is included, so that, for example, a list of at least one of A, B, or C represents A or B or C or AB or AC or BC or ABC (i.e., A and B and C). In addition, as used herein, the phrase "based on" should not be interpreted as a reference to a closed set of conditions. For example, exemplary steps described as "based on condition A" may, without departing from the scope of the present disclosure, be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0175] Computer-readable medium includes non-transitory computer storage medium and communication medium, and communication medium includes any medium that promotes computer program to be transferred from one place to another place.Non-transitory storage medium can be any available medium that can be accessed by general or special-purpose computer.As an example and not limitation, non-transitory computer-readable medium can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage device, magnetic disk storage device or other magnetic storage device or can be used to carry or store required program code member and any other non-transitory medium that can be accessed by general or special-purpose computer or general or special-purpose processor in the form of instruction or data structure.In addition, any connection is suitably referred to as computer-readable medium.For example, if using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology such as infrared, radio and microwave to transmit software from website, server or other remote source, then coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology such as infrared, radio and microwave are included in the definition of medium. Disk and disc, as used herein, includes CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc, where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0176] The description herein is provided to enable one skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method comprising: configuring a memory device including a memory array to operate in a first mode associated with a command sequence having a reduced duration relative to a second mode; After configuring the memory device to operate in the first mode, receiving a precharge command associated with a memory cell of the memory array; and A first set of operations for executing the precharge command is performed based at least in part on configuring the memory array to operate in the first mode, wherein the first set of operations is performed in a shorter duration than a second set of operations for executing the precharge command when the memory device is configured in the second mode.

2. The method according to claim 1, further comprising: The first set of operations rather than the second set of operations is selected for executing the precharge command based at least in part on configuring the memory array to operate in the first mode.

3. The method according to claim 1, wherein: Executing the first set of operations includes: As a first operation of the first set of operations, a voltage of a plate line coupled to the memory cell and a voltage of a digit line coupled to the memory cell are equalized.

4. The method according to claim 3, wherein: After equalizing the voltage of the plate line and the voltage of the digit line, performing the first set of operations includes: disabling a word line coupled to the memory cell; disabling a sensing component coupled to the memory cell; and A voltage at a first node of the sensing component and a voltage at a second node of the sensing component are equalized. 5 . The method of claim 4 , wherein the sensing component is disabled after the word line is disabled, and wherein the voltage of the first node and the voltage of the second node are equalized after the sensing component is disabled.

6. The method according to claim 1, wherein: Executing the first set of operations includes: As a first operation in the first set of operations, a word line coupled to the memory cell or a sensing component coupled to the memory cell is disabled.

7. The method according to claim 6, wherein: Executing the first set of operations includes: as a second operation in the first set of operations occurring after the first operation, disabling the word line or the sensing component based at least in part on whether the word line or the sensing component was disabled in the first operation; as well as A voltage of a first node of the sensing component and a voltage of a second node of the sensing component are equalized after deactivating the word line or the sensing component.

8. The method according to claim 1, further comprising: configuring the memory device to operate in the second mode; After configuring the memory device to operate in the second mode, receiving a second precharge command associated with the memory cell; and The second set of operations is performed based at least in part on configuring the memory array to operate in the second mode to execute the second precharge command.

9. The method according to claim 8, wherein: Executing the second set of operations includes: coupling an output of a sense component to a digit line coupled to the memory cell, wherein a voltage of the output corresponds to a logic state stored by the memory cell as sensed by the sense component prior to the coupling; applying a voltage to a plate line coupled to the memory cell based at least in part on coupling the output of the sense component to the digit line; equalizing a voltage of the plate line and a voltage of the digit line based at least in part on applying the voltage to the plate line; After equalizing the voltage of the plate line and the voltage of the digit line, waiting for a duration associated with removing charge from a bottom of the memory cell; disabling a word line coupled to a selection component coupled to the memory cell after waiting the duration; disabling the sensing component based at least in part on disabling the word line; as well as A voltage of a first node of the sense component and a voltage of a second node of the sense component are equalized based at least in part on deactivating the sense component.

10. The method according to claim 1, further comprising: executing an activate command associated with the memory cell prior to receiving the precharge command; and A logic state is sensed from the memory cell based at least in part on executing the active command, wherein the logic state sensed from the memory cell is discarded based at least in part on executing the first set of operations.

11. The method according to claim 10, wherein: Executing the first set of operations includes: The logic state sensed from the memory cell by a sensing component is inhibited from being written back to the memory cell.

12. The method of claim 11 , wherein inhibiting the logic state sensed from the memory cell from being written back to the memory cell comprises: coupling an output of the sensing component to a digit line coupled to the memory cell; applying a voltage to a plate line coupled to the memory cell based at least in part on coupling the output of the sense component to the digit line; equalizing the voltage of the plate line and the voltage of the digit line; or Any combination thereof.

13. The method of claim 1, wherein the memory cell stores a logic state prior to receiving the precharge command and stores a different logic state after performing the first set of operations.

14. The method of claim 1, wherein the precharge command is associated with a plurality of memory cells including the memory cell, and wherein the first set of operations is performed for the plurality of memory cells.

15. The method of claim 1, wherein the memory array includes one or more ferroelectric memory cells, and wherein the memory cells are ferroelectric memory cells.

16. The method of claim 1, wherein the first mode is associated with one or more of a wafer level margin test, a wafer level burn-in test, a wafer level reliability test, a package burn-in test, a unit level reliability test, a qualification test, or a bench characterization test.

17. The method of claim 1, wherein the memory cell is located in a first memory portion of a first memory bank, and wherein the precharge command is associated with a second memory cell in a second memory portion of the first memory bank or a second memory bank, the method further comprising: The first set of operations associated with operating the second memory cell is performed wherein a current level remains below a threshold based at least in part on the first mode being configured.

18. The method according to claim 1, further comprising: A voltage sequence is applied to a plate line coupled to the memory cell prior to receiving the precharge command while performing a test associated with the plate line, wherein no additional voltages are applied to the plate line based at least in part on the first mode being configured.

19. An apparatus comprising: a memory unit; and a memory controller coupled to the memory unit and configurable to operate in a first mode associated with a command sequence having a reduced duration relative to a second mode, wherein the memory controller is operable to: When configured in the first mode, a first set of operations associated with the first mode is performed to execute a precharge command for accessing the memory cell, or when configured in the second mode, a second set of operations associated with the second mode is performed to execute the precharge command for accessing the memory cell, wherein a duration for executing the first set of operations is shorter than a duration for executing the second set of operations.

20. The device according to claim 19, wherein The memory controller comprises: A configuration component is operable to identify a mode requested by an external device and configure the apparatus for the identified mode, the mode comprising the first mode or the second mode.

21. The device according to claim 19, wherein The memory controller comprises: a first operating mode component operable to store a first plurality of command sequences corresponding to the plurality of access commands; and A second operating mode component is operable to store a second plurality of command sequences corresponding to the plurality of access commands, wherein at least one command sequence of the first plurality of command sequences is executable within a shorter period of time than a corresponding command sequence of the second plurality of command sequences.

22. The apparatus according to claim 19, further comprising: A sensing component is coupled to the memory cell and is operable to refrain from writing a logic state back to the memory cell after sensing the memory cell when the first mode is configured.

23. An apparatus comprising: a memory array comprising memory cells; a memory controller coupled to the memory array, the memory controller being operable to: configuring a first mode associated with one or more command sequences having a reduced duration relative to a second mode; receiving a precharge command associated with the memory cell after configuring the first mode; and A first set of operations for executing the precharge command is performed based at least in part on configuring the memory array to operate in the first mode, wherein the first set of operations is performed within a shorter duration than a second set of operations for executing the precharge command when the second mode is configured.

24. The apparatus of claim 23, wherein the memory controller is further operable to: As an initial operation of the first set of operations, equalizing a voltage of a plate line coupled to the memory cell and a voltage of a digit line coupled to the memory cell; and As an operation of the first set of operations that is a next operation after the initial operation, a word line coupled to the memory cell or a sensing component coupled to the memory cell is disabled.

25. The apparatus of claim 23, wherein the memory controller is further operable to: As an initial operation of the first set of operations, a word line coupled to the memory cell or a sensing component coupled to the memory cell is disabled.

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