Non-volatile memory device and method of writing thereof

Abstract

Disclosed are a nonvolatile memory device and a write method thereof. The write method of the nonvolatile memory device includes performing a sensing operation, comparing write data with read data obtained through the sensing operation, determining whether the write data is a set state when the write data is the same as the read data, performing a set operation when the write data is the set state, and not performing a write operation when the write data is not the set data.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0140134, filed with the Korean Intellectual Property Office on November 5, 2019, the publication of which is incorporated herein by reference. Technical Field

[0002] Example embodiments of the inventive concept relate to a non-volatile memory device, a writing method for writing data to a non-volatile memory, and a storage device including a non-volatile memory device. Background Technology

[0003] Data Comparison Write (DCW) has been used to reduce power consumption and improve write operations performed by phase-change memory (PCM) devices. The DCW method involves reading a stored value from a PCM cell during a write operation and writing the input value to the PCM cell when the input value differs from the stored value. Therefore, additional power used for performing the write operation can be saved when the stored value of the PCM cell is not different from the input value. In the DCW method, a read operation can be performed before the write operation to determine the stored value of the PCM cell. However, when the input value is known to be the same as the stored value, the read operation can be omitted. Summary of the Invention

[0004] Specific example embodiments of the inventive concept provide non-volatile memory devices exhibiting reduced power consumption and improved reliability. Other example embodiments of the inventive concept provide writing methods to such non-volatile memory devices and storage devices including such non-volatile memory devices.

[0005] According to an example embodiment of the inventive concept, a non-volatile memory (NVM) device includes: a memory cell array including a plurality of resistive memory cells connected to a plurality of bit lines and a plurality of word lines; a word line driver configured to: apply a word line voltage to the selected word line in response to address selection of the plurality of word lines; a bit line driver configured to: apply a bit line voltage to the selected bit line in response to address selection of the plurality of bit lines; a write circuit configured to: generate a bit line voltage and a word line voltage in response to a write control signal; a read circuit configured to: read data from the resistive memory cell connected to the selected word line and the selected bit line in response to a read control signal; an input and output (I / O) circuit configured to receive write data from an external device; and control logic configured to: select a write mode from a plurality of write modes, generate a write control signal based on at least one of the selected write mode, write data, and read data, and generate a read control signal based on at least one of the selected write mode and write data.

[0006] According to an example embodiment of the inventive concept, a writing method for a non-volatile memory (NVM) device includes: performing a sensing operation; comparing write data with read data obtained through the sensing operation; determining whether the write data is in a set state when the write data and read data are the same; performing a set operation when the write data is set data, and not performing a write operation when the write data is not set data.

[0007] According to an example embodiment of the inventive concept, a writing method for a non-volatile memory (NVM) device includes: receiving write data; determining whether the write data corresponds to a set state; performing a set operation when the write data corresponds to a set state; performing a sensing operation when the write data does not correspond to a set state, and not performing a write operation when read data obtained through the sensing operation corresponds to a reset state; and performing a reset operation when the read data does not correspond to a reset state. Attached Figure Description

[0008] The above and other aspects, features, and advantages of the inventive concept can be more clearly understood in light of the following detailed description and accompanying drawings, in which:

[0009] Figure 1 This is a diagram illustrating an example of a non-volatile memory device 100 according to an exemplary embodiment of the inventive concept;

[0010] Figure 2A , Figure 2B , Figure 2C and Figure 2D This is a diagram illustrating an example of a memory cell according to an exemplary embodiment of the inventive concept;

[0011] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E and Figure 3F This is a diagram illustrating an example of the three-dimensional structure of a memory cell;

[0012] Figure 4 This is a diagram illustrating an example of a three-dimensional stacked structure of a memory cell array 110 according to an exemplary embodiment of the inventive concept;

[0013] Figure 5 It is shown Figure 4 A diagram illustrating an example of a single memory cell array 110-1;

[0014] Figure 6 This is a diagram illustrating an example of a memory cell array 110a according to another exemplary embodiment of the inventive concept;

[0015] Figure 7This is a diagram illustrating an example of a memory cell array 110b according to another exemplary embodiment of the inventive concept;

[0016] Figure 8 This is a diagram illustrating an example of a sensing amplifier 152 of a readout circuit 150 according to another exemplary embodiment of the inventive concept;

[0017] Figure 9A This is a diagram illustrating a write data latch 172-1 according to an exemplary embodiment of the inventive concept.

[0018] Figure 9B This is a diagram illustrating a write data latch 172-2 according to an exemplary embodiment of the inventive concept;

[0019] Figure 10A , Figure 10B and 10C This is a diagram illustrating an example of control signals generated in control logic 170 according to the operation mode of a write operation;

[0020] Figure 11 This is a diagram illustrating an example of the distribution of memory cells after a write operation performed in normal mode;

[0021] Figure 12 This is a diagram illustrating an example of the distribution of memory cells after a write operation performed in DCW mode;

[0022] Figure 13 This is a diagram showing an example of a data table corresponding to a write operation performed in DCW mode;

[0023] Figure 14 This is a diagram illustrating an example of a data table corresponding to a write operation mode according to an exemplary embodiment of the inventive concept;

[0024] Figure 15 This is a diagram illustrating an example of a data table related to a write operation performed in aDCW mode, according to an exemplary embodiment of the inventive concept.

[0025] Figure 16 This is a diagram illustrating an example of a data table related to a write operation mode according to another exemplary embodiment of the inventive concept;

[0026] Figure 17 This is a diagram illustrating an example of the distribution of memory cells when a write operation is performed in aDCW mode, according to an exemplary embodiment of the inventive concept.

[0027] Figure 18 This is a diagram illustrating an example of the distribution of memory cells when a write operation is performed in aDCW mode, according to another exemplary embodiment of the inventive concept.

[0028] Figure 19 This is a flowchart illustrating an example of a write operation of a non-volatile memory device 100 according to an exemplary embodiment of the inventive concept;

[0029] Figure 20 This is a flowchart illustrating an example of a write operation of a non-volatile memory device 100 according to another exemplary embodiment of the inventive concept;

[0030] Figure 21 This is a diagram illustrating an example of the timing of the operation of writing data "1" in aDCW mode according to an exemplary embodiment of the inventive concept;

[0031] Figure 22 This is a diagram illustrating an example of the timing of the operation of writing data "0" in aDCW mode according to an exemplary embodiment of the inventive concept;

[0032] Figure 23A and Figure 23B This is a diagram illustrating the effect of a write operation on a non-volatile memory device according to an exemplary embodiment of the inventive concept;

[0033] Figure 24 This is a diagram illustrating an example of a storage device 1000 according to an exemplary embodiment of the inventive concept;

[0034] Figure 25 This is a diagram illustrating an example of a memory system 2000 in which a particular write mode is applied to an edge portion according to an exemplary embodiment of the inventive concept;

[0035] Figure 26 This is a diagram illustrating an example of a memory system 3000 that selectively operates a write mode based on environmental information according to an exemplary embodiment of the inventive concept.

[0036] Figure 27 This is a diagram illustrating an example of a server system 4000 according to an exemplary embodiment of the inventive concept;

[0037] Figure 28 This is a diagram illustrating an example of a computing system 5000 according to an exemplary embodiment of the inventive concept;

[0038] Figure 29 This is a diagram illustrating an example of a computing system 6000 according to another exemplary embodiment of the inventive concept; and

[0039] Figure 30 This is a diagram illustrating an example of a computing system 7000 according to another exemplary embodiment of the inventive concept. Detailed Implementation

[0040] In the following description, embodiments of the inventive concept will be illustrated with reference to the accompanying drawings.

[0041] A write method used in conjunction with a non-volatile memory (NVM) device in a specific example embodiment of the inventive concept may include: (1) performing a read (or sense) operation using a second read level greater than or equal to a first read level, (2) comparing a “stored value” generated by the read operation with an “input value” of data to be written to the NVM device to generate a comparison result, and (3) determining whether to perform a write operation based on (or in response to) the comparison result. For example, a write operation may not be performed when the comparison between the stored value and the input value generates (or corresponds to) a reset state. Therefore, an NVM device using the aforementioned write method can prevent, for example, write operation failures caused by resistance drift.

[0042] Figure 1 This is a diagram illustrating a non-volatile memory (NVM) device 100 according to an example embodiment. (Refer to...) Figure 1 The NVM device 100 may include a memory cell array 110, a word line driver 120, a bit line driver 130, a write circuit 140, a read circuit 150, a data input and output (I / O) circuit 160, and control logic 170.

[0043] The memory cell array 110 can be connected to the word line driver 120 via multiple word lines WL, and can also be connected to the bit line driver 130 via multiple bit lines BL. The memory cell array 110 may include multiple memory cells connected to the multiple word lines WL and the multiple bit lines BL. Figure 1 As shown, the memory cell MC can be connected between the word line WL and the bit line BL. The memory cell MC can be used to store one or more bits using resistive material. Figure 1 A single memory cell array is shown, but the example embodiment is not limited thereto. The NVM device 100 may have a structure in which multiple memory cell arrays are stacked along a direction perpendicular to the substrate (e.g., vertical direction).

[0044] Word line driver 120 can be connected to memory cell array 110 via multiple word lines WL. Word line driver 120 can select one word line from the multiple word lines WL using a row address provided under the control of control logic 170. Furthermore, word line driver 120 can apply word line voltages to the selected word line. Word line voltages may include read word line voltages, write word line voltages, etc.

[0045] Bit line driver 130 can be connected to memory cell array 110 via multiple bit lines BL. Bit line driver 130 can select one bit line from the multiple bit lines BL using a column address, controlled by control logic 170. Furthermore, bit line driver 130 can apply bit line voltages to the selected bit line. Bit line voltages may include read voltages, set bit line voltages, reset bit line voltages, etc.

[0046] Write circuitry 140 may be connected to word line driver 120 and bit line driver 130. Write circuitry 140 may be configured to write data (e.g., set or reset operations) to memory cells connected to selected bit lines and selected word lines under the control of control logic 170. For example, write circuitry 140 may apply word line voltages to selected word lines and may apply bit line voltages to selected bit lines in response to a write control signal from control logic 170. In one example embodiment, write circuitry 140 may generate a set pulse or reset pulse corresponding to the data to be written during a write operation and may apply the set pulse or reset pulse to the selected word line / bit line.

[0047] The read circuit 150 can be configured to read data from memory cells connected to selected word lines and selected bit lines under the control of control logic 170. For example, the read circuit 150 can read data from memory cells connected to selected word lines and selected bit lines in response to a read control signal from control logic 170. In one example embodiment, the read circuit 150 can perform a sensing operation to sense the voltage difference between the voltage of the selected word line / bit line and a reference voltage and distinguish the on / off cells from each other based on the sensed voltage difference.

[0048] The write circuit 140 and / or read circuit 150 may be collectively or separately referred to as a read-write circuit (RWC). For example... Figure 1 As shown, the RWC can be located below the word line driver 120.

[0049] Data I / O circuitry 160 can be configured, under the control of control logic 170, to transfer write data received from an external device (e.g., a memory controller) to data latch (DL) 172 during a write operation. Data I / O circuitry 160 can also be configured to transfer read data obtained from data latch 172 during a read operation to an external device (e.g., a memory controller).

[0050] Control logic 170 can be configured to control the overall operation of NVM device 100. Therefore, control logic 170 can be used to control word line driver 120, bit line driver 130, write circuit 140, read circuit 150 and / or data I / O circuit 160 in response to one or more command CMD, address ADD, data and / or control signals.

[0051] Control logic circuitry 170 can be used to select a write mode from a plurality of possible write modes, and then control the execution of the write operation according to the selected write mode. In an example embodiment, control logic 170 can be used to generate a write control signal in response to at least one of the selected write mode, write data, and read data. Control logic 170 can also be used to generate a read control signal in response to at least one of the selected write mode and write data.

[0052] In one example embodiment, a specific write mode selected from multiple write modes can be used to define the execution of a write operation. The multiple write modes may include: normal mode, data comparison write (DCW) mode, active data comparison write (aDCW) mode, and / or read skip active data comparison write (RDSKIP aDCW) mode. Here, normal mode is a write mode that does not reflect resistance drift, DCW mode is a write mode that reflects resistance drift in the reset state, and aDCW mode and RDSKIP aDCW mode are write modes that reflect resistance drift in both the set and reset states.

[0053] For write operations performed in normal mode, control logic 170 can control write circuit 140 to perform set and / or reset operations based on the input (or write) data to be written to the memory cell.

[0054] For a write operation performed in DCW mode, control logic 170 can control write circuit 140 and read circuit 150 to compare the stored data (i.e., "read data") obtained from the memory cell using a sensing operation with the write data to be written, and then perform a set operation or a reset operation based on the comparison result.

[0055] For write operations performed in aDCW mode, control logic 170 controls write circuit 140 and read circuit 150 to compare read data obtained from the memory cell using a sensing operation with the write data to be written, and then uses the comparison result and the write data to be written to perform a set operation or a reset operation. For write operations performed in aDCW mode, if both the read data and the write data correspond to reset data, the write operation may not be performed.

[0056] For write operations performed in RDSKIP aDCW mode, when the write data is set data, control logic 170 may perform a set operation instead of a sensing operation. However, when the write data is not set data, control logic 170 may perform a sensing operation, comparing the read data obtained from the memory cell using the sensing operation with the write data, and using the comparison result to determine whether to perform a reset operation or not to perform a write operation.

[0057] Here, it should generally be noted that NVM devices are prone to spreading the resistance distribution over time by drifting the resistance values ​​of memory cells. This phenomenon can cause reliability issues related to the data stored in the constituent memory cells of an NVM device. Compared to this general result, when a write operation is performed according to one of the DCW mode / aDCW mode / RDSKIP aDCW mode, Figure 1 The NVM device 100 can accurately reflect resistance drift during its operation, thereby improving data reliability.

[0058] In a particular embodiment of the inventive concept, Figure 1 The memory cell MC shown may include a variable resistor.

[0059] Figure 2A , Figure 2B , Figure 2C and Figure 2D These are respective diagrams illustrating examples of memory cells that can be used in example embodiments.

[0060] Reference Figure 2A The memory cell MC may include a variable resistor R and a diode D. In one example embodiment, the variable resistor R may be a phase change material. For example, the phase change material may be implemented as various types of materials (such as GaSb, InSb, InSe, Sb2Te3, GeTe formed by combining two elements; GeSbTe, GaSeTe, InSbTe, SnSb2Te4, InSbGe formed by combining three elements; AgInSbTe, (GeSn)SbTe, GeSb(SeTe), Te formed by combining four elements). 81 Ge 15 (e.g., Sb2S2). In another example embodiment, the variable resistor R may include perovskite compounds, transition metal oxides, magnetic materials, ferromagnetic materials, antiferromagnetic materials, etc., instead of phase change materials.

[0061] Reference Figure 2B The memory cell MC may include a variable resistor R and a bidirectional diode BD.

[0062] Reference Figure 2C The memory cell MC may include a variable resistor R and a transistor T. The word line WL may be connected to the gate of the transistor T.

[0063] Reference Figure 2DThe memory cell MC may include a bidirectional threshold switch (OTS) and a variable resistor R. The bidirectional threshold switch (OTS) may include materials similar to germanium-antimony-telluride (GST, Ge2Sb2Te5). For example, the bidirectional threshold switch (OTS) may be a combination of selenium (Se), arsenic (As), germanium (Ge), and silicon (Si), and may include chalcogenides that can change their crystalline state and amorphous state.

[0064] The structure of the memory cell MC in the example embodiments is not limited to... Figure 2A , Figure 2B , Figure 2C and Figure 2D The example shown is shown in the image.

[0065] In the following description, a specific three-dimensional memory cell structure configured as a switching device will be described according to an example embodiment.

[0066] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E and Figure 3F These are respective diagrams illustrating examples of three-dimensional memory cell structures that can be used in exemplary embodiments.

[0067] Figure 3A A first memory cell MC1 and a second memory cell MC2 are shown arranged between multiple conductors 101, 102, and 103. The first memory cell MC1 and the second memory cell MC2 can operate as independent memory cells. In one example embodiment, when the first conductor 101 and the second conductor 102 are word lines, the third conductor 103 can be a bit line. In the following description, for ease of description, the first conductor 101 and the second conductor 102 may be referred to as the first word line and the second word line, respectively.

[0068] In an example embodiment, the first memory unit MC1 may include a first heating electrode 111, a first information storage device 112, and a first switching device 113. In an example embodiment, the first switching device 113 may include a first switching electrode 113-1, a second switching electrode 113-2, and a first selection layer 113-3 disposed between the first switching electrode 113-1 and the second switching electrode 113-2. In an example embodiment, the first selection layer 113-3 may include a bidirectional threshold switching (OTS) material. When a voltage level greater than a threshold voltage is applied between the first switching electrode 113-1 and the second switching electrode 113-2, current can flow through the first selection layer 113-3. The first information storage device 112 may include a phase change material. In an example embodiment, the first information storage device 112 may include a chalcogenide material. For example, the first information storage device 112 may include Ge-Sb-Te (GST). The crystallization temperature, melting point, and phase change rate depending on the crystallization energy of the first information storage device 112 may be determined based on the types and chemical composition ratios of the elements included in the first information storage device 112.

[0069] The second memory unit MC2 may have a structure similar to that of the first memory unit MC1.

[0070] In the following description, methods for writing and erasing data will be described with reference to the first memory cell MC1. When a voltage is applied through the first word line 101 and the bit line 103, Joule heating based on the voltage can be generated on the interface surface between the first heating electrode 111 and the first information storage device 112. Through Joule heating, the phase change material included in the first information storage device 112 can change from an amorphous state to a crystalline state, or vice versa. The first information storage device 112 may have relatively high resistance in the amorphous state and relatively low resistance in the crystalline state. In one example embodiment, data “0” or “1” may be defined based on the resistance value of the first information storage device 112.

[0071] To write data into the first memory cell MC1, a programming voltage can be applied via the first word line 101 and the bit line 103. The programming voltage can be greater than the threshold voltage of the bidirectional threshold switching material included in the first switching device 113. Therefore, current can flow through the first switching device 113. Through the programming voltage, the phase change material included in the first information storage device 112 can change from an amorphous state to a crystalline state. Therefore, data can be stored in the first memory region. In one example embodiment, when the phase change material included in the first information storage device 112 is in a crystalline state, the state of the first memory cell MC1 can be defined as a set state.

[0072] To erase the data stored in the first memory cell MC1, the phase change material included in the first information storage device 112 can be restored from a crystalline state to an amorphous state. For example, a predetermined erase voltage can be applied via the first word line 101 and the bit line 103. The erase voltage restores the phase change material included in the first information storage device 112 from a crystalline state to an amorphous state. When the phase change material included in the first information storage device 112 is in an amorphous state, the state of the first memory cell MC1 can be defined as a reset state. In one example embodiment, the maximum value of the erase voltage can be greater than the maximum value of the programming voltage. The time for applying the erase voltage can be shorter than the time for applying the programming voltage.

[0073] Figure 3A An example is shown where the first memory cell MC1 and the second memory cell MC2 may have the same directionality. However, the exemplary embodiments of the inventive concept are not limited thereto.

[0074] Reference Figure 3B When the first conductor 101 and the second conductor 102 are the first word line and the second word line respectively, and... Figure 3A The memory cells shown are different, and the orientations of the first memory cell MC1 and the second memory cell MC2 may be different. For example, the heating electrode 111 of the first memory cell MC1 may be connected to the first word line 101, and the heating electrode 114 of the second memory cell MC2 may be connected to the bit line 103.

[0075] Figure 3A The first memory cell MC1 and the second memory cell MC2 shown in the diagram can be referred to as having a first orientation. Figure 3B The first memory cell MC1 shown may be described as having a first directionality, and the second memory cell MC2 may be described as having a second directionality.

[0076] exist Figure 3A and Figure 3B In this embodiment, a first memory cell MC1 connected to a first word line disposed on the first layer and a second memory cell MC2 connected to a second word line disposed on the second layer may share a bit line. However, exemplary embodiments of the inventive concept are not limited thereto.

[0077] Reference Figure 3C The first memory cell MC1 can be arranged at the intersection of the first word line 101 and the first bit line 102 on the first layer. The second memory cell MC2 can be arranged at the intersection of the second word line 103 and the second bit line 104 on the second layer. The first memory cell MC1 can have a first directionality, and the second memory cell MC2 can have a second directionality. (Refer to...) Figure 3DEach of the first memory unit MC1 and the second memory unit MC2 may have the same as Figure 3C The memory cells shown in the figure have different first orientations.

[0078] The memory cells in certain example embodiments may not have heating electrodes, but may be self-heating.

[0079] Figure 3E Further examples of... Figure 3C The memory cell shown is similar to a memory cell with the heating electrode removed. Figure 3F It shows the relationship with Figure 3D The memory cell shown is similar to a memory cell with the heating electrode removed.

[0080] The memory cell array 110 may have a three-dimensional stacked structure.

[0081] Figure 4 This illustrates an example embodiment. Figure 1 An illustration of an example of a three-dimensional stacked structure of a memory cell array 110. The three-dimensional stacked structure may include a structure in which multiple memory cell layers (e.g., 110-1 to 110-8) are stacked vertically (e.g., stacked on top of each other perpendicular to the substrate).

[0082] Figure 4 The example shown illustrates eight (8) stacked memory cell layers 110-1 to 110-8, but any reasonable number of layers can be used. Each of the memory cell layers 110-1 to 110-8 may include multiple groups of resistive memory cells and / or multiple groups of redundant memory cells. When the memory cell array 110 has a three-dimensional stacked structure, as in Figure 4 As in the example embodiment shown, memory cell layers 110-1 to 110-8 may have a cross-point structure.

[0083] In the example embodiment, at least two of the memory cell layers 110-1 to 110-8 can perform corresponding write operations according to different write modes.

[0084] Figure 5 It is to further demonstrate Figure 4 An example diagram of a single memory cell array 110-1 is shown. Here, the memory cell array 110-1 may include an intersection structure. The intersection structure may represent a structure in which a single resistive memory cell MC is disposed in a region where one line intersects with another line. For example, bit lines BL1_1 to BL4_1 may extend along a first direction, word lines WL1_1 to WL3_1 may extend along a second direction to intersect with bit lines BL1_1 to BL4_1, and resistive memory cells MC may be disposed in the regions where bit lines BL1_1 to BL4_1 intersect with word lines WL1_1 to WL3_1, respectively.

[0085] In one example embodiment, the memory cell MC may be configured as a single-level cell (SLC) storing a single data bit. In another example embodiment, the memory cell MC may be configured as a multi-level cell (MLC) capable of storing two or more data bits. In yet another example embodiment, memory cells in a portion of the memory cell array 110 may be configured as SLCs, and memory cells in another portion of the memory cell array 110 may be configured as MLCs.

[0086] The memory cell array 110 in a particular example embodiment may also include a memory cell array portion that performs buffer functions.

[0087] Figure 6 This is a diagram illustrating an example of a memory cell array 110a according to another exemplary embodiment. (Refer to...) Figure 6 The memory cell array 110a may include a first memory cell array 110a-1 and a second memory cell array 110a-2. Here, the first memory cell array 110a-1 can operate as a main memory cell array, and the second memory cell array 110a-2 can operate as a buffer.

[0088] In one example embodiment, the first memory cell array 110a-1 and the second memory cell array 110a-2 can perform corresponding write operations according to different write modes.

[0089] In addition, such as Figure 6 As shown, the RWC layer can be disposed below the memory cell array 110a. The RWC layer (including, for example...) Figure 1 The write circuit 140 and / or read circuit 150 can be used to perform write and / or read operations related to a plurality of memory cells included in the memory cell array 110a. Figure 6 The RWC layer shown can be located below the memory cell array 100a, but the location of the RWC layer is not limited to this.

[0090] Figure 6 The first memory cell array 110a-1 and the second memory cell array 110a-2 may be disposed on the same layer. However, exemplary embodiments of the inventive concept are not limited thereto, and the first memory cell array and the second memory cell array may be disposed on different layers.

[0091] Figure 7 This is a diagram illustrating an example of a memory cell array 110b according to another exemplary embodiment. (Refer to...) Figure 7The memory cell array 110b may include a plurality of first memory cell arrays 110b-1 and 110b-2 disposed at different layers, and a second memory cell array 110b-3 disposed at a different layer than any of the layers where the first memory cell arrays 110b-1 and 110b-2 are disposed.

[0092] In one example embodiment, at least two of the first memory cell arrays 110b-1 and 110b-2 and the second memory cell array 110b-3 can perform corresponding write operations according to different write modes.

[0093] Figure 8 This illustrates that, according to another example embodiment, it may include... Figure 1 A diagram illustrating an example of the sensing amplifier 152 in the readout circuit 150. (Refer to...) Figure 8 The sensing amplifier (SA) 152 can be used to compare the voltage of the word line WL connected to the memory cell MC with a reference voltage Vref to output a sensing result SAOUT. The memory cell MC can be positioned between a selected word line WL and a selected bit line BL. During a read operation, a read voltage Vread can be applied to the selected bit line BL.

[0094] In one example embodiment, the level of the read voltage Vread may vary depending on the selected write mode for the write operation (e.g., normal mode, DCW mode, aDCW mode, and RDSKIP aDCW mode).

[0095] In another example embodiment, the level of the read voltage Vread may vary according to (or further according to) an internal strategy for the NVM device 100. For example, the internal strategy may include an acceptable range of memory cell degradation for the memory cells of the NVM device 100, environmental information, timing information, etc.

[0096] In another example embodiment, the level of the read voltage Vread may vary according to (or further according to) control information received from an external device (e.g., a memory controller).

[0097] Figure 8 The sensing amplifier 152 shown is one example of a selection of elements that can be used to achieve the foregoing (e.g., sensing data by comparing word line voltage with reference voltage Vref).

[0098] In the following description, the write operation performed according to the selected write mode will be described in some additional detail with reference to an example embodiment.

[0099] Figure 9A This is a diagram illustrating a write data latch 172-1 according to an example embodiment. Figure 9B This is a diagram illustrating a write data latch 172-2 according to an example embodiment. (Refer to...) Figure 9A The write data latch 172-1 may include a trigger. The data to be written, WR_Data, can be output by the trigger. (See reference...) Figure 9B The write data latch 172-2 may include a trigger. Figure 8 The data RD_Data read out by the sensing amplifier 152 shown can be output as readout data D_RD by a trigger.

[0100] Figure 9A and Figure 9B The data latches 172-1 and 172-2 shown are implemented as triggers. However, the configuration of the data latches is not limited to this.

[0101] Figure 10A , Figure 10B and Figure 10C It shows that it can be generated by Figure 1 The control logic 170 generates control signals based on the selected write mode, and the respective logic diagrams are examples of these.

[0102] Reference Figure 10A The event activation signal generator 173 may include a first logic circuit 173-1 to a fifth logic circuit 173-5.

[0103] The first logic circuit 173-1 can write data D_WR (see...) Figure 9A The first logic circuit 173-1 performs an XOR operation on the output of the first logic circuit 173-1 and the DCW mode activation signal DCW_EN. The second logic circuit 173-2 performs an AND operation on the output of the first logic circuit 173-1 and the DCW mode activation signal DCW_EN. The third logic circuit 173-3 performs an AND operation on the output of the read data D_RD and the aDCW mode activation signal aDCW_EN. The fourth logic circuit 173-4 performs a NOR operation on the DCW mode activation signal DCW_EN, the aDCW mode activation signal aDCW_EN, and the read skip aDCW mode activation signal aDCW_RDSKIPEN. The fifth logic circuit 173-5 performs an OR operation on the output of the second logic circuit 173-2, the third logic circuit 173-3, and the fourth logic circuit 173-4, and generates the event activation signal EVNT_EN.

[0104] However, Figure 10A The event activation signal generator shown is just an example.

[0105] Reference Figure 10BThe write control signal generator 174 may include sixth logic circuits 174-1 to ninth logic circuits 174-4. The sixth logic circuit 174-1 performs an AND operation on the event activation signal EVNT_EN and the write activation signal WR_EN. The seventh logic circuit 174-2 inverts the write data D_WR. The eighth logic circuit 174-3 performs an AND operation on the write data D_WR and the output of the sixth logic circuit 174-1, and generates a set activation signal SET_EN (write control signal). The ninth logic circuit 174-4 performs an AND operation on the output of the sixth logic circuit 174-1 and the output of the seventh logic circuit 174-2, and generates a reset activation signal RST_EN (write control signal).

[0106] Reference Figure 10C The read control signal generator 175 may include a tenth logic circuit 175-1. The tenth logic circuit 175-1 can perform an AND operation on the read skip aDCW mode activation signal aDCW_RDSKIPEN and the write data D_WR, and can generate the read skip activation signal RD_SKIPEN (read control signal).

[0107] The resistance value of a resistive memory cell can drift over time, causing the distribution of the resistance value of the memory cell to expand.

[0108] Figure 11 This is a diagram illustrating an example of the voltage distribution of memory cells after a write operation performed according to normal mode. (Refer to...) Figure 11 Memory cells in a set (SET) or reset (RST) state can drift over time after a write operation. For example... Figure 11 As shown in the diagram, as a worst-case example, some memory cells in the set state may drift significantly beyond the read voltage Vread. In this case, when a read operation is performed using the read voltage Vread, although the memory cell is programmed in the set state, it may be identified as being programmed in the reset state. Therefore, when DCW mode is activated, the memory cell state may be difficult to accurately identify due to the drift experienced by the previous distribution.

[0109] Subsequently, when the memory cell state has drifted, a write operation can be performed according to the DCW mode.

[0110] Figure 12 This is a diagram illustrating an example of the memory cell distribution after a write operation performed according to DCW mode. (Refer to...) Figure 12The distribution of memory cells can be represented by one of four states. That is, after a write operation according to DCW mode, the state of a memory cell can be one of the following: Old SET, New SET, Old RST, and New RST. Here, Old SET indicates that the set state has been maintained, New SET indicates that the state has been programmed from the reset state to the set state, Old RST indicates that the reset state has been maintained, and New RST indicates that the state has been programmed from the set state to the reset state.

[0111] Problems arising from write operations performed in DCW mode may include: cell 'A' not exceeding the read voltage Vread in the drift set state, and cell 'B' exceeding the read voltage Vread in the drift set state.

[0112] Figure 13 This is a data table listing the results of write operations performed according to DCW mode. In the following description, set data (i.e., setting the memory cell state) is assumed to correspond to the data value "1", and reset data (i.e., resetting the memory cell state) is assumed to correspond to the data value "0". However, the data values ​​corresponding to the set and reset memory cell states are not limited to these.

[0113] Reference Figure 13 The result of a write operation performed in DCW mode can vary relative to the old data, the read data (sensed data), and the written data.

[0114] When the old data (or previous data) is "1", the memory cell can be in a drifting set state. For example... Figure 11 and Figure 12 As shown, the set states of the drift can be divided into a first distribution where the cells do not exceed the read voltage Vread and a second distribution where the cells exceed the read voltage Vread. Therefore, the read data D_RD read in the read operation (see...) Figure 9B The data stored in the read latch can be represented by either "1" or "0".

[0115] A memory cell where the old data is "1" and the read data D_RD is "1" can represent a memory cell in the first distribution A that has drifted but remains in the set state. When the write data D_WR in the memory cell in the first distribution A (see...) Figure 9A When the data stored in the write latch is "1", a write operation is not required (indicated by "X"). When the write data D_WR in the memory cell of the second distribution B is "0", a reset operation RST can be performed on the memory cell.

[0116] A memory cell whose old data is "0" and whose read data D_RD is "0" can represent a memory cell included in the second distribution B. Memory cells included in the second distribution B can be identified as being in a reset state due to excessive drift. When the write data D_WR in a memory cell in the second distribution B is "1", a set operation (SET) can be performed on the memory cell. When the write data D_WR in a memory cell in the second distribution B is "0", no operation can be performed on the memory cell. Therefore, the memory cell can have meta-state data.

[0117] When the old data is "0", the memory cell can be in a drifting reset state. When the written data D_WR in the memory cell where the read data D_RD is "0" is "1", a set operation can be performed on the memory cell. When the written data D_WR in the memory cell where the read data D_RD is "0" is "0", no operation can be performed on the memory cell.

[0118] Figure 14 , Figure 15 and Figure 16 These are data tables that illustrate the read / write data relationships associated with write modes according to the example embodiments, but in different ways.

[0119] Reference Figure 14 It can perform set / reset operations based on the read data D_RD and the written data D_WR. Figure 14 In this context, "X" indicates that no operation is performed, and "O" indicates that a set / reset operation is performed.

[0120] When reading data D_RD is "1" and writing data D_WR is "1", a write operation is not performed in DCW mode, but a set operation is performed in aDCW mode. When reading data D_RD is "1" and writing data D_WR is "0", a reset operation can be performed in both DCW and aDCW modes. When reading data D_RD is "0" and writing data D_WR is "1", a set operation can be performed depending on whether it is DCW or aDCW mode. When reading data D_RD is "0" and writing data D_WR is "0", a write operation is not performed in either DCW or aDCW mode.

[0121] Therefore, when the read data D_RD and the write data D_WR are the same in DCW mode, the write operation can be blocked, and when the read data D_RD and the write data D_WR are "0" (reset state) in aDCW mode, the write operation can be blocked.

[0122] Reference Figure 15The set / reset operation can be performed based on the old data, read data D_RD, and write data D_WR as follows.

[0123] In a memory cell where the old data (or previous data) is "1" (set state) and the read data D_RD is "1", a set operation can be performed on the memory cell when the write data D_WR is "1". In a memory cell where the old data is "1" (set state) and the read data D_RD is "1", a reset operation can be performed on the memory cell when the write data D_WR is "0".

[0124] The read voltage used in a write operation performed according to aDCW mode can be greater than or equal to the read voltage Vread used in normal mode. Therefore, a drifting memory cell in the reset state can be identified as being in the set state. That is, although the old data can be "0", the read data D_RD can be "1" or "0".

[0125] In a memory cell where the old data is "0" (reset state) and the read data D_RD is "1", a set operation can be performed on the memory cell when the write data D_WR is "1". This configuration can correspond to Figure 13 The original state data is shown in the figure. In a memory cell where the old data is "0" (reset state) and the read data D_RD is "1", a reset operation can be performed on the memory cell when the write data D_WR is "0".

[0126] In a memory cell where the old data is "0" (reset state) and the read data D_RD is "0", a set operation can be performed on the memory cell when the write data D_WR is "1". In a memory cell where the old data is "0" (reset state) and the read data D_RD is "0", no operation can be performed on the memory cell when the write data D_WR is "0".

[0127] In one example implementation, read skipping can be applied based on the data to be written in aDCW mode. For example, read skipping may not be necessary when the data to be written is set data.

[0128] Reference Figure 16 ,and Figure 14The examples shown differ; a read skip aDCW mode can be added to the write operation mode. When the write data D_WR is "0" and the read data D_RD is "0", a write operation can be skipped in read skip aDCW mode. When the write data D_WR is "0" and the read data D_RD is "1", a reset operation can be performed in read skip aDCW mode. When the write data D_WR is "1" and the read data D_RD is "0", a set operation can be performed in read skip aDCW mode. When the write data D_WR is "1" and the read data D_RD is "1", a set operation can be performed in read skip aDCW mode.

[0129] Figure 17 This is a diagram illustrating an example of the memory cell distribution when a write operation is performed according to the aDCW mode, based on an example embodiment. (Refer to...) Figure 17 When performing a write operation according to aDCW mode, a read operation (sensing operation) can be performed using a read voltage Vread_aDCW that is determined to be greater than or equal to the read voltage Vread used in normal mode. When performing an aDCW write operation based on the read data D_RD obtained through the above read operation, a data comparison write operation excluding the primitive state can be performed. For example... Figure 17 As shown, memory cells in the reset state can be drifted, and write operations can be performed regardless of data in the set state, thereby ensuring a relatively wide margin.

[0130] Figure 17 The distribution shown is an example in which all memory cells in the set / reset state have drifted under the influence of a write operation. However, this example embodiment is not limited to this.

[0131] Figure 18 This is a diagram illustrating an example of the memory cell distribution when a write operation is performed according to aDCW mode, based on another example embodiment. (Refer to...) Figure 18 When only a memory cell in the set state has drifted after a write operation, or when the drift speed of a memory cell in the set state is greater than the drift speed of a memory cell in the reset state, the distribution corresponding to the set state may partially overlap with the distribution corresponding to the reset state. When performing a write operation according to aDCW mode, a set or reset operation can be performed using the read voltage Vread_aDCW.

[0132] When the written data is "0", the memory cells in the overlapping portion C with old data of "0" can remain unchanged. The memory cells in the overlapping portion C with old data of "1" can be set or reset based on the written data D_WR. Therefore, as... Figure 18As shown, sufficient sensing margin between the set state and the reset state can be ensured.

[0133] Compared to write operations performed according to DCW mode, write operations performed according to aDCW mode can reduce the write settling time tWTR. The write settling time tWTR can include the time period during which the write operation is performed and the time period during which the amorphous state of the phase change material included in the resistive memory cell is stabilized by heat. A stable state can represent a state in which sufficient drift is stabilized for a memory cell in a reset state.

[0134] Figure 19 This is an overview of the possible embodiments based on example examples. Figure 1 A flowchart of an example of the write method (or execution of a write operation) used by the NVM device 100.

[0135] Reference Figures 1 to 19 When a write command, address, and write data are received from an external entity (e.g., a memory controller), a sensing operation can be performed on the data of the memory cell corresponding to the address (S110). The write data D_WR can be compared with the read (or sensed) data (i.e., read data D_RD) obtained through the sensing operation (S120). It is determined whether the write data D_WR is the same as the read data D_RD (S130).

[0136] When the written data D_WR is the same as the read data D_RD (S130 = Yes), it is further determined whether the written data D_WR is set data (S140). When the written data D_WR is set data (S140 = Yes), a set operation can be performed on the memory cell (S145). When the written data D_WR is not set data (S140 = No), the write operation ends.

[0137] However, when the written data D_WR is different from the read data D_RD (S130 = No), it is further determined whether the written data D_WR is reset data (S160). When the written data D_WR is not reset data (S160 = No), a set operation can be performed on the memory cell (S150). When the written data D_WR is reset data (S160 = Yes), a reset operation can be performed on the memory cell (S170).

[0138] In the write method performed according to an example embodiment of the inventive concept (or during the execution of a write operation), a data comparison write DWC method can be used, and read skipping can be applied simultaneously based on the write data.

[0139] Figure 20 This illustrates a possible embodiment according to another example. Figure 1Another flowchart illustrating an example of the write method (or execution of a write operation) used by the NVM device 100.

[0140] Reference Figures 1 to 10C The NVM device 100 can receive a write command, write data, and / or address from an external entity (S210). It can then determine whether the write data D_WR is set data corresponding to a set state (e.g., data value "1") (S220). When the write data D_WR is "1" (S220 = Yes), a set operation can be performed on the memory cell corresponding to the address (S230).

[0141] However, when the written data D_WR is reset data corresponding to the reset state (e.g., data value "0") (S220 = No), a read operation can be performed on the memory cell corresponding to the address (S240). The read operation can be performed using a read voltage determined to be greater than or equal to the read voltage used during normal mode.

[0142] If the read operation determines that the read data D_RD is reset data (S250 = Yes), then the write operation may not be performed. However, if the read data D_RD is not reset data (S250 = No), a reset operation may be performed on the memory cell (S260).

[0143] Figure 21 and Figure 22 It is a timing diagram. Figure 21 This illustrates a timing example of a write operation for writing data "1" according to an example embodiment of an aDCW mode. (Refer to...) Figure 21 In normal mode read operations, the first read level read voltage Vread can be applied to bit line BL, and the read word line voltage Vrd_WL can be applied to word line WL.

[0144] In a read operation according to the aDCW mode, a read voltage Vread_aDCW with a second read level can be applied to bit line BL, and a read word line voltage Vrd_WL can be applied to word line WL. The read voltage Vread_aDCW can be variable. In one example embodiment, the read voltage Vread_aDCW with the second read level can be greater than the read voltage Vread with the first read level in normal mode.

[0145] In a write operation according to aDCW mode, a reset pulse or a set pulse can be applied to the bit line BL / word line WL. Compared to the set pulse, the reset pulse can have a relatively higher amplitude and a relatively shorter application time. For example, in a reset operation, the reset bit line voltage Vrst_BL can be applied to the bit line, and the write word line voltage Vwr_WL can be applied to the word line. Similarly, in a set operation, the set bit line voltage Vset_BL can be applied to the bit line, and the write word line voltage Vwr_WL can be applied to the word line.

[0146] In one example embodiment, the read word line voltage Vrd_WL and the write word line voltage Vwr_WL can be negative voltages.

[0147] In one example embodiment, the reset bit line voltage Vrst_BL may be greater than the set bit line voltage Vset_BL.

[0148] Figure 22 This illustrates a timing example of writing data "0" according to an example embodiment in aDCW mode. (Refer to...) Figure 22 ,and Figure 21 The timing of the write operations shown is different. Figure 22 The timing of the write operation shown may not include a reset pulse. Therefore, unlike the aforementioned example embodiment, in Figure 22 In the example embodiment shown, the reset pulse corresponding to the reset state may not be applied to bit line BL / word line WL, and other operations may be the same as those in the aforementioned example embodiment.

[0149] Figure 23A and Figure 23B This is a graph further illustrating the various effects of write operations on an NVM device according to an example embodiment. (Refer to...) Figure 23A The power consumption of each write mode was compared. The write mode with DCW (w DCW) consumed the least power, the write mode with aDCW (w aDCW) consumed the second most power, and the write mode without DCW (w / o DCW) consumed the most power. (See reference...) Figure 23B The figure shows the failure rate for each write mode. The failure rate of the write mode with DCW increases over time, while the failure rate of the write mode with aDCW can be 0 over time.

[0150] Figure 24 This is a diagram illustrating a storage device 1000 according to an example embodiment. (Refer to...) Figure 24 The storage device 1000 may include at least one non-volatile memory (NVM) device 1100 and a memory controller 1200.

[0151] To reduce power consumption and improve data reliability during write operations, an NVM device and write method according to embodiments of the inventive concept (such as those described above) can be used. Figures 1 to 22 The NVM device 1100 is implemented using those described. In one example embodiment, the NVM device 1100 may (optionally) be configured to receive an external high voltage Vpp.

[0152] The memory controller 1200 can be connected to the NVM device 1100. The memory controller 1200 may include at least one processor (CPU) 1210, a buffer memory 1220, an error correction circuit (ECC) 1230, a code memory 1240, a host interface 1250, and an NVM interface 1260.

[0153] Processor 1210 can be configured to control overall operation. Processor 1210 can be implemented as a central processing unit (CPU) or an application processor (AP).

[0154] The buffer memory 1220 can temporarily store data required for the operation of the memory controller 1200. Figure 24 The buffer memory 1220 shown may be located within the memory controller 1200, but the example embodiment is not limited thereto. In the example embodiment, the buffer memory 1220 may be located in a separate intellectual property block arranged outside the memory controller 1200.

[0155] Error correction circuit 1230 can calculate error correction code values ​​for the data to be programmed during write operations, correct errors in read data based on the error correction code values ​​during read operations, and correct errors in data recovered from NVM device 1100 during data recovery operations. Error correction circuit 1230 can use coding modulation (such as low-density parity-check (LDPC) codes, BCH codes, turbo codes, Reed-Solomon codes, convolutional codes, recursive systematic codes (RSC), trellis-coded modulation (TCM), block code modulation (BCM), etc.) for error correction. Code memory 1240 can store code data required to operate memory controller 1200. Code memory can be implemented as an NVM device. Host interface 1250 provides functionality for interfacing with external devices. NVM interface 1260 provides functionality for interfacing with NVM device 1100. Although not shown in the figures, memory controller 1200 may include wireless communication functionality (e.g., Wi-Fi).

[0156] The storage device 1000 may include an NVM device capable of performing a write mode that provides increased immunity to resistance drift while reducing power consumption, thereby significantly improving system performance.

[0157] The NVM device in the example embodiment may, under other conditions, perform the optimal write mode based on the location of the memory cells within the memory cell array.

[0158] Figure 25 This is an illustration of an example memory system 2000 according to an exemplary embodiment, in which a specific write mode is applied to memory cells located in edge portions. The memory system 2000 generally includes a memory controller 2200 and a storage device 2100 including an NVM device according to an embodiment of the inventive concept. (Refer to...) Figure 25 When an address ADD is received from the memory controller 2200 in the storage device 2100, the control logic 2170 can determine, for example, whether the memory cell indicated by the received address is located in the edge portion of the memory cell array 2110. Based on this determination, the control logic 2170 can select an appropriate write mode for the write operation to be performed.

[0159] Here, different write modes can be used depending on environmental conditions (e.g., temperature), memory cell information (e.g., lifespan, degree of degradation, bit error rate, etc.).

[0160] Figure 26 This is a diagram illustrating an example of a memory system 3000 that selectively performs write operations according to various selected write modes, taking into account environmental conditions, based on an exemplary embodiment. (Refer to...) Figure 26 The memory controller 3200 can collect environmental information and select the optimal reliability write mode based on the collected information.

[0161] In one example embodiment, environmental information may include cycle information, temperature information, number of bit errors, etc., relating to the number of write or read operations performed on the memory cell.

[0162] The memory controller 3200 can transmit write mode setting information to the NVM device 3100, and the NVM device 3100 can select a write mode based on the write mode setting information. The NVM 3100 can also change the level of the read voltage Vread according to the selected write mode in the read voltage setting logic 3172.

[0163] In a particular embodiment of the inventive concept, one or more NVM devices may be applied to a server system. For example, Figure 27 This is a diagram illustrating an example of a server system 4000 according to an example embodiment.

[0164] Reference Figure 27The server system 4000 may include at least one memory module 4100 (DIMM), at least one NVM module 4200 (NVDIMM), and at least one processor 4300. The at least one NVM module 4200 may include NVM devices as previously described. Therefore, the server system 4000 can enjoy increased data reliability with reduced power consumption, enabling the server system 4000 to perform data management in an economical manner.

[0165] The above example embodiments can be applied to various types of computing systems (e.g., central processing unit (CPU) / graphics processing unit (GPU) / neural processor (NPU) platforms).

[0166] Figure 28 This is a diagram illustrating an example of a computing system 5000 according to an example embodiment. (Refer to...) Figure 25 The computing system 5000 may include a central processing unit (CPU) 5110, an accelerator 5120, a memory device 5210 or a storage device 5220 connected to the system bus 5001, an I / O device 5310, a modem 5320, a network device 5330 or a storage device 5340 connected to the expansion bus 5002.

[0167] System bus 5001 can be configured as a PCI bus or a PCIe bus, and expansion bus 5002 can be connected to system bus 5001 via expansion bus interface 5003. However, the example embodiments are not limited to this, and I / O devices, modems, network devices, etc., can be connected to the system bus. Peripheral devices can use direct memory access methods to independently and directly access the CPU's main memory through the DMA engine. The CPU can initiate a transfer operation and perform other tasks, and when the transfer operation terminates, the CPU can be interrupted by the DMA controller.

[0168] exist Figure 28 In the example embodiments, the system bus 5001 or the expansion bus 5002 can be configured based on a serial / parallel connection. The serial / parallel connection can use a multi-drop method, a daisy-chain method, a switching hub method, etc.

[0169] In one example embodiment, the CPU 5110, accelerator 5120, main memory 5114, and storage device 5220 are interconnected via a system bus 5001. The accelerator may be configured as a GPU, NPU, or dedicated processing device. In one example embodiment, the CPU 5110 and accelerator 5120 may be configured as multi-core.

[0170] Each of the CPU 5110 and accelerator 5120 (GPU, NPU, or dedicated processing device) may have an on-chip cache, an off-chip cache, or a back-end bus cache between the CPU 5110 and accelerator 5120 and the system bus 5001. In one example embodiment, off-chip caches 5112 and 5122 may be connected to the CPU 5110 / accelerator 5120 via separate buses. In one example embodiment, the CPU 5110 and accelerator 5120 may include on-chip caches 5111 and 5121. Each of the off-chip caches 5112 and 5122 may be connected to the respective CPU 5110 and the respective accelerator 5120. In one example embodiment, the on-chip / off-chip cache may include volatile memory (such as dynamic random access memory (DRAM), static random access memory (SRAM), etc.) or NVM (such as NAND flash memory, phase-change random access memory (PRAM), resistive random access memory (RRAM), etc.).

[0171] Main memories 5114 and 5210 (e.g., memories other than bridge memory or memory associated with the accelerator) can be connected to the CPU 5110 and the accelerator 5120 via corresponding memory controllers 5113 and 5211. In one example embodiment, main memories 5114 and 5210 may include volatile memory (such as DRAM, SRAM, etc.) or NVM (such as NAND flash memory, PRAM, etc.).

[0172] The main memory can communicate with the memory controller via standard interfaces such as DDR, LPDDR, GDDR, HBM, and NVDIMM. The memory controller can send commands via a command chip, send addresses via address pins, and send and receive data via the DQ pin. In one example embodiment, the Din pin can be separated from the Dout pin. The memory controller can provide a CLK signal via the CLK pin and can provide control signals for receiving other signals via corresponding pins (e.g., CS, CLE, ALE, WE, RE, DQS). The memory can provide data to the memory controller via the DQ pin and can provide control signals for receiving signals via corresponding pins (e.g., DQS). A portion of the control signals can be strobe signals. Some of the aforementioned pins can be combined. For example, the command pin and address pin can be combined into a CA pin.

[0173] When the processor (CPU / accelerator) uses programs and data, the programs and data can be stored in main memory or accelerator-specific memory 5114, 5116, and 5210. Specific programs and data can be stored in accelerator-specific memory dedicated to the corresponding programs and data. Main memory can be used as a directly accessible space within the CPU / accelerator. When software is executed, main memory / accelerator-specific memory can be used as the software's execution space. When software is executed, the corresponding programs and data used by the processor can be copied from storage devices to main memory or vice versa. Programs and data related to the accelerator's application can be copied from main memory or storage devices to accelerator-specific memory, or vice versa. Furthermore, if necessary, only a portion of the data used in the program can be copied to main memory or accelerator-specific memory. Only a portion of the data used in the program can be copied to main memory or accelerator-specific memory 5114, 5116, and 5210. In one example embodiment, memory 5210 can be dedicated to CPU 5110 or can be shared by CPU 5110 and accelerator 5120. In one example embodiment, a portion of memory 5210 may be dedicated to accelerator 5120. In one example embodiment, CPU 5110 and accelerator 5120 may share a bridge.

[0174] Bridged memories 5116 and 5126 can be connected to CPU 5110 and accelerator 5120 via bridges 5115 and 5125. Bridges 5115 and 5125 may include memory controllers for controlling the respective memories 5116 and 5126. In one example embodiment, each of bridges 5115 and 5125 may be implemented as a network device, a wireless network device, a switch, a bus, a cloud, or an optical channel.

[0175] For example, CPU 5110 and / or accelerator 5120 can perform write operations on NVM devices, as described above. Figures 1 to 26 The operations described. Memory controllers 5113 / 5123 / 5115 / 5125 / 5211 can receive write commands from CPU 5110 / accelerator 5120. Memory controllers 5113 / 5123 / 5115 / 5125 / 5211 can receive write commands and can perform read-ahead operations. Memory controllers 5113 / 5123 can compare the read data generated by the read-ahead operation with the write data, and can determine whether to perform an overwrite operation based on the comparison result.

[0176] In one example embodiment, memories 5116 and 5126 can be connected to CPU 5110 and accelerator 5120 via bridges 5115 and 5125. Bridges 5115 and 5125 may include memory controllers for controlling the respective memories 5116 and 5126. In one example embodiment, each of bridges 5115 and 5125 may be implemented as a network device, a wireless network device, a switch, a bus, a cloud, or an optical channel.

[0177] In one example embodiment, CPU 5110, CPU caches 5111 and 5112, accelerator 5120, or accelerator caches 5121 and 5122 may be connected to system bus 5001 via corresponding bridges 5115 and 5125. In another example embodiment, CPU 5110, CPU caches 5111 and 5112, accelerator 5120, or accelerator caches 5121 and 5122 may be directly connected to system bus 5001 without a bridge.

[0178] A single memory can be connected to Figure 28 Each of bridges 5115 and 5125 is shown, but exemplary embodiments thereof are not limited thereto. The number of memories connected to bridges 5115 and 5125 may be two or more.

[0179] In one example embodiment, memory 5126 may include GPU memory, NPU memory, or dedicated memory.

[0180] When accelerator 5120 is configured as a GPU, memories 5124 and 5126 may include GPU memory. GPU memory can hold commands and data interacting with main memory. Commands and data can be copied to main memory or a storage device. GPU memory can store image data and may have a higher bandwidth than main memory 5210 / CPU ​​memory 5116. GPU memory can use a clock different from the clock of main memory 5210 / CPU ​​memory 5116. The GPU can read image data from GPU memory, process image data, and write image data to GPU memory. GPU memory can be configured to accelerate graphics processing operations. In one example embodiment, the CPU communicates with main memory / CPU memory via a DDR interface, and the GPU communicates with GPU memory via GDDR, HBM interfaces, and other interfaces dedicated to GPU memory. The GPU can be connected to GPU memory via an inserter.

[0181] When accelerator 5120 is configured as an NPU, memories 5124 and 5126 may include NPU memory. The NPU memory can hold commands and data interacting with the NPU. Commands and data can be copied to main memory or a storage device. Copying in main memory can be performed by the CPU or by a DMA method of a DMA engine. The NPU memory can hold weight data for the neural network. The NPU memory may have a higher bandwidth than the main memory 5210 / CPU ​​memory 5116. The NPU memory can use a clock different from the clock of the main memory 5210 / CPU ​​memory 5116. The NPU can read weight data from the NPU memory, update the data, and use the data for the NPU memory during training. The NPU memory can be configured to accelerate machine learning, such as neural training and inference. In one example embodiment, the CPU can communicate with the main memory / CPU memory via a DDR interface, and the NPU can communicate with the NPU memory via GDDR, HBM interfaces, and other interfaces dedicated to the NPU memory. The NPU can be connected to the NPU memory via an inserter.

[0182] CPU 5110 or accelerator 5120 can access auxiliary storage devices 5210, 5220, and 5340 via system bus 5001 or expansion bus 5002. Memory 5210 may be controlled by memory controller 5211. Memory controller 5211 may be connected to system bus 5001. In one example embodiment, memory 5210 may include, as described above... Figures 1 to 26 The NVM devices described herein are NVM devices. Storage devices 5220 and 5340 can be controlled by storage controllers 5221 and 5341. Storage controllers 5221 and 5341 can be connected to system bus 5001 or expansion bus 5002. Storage devices 5220 and 5340 can be configured to store data. Storage controllers 5221 and 5341 can be configured to read data from the respective storage device 5220 or the respective storage device 5340 and send the read data to the host. Storage controllers 5221 and 5341 can be configured to store the data to be sent in the respective storage device 5220 or the respective storage device 5340 in response to a request from the host.

[0183] Storage devices can connect to a storage controller via SATA, SAS, SCSI, PCI, PCIe, AHCI, and NVMe interfaces. The storage controller can send commands via command pins, send addresses via address pins, and send and receive data via the DQ pin. In one example embodiment, the Din pin may be separate from the Dout pin. The storage controller provides a CLK signal via the CLK pin and can provide control signals for receiving other signals via corresponding pins (e.g., CS, CLE, ALE, WE, RE, and DQS). The storage device provides data to the storage controller via the DQ pin and can provide control signals for receiving signals via corresponding pins (e.g., DQS). A portion of the control signals may be strobe signals. A portion of the aforementioned pins may be combined. For example, the command pin and address pin may be combined into a CA pin.

[0184] Each of the storage device 5220 and the storage controller 5221 may include a buffer for storing metadata, mapping data, etc., or a read cache for storing frequently accessed data, or may include a write cache for improving write performance. For example, the write cache may store data for which write requests are frequently received, and may transmit the write request to the storage medium only after a write request is received on a unit-by-unit basis, rather than transmitting the request every time it is received. In other words, write requests on a bit-by-bit basis may be preferentially stored in the write cache, and the received write request may be transmitted to the storage medium when a write request on a unit-by-unit basis is received. For example, a unit-by-unit may be the same as an operating unit (e.g., a page unit) of flash memory. Therefore, a unit-by-unit may be a storage device-friendly unit.

[0185] In one example embodiment, Figure 28 One or more of the elements shown may include a buffer. The buffer may be volatile memory (such as SRAM, DRAM) or may be NVM (such as non-volatile random access memory (NVRAM), NAND flash, NOR flash, phase-change random access memory (PRAM), storage-class memory (SCM) or new memory).

[0186] Storage device 5220 may include volatile memory (such as hard disk drive (HDD)) and may include NVM (such as NVRAM, solid-state drive (SSD), SCM and new memory).

[0187] Figure 29 This is a diagram illustrating an example of a computing system 6000 according to another exemplary embodiment. (Refer to...) Figure 29The computing system 6000 may include a central processing unit (CPU) 6110, a graphics processing unit (GPU) 6120, a neural processing unit (NPU) 6130 or a dedicated processing unit connected to a system bus 6001; a memory device 6210 or a storage device 6220 connected to the system bus 6001; and an I / O device 6310, a modem 6320, a network device 6330 or a storage device 6340 connected to an expansion bus 6002. The expansion bus 6002 may be connected to the system bus 6001 via an expansion bus interface 6003.

[0188] Each of the CPU 6110, GPU 6120, and NPU 6130 may include on-chip caches 6111, 6121, and 6131, respectively. Off-chip caches (e.g., 6112, etc.) may be connected to the respective CPU 6110, GPU 6120, and NPU 6130, respectively. Each of the on-chip / off-chip caches 6111, 6121, 6131, and 6112 may include volatile memory (such as dynamic random access memory (DRAM), static random access memory (SRAM), etc.) or NVM (such as NAND flash memory, phase-change random access memory (PRAM), resistive random access memory (RRAM), etc.).

[0189] The first memories 6114, 6124 and 6134 can be connected to the CPU 6110, GPU 6120 and NPU 6130 via the corresponding memory controllers 6113, 6123 and 6133.

[0190] Secondary memories 6116, 6126, and 6136 can be connected to CPU 6110, GPU 6120, and NPU 6130 via bridges 6115, 6125, and 6135. Bridges 6115, 6125, and 6135 may include memory controllers for controlling the respective memories 6116, 6126, and 6136. Each of bridges 6115, 6125, and 6135 can be implemented as a network device, a wireless network device, a switch, a bus, a cloud, or an optical channel.

[0191] In one example embodiment, memories 6124 and 6126 may include GPU memory. In one example embodiment, memories 6124 and 6126 may include NPU memory. In one example embodiment, one or more of main memories 6114, 6116, 6124, 6126, 6134, 6136, and 6210 may be implemented to use as previously described. Figures 1 to 26The write operations (e.g., write methods) described in the example embodiments are performed. At least one of main memories 6114, 6116, 6124, 6126, 6134, 6136, and 6210 may include volatile memory (such as DRAM, SRAM, etc.) or NVM (such as NAND flash memory, PRAM, etc.). Memory 6210 may have a lower latency and capacity than storage device 6220.

[0192] The CPU 6110, GPU 6120, or NPU 6130 can access the auxiliary storage device 6220 via the system bus 6001.

[0193] Memory 6210 can be controlled by memory controller 6211. Memory controller 6211 can be connected to system bus 6001. Storage device 6220 can be controlled by memory controller 6221. Memory controller 6221 can be connected to system bus 6001.

[0194] Storage device 6220 can be configured to store data. Storage controller 6221 can be configured to read data from storage device 6220 and send the read data to a host. Storage controller 6221 can be configured to store the sent data in storage device 6220 in response to a request from the host. Each of the storage devices 6220 and storage controller 6221 may store metadata, may be read-cached to store frequently accessed data, or may include a write cache for improving write efficiency. For example, the write cache may receive a specific number of write requests and may process those requests. Storage device 6220 may include volatile memory (such as a hard disk drive (HDD)) and may include NVM (such as NVRAM, solid-state drive (SSD), SCM, new memory).

[0195] Figure 30 This is a diagram illustrating an example of a computing system 7000 according to another example embodiment. (Refer to...) Figure 30 The computing system 7000 may include a CPU 7100, a GPU / NPU 7200, a frame buffer 7410, a memory controller 7350, and a user interface 7500 connected to a system bus 7001. The system memory 7300 may be connected to the memory controller 7350, and the display 7430 may be connected to the frame buffer 7410 via a display interface 7420.

[0196] The CPU 7100 may include a DRAM controller 7110. The DRAM controller 7110 controls DRAM 7150. The GPU / NPU 7200 may include a DRAM controller 7210. The DRAM controller 7210 controls DRAM 7250.

[0197] The frame buffer 7410 can store at least one frame of data under the control of the GPU / NPU 7200, so as to output the same image data and still image data to the display 7430 through panel self-refresh (PSR) within a specific time period. In an example embodiment, the frame buffer 7410 may include volatile memory (such as dynamic random access memory (DRAM), static random access memory (SRAM), etc.) or NVM (such as NAND flash memory, phase change random access memory (PRAM), resistive random access memory (RRAM), etc.).

[0198] System memory 7300 can operate under the control of memory controller 7350. System memory 7300 may include functions that can be configured to perform the above-mentioned... Figures 1 to 26 The example embodiments described herein are NVM devices for write operations. The memory controller 7350 may receive a write request from the CPU 7100 or the GPU / NPU 7200. The system memory 7300 may perform a pre-fetch operation based on a write command from the memory controller 7350, comparing read data obtained as a result of the pre-fetch operation with write data, and determining whether to perform an overwrite operation based on the comparison result. Therefore, a write operation may be performed to apply a write pulse based on the read data and the write data, or the write operation may be completed without applying a write pulse.

[0199] According to the foregoing example embodiments, a particular NVM device and the write method (or execution of a write operation) performed by the NVM device can be used in various storage devices, thereby improving both data reliability and power consumption.

[0200] Although exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A non-volatile memory device, comprising: A memory cell array comprising multiple resistive memory cells connected to multiple bit lines and multiple word lines; A word line driver is configured to: in response to address selection of one of the plurality of word lines, apply a word line voltage to the selected word line; The bit line driver is configured to: in response to address selection of one of the plurality of bit lines, and apply a bit line voltage to the selected bit line; The write circuit is configured to generate bit line voltage and word line voltage in response to a write control signal; The read circuit is configured to read data from a resistive memory cell connected to a selected word line and a selected bit line in response to a read control signal; The input and output circuits are configured to receive written data from external devices; as well as The control logic is configured to: select a write mode from multiple write modes; generate a write control signal based on at least one of the selected write mode, write data, and read data; and generate a read control signal based on at least one of the selected write mode and write data. Wherein, at least one of the plurality of write modes defines a write operation that performs a read operation. When a read operation is performed, a bit line voltage with a second read level is applied to the selected bit line, and The second read level is higher than the first read level used for read operations performed in normal mode.

2. The non-volatile memory device according to claim 1, wherein, The memory cell array comprises multiple layers of memory cells stacked vertically in a direction perpendicular to the substrate.

3. The non-volatile memory device according to claim 2, wherein, At least one write mode is selected from the plurality of write modes based on the location of at least one memory cell layer among the plurality of memory cell layers.

4. The non-volatile memory device according to any one of claims 1 to 3, wherein, Select at least one of the plurality of write modes based on the address.

5. The non-volatile memory device according to any one of claims 1 to 3, wherein, The control logic includes: The write latch is configured to store the written data; and The read latch is configured to store read data.

6. The non-volatile memory device according to any one of claims 1 to 3, wherein, The multiple write modes include: normal mode, data comparison write DCW mode, active data comparison write aDCW mode, and read skip active data comparison write RDSKIP aDCW mode. Specifically, for write operations performed in aDCW mode, the read data obtained from the resistive memory cell using sensing operations is compared with the write data, and a set or reset operation is performed using the comparison result and the write data. For write operations performed in RDSKIP aDCW mode, when the data being written is set data, a set operation is performed instead of a sensing operation.

7. The non-volatile memory device according to claim 6, wherein, When the data to be written and the data to be read are the same, DCW mode does not perform a write operation.

8. The non-volatile memory device according to claim 6, wherein, When both the data being written and the data being read are reset data, the aDCW mode does not perform a write operation.

9. The non-volatile memory device according to claim 6, wherein, When both the data being written and the data being read are reset data, RDSKIP aDCW mode does not perform a write operation, and Specifically, when the written data is set data, the RDSKIP aDCW mode does not perform sensing operations.

10. The non-volatile memory device according to claim 6, wherein, The control logic includes an event activation signal generator, which includes: The first logic circuit is configured to perform an XOR operation on the written data and the read data; The second logic circuit is configured to perform an AND operation on the output of the first logic circuit and the DCW mode activation signal; The third logic circuit is configured to perform a bitwise AND operation on the read data and the aDCW mode activation signal; The fourth logic circuit is configured to perform a NOR operation on the DCW mode activation signal, the aDCW mode activation signal, and the RDSKIP aDCW mode activation signal; and The fifth logic circuit is configured to generate an event activation signal by performing an OR operation on the outputs of the second logic circuit, the third logic circuit, and the fourth logic circuit.

11. The non-volatile memory device according to claim 10, wherein, The control logic also includes a write control signal generator, which includes: The sixth logic circuit is configured to perform a bitwise AND operation on the event activation signal and the write activation signal; The seventh logic circuit is configured to invert the written data; The eighth logic circuit is configured to generate a set activation signal by performing a bitwise AND operation on the written data and the output of the sixth logic circuit; and The ninth logic circuit is configured to generate a reset activation signal by performing a bitwise AND operation on the outputs of the sixth and seventh logic circuits.

12. The non-volatile memory device according to claim 11, wherein, The control logic also includes a read control signal generator, which includes: The tenth logic circuit is configured to generate a read skip activation signal by performing a bitwise AND operation on the RDSKIP aDCW mode activation signal and the written data.

13. The non-volatile memory device according to any one of claims 1 to 3, wherein, The control logic is also configured to control the execution of a read operation, during which a read voltage is applied to the selected bit line, and The read circuitry includes a sense amplifier configured to compare the voltage of the selected word line with a reference voltage.

14. A method for writing to a non-volatile memory device, the method comprising: Perform sensing operations; Compare the written data with the read data obtained through sensing operations; When the written data is the same as the read data, determine whether the written data is a set data; When the data to be written is set data, the set operation is performed; when the data to be written is not set data, the write operation is not performed.

15. The writing method according to claim 14, wherein, The read operation performed according to normal mode uses a read voltage with a first read level. The sensing operation is performed using a read voltage with a second read voltage greater than the first read voltage level, and The steps of performing the sensing operation also include: applying a read voltage to a selected bit line and applying a read word line voltage to a selected word line.

16. The writing method according to claim 14 or 15, wherein, The steps for performing a set operation include: applying a set bit line voltage to the selected bit line and applying a write word line voltage to the selected word line.

17. The writing method according to claim 14 or 15, further comprising: When the written data is different from the read data, determine whether the written data is reset data; When the data written is reset data, a reset operation is performed; as well as When the data written is not reset data, a set operation is performed.

18. The writing method according to claim 17, wherein, The steps of performing the reset operation also include: applying a reset bit line voltage to the selected bit line and applying a write word line voltage to the selected word line.

19. A method for writing to a non-volatile memory device, the method comprising: Receive and write data; Determine if the written data corresponds to the set state; When the written data corresponds to the set state, the set operation is performed; When the written data does not correspond to the set state, a sensing operation is performed; and when the read data obtained through the sensing operation corresponds to the reset state, no write operation is performed. as well as A reset operation is performed when the read data does not correspond to the reset state.

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