Memory and method of forming the same

Abstract

A memory and a forming method thereof, the forming method comprising: providing a substrate; forming a first mask layer on a surface of the substrate, a plurality of strip-shaped patterns being formed in the first mask layer; forming a second mask layer on the first mask layer, a plurality of first patterns and a plurality of second patterns being formed in the second mask layer, the plurality of first patterns being arrayed and overlapping the strip-shaped patterns, the plurality of second patterns covering end portions of the strip-shaped patterns; and etching layer by layer to the substrate with the first mask layer and the second mask layer as masks, so as to transfer the strip-shaped patterns, the first patterns and the second patterns into the substrate, and form a plurality of discrete active regions arrayed and a split groove corresponding to the first patterns and the second patterns. The memory formed by the method has improved reliability.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and more particularly to a memory and a method for forming the same. Background Technology

[0002] The memory comprises multiple arrayed memory cells, each formed on an active region (AA). In the fabrication process of existing memory technologies, the substrate is typically etched to form the arrayed active regions.

[0003] As memory storage capacity and density increase, the linewidth of active regions gradually shrinks. When forming multiple arrayed mask patterns on the substrate surface as masks for active regions, a double patterning process (SADP) is required to form AA masks with smaller linewidth patterns to form elongated AA regions; then, an STI mask is formed on the AA mask to cut the elongated AA regions, thus forming an array of active regions.

[0004] When forming the active region of a memory array using the SADP process, the active region is very small due to the small size of the AA mask. This can lead to problems such as collapse and stress at the edges of the active region array, affecting the product yield.

[0005] Improving the edge problem of active area arrays in memory is an urgent issue that needs to be addressed. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a memory and a method for forming the same, which can improve the edge problem of the active region array of the memory.

[0007] To address the aforementioned problems, the present invention provides a method for forming a memory, comprising: providing a substrate, the substrate including an array region; forming a first mask layer on the surface of the substrate, the first mask layer having a plurality of parallel-arranged elongated strip-shaped patterns formed therein, for forming a plurality of parallel-arranged elongated continuous active regions in the array region of the substrate; forming a second mask layer on the first mask layer, the second mask layer having a plurality of first patterns and a plurality of second patterns formed therein, the plurality of first patterns being arrayed and overlapping the elongated strip-shaped patterns, for forming a memory within the substrate. The continuous active region is divided into several independent arrayed discrete active regions by cutting trenches. The several second patterns cover the ends of the elongated patterns and are used to remove the secondary active regions located at the ends of the continuous active regions after being divided by the first pattern, which are smaller than the length of the discrete active regions. Using the first mask layer and the second mask layer as masks, the substrate is etched layer by layer to transfer the elongated patterns, the first patterns and the second patterns into the substrate, forming several discrete active regions arranged in an array, and dividing trenches corresponding to the first patterns and the second patterns.

[0008] Optionally, the elongated graphic is formed using a dual graphicization method.

[0009] Optionally, the plurality of first graphics include a central first graphic and a peripheral first graphic, wherein the peripheral first graphic is the outermost first graphic, the central first graphic is located inside the peripheral first graphic, and the peripheral first graphic extends outward along the length direction of the elongated graphic, such that the size of the peripheral first graphic is larger than the size of the central first graphic.

[0010] Optionally, the outermost segmentation groove may be larger than the segmentation grooves at other locations.

[0011] Optionally, the substrate further includes a peripheral region surrounding the array region, and a third pattern is formed within the second mask layer, located on the peripheral region of the substrate and surrounding all the elongated patterns, the third pattern being used to form a peripheral trench surrounding the array region within the peripheral region of the substrate.

[0012] Optionally, the sidewall of the peripheral groove facing the array region is curved.

[0013] Optionally, it also includes filling the dividing trench and the peripheral trench with insulating material to form a shallow trench isolation structure.

[0014] The present invention also provides a memory, comprising: a substrate, the substrate including an array region; a plurality of discrete active regions formed in an array within the array region; each discrete active region being isolated from the others by a shallow trench isolation structure, wherein at least a portion of the outermost shallow trench isolation structure has a dimension in the length direction of the discrete active region that is larger than the dimension of the shallow trench isolation structures at other locations in the length direction of the discrete active region.

[0015] Optionally, the substrate further includes a peripheral region surrounding the array region, and a peripheral shallow trench isolation structure is formed in the peripheral region of the substrate, the peripheral shallow trench isolation structure being disposed around the array region.

[0016] Optionally, the discrete active region and the peripheral region are isolated by a shallow trench isolation structure.

[0017] Optionally, the sidewall of the peripheral shallow trench isolation structure facing the array region is curved.

[0018] Optionally, the peripheral shallow trench isolation structure has a certain distance between it and the array region.

[0019] Optionally, in the shallow trench isolation structure, the outermost shallow trench isolation structure has a larger size than the shallow trench isolation structures at other locations.

[0020] The memory formation method of the present invention removes the smaller secondary active regions at the edges of the formed discrete active region array during the process of dividing the continuous active regions. Therefore, it can avoid problems such as collapse caused by the presence of smaller secondary active regions at the edges of the active region array, and improve the reliability of the memory.

[0021] Furthermore, the shallow trench isolation structure located on the periphery for dividing the continuous active area is larger in size, which can avoid the etching load effect during the etching process to form the trench, thereby reducing the photolithography etching process window, improving the pattern accuracy of the formed shallow trench isolation structure, and further improving the performance of the memory. Attached Figure Description

[0022] Figures 1 to 8 This is a schematic diagram illustrating the formation process of the memory according to a specific embodiment of the present invention. Detailed Implementation

[0023] The specific embodiments of the memory and its formation method provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0024] Please refer to Figure 1 This is a schematic diagram of the formation process of a memory according to a specific embodiment of the present invention.

[0025] Please refer to Figure 1 A substrate 100 is provided, the substrate 100 including an array region 101 and a peripheral region 102 surrounding the array region 101.

[0026] The array region 101 is used to form an active area array for the memory, while the peripheral region 102 is used to form peripheral devices for the memory, such as logic control circuits.

[0027] Please refer to Figure 2a and Figure 2b A first mask layer 200 is formed on the surface of the substrate 100. Within the first mask layer 200, a plurality of parallel elongated strip-shaped patterns 201 are formed, including elongated strip-shaped patterns 201a and 201b. The elongated strip-shaped patterns 201 are masking patterns used to form a plurality of discrete and parallel elongated continuous active regions within the array region 101 of the substrate 100. Openings 202 are provided between the elongated strip-shaped patterns 201 to separate them. Figure 2a This is a top-down view. Figure 2b along Figure 2a A cross-sectional view of the secant line AA'. Before forming the first mask layer 200, a buffer layer, a hard mask layer, etc., may also be formed on the surface of the substrate 100 to improve the accuracy of pattern transfer during subsequent etching processes.

[0028] The elongated graphic is formed using a dual graphicization method. For details, please refer to [link / reference needed]. Figures 3a to 3f This is a schematic diagram of the structure of a method for forming the first mask layer according to a specific embodiment of the present invention.

[0029] Please refer to Figure 3a and 3b A mask pattern 301 is formed on the surface of the substrate 100. Figure 3a This is a top view of mask pattern 301. Figure 3b along Figure 3a A cross-sectional view of the secant line BB'. The mask pattern 301 has elongated strip-shaped patterns arranged in parallel. In this specific embodiment, the mask pattern 301 is arranged at an angle to increase the arrangement density of the subsequently formed discrete active regions. In other specific embodiments, the mask pattern 301 may also be arranged horizontally or vertically.

[0030] Please refer to Figure 3c and Figure 3d A sidewall 302 is formed on the sidewall of the mask pattern 301, and the sidewall 302 surrounds the sidewall of the mask pattern 301.

[0031] Please refer to Figure 3eA first mask material 310 is formed by filling the surface of the substrate 100, and the surface of the first mask material 310 is flush with the surface of the mask pattern 301.

[0032] Please refer to Figure 3f The sidewall 302 is removed to form an opening 303 (corresponding to opening 202 in Figure 2). The mask patterns 301 (corresponding to elongated patterns 201a and 202b in Figure 2) on both sides of the opening serve as elongated patterns to define the width and length of the continuous active regions subsequently formed in the substrate. This dual patterning method reduces the spacing between adjacent elongated patterns and increases the density of the elongated patterns.

[0033] Please refer to Figure 4a and Figure 4b A second mask layer 400 is formed on the first mask layer 200. A plurality of first patterns 401 and a plurality of second patterns 402 are formed in the second mask layer 400. The plurality of first patterns 401 are arranged in an array and overlap with the elongated patterns 201a and 201b to form a dividing trench in the substrate 100, dividing the continuous active region into a plurality of independent arrayed discrete active regions. The plurality of second patterns 402 cover part of the end of the elongated pattern 201a to remove the secondary active regions located at the end of part of the continuous active region after being divided by the first patterns 401, which are smaller than the length of the discrete active region.

[0034] Figure 4a The image shows only the first pattern 401 and the second pattern 402 within the second mask layer 400. Both the first pattern 401 and the second pattern 402 are open patterns, while other areas are masked patterns (not shown in the image). Figure 4b For along Figure 4a A cross-sectional view of the secant AA'.

[0035] Before forming the second mask layer 400, a filler layer 410 with a flat surface that fills the openings 202 within the first mask layer 200 is formed, and the second mask layer 400 is formed on the surface of the flat filler layer 410. The filler layer 410 can be made of an organic anti-reflective layer, silicon oxide, or the like.

[0036] Since the first pattern 401 is an open pattern, and the elongated patterns 201a and 201b are masking patterns, after etching the substrate 100 along the first pattern 401, it is used to cut off the continuous active regions formed in the substrate 100 corresponding to the elongated patterns 201a and 201b, forming a dividing trench.

[0037] To increase storage density, the first pattern 401 is arranged in an interleaved manner, resulting in an interleaved arrangement of discrete active regions after segmentation, thereby increasing the number of discrete active regions. This leads to a situation where, after some continuous active regions are segmented, the length of the active region at the end is shorter than the length of a normal discrete active region, and these are called secondary active regions. These secondary active regions cannot form complete storage cells and are also prone to collapse. The formation location of these secondary active regions typically corresponds to the end of the elongated pattern 201a surrounded by the opening 202.

[0038] In this specific embodiment, a second pattern 402 is also formed in the second mask layer 400. The second pattern 402 is also an open pattern, covering the position of the end of the elongated pattern 201 corresponding to the secondary active region, which is used to remove the secondary active region, thereby avoiding the possible collapse problem of the secondary active region, and thus improving the edge problem of the active region array.

[0039] In this specific embodiment, the elongated pattern 201b located outside the opening 202 is connected to the first mask layer on the peripheral region of the substrate 100 at its end. Therefore, the end of the continuous active region formed in the substrate 100 is connected to the peripheral region of the substrate, and even if its size is smaller than the size of the discrete active region, it usually will not collapse or other problems. Therefore, the second pattern 402 is usually formed above the end of the elongated pattern 201 that is partially surrounded by the opening 202.

[0040] In other specific embodiments, a pattern between the outer regions of the cut strip-shaped pattern 201b may also be formed in the second mask layer 400. This would cause a secondary active region to appear at the end of the continuous active region 201b after it is divided. Accordingly, the second pattern 402 also needs to be formed on the end of part of the strip-shaped pattern 201b.

[0041] In this specific embodiment, a third pattern 403 is also formed within the second mask layer 400, located above the peripheral region 102 and surrounding all the source line patterns 201a and 201b. The third pattern 403 is used to form a peripheral trench surrounding the array region 101 within the peripheral region 102 of the substrate 100. The third pattern 403 is also an open pattern.

[0042] Please refer to Figure 5Using the first mask layer 400 and the second mask layer 200 as masks, the substrate 100 is etched layer by layer to transfer the elongated patterns 201a and 201b, the first pattern 401 and the second pattern 402 into the substrate 100, forming a plurality of discrete active regions 501 arranged in an array. Adjacent discrete active regions on the same straight line and adjacent discrete active regions on different straight lines are separated by dividing trenches. The dividing trenches are filled with insulating material to form a shallow trench isolation structure.

[0043] Wherein, the first shape 401 corresponds to the shallow trench isolation structure 512, the second shape 402 corresponds to the shallow trench isolation structure 513, and the opening 202 corresponds to the shallow trench isolation structure 511.

[0044] Simultaneously, a peripheral shallow trench isolation structure 514 is formed in the peripheral region of the substrate 100, corresponding to the third pattern 403 (see reference). Figure 4a ).

[0045] In another specific embodiment, the third pattern 403 is curved on the side facing the array region, so that the formed peripheral shallow trench isolation structure 601 (see reference) Figure 6 The sidewalls facing the array area are curved, which can increase the total length of the sidewalls, improve stability, further alleviate the stress generated by the peripheral shallow trench isolation structure 514, and reduce the stress impact on the discrete active regions 501 located at the edge.

[0046] Please refer to Figure 7 This is a schematic diagram after the second mask layer 200 is formed, as shown in another specific embodiment of the present invention.

[0047] The first pattern within the second mask layer includes a central first pattern 401a and a peripheral first pattern 401b. The peripheral first pattern 401b is the outermost first pattern, and the central first pattern 401a is located inside the peripheral first pattern 401b. The peripheral first pattern 401b extends outward along the length of the elongated pattern 201a and the elongated pattern 201b, making the size of the peripheral first pattern 401b larger than the size of the central first pattern 401a. Because the pattern density on the outer side of the peripheral first pattern is lower, the etching load effect caused by the different pattern density during etching can easily lead to distortion in the transmission of the outermost first pattern. Therefore, in this specific embodiment, making the size of the peripheral first pattern 401b larger than the size of the inner central first pattern 401a can overcome the etching load effect, increase the photolithography etching window, and improve the accuracy of pattern transmission.

[0048] exist Figure 7In the specific embodiment shown, the outermost pattern 401a and the second pattern 402 correspond to the outermost segmentation trench formed in the substrate array region, and the size of the outermost segmentation trench is larger than the size of the segmentation channels at other locations.

[0049] In other specific embodiments, the second mask layer 200 may not form the second pattern 402, but only includes the central first pattern 401a and the peripheral first pattern 401b, so as to form a segmentation trench that divides the continuous active region.

[0050] In the above specific embodiments, after forming multiple mask layers with different patterns, the substrate is etched to directly form an active region array within the substrate.

[0051] In a specific embodiment of the present invention, another method for forming a memory is also provided.

[0052] The method includes the following steps: providing a substrate, the substrate including an array region and a peripheral region surrounding the array region; forming a plurality of discrete and parallel elongated continuous active regions within the array region of the substrate; forming arrayed dividing trenches within the array region of the substrate to divide the continuous active region into a plurality of discrete active regions arranged in an array; wherein, while dividing each of the continuous active regions, a secondary active region smaller than the length of the discrete active region at the rear end of a portion of the continuous active region is removed.

[0053] It can be achieved by forming, for example, on the surface of the substrate Figure 2a The first mask layer 200, which has elongated patterns 201a and 201b, is shown. Using the first mask layer 200 as a mask, the substrate is etched to form an elongated continuous active region within the substrate.

[0054] Then, after removing the first mask layer 200, a layer such as... is formed on the substrate. Figure 4a and Figure 4b The second mask layer 400 shown has a first pattern 401 and a second pattern 402. The substrate is etched using the second mask layer 400 as a mask. By transferring the first pattern 401 and the second pattern 402 into the substrate, the continuous active region in the substrate is divided into a plurality of discrete active regions. Since the second pattern 402 is formed in the second mask layer 400, while dividing each of the continuous active regions, a secondary active region smaller than the length of the discrete active region at the rear end of the divided continuous active region is removed.

[0055] In other specific embodiments, after forming a continuous active region within the substrate, a structure such as... can also be formed on the substrate. Figure 7The second mask layer shown has a first pattern including a peripheral first pattern 401b and a central first pattern 401a. The size of the peripheral first pattern 401b is larger than the size of the central first pattern 401a, such that the size of the outermost dividing trench formed in the substrate is larger than the size of the dividing trench at other locations.

[0056] A third pattern may also be formed within the second mask layer 200. Simultaneously with forming the segmentation trenches, the peripheral region of the substrate is etched to form peripheral trenches surrounding the array region within the peripheral region. The sidewalls of the peripheral trenches facing the array region may be curved to reduce stress effects and improve stability.

[0057] Finally, insulating material is filled into the dividing trench and the outer trench to form a shallow trench isolation structure.

[0058] In the memory formation process of this specific embodiment, the substrate is etched once for each mask layer formed. By etching the substrate multiple times, a discrete active region array is formed.

[0059] A specific embodiment of the present invention also provides a memory formed using the above-described specific embodiments.

[0060] Please refer to Figure 5 This is a schematic diagram of the structure of a memory according to a specific embodiment of the present invention.

[0061] The memory includes a substrate 100, which includes an array region 101 and a peripheral region 102 surrounding the array region 101. A plurality of discrete active regions 501 are formed within the array region 102 and arranged in an array. Each discrete active region 501 is isolated from the others by shallow trench isolation structures 512, 513, and 511. The shallow trench isolation structures 512 and 513 divide the continuous active region into separate discrete active regions 501, and the trenches are formed using the same etching process. The shallow trench isolation structure 511 isolates different continuous active regions.

[0062] A shallow trench isolation structure 514 is formed in the peripheral region 102 of the substrate 100, and the shallow trench isolation structure 514 is disposed around the array region 101. The shallow trench isolation structure 514 and the array region 101 have a certain distance between them, serving as an electrical isolation structure between the array region 101 of the substrate and the peripheral region 102.

[0063] In another specific embodiment, the peripheral shallow trench isolation structure 601 (please refer to) Figure 6The sidewall facing the array region 101 is curved to reduce stress on the discrete active region 501 located at the edge and to improve stability.

[0064] The shallow trench isolation structure 513 at the ends of some of the outermost discrete active regions 501 is larger than the size of shallow trench isolation structures at other locations. The discrete active regions 501 are formed by dividing continuous active regions. At the ends of some continuous active regions, secondary active regions with smaller dimensions than the discrete active regions are generated, making them prone to collapse. The shallow trench isolation structure 513 is formed at the locations of these secondary active regions, removing them and thus improving the problem of collapse of discrete active regions located at the edges of the active region array.

[0065] Please refer to Figure 8 In this specific embodiment, a shallow trench isolation structure 810 is formed at the end of the peripheral discrete active area after the continuous active area without secondary active area is divided. The size of the shallow trench isolation structure 810 is larger than the size of the shallow trench isolation structure 512 located in the display area 102. This can overcome the etching load effect caused by different pattern densities, improve the photolithography etching window for forming the shallow trench isolation structure 512, the shallow trench isolation structure 810, and the shallow trench isolation structure 513, and improve the accuracy of the size of the discrete active area 501.

[0066] Figure 8 In the middle, the dimensions of the shallow trench isolation structure 513 and shallow trench isolation structure 810 located on the periphery are larger than the dimensions of the shallow trench isolation structure 512 located at other positions.

[0067] In the aforementioned memory, the smaller secondary active regions at the edges of the discrete active region array are removed. Therefore, problems such as collapse caused by the presence of smaller secondary active regions at the edges of the discrete active region array can be avoided, thus improving the reliability of the memory.

[0068] Furthermore, the shallow trench isolation structure located on the periphery, which is used to divide the continuous active area, is larger in size. This can avoid the etching load effect during the etching process to form the trench, thereby reducing the photolithography etching process window, improving the pattern accuracy of the formed shallow trench isolation structure, and further improving the performance of the memory.

[0069] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for forming a memory, characterized in that, include: A substrate is provided, the substrate including an array region; A first mask layer is formed on the surface of the substrate, and a plurality of parallel elongated patterns are formed in the first mask layer for forming a plurality of parallel elongated continuous active regions in the array region of the substrate. A second mask layer is formed on the first mask layer. A plurality of first patterns and a plurality of second patterns are formed in the second mask layer. The plurality of first patterns are arranged in an array and overlap with the elongated pattern to form a dividing trench in the substrate, dividing the continuous active region into a plurality of independent arrayed discrete active regions. The plurality of first patterns include a central first pattern and a peripheral first pattern. The peripheral first pattern is the outermost first pattern. The central first pattern is located inside the peripheral first pattern. The peripheral first pattern extends outward along the length direction of the elongated pattern, such that the size of the peripheral first pattern is larger than the size of the central first pattern. The plurality of second patterns cover part of the end of the elongated pattern to remove the secondary active regions located at the end of part of the continuous active region after being divided by the first pattern, which are smaller than the length of the discrete active region. Using the first and second mask layers as masks, the substrate is etched layer by layer to transfer the elongated pattern, the first pattern, and the second pattern into the substrate, forming a plurality of discrete active regions arranged in an array.

2. The forming method according to claim 1, characterized in that, The elongated graphic is formed using a dual graphicization method.

3. The forming method according to claim 1, characterized in that, The outermost dividing groove is larger than the dividing grooves at other locations.

4. The forming method according to claim 3, characterized in that, The substrate further includes a peripheral region surrounding the array region, and a third pattern is formed in the second mask layer, located on the peripheral region of the substrate and surrounding all the elongated patterns. The third pattern is used to form a peripheral trench surrounding the array region in the peripheral region of the substrate.

5. The forming method according to claim 4, characterized in that, The sidewall of the outer groove facing the array region is curved.

6. The forming method according to claim 4, characterized in that, Also includes: Insulating material is filled into the dividing trench and the outer trench to form a shallow trench isolation structure.

7. A memory, characterized in that, include: Substrate, the substrate including an array region; The array region contains several discrete active regions arranged in an array, and the discrete active regions are arranged alternately. Each discrete active region is isolated by a shallow trench isolation structure, wherein at least some of the outermost shallow trench isolation structures have a larger dimension in the length direction of the discrete active region than the shallow trench isolation structures at other locations in the length direction of the discrete active region.

8. The memory according to claim 7, characterized in that, The substrate also includes a peripheral region surrounding the array region, and a peripheral shallow trench isolation structure is formed in the peripheral region, the peripheral shallow trench isolation structure being disposed around the array region.

9. The memory according to claim 8, characterized in that, The separate active area is isolated from the peripheral area by a shallow trench isolation structure.

10. The memory according to claim 8, characterized in that, The sidewall of the peripheral shallow trench isolation structure facing the array region is curved.

11. The memory according to claim 8, characterized in that, There is a gap between the peripheral shallow trench isolation structure and the array region.

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