Semiconductor package and related methods

Abstract

The present invention relates to semiconductor packages and related methods. Embodiments disclose a method for forming a semiconductor package, the method including providing a first insulator layer coupled with a first metal layer. A recess is formed in the first metal layer, and a semiconductor die is mechanically coupled therein. The die is mechanically coupled with a second metal layer, and the second metal layer is coupled with a second insulator layer. The die and the layers are at least partially encapsulated to form the semiconductor package. The first metal layer and / or the second metal layer can be an insulator-metal substrate, a metal-insulator-metal (MIM) substrate, or can be formed from a leadframe. In embodiments, the package does not include a spacer between the die and the first metal layer, and does not include a spacer between the die and the second metal layer. In embodiments, the first insulator layer and the second insulator layer are exposed by an encapsulant, or are mechanically coupled with a metal layer exposed by the encapsulant.

Description

TECHNICAL FIELD

[0001] Aspects of the present document relate generally to semiconductor packages. More particular implementations relate to substrates for forming semiconductor packages. BACKGROUND

[0002] Semiconductor packages can be used to electrically interconnect electrical contacts of a die with electrical leads that electrically couple the semiconductor package with a printed circuit board (PCB). Various semiconductor packages can be attached to a heat spreader to draw heat away from a semiconductor die. SUMMARY

[0003] Implementations of a method of forming a semiconductor package can include providing a first insulator layer coupled with a first metal layer; forming a recess in the first metal layer; mechanically coupling a semiconductor die at least partially within the recess, a perimeter of the semiconductor die being entirely within a perimeter of the recess; mechanically coupling the semiconductor die with a second metal layer, the second metal layer being coupled with a second insulator layer; and at least partially sealing the first insulator layer, the first metal layer, the semiconductor die, the second insulator layer, and the second metal layer in a sealant to form a semiconductor package.

[0004] Implementations of a method of forming a semiconductor package can include one, all, or any of:

[0005] The semiconductor package can not include a spacer between the semiconductor die and the first metal layer, and the semiconductor package can not include a spacer between the semiconductor die and the second metal layer.

[0006] A leadframe can form the first metal layer.

[0007] A leadframe can form the second metal layer.

[0008] The first insulator layer and the second insulator layer can be exposed by the sealant.

[0009] Embodiments of a method of forming a semiconductor package can include providing a first metal-insulator-metal (MIM) substrate having a first metal layer and a second metal layer coupled on opposite sides of a first insulator layer, forming a recess in the first metal layer, mechanically coupling a semiconductor die at least partially within the recess, a perimeter of the semiconductor die being entirely within a perimeter of the recess, mechanically coupling the semiconductor die with a third metal layer of a second MIM substrate, the second MIM substrate including the third metal layer and a fourth metal layer on opposite sides of a second insulator layer, and at least partially sealing the first MIM substrate, the semiconductor die, and the second MIM substrate in a sealant to form a semiconductor package.

[0010] Embodiments of a semiconductor package can include one, all, or any of:

[0011] The semiconductor package can not include a spacer between the semiconductor die and the first metal layer, and the semiconductor package can not include a spacer between the semiconductor die and the third metal layer.

[0012] The first metal layer can include two metal segments that are electrically isolated from each other prior to coupling the semiconductor die with the first metal layer.

[0013] The second metal layer and / or the fourth metal layer can include a slot configured to reduce warpage of the semiconductor package.

[0014] Embodiments of a semiconductor package can include a first insulator layer coupled with at least a first metal layer, the first metal layer including a recess therein, a semiconductor die mechanically coupled at least partially within the recess, a perimeter of the semiconductor die being entirely within a perimeter of the recess, at least a second metal layer coupled with a second insulator layer, the second metal layer mechanically coupled with the semiconductor die, and a sealant at least partially sealing the first insulator layer, the first metal layer, the semiconductor die, the second insulator layer, and the second metal layer.

[0015] Embodiments of a semiconductor package can include one, all, or any of:

[0016] The semiconductor die can be mechanically coupled within the recess using one of a solder metal and / or a sintered metal, and the semiconductor die can be mechanically coupled with the second metal layer using a solder metal and / or a sintered metal.

[0017] The semiconductor package can not include a spacer between the semiconductor die and the first metal layer, and the semiconductor package can not include a spacer between the semiconductor die and the second metal layer.

[0018] The leadframe can form the first metal layer.

[0019] The leadframe can be mechanically attached to the first insulator layer using a silicone elastomer.

[0020] The leadframe can form the second metal layer.

[0021] The first insulator layer and the second insulator layer can be exposed by an encapsulant.

[0022] The first insulator layer and the first metal layer can be components of a first metal- insulator-metal substrate, the first MIM substrate including the first metal layer and a third metal layer, the first metal layer and the third metal layer coupled on opposite sides of the first insulator layer.

[0023] The second insulator layer and the second metal layer can be components of a second metal- insulator-metal substrate, the second MIM substrate including the second metal layer and a fourth metal layer, the second metal layer and the fourth metal layer coupled on opposite sides of the second insulator layer.

[0024] The first metal layer can include two metal segments that are electrically isolated from each other prior to coupling the semiconductor die with the first metal layer.

[0025] The second metal layer and / or the fourth metal layer can include a slot configured to reduce warpage of the semiconductor package.

[0026] The above described as well as other aspects, features, and advantages will become apparent to those of ordinary skill in the art through review of the following description in conjunction with the accompanying drawings and claims. BRIEF DESCRIPTION OF DRAWINGS

[0027] Implementations will be described below with reference to the attached drawings, in which like elements are labeled similarly and in which:

[0028] Figure 1 is a cross-sectional view of an implementation of a semiconductor assembly;

[0029] Figure 2 is a cross-sectional view of an implementation of a semiconductor package;

[0030] Figure 3 is a top view of an implementation of a semiconductor package of a semiconductor assembly including Figure 1

[0031] ​Figure 4 is a side view of a semiconductor package; Figure 3

[0032] Figure 5 is a top perspective view of another embodiment of a semiconductor package;

[0033] Figure 6 is a top perspective view of another embodiment of a semiconductor package;

[0034] Figure 7 is a top perspective view of another embodiment of a semiconductor package;

[0035] Figure 8 is a cross-sectional view of a semiconductor package; Figure 5

[0036] Figure 9 is a cross-sectional view of a semiconductor package; Figure 6

[0037] Figure 10 is a cross-sectional view of a semiconductor package; Figure 7

[0038] Figure 11 is a cross-sectional view of another embodiment of a semiconductor package;

[0039] Figure 12 is a cross-sectional view of another embodiment of a semiconductor package;

[0040] Figure 13 is a cross-sectional view of another embodiment of a semiconductor package;

[0041] Figure 14 is a cross-sectional view of another embodiment of a semiconductor package;

[0042] Figure 15 is a top view of an embodiment of a substrate configuration for forming a semiconductor package; and

[0043] Figure 16 is a top view of another embodiment of a substrate configuration for forming a semiconductor package. DETAILED DESCRIPTION

[0044] ​​​​This disclosure, its aspects, and embodiments are not limited to the specific components, assembly processes, or method elements disclosed herein. Numerous additional components, assembly processes, and / or method elements known in the art for the intended operation and methods of semiconductor packages and related methods will be readily apparent for use with specific embodiments of this disclosure. Therefore, for example, although specific embodiments are disclosed, such embodiments and implementing components may include any shape, size, style, type, model, version, measurement result, concentration, material, quantity, method element, step, etc., of such structures and methods for semiconductor packages and related methods known in the art for the intended operation and methods.

[0045] Now see that the component dimensions and thicknesses are not necessarily drawn to scale (as with other appendices). Figure 1 (like) Figure 1 This illustrates an implementation of semiconductor component (component) 2. Figure 1 In this embodiment, component 2 is shown without a sealant to focus on the other elements of the component, but the component can be sealed to form a semiconductor package. Component 2 includes a top metal layer 4, which in the illustrated embodiment is a 200 μm (or about 200 μm) copper layer. Layer 4 is coupled to an insulating layer 6, which in the illustrated embodiment is a 320 μm (or about 320 μm) Al2O3 layer. Layer 6 is coupled to a metal layer 8, which in the illustrated embodiment is a 400 μm (or about 400 μm) copper layer. In the illustrated embodiment, layers 4, 6, and 8 are all contained within a first direct copper-clad (DBC) substrate.

[0046] The first DBC substrate is coupled to a first solder layer (layer 10), which in this embodiment is a 200 μm (or approximately 200 μm) solder layer. In some embodiments, the solder may be SAC305 lead-free solder or other conductive attachment materials. Layer 10 is coupled to a spacer 12, which in the illustrated embodiment is a 1.93 mm (or approximately 1.93 mm) conductive material layer, such as CuMo. 70A layer or Cu layer. A spacer is coupled to a second solder layer (layer) 14, which in the illustrated embodiment is a 200 μm (or approximately 200 μm) PbSn8Ag2 solder layer or other conductive attachment material layer. Layer 14 is coupled to a semiconductor die (die) 16, which in the illustrated embodiment is an insulated-gate bipolar transistor (IGBT) or MOSFET. The IGBT or MOSFET has one or more polyimide (PI) layers (layers) 18 having portions that are selectively removed to apply solder top metal / solderable top metal (STM) 20, and is subsequently coupled to a third solder or conductive material layer (layer) 22 (which in the illustrated embodiment includes two separate solder regions) to couple the IGBT to the second substrate. In the illustrated embodiment, layer 22 is a 200 μm (or approximately 200 μm) SnSb5 solder layer or other solder layer or other conductive material layer.

[0047] The second substrate includes a metal layer 26, which in the illustrated embodiment is a 400 μm (or about 400 μm) copper layer or other metal layer (and includes two or more separate portions forming the layer). Layer 26 is coupled to an insulating layer 28, which in the illustrated embodiment is a 320 μm (or about 320 μm) Al2O3 layer or other ceramic material layer. Layer 28 is coupled to a layer 30, which in the illustrated embodiment is a 200 μm (or about 200 μm) copper layer or other metal layer. In the illustrated embodiment, layers 26, 28, and 30 form the second DBC substrate. A photoimageable solder resist (PSR) layer 24 is coupled to the second DBC substrate, and portions thereof are selectively removed before layer 26 is mechanically coupled to an IGBT or MOSFET using solder layer 22. In addition to mechanical coupling, the IGBT can also be electrically coupled to layer 8 via layer 26 and / or via spacers to be electrically coupled to the leads of the package.

[0048] As used herein, the term "layer" includes a layer consisting of multiple parts that lie in a similar plane, are made of similar materials, and have similar heights.

[0049] As shown in the figure, semiconductor component 2 includes three solder layers and a spacer, and is formed into a package (such as...) by sealing and / or cutting. Figures 3-4 When the semiconductor component is a semiconductor package 58), the semiconductor component has (or has about) a package size of 55.0 mm × 55.0 mm × 4.7 mm (as with other package sizes disclosed herein, the package size includes the size of the sealing portion but does not include the leads extending from the sealant). Figure 3The metal layer (layer) 61 (such as layer 4 and / or 30) is exposed through sealant 60 (such as on the top and bottom), and leads 62 extend from the sealant to electrically couple the die's electrical contacts to a power source and other components, such as for transmitting signals to / from the die and controlling the connected power source / receiving power from the connected power source. Figure 4 Leads are shown that can be configured in various ways to couple with external components as needed.

[0050] Metals other than copper can be used for the copper layer, and in such embodiments, the DBC substrate can alternatively be a metal-insulator-metal (MIM) substrate. Aluminum is merely one example for the exemplary purposes of this disclosure. Similarly, other insulating materials can be used for the insulating layer, and other metals can be used for the solder layer and spacers. In the illustrated embodiment, the two DBC substrates act as heat sinks to draw heat away from the die, and the package formed by the assembly is a double-sided cooled automotive high-power module (AHPM), although the layers and methods discussed can be used to form other types of semiconductor packages.

[0051] In some embodiments, the spacer may be narrower than the die. However, in such embodiments, die breakage and / or fragmentation may occur near the spacer mounting area during processing. In other embodiments, the spacer may be wider than the die (e.g., Figure 1 (As shown). This eliminates some die cracks near the spacer, but this dimensional mismatch can lead to solder "voids" between the spacer and the die at die corners, and can cause die corner breakage. Such solder "voids" are representatively shown in... Figure 1 In this embodiment, there are areas between spacer 12 and die 16 where no solder is present above the die. In this embodiment, die corner breakage is caused by a mismatch in the coefficients of thermal expansion (CTE) between the spacer, solder, and molding underfill (MUF) epoxy resin or epoxy molding compound (EMC). When the package cools after sealing, the spacer shrinks faster than the MUF or EMC, and the MUF or EMC prevents die movement at the die corner due to solder voids causing die corner breakage (caused by spacer shrinkage).

[0052] See now Figure 2, showing another embodiment of a semiconductor package. The semiconductor package (package) 2 includes a first MIM substrate formed of a metal layer (layer) 34, an insulator layer (layer) 36, and a metal layer (layer) 38. A second MIM substrate is formed of a metal layer (layer) 48, an insulator layer (layer) 50, and a metal layer (layer) 52. In the illustrated embodiment, the MIM substrates are DBC substrates using copper layers coupled with AI2O3 insulator layers, although materials other than copper can be used for the metal layers, and insulator materials other than AI2O3 can be used for the insulator layers. In embodiments, the metal layers can be, for example, aluminum, copper, or stainless steel. As non-limiting examples, in various embodiments, the insulator layers can be AI2O3, Zr-doped AI2O3, AIN, BeO, epoxy-based layers, and other ceramic, composite, or organic insulator materials. One or more of the MIM substrates can be an insulated metal substrate (IMS) including an aluminum layer, an insulator layer, and a copper layer.

[0053] The metal layer (layer) 38 has a recess 40 formed therein. The recess can be formed by any material removal technique, which can include, as non-limiting examples, etching, grinding, laser ablation, casting, shaping, drilling, and any other material removal or formation process. A semiconductor die (die) 44 is mechanically coupled within the recess using a metal layer 43, which is formed, in the illustrated embodiment, of a high-melting temperature solder, such as PbSn8Ag2, as a non-limiting example, or formed using Ag sintering to form a solder or sinter layer. Metals other than Ag can be used for the sinter layer, such as gold, as a non-limiting example, and / or solders other than PbSn8Ag2 can be used for the solder layer. The sinter layer can be formed using a dry powder or paste that is heated to form the sinter layer. In the illustrated embodiment, the die 44 is a metal-oxide-semiconductor field-effect transistor (MOSFET) die or an IGBT die, although in other embodiments it can be any other type of semiconductor die.

[0054] After the die is coupled within the recess, a photoresist layer 42 is deposited, which in this embodiment is shown as penetrating into the area between the die and the sidewalls of the recess, and also covering the bottom of the metal layer 38 and the die 44. As a non-limiting example, the photoresist layer can be a polyimide (PI) photoresist or a photo-solder resist (PSR), and can be imaged and selectively removed to expose electrical contacts of the die. After the electrical contacts are exposed, a metal layer (layer) 46 is used to mechanically couple the die with the layer 48. The photoresist helps to prevent the layer 46 from spilling over into undesired areas. The die can be electrically coupled with leads (not shown) of the package, such as through leads that are later electrically coupled with the layer 38 and / or 48.

[0055] Metal layer 46 can be formed of a solder having a lower melting temperature than metal layer 43, such that metal layer 43 does not reflow when layer 46 is reflowed. As a non-limiting example, layer 46 can be a SnSb5solder, while layer 43 is a PbSn8Ag2solder. Alternatively, if layer 43 is formed by Ag sintering, then layer 46 can be formed of a high melting temperature solder, or both layer 46 and layer 43 can be formed using Ag sintering.

[0056] Sealant 56 is applied to at least partially seal the die and layers to form package 32 using various sealing techniques, such as molding, transfer molding, cavity molding, or injection molding, as non-limiting examples. Metal layers 34 and 52 are exposed through the sealant, which helps to draw heat away from the die. In Figure 2 In the illustrated embodiment, there are only two solder layers or sintered layers, and there are no spacers between the die and any of the MIM substrates. As used herein, the term "spacers" does not include solder layers, sintered layers, solder bumps, solderable top metal (STM) layers, under bump metal (UBM) layers, substrates or any portion thereof, and semiconductor dies or any portion thereof.

[0057] As shown, in various embodiments, a slot 54 can be included in layer 52 to reduce, control, and / or balance warpage of the package. The slot can be formed using any material removal technique. In embodiments, package 32 has (or is about) a size of 55.0 mm x 55.0 mm x 2.3 mm to 2.6 mm. Thus, it can have a similar top profile as Figure 3 Package 58 of FIG. 1 has a similar top profile as package 32, but can have a thinner side profile than package 32 due to the thickness having been reduced from 4.7 mm to about 2.3 mm to 2.6 mm. Figure 4 The illustrated profile is thinner than the profile of package 32, due to the thickness having been reduced from 4.7 mm to about 2.3 mm to 2.6 mm. In the illustrated embodiment, package 32 is an ultra-thin double-sided cooled (DSC) automotive high power module (AHPM) having one or more embedded dies on a DBC or MIM substrate. In other embodiments, the package can be a non-AHPM package.

[0058] Referring now to Figure 5 and Figure 8 another embodiment of a semiconductor package is shown. In Figure 5 semiconductor package (package) 64 is shown as including a sealant 90 through which a metal layer (layer) 66 is exposed (and similar metal layers can be exposed through the bottom of the package), while leads 88 extend from the sealant to couple the internal die with other components.

[0059] Referring to Figure 8, package 64 is shown to include a first MIM substrate that includes a metal layer (layer) 66, an insulator layer (layer) 68, and a metal layer (layer) 70. Also shown is a second MIM substrate that includes a metal layer (layer) 82, an insulator layer (layer) 84, and a metal layer (layer) 86. In the illustrated implementation, both MIM substrates are DBC substrates, although they can be any other substrate type as described herein for other packages. A solder layer (layer) 72 is used to couple the topmost MIM substrate with a standoff 74, which can have the same characteristics as other standoffs described herein, and a solder layer (layer) 76 is used to mechanically couple the standoff with a semiconductor die (die) 78, which is an IGBT in the illustrated implementation, although in other implementations they can be other die types. A solder layer 80, which is a solder bump deposited onto the die / chip first in this flip-chip design, is used to mechanically couple the die with the bottommost MIM substrate. Although photoresists, such as PI or PSR photoresists, can be used at different stages, they are not shown in the figures to facilitate viewing of other elements. Leads 88 and an encapsulant 90 are shown. Figure 8 Metal layers 66 and 86 are shown to be exposed through the encapsulant. Package 64 is an AHPM package, although in other implementations package 64 can be configured as another package type. In implementations, the die can be electrically coupled with the leads through layer 70 and / or layer 82.

[0060] Referring now to Figure 6 , Figure 7 and Figures 9-11 , other implementations of semiconductor packages are shown. Figures 6-7 Semiconductor packages (packages) 92 and 120 are shown to be thinner than package 64, although have a relatively similar footprint. Figure 9 Package 92 is shown to be thinner than package 64, and Figures 10-11 Packages 120 and 150 are similarly thinner than package 64.

[0061] Referring to Figure 6 and Figure 9The illustrated embodiment, semiconductor package (package) 92 includes first and second MIM substrates and is formed using a flip chip method. The first MIM substrate includes a metal layer (layer) 94 (with slots 96 to reduce warpage, as previously discussed), an insulator layer (layer) 98, and a metal layer (layer) 100 with a recess 102 therein. The second MIM substrate includes a metal layer (layer) 114 (with slots 115 to reduce warpage, as previously discussed), an insulator layer (layer) 112, and a metal layer (layer) 110. The MIM substrates in the illustrated embodiment are DBC substrates, each with two copper layers on opposite sides of an AI2O3 layer, but they can be formed of other insulators and metals as discussed herein with respect to other packages.

[0062] A metal layer (layer) 104 (which can be a high melting temperature solder or Ag sinter as previously discussed) is used to couple a semiconductor die (die) 106 within the recess; and a metal layer (layer) 108 (which in this flip chip design includes solder bumps that are deposited first onto the die / chip) (which can be a lower melting temperature solder (or Ag sinter, or a high melting temperature solder if layer 106 is an Ag sinter)) is used to mechanically couple the die (including electrical leads of the die) with layer 110. This can for example include reflowing the solidified solder bumps once the die is properly positioned. In embodiments, the die can be electrically coupled with leads 116 through layer 110 and / or layer 100 (such as through leads that are later electrically coupled with layer 110 and / or layer 100).

[0063] The die in the illustrated embodiment is a MOSFET die, and the package is an AHPM package, but in other embodiments another type of die and / or package can be formed using the same techniques. Photoresist (such as PI or PSR) can be used in conjunction with metal layers 104 and / or 108, but they are not shown to facilitate easy viewing of the other elements. Leads 116 in the illustrated embodiment are electrically coupled with the die through layer 110, and a sealant 118 is used to at least partially seal the die and layers. Figure 9 Layers 94 and 114 are shown as both being exposed through the sealant. Slots 96 and 115 can not extend the entire length of the package, but can be intermittent, as Figure 6 Embodiments are illustratively shown in FIG. 1.

[0064] Package 92 is similar in many respects to package 64, except that it includes fewer layers of solder (or other metal reflow / sintering), does not include spacers, and has a thinner profile. Package 64 has (or approximately has) a package size of 55.0 mm x 55.0 mm x 4.7 mm and is formed using a flip chip method. Package 92, also formed using a flip chip method, has (or approximately has) a package size of 55.0 mm x 55.0 mm x 2.30 mm. Thus, package 92 is an ultra-thin DSC AHPM with embedded die on a DBC / MIM substrate.

[0065] Referring to Figure 7 and Figure 10 Semiconductor package (package) 120 includes first and second MIM substrates and is formed using a chip-up design. The first MIM substrate includes a metal layer (layer) 122 (with slots 124 to reduce warpage, as previously discussed), an insulator layer (layer) 126, and a metal layer (layer) 128. The second MIM substrate includes a metal layer (layer) 142 (with slots 144 to reduce warpage, as previously discussed), an insulator layer (layer) 140, and a metal layer (layer) 136 with a recess 138 therein. The MIM substrates in the illustrated embodiment are DBC substrates, each having two copper layers on opposite sides of an AI2O3 layer, but they can be formed of other insulators and metals as discussed herein with respect to other packages.

[0066] Metal layer (layer) 134 (which can be a high-melting temperature solder or Ag sinter as previously discussed) is used to couple semiconductor die (die) 132 within the recess, and metal layer (layer) 130 (which can be a lower-melting temperature solder (or Ag sinter, or a high-melting temperature solder if layer 134 is Ag sinter)) is used to mechanically couple the die with layer 128. In embodiments, the die can be electrically coupled with leads 146 through layer 136 and / or layer 128, such as through leads that are later electrically coupled with layer 136 and / or layer 128.

[0067] The die in the illustrated embodiment is a MOSFET die or an IGBT die, and the package is an AHPM package, but in other embodiments another type of die and / or package can be formed using the same techniques. Photoresist, such as PI or PSR, can be used in conjunction with metal layers 130 and / or 134, but they are not included in the figures in order to easily view the other elements. Leads 146 in the illustrated embodiment are electrically coupled with the die through layer 136, and encapsulant 148 is used to at least partially encapsulate the die and layers. As Figure 10As shown, both layers 122 and 142 are exposed through the encapsulant. Slots 124 and 144 can not extend the entire length of the package, but can be intermittent, as is representatively shown in Figure 7 .

[0068] Package 120 is similar in many respects to package 64, except that it includes fewer layers of solder (or other metal reflow / sinter), does not include a spacer, and has a thinner profile. Package 120 has (or about has) a package size of 55.0 mm x 55.0 mm x 2.30 mm. Thus, package 120 is an ultra-thin DSC AHPM with embedded dies on a DBC / MIM substrate.

[0069] Referring to Figure 11 , a semiconductor package (package) 150 can look the same as package 120, including a first MIM substrate and a second MIM substrate, and formed using a chip-down design, from a perspective similar to Figure 7 . The first MIM substrate includes a metal layer (layer) 152 (with slots 154 to reduce warpage, as previously discussed), an insulator layer (layer) 156, and a metal layer (layer) 158 with grooves 160 therein. The second MIM substrate includes a metal layer (layer) 172 (with slots 174 to reduce warpage, as previously discussed), an insulator layer (layer) 170, and a metal layer (layer) 168. The MIM substrates in the illustrated embodiment are DBC substrates, each having two copper layers on opposite sides of an AI2O3 layer, but the substrates can be any other substrate type disclosed in this document.

[0070] A metal layer (layer) 162 (which can be a high-melting temperature solder or Ag sintered as previously discussed) is used to couple a semiconductor die (die) 164 within the grooves. A metal layer (layer) 166 (which can be a low-temperature solder (or Ag sintered, or a high-melting temperature solder if layer 162 is Ag sintered)) is used to mechanically couple the die with layer 168. In embodiments, the die can be electrically coupled with leads 176 through layer 158 and / or layer 168, such as through leads that are later electrically coupled with layer 158 and / or layer 168.

[0071] The die in the illustrated embodiment is a MOSFET or IGBT die, and the package is an AHPM package, but in other embodiments another type of die and / or package can be formed using the same techniques. Photoresist, such as PI or PSR, can be used in conjunction with metal layers 162 and / or 166, but they are not shown to facilitate easy viewing of the other elements. Leads 176 in the illustrated embodiment are electrically coupled with the die through layer 168, and encapsulant 178 is used to at least partially encapsulate the die and layers. Figure 11Both layers 152 and 172 are shown exposed through the encapsulant. Slots 154 and 174 can not extend the entire length of the package, but can be intermittent, as shown with respect to Figures 6-7 a representative showing of the package.

[0072] Package 150 is similar in many respects to package 64, except that it includes fewer layers of solder (or other metal reflow / sinter), does not include spacers, and has a thinner profile. Package 150 has (or is about) a package size of 55.0 mm x 55.0 mm x 2.30 mm. Thus, package 150 is an ultra-thin DSC AHPM with embedded die on a DBC / MIM substrate.

[0073] Signal pad solder joint plastic peel strain and die top stress were modeled using finite element analysis (FEA) for packages 64 and 92 (both flip-chip designs), and it was found that the solder peel plastic strain of package 92 was less than 0.5 times the solder peel plastic strain of package 64. The die top stress of package 92 was less than 0.8 times the die top stress of package 64.

[0074] Referring now to Figure 12 , another embodiment of a semiconductor package is shown. Semiconductor package (package) 180 includes a first and second insulated-metal substrate. The first insulated-metal substrate is formed from an insulator layer (layer) 182 coupled with a metal layer (layer) 184 having a recess 186 formed therein. The second insulated-metal substrate is formed from an insulator layer (layer) 198 coupled with a metal layer (layer) 196. The MIM substrates in the illustrated embodiment are single-sided copper clad (SBC) substrates, each having a copper layer coupled with an AI2O3 layer, but they can be formed from other insulators and metals as discussed herein with respect to other packages.

[0075] A metal layer (layer) 190 (which can be a high-melting temperature solder as previously discussed or Ag sintered) is used to couple a semiconductor die (die) 192 within the recess. Photoresist 188 (such as PI or PSR) is deposited and selectively removed to expose electrical contacts of the die. After the electrical contacts are exposed, a metal layer (layer) 194 (which can be a low-temperature solder (or Ag sintered, or a high-melting temperature solder if layer 190 is Ag sintered) is used to mechanically couple the electrical contacts of the die with layer 196. In embodiments, the die can be electrically coupled with leads (not shown) of the package (such as through leads that are later electrically coupled with layer 184 and / or 196). An encapsulant 200 is used to at least partially encapsulate the die and layers.

[0076] The die in the illustrated embodiments is a MOSFET or IGBT die, and the package is an AHPM package, but in other embodiments another type of die and / or package can be formed using the same technology. As Figure 12 As illustrated, in various embodiments, both insulator layers 182 and 198 are exposed through the encapsulant. In embodiments, the insulator layers can be formed of a high-thermal-conductivity ceramic material, such as AI2O3, AIN, Si3N4, or other thermally-conductive material, as non-limiting examples, to help draw heat away from the die.

[0077] Package 180 has (or is approximately) a size of 55.0 mm x 55.0 mm x 1.7 mm to 2.0 mm, which gives it a similar footprint as package 58, except with a thinner side profile. It also has only two sintered or reflowed metal layers and no spacers. Package 180 has no exposed metal layers on the outside of the package, which can help reduce warping, such as during a die attach process that couples the die within a recess, and can help reduce the likelihood of peeling or breaking either of the sintered or reflowed metal layers, one or both of which can be signal carriers. Alternative versions of the design of package 180 can use one or more leadframes instead of one or more of the insulator-metal substrates. Package 180 is a super-thin DSC AHPM SBC on SBC (with embedded chip). In other embodiments, since the package is already relatively thin, layer 184 can not include a recess, and the die can simply be coupled to the non-recessed surface of layer 184.

[0078] Referring now to Figure 13 another embodiment of a semiconductor package is shown. Semiconductor package (package) 202 includes a leadframe coupled with an insulator layer and a MIM substrate. Leadframe 208 is mechanically coupled with insulator layer (layer) 204 using a high-thermal-conductivity adhesive layer (layer) 206, which can be an epoxy, a glue, a polyurethane, a silicone elastomer, and any other adhesive type, as non-limiting examples. In the illustrated embodiment, layer 206 is a silicone elastomer. The leadframe has a recess 209 formed therein. The MIM substrate is formed of a metal layer (layer) 218 coupled with an insulator layer (layer) 220, which in turn is coupled with a metal layer (layer) 222. The MIM substrate in the illustrated embodiment is a DBC substrate with two copper layers coupled with AI2O3 layers, but it can be formed of other insulators and metals as discussed herein with respect to other packages.

[0079] A metal layer(s) 210 (which can be high melting temperature solder or Ag sintered as previously discussed) is used to couple a semiconductor die(s) 212 within the recess. A photoresist 214 (such as PI or PSR) is deposited and selectively removed to expose the electrical contacts of the die. After the electrical contacts are exposed, a metal layer(s) 216 (which can be lower melting temperature solder (or Ag sintered, or high melting temperature solder if layer 210 is Ag sintered) is used to mechanically couple the electrical contacts of the die with a metal layer 218. In embodiments, the die can be electrically coupled with the leads (not shown) of the package through the leadframe and / or layer 218 (such as through leads that are later electrically coupled with the leadframe and / or layer 218). An encapsulant 224 is used to at least partially encapsulate the die, layers, and leadframe.

[0080] The die in the illustrated embodiment is a MOSFET die or an IGBT die, and the package is an AHPM package, but in other embodiments another type of die and / or package can be formed using the same techniques. As Figure 13 As illustrated, both the insulator layer 204 and the metal layer 222 are exposed through the encapsulant. In embodiments, the insulator layer can be formed of a high thermal conductivity ceramic material as discussed herein for other packages to help draw heat away from the die.

[0081] The package 202 has (or is approximately) a size of 55.0 mm x 55.0 mm x 2.6 mm to 3.2 mm, which gives it a similar footprint as the package 58, except with a thinner side profile. It also has only two sintered or reflowed metal layers and does not have spacers. The package 202 has only one exposed metal layer on the outside of the package, which can help reduce warping (such as during a die attach process that couples the die within the recess), and can help reduce the likelihood of peeling or breaking either of the sintered or reflowed metal layers (one or both of which can be signal carriers). The package 202 is an ultra-thin DSC AHPM, with the die on a leadframe / insulator that is coupled with a DBC substrate. In other embodiments, the leadframe can not include a recess, and the die can simply be coupled to a non-recessed surface of the leadframe. The leadframe can initially have a recess formed therein, or the recess can be formed therein later using any of the material removal processes disclosed herein.

[0082] Referring now to Figure 14, another embodiment of a semiconductor package is shown. The semiconductor package (package) 226 includes a first leadframe coupled with an insulator layer and a second leadframe coupled with an insulator layer. The first leadframe 232 is mechanically coupled with the insulator layer (layer) 228 using a high thermal conductivity adhesive layer (layer) 230, which can be an epoxy, a glue, a polyurethane, a silicone elastomer, and other various adhesive materials as non-limiting examples. In the illustrated embodiment, the layer 230 is a silicone elastomer. The leadframe has a recess 234 formed therein. The second leadframe 244 is mechanically coupled with the insulator layer (layer) 248 using a high thermal conductivity adhesive layer (layer) 246, which can have the same or different material as the layer 230. In the illustrated embodiment, the layer 246 is a silicone elastomer.

[0083] A metal layer (layer) 236, which can be a high melting temperature solder as previously discussed or Ag sintered, is used to couple a semiconductor die (die) 238 within the recess. A photoresist 240, such as a PI or PSR, is deposited and selectively removed to expose electrical contacts of the die. After the electrical contacts are exposed, a metal layer (layer) 242, which can be a lower melting temperature solder (or Ag sintered, or a high melting temperature solder if the layer 236 is Ag sintered), is used to mechanically couple the electrical contacts of the die with the second leadframe 244. In embodiments, the die can be electrically coupled with leads (not shown) of the package, such as through leads that are later electrically coupled with the first leadframe and / or the second leadframe. An encapsulant 250 is used to at least partially encapsulate the die and the layers.

[0084] The die in the illustrated embodiment is a MOSFET die or an IGBT die, and the package is an AHPM package, but in other embodiments another type of die and / or package can be formed using the same techniques. As Figure 14 As shown, both of the insulator layers 228 and 248 are exposed by the encapsulant. In embodiments, the insulator layers can be formed of a high thermal conductivity ceramic material as discussed herein with respect to other packages to help draw heat away from the die.

[0085] Package 226 has (or is approximately) 55.0 mm x 55.0 mm x 2.6 mm to 3.2 mm in size, which gives it a similar footprint as package 58, except with a thinner side profile. It also has only two sintered or reflowed metal layers and no spacers. Package 226 has no exposed metal layers on the outside of the package, which can help reduce warpage (such as during a die attach process that couples a die within a recess), and can help reduce the likelihood of peeling or breaking either of the sintered or reflowed metal layers (one or both of which can be signal carriers). Package 226 is an ultra-thin DSC AHPM, with a die on a leadframe / insulator that is coupled with a leadframe / insulator. In other embodiments, the first leadframe can not include a recess, and the die can be coupled only to a non-recess surface of the first leadframe. The first leadframe can initially have a recess formed therein, or a recess can be formed therein later using any material removal technique.

[0086] Any of the methods and packages herein that show a single die coupled within a recess only can be scaled to include multiple dies coupled within multiple recesses or multiple dies coupled within a common recess. The leadframe of any of the packages discussed herein can be formed from any metal, including copper, copper alloys, steel, and any other electrically conductive material, as non-limiting examples. The encapsulant material can be formed from a polymer resin / epoxy resin, a thermoset resin / epoxy resin, and the like, as non-limiting examples.

[0087] Referring now to Figure 15 , embodiments of a MIM structure are shown. Only the metal layers of the MIM structure are shown to facilitate viewing them, but there will be insulator layers between the two. In the structure of Figure 15 , the first metal layer (layer) 252 is formed from a single contiguous piece of metal. However, the second metal layer (layer) 254 is formed from a first portion 256 and a second portion 258, which are initially electrically isolated from each other by a slit 260 between them. They can be electrically coupled later, if desired, during formation of the package. In the first portion 256, a recess 257 is shown, and a semiconductor die (die) 261 is shown coupled within it. The top view shows that the outer perimeter of the die is entirely within the outer perimeter of the recess, and this is also the case for all other packages disclosed herein that position a die within a recess.

[0088] The second portion 258 is shown without a recess, but it can also have a recess, and in various embodiments, with a die, and the recess of each portion can additionally include other elements / dies and / or can include additional recesses for additional elements / dies. In the illustrated embodiment, the MIM substrate is a DBC substrate using a copper layer coupled with an insulator layer (not shown), but in other embodiments, other metal layer materials and / or insulator layer materials can be used as discussed with respect to other packages herein. In some embodiments, splitting the second metal layer into separate portions can facilitate, for example, embedding a high side (HS) die within a recess of one portion and a low side (LS) die within a recess of another portion. This concept can also apply to an insulator-metal substrate that includes only one metal layer, where the single metal layer is split into multiple portions.

[0089] Figure 16 An analogous MIM structure is shown, again showing a first metal layer (layer) 262 and a second metal layer (layer) 264, but not showing an insulator layer. The second metal layer includes a first portion 266 and a second portion 268, and in this case, the slit 270 is a straight vertical slit. Thus, the slit can be designed as needed to accommodate different components on the two portions. The two portions of layer 264 can again be used for a high side die and a low side die that can be embedded in a recess. For example, as non-limiting examples, each portion can include a separate MOSFET (HS MOSFET and LS MOSFET), or each portion can include a separate insulated gate bipolar transistor (IGBT) and fast recovery diode (FRD).

[0090] In embodiments, instead of a single metal layer of one substrate being split into two portions, a separate substrate can be used on one side (top or bottom side) of the package to achieve separation of HS and LS dies / components. In this embodiment, there can then be at least three substrates— one on the top or bottom side, and two on opposite sides to hold the HS / LS dies within recesses.

[0091] In forming embodiments of the packages disclosed herein, a solder mask / photoresist layer can be used prior to laying or depositing the first metal layer that couples the dies within the recesses. While high melting temperature solders and Ag sintering for coupling the dies within the recesses are disclosed herein, in other embodiments, any thermally conductive die attachment material can be used, and this thermally conductive die attachment material can need to be reflowed to form a first portion or half of the package (the top substrate or lead frame with which the dies are coupled). The lower half or portion is formed by providing or forming a bottom substrate / lead frame structure. The two halves or portions are coupled together using a solder layer or sintering layer, as discussed herein, and the dies and layers are then sealed to form the package.

[0092] Some of the embodiments of semiconductor packages disclosed herein protect the die from damage, in part, due to not including spacers and also by embedding the die within a recess of a metal layer or leadframe. For those packages without spacers, all failure modes associated with spacers are removed. Embedding the die within a recess can also reduce or eliminate solder voids, thus reducing or eliminating damage caused by such voids. Some of the packages herein have shorter thermal and electrical paths due to not including spacers and embedding the die within a recess, thus enhancing thermal and electrical performance. For packages that do not include spacers and have less reflow or sintered metal layers, material costs are also reduced. The packages disclosed herein can allow for ultra-thin AHPM to enable three-phase inverters to be more compact and enable increased power density.

[0093] Other steps not discussed herein can be used to form the packages, and those disclosed highlight only some of the steps of the manufacturing process. For example: multiple photoresist layers can be laid down and sequentially patterned to be patterned simultaneously for patterning purposes, and those layers exposed with exposed portions removed (or left); passivation layers can be formed on metal layers with portions of the passivation removed by selective material removal (such as using photoresist and etching, etc.); dicing can be performed after sealing, etc.

[0094] As used herein, the terms“partially sealed,”“fully sealed,” and variations thereof have specific meanings. See Figures 2-14 After the sealing step, each of the dies is considered fully sealed in the encapsulant, even if there is no encapsulant directly above and / or directly below each die (but rather one or more solder or sintered metal and / or residual photoresist), because each die is fully surrounded by the combination of the encapsulant and the elements within the encapsulant that are at least partially sealed by the encapsulant themselves. Each metal layer or insulator layer exposed by the encapsulant is only partially sealed in the encapsulant because a portion is exposed by the encapsulant. To facilitate viewing of other elements, not all packages shown in the figures show electrical leads in addition to the metal layers exposed on the outside of the package, but all packages shown in the figures can have leads exposed by or extending from the encapsulant, and such leads would only be partially sealed in the encapsulant.

[0095] In various package embodiments, the first metal layer can include two metal segments that are electrically isolated from each other prior to coupling the semiconductor die with the first metal layer.

[0096] In various package embodiments, the leadframe can be mechanically attached to the first insulator layer using a silicone elastomer.

[0097] In various package embodiments, the leadframe can include a first metal layer.

[0098] In various package embodiments, the leadframe can include a second metal layer.

[0099] In various package embodiments, the semiconductor die can be mechanically coupled within the recess using a solder metal or a sintered metal, wherein the semiconductor die is mechanically coupled with the second metal layer using the solder metal or the sintered metal.

[0100] In various package embodiments, the semiconductor package does not include a spacer between the semiconductor die and the first metal layer, and wherein the package does not include a spacer between the semiconductor die and the second metal layer.

[0101] Where the above description refers to particular embodiments of semiconductor packages and related methods, and to parts, components, methods, and sub-methods of implementing same, it will be apparent that modifications can be made without departing from the spirit thereof, and that these embodiments, parts, components, methods, and sub-methods can be applied to other semiconductor packages and related methods.

Claims

1. A method of forming a semiconductor package, the method comprising: providing a first insulator layer coupled with a first surface of a first metal layer; forming a recess in the first metal layer; mechanically coupling a first surface of a semiconductor die at least partially within the recess, a perimeter of the semiconductor die being entirely within a perimeter of the recess; depositing a photoresist layer such that the photoresist layer penetrates into an area between the semiconductor die and a sidewall of the recess and also covers a second surface of the first metal layer and partially covers a second surface of the semiconductor die, wherein the first surface of the first metal layer and the second surface of the first metal layer are opposite surfaces and the first surface of the semiconductor die and the second surface of the semiconductor die are opposite surfaces; mechanically coupling the semiconductor die with a second metal layer, the second metal layer being coupled with a second insulator layer; and sealing the first insulator layer, the first metal layer, the semiconductor die, the second insulator layer, and the second metal layer at least partially in a sealant to form a semiconductor package; wherein the first insulator layer and the second insulator layer are exposed by the sealant.

2. A method of forming a semiconductor package, the method comprising: providing a first metal-insulator-metal (MIM) substrate having a first metal layer and a second metal layer coupled on opposite sides of a first insulator layer, wherein the first insulator layer is coupled with a first surface of the first metal layer; forming a recess in the first metal layer; mechanically coupling a first surface of a semiconductor die at least partially within the recess, a perimeter of the semiconductor die being entirely within a perimeter of the recess; depositing a photoresist layer such that the photoresist layer penetrates into an area between the semiconductor die and a sidewall of the recess and also covers a second surface of the first metal layer and partially covers a second surface of the semiconductor die, wherein the first surface of the first metal layer and the second surface of the first metal layer are opposite surfaces and the first surface of the semiconductor die and the second surface of the semiconductor die are opposite surfaces; mechanically coupling the semiconductor die with a third metal layer of a second metal-insulator-metal substrate, the second metal-insulator-metal substrate including the third metal layer and a fourth metal layer on opposite sides of a second insulator layer; and sealing the first metal-insulator-metal substrate, the semiconductor die, and the second metal-insulator-metal substrate at least partially in a sealant to form a semiconductor package.

3. The method of claim 2, wherein the first metal layer includes two metal segments that are electrically isolated from each other prior to coupling the semiconductor die with the first metal layer.

4. The method of claim 2, wherein one of the second metal layer and the fourth metal layer includes a slot configured to reduce warpage of the semiconductor package.

5. A semiconductor package comprising: a first insulator layer coupled with a first surface of at least a first metal layer, the first metal layer including a recess therein; a semiconductor die having a first surface at least partially mechanically coupled within the recess, a perimeter of the semiconductor die being entirely within a perimeter of the recess; a photoresist layer having a first portion disposed between the semiconductor die and a sidewall of the recess and a second portion covering a second surface of the first metal layer and partially covering a second surface of the semiconductor die, wherein the first surface of the first metal layer and the second surface of the first metal layer are opposite surfaces and the first surface of the semiconductor die and the second surface of the semiconductor die are opposite surfaces; at least a second metal layer coupled with a second insulator layer, the second metal layer mechanically coupled with the semiconductor die; and a sealant at least partially sealing the first insulator layer, the first metal layer, the semiconductor die, the second insulator layer, and the second metal layer; wherein the first insulator layer and the second insulator layer are exposed by the sealant.

6. The semiconductor package of claim 5, wherein the first insulator layer and the first metal layer are included in a first metal-insulator-metal substrate, the first metal- insulator-metal substrate including the first metal layer and a third metal layer coupled on opposite sides of the first insulator layer.

7. The semiconductor package of claim 5, wherein the second insulator layer and the second metal layer are included in a second metal-insulator-metal substrate, the second metal- insulator-metal substrate including the second metal layer and a fourth metal layer coupled on opposite sides of the second insulator layer.

8. The semiconductor package of claim 5, wherein one of the second metal layer and the fourth metal layer includes a slot configured to reduce warpage of the semiconductor package. ​

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