Semiconductor structure, preparation method and semiconductor packaging structure

Abstract

The present invention relates to a semiconductor structure, comprising: a substrate, a pad, a first protective layer, a connection plug, a redistribution layer, a bump, and a second protective layer; the redistribution layer comprises a first metal wire and a second metal wire; the second metal wire is not electrically connected. Since the second metal wire and the first metal wire are of equal height, the bump on the first metal wire and the bump on the second metal wire are equivalent to being formed on the same layer, so the bump on the first metal wire and the bump on the second metal wire have a high coplanarity, the second metal wire is insulated from the pad, so the bump formed on the second metal wire does not play a conductive role, and when the substrate warps and generates stress, the stress is transferred to the first protective layer. The bump in the substrate of the present application has good coplanarity, which reduces the probability of poor wetting when flip-chip mounted on the substrate, and improves the reliability of the entire package.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging, and in particular to a semiconductor structure, a preparation method and a semiconductor packaging structure. Background Art

[0002] Flip chip packaging technology is an interconnection method based on small chip size, high I / O density, and excellent electrical and thermal performance. It is mounted on the circuit board after preparing solder balls or bumps on the chip pads.

[0003] In the prior art, in order to solve the stress problem generated during packaging, bumps or solder balls are usually prepared at positions where there are no solder pads. However, the bumps or solder balls prepared at positions where there are no solder pads have coplanarity problems with the bumps or solder balls at the solder pad positions, which makes it easy for poor wetting to occur when flip-chip mounted on the substrate, affecting the reliability of the entire package. Summary of the invention

[0004] Based on this, it is necessary to provide a semiconductor structure, a preparation method and a semiconductor packaging structure to address the problem of poor coplanarity of bumps.

[0005] substrate;

[0006] A pad located on the substrate;

[0007] A first protective layer, covering a portion of the pad;

[0008] a connecting plug, wherein the connecting plug is located in the first protective layer;

[0009] a redistribution layer, located on the first protection layer; the redistribution layer comprises a first metal line and a second metal line; the first metal line is electrically connected to the pad via the connection plug; the second metal line is flush with the upper surface of the first metal line, and the second metal line is not electrically connected;

[0010] A second protection layer is located on an upper surface of the first protection layer and covers the redistribution layer; a first opening and a second opening are formed in the second protection layer, the first opening exposes the first metal line, and the second opening exposes the second metal line;

[0011] The bump is located on the upper surface of the first metal wire and the second metal wire.

[0012] Through the above technical solution, since the second metal wire and the first metal wire are at the same height, the bumps on the first metal wire and the bumps on the second metal wire are equivalent to being formed in the same layer, so the bumps on the first metal wire and the bumps on the second metal wire have a high coplanarity, and the second metal wire is insulated from the pad, so the bumps formed on the second metal wire do not play a conductive role, and when stress is generated by warping of the substrate, the stress is transferred to the first protective layer. The coplanarity of the bumps in the substrate of the present application is better, which reduces the probability of poor wetting when flip-chip mounted on the substrate, and improves the reliability of the entire package.

[0013] In one embodiment, an under-bump metallization layer is further included. The under-bump metallization layer is located on the inner surfaces of the first opening and the second opening and is in contact with the bump, the first metal wire, and the second metal wire.

[0014] Through the above technical solution, the bonding force between the bump and the metal layer under the bump is higher, which is more stable and reliable than the bump directly growing on the side walls of the first opening and the second opening.

[0015] In one embodiment, there is a gap between the second metal line and the first metal line.

[0016] In one embodiment, the width of the second opening is smaller than the width of the second metal line, and the distance between the edge of the second opening and the edge of the second metal line is 2.5 um to 7 um.

[0017] In one embodiment, the redistribution layer also includes a plurality of plugs, which penetrate the first protective layer along the thickness direction of the first protective layer; the first metal line and the second metal line are respectively connected to different plugs, and the width of the first metal line and the width of the second metal line are both greater than the width of the plug.

[0018] In one of the embodiments, the first protection layer includes a polymer layer and a passivation layer, the passivation layer is located on the upper surface of the substrate, and the polymer layer is located on the upper surface of the passivation layer.

[0019] In one embodiment, a method for preparing a semiconductor structure is also provided, comprising the following steps:

[0020] Providing a substrate, wherein a pad is formed on the substrate;

[0021] forming a first protective layer on the substrate to cover a portion of the pad;

[0022] A connection plug is formed in the first protective layer, and a redistribution layer is formed on the upper surface of the first protective layer, wherein the redistribution layer includes a first metal line and a second metal line; the first metal line is electrically connected to the pad via the connection plug; the second metal line is flush with the upper surface of the first metal line, and the second metal line is not electrically connected;

[0023] forming a second protective layer on the upper surface of the first protective layer;

[0024] forming a first opening and a second opening in the second protection layer, wherein the first opening exposes the first metal line, and the second opening exposes the second metal line;

[0025] Bumps are formed on upper surfaces of the first metal line and the second metal line.

[0026] Through the above technical solution, since the second metal wire and the first metal wire are at the same height, the bumps on the first metal wire and the bumps on the second metal wire are equivalent to being formed in the same layer, so the bumps on the first metal wire and the bumps on the second metal wire have a high coplanarity, and the second metal wire is insulated from the pad, so the bumps formed on the second metal wire do not play a conductive role, and when stress is generated by warping of the substrate, the stress is transferred to the first protective layer. The coplanarity of the bumps in the substrate of the present application is better, which reduces the probability of poor wetting when flip-chip mounted on the substrate, and improves the reliability of the entire package.

[0027] In one embodiment, providing a chip including a pad further includes:

[0028] Forming a first protective layer on the substrate comprises:

[0029] forming a passivation layer on the upper surface of the substrate;

[0030] A polymer layer is formed on the passivation layer.

[0031] In one embodiment, the width of the second opening is smaller than the width of the second metal line, and the distance between the edge of the second opening and the edge of the second metal line is 2.5 um to 7 um.

[0032] In one embodiment, after forming the first opening and the second opening in the second protection layer and before forming the bump, the following steps are further included:

[0033] An under-bump metallization layer is formed on the inner surfaces of the first opening and the second opening, and the under-bump metallization layer is in contact with both the first metal line and the second metal line; the bump is formed on the surface of the under-bump metallization layer.

[0034] In one embodiment, forming a connection plug in the first protection layer and forming the redistribution layer on the upper surface of the first protection layer comprises the following steps:

[0035] forming a connection opening in the first protective layer, wherein the connection opening exposes the pad;

[0036] forming the connection plug in the connection opening;

[0037] The first metal line and the second metal line are formed on the upper surface of the first protection layer; the first metal line is connected to the connection plug.

[0038] In one embodiment, the redistribution layer further includes a plurality of plugs; forming the connection plugs in the first protective layer and forming the redistribution layer on the upper surface of the first protective layer includes the following steps:

[0039] forming a connection opening and a through hole in the first protective layer, wherein the connection opening exposes the pad;

[0040] forming the connection plug in the connection opening and forming the plug in the through opening;

[0041] The first metal wire and the second metal wire are formed on the upper surface of the first protective layer; the first metal wire is connected to the connecting plug and part of the plug; the second metal wire is connected to the remaining plugs, and the width of the first metal wire and the width of the second metal wire are both greater than the width of the plug.

[0042] In one of the embodiments, a semiconductor package structure is further provided, and the semiconductor package structure includes the above-mentioned semiconductor structure.

[0043] In one embodiment, the semiconductor structure is flipped on a substrate, the bump is attached to the substrate, a plastic encapsulation layer is formed on the periphery of the semiconductor structure, and the plastic encapsulation layer wraps the bump. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 A schematic diagram showing a semiconductor structure in one embodiment of the present invention;

[0045] Figure 2 A schematic structural diagram showing a semiconductor structure according to another embodiment of the present invention;

[0046] Figure 3 A schematic structural diagram showing a semiconductor packaging structure according to an embodiment of the present invention;

[0047] Figure 4A flow chart of a method for preparing a semiconductor structure in one embodiment of the present invention;

[0048] Figure 5-Figure 11 A schematic diagram showing the structures of various steps in a method for preparing a semiconductor structure according to an embodiment of the present invention;

[0049] Figure 12-14 The following is a schematic structural diagram showing the various steps in a method for preparing a semiconductor structure according to another embodiment of the present invention. DETAILED DESCRIPTION

[0050] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0051] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0052] In the description of the present invention, it is necessary to understand that the terms "upper", "lower", "vertical", "horizontal", "inside", "outside", etc., indicating the orientation or positional relationship, are based on the method or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0053] like Figure 1 As shown, in one embodiment of the present application, a semiconductor structure is provided, a substrate 10, and a chip (not shown in the drawings) is formed in the substrate 10;

[0054] The pad 11 is located on the substrate 10 and is electrically connected to the chip;

[0055] A first protective layer 12 is located on the substrate 10 and covers a portion of the pad 11;

[0056] A connecting plug formed in the first protective layer 12;

[0057] A redistribution layer is located on the first protection layer 12; the redistribution layer includes a first metal line 13 and a second metal line 14; the first metal line 13 is electrically connected to the pad 11 via a connection plug; the second metal line 14 is flush with the upper surface of the first metal line 13, and the second metal line 14 is not electrically connected;

[0058] The second protection layer 15 is located on the upper surface of the first protection layer 12 and covers the redistribution layer. A first opening and a second opening are formed in the second protection layer 15. The first opening exposes the first metal line 13, and the second opening exposes the second metal line 14.

[0059] A bump 20 is formed on the upper surface of the first metal wire 13 , and a bump 21 is formed on the upper surface of the second metal wire 14 .

[0060] Specifically, in an optional embodiment, the substrate can be a bulk silicon substrate, a silicon-on-insulator substrate, or other semiconductor materials including group III, group IV, and group V. The pad 11 is metal and can be made of aluminum or an aluminum alloy. The pad 11 is electrically connected to the chip in the substrate 10.

[0061] The first protective layer 12 includes a polymer layer 22 and a passivation layer 16. The polymer layer 22 is formed on the upper surface of the substrate 10 and is made of a polymer having certain elasticity and insulation, and can be a polyimide layer. In other embodiments, the polymer layer 22 can also be formed of epoxy resin, benzocyclobutene or polybenzoxazole. The thickness of the polymer layer 22 is between 3-7um and can be 5um. The passivation layer 16 is formed on the upper surface of the polymer layer 22 and wraps the edge of the pad 11.

[0062] The first metal wire 13 and the second metal wire 14 are formed simultaneously, so the two have the same height. The first metal wire 13 and the second metal wire 14 can be formed of aluminum. The first metal wire 13 contacts the pad 11 through the opening set on the first protective layer 12 corresponding to the pad 11 through the connecting plug, thereby realizing the electrical connection between the first metal wire 13 and the pad 11. In addition to the pad 11 and the first metal wire 13, the semiconductor structure can also have other conductive structures such as pads or wires. The second metal wire 14 is insulated and isolated from all conductive structures in the semiconductor structure.

[0063] The bump 20 includes a metal bump 201 and a solder layer 202. The metal bump 201 is electrically connected to the pad 11 through the first metal wire 13. The metal bump 201 can be formed of copper. The solder layer 202 is formed at one end of the metal bump 201 away from the first metal wire 13 and can be formed of tin or tin-silver alloy.

[0064] A bump 21 is prepared on the second metal wire 14. The bump 21 includes a metal bump 211 and a solder layer 212. The metal bump 211 can be formed of copper. The solder layer 212 is formed at one end of the metal bump 211 away from the first metal wire 13, and can be formed of tin or a tin-silver alloy. Since the second metal wire 14 is insulated from the pad 11, the bump 21 is also insulated from the pad 11, and the bond between metal and metal is more reliable, the bump will not drift, and the stability is higher.

[0065] The height of the metal bump 201 and the metal bump 211 is between 25-40um, and can be 30um. The height of the solder layer 202 and the solder layer 212 is between 15-30um, and can be 20um. The height of the bump 20 and the bump 21 can be 50um. Since the second metal wire 14 is formed on the first protective layer 12, the stress it receives can be transferred to the polymer layer 22. Since the second metal wire 14 and the first metal wire 13 are of the same height, the bump 20 and the bump 21 are equivalent to being formed on the same layer, so that the coplanarity of the bump 20 and the bump 21 is high, which can reduce the probability of poor wetting when flip-chipped onto the substrate, and improve the reliability of the entire package.

[0066] In other optional embodiments, there is a buffer gap between the second metal wire 14 and the first metal wire 13 , and the second metal wire 14 does not directly contact the first metal wire 13 physically, so there is more space to transfer stress when the second metal wire 14 is subjected to greater stress.

[0067] The material of the second protection layer 15 can be consistent with that of the polymer layer 22 . The first metal wire 13 and the second metal wire 14 are located between the polymer layer 22 and the second protection layer 15 , so that the first metal wire 13 and the second metal wire 14 are not easy to fall off from the polymer layer 22 and are more stable and firm.

[0068] In an optional embodiment, the second protective layer 15 has a first opening corresponding to the first metal wire 13, and the second protective layer 15 has a second opening corresponding to the second metal wire 14. The inner surfaces of the first opening and the second opening are sputtered with an under-bump metal layer 17, and the bumps 20 and the bumps 21 are both grown on the under-bump metal layer 17, so that the bumps 20 and the bumps 21 can be effectively combined with the side walls of the first opening or the second opening, which is more reliable and has a higher bonding strength than metal growing directly on the second protective layer 15.

[0069] The width of the second opening is smaller than the width of the second metal line 13 , and the distance between the edge of the second opening and the edge of the second metal line 13 is 2.5 um to 7 um, which is helpful for the opening of the second opening.

[0070] like Figure 2As shown, in other optional embodiments, a connection groove is opened on the polymer layer 22, a plug 18 is grown in the connection groove, the first metal wire 13 and the plug 18 fixedly connected to the first metal wire 13 are integrally arranged, and the second metal wire 14 and the plug 18 fixedly connected to the second metal wire 14 are integrally arranged, so that the connection between the first metal wire 13, the second metal wire 14 and the polymer layer 22 is more stable and reliable and not easy to fall off.

[0071] The cross section of the plug 18 is smaller than the cross section of the second metal line 14 , so when the bump 21 on the second metal line 14 is subjected to stress, the stress can be better transferred to the polymer layer 22 .

[0072] like Figure 3 As shown, in an optional embodiment, the present application also provides a semiconductor packaging structure, which includes the above-mentioned semiconductor structure. Specifically, the above-mentioned semiconductor structure is bonded to a substrate, and a plastic sealing layer 23 is formed on the periphery of the semiconductor structure. The plastic sealing layer 23 can be made of epoxy resin. The plastic sealing layer 23 wraps the metal bump 201 and the metal bump 211, and the solder layer 212 and the solder layer 202 pass through the plastic sealing layer 23 and are bonded to the substrate. The plastic sealing layer 23 can protect the bump 20 and the bump 21, and at the same time make it difficult for the semiconductor structure to fall off from the substrate.

[0073] like Figure 4 As shown, in other optional embodiments, a method for preparing a semiconductor structure is also provided, comprising the following steps:

[0074] Step S1: providing a substrate 10, on which a pad 11 is formed, such as Figure 5 shown.

[0075] Specifically, a chip is formed in the substrate 10, and the pad 11 is electrically connected to the chip. In an optional embodiment, step S1 specifically includes:

[0076] Step S101: cleaning the surface of the substrate 10 to remove surface particles and organic matter;

[0077] Step S102 : forming a plurality of pads 11 on the substrate 10 , and electrically connecting the pads 11 to the chip in the substrate 10 .

[0078] Step S2: forming a first protective layer 12 on the substrate 10, such as Figure 5-Figure 6 shown.

[0079] Step S2 specifically includes:

[0080] Step S201: forming a passivation layer 16 on the substrate 10, wherein the passivation layer 16 surrounds the edge of the pad 11;

[0081] Step S202 : forming a polymer layer 22 on the upper surface of the passivation layer 16 .

[0082] Specifically, the thickness of the polymer layer 22 is between 3-7 um, and may be 5 um. The polymer layer 22 is made of a polymer having certain elasticity and insulation, and may be a polyimide layer. In other embodiments, the polymer layer 22 may also be formed of epoxy resin, benzocyclobutene or polybenzoxazole.

[0083] Step S3: forming a connection plug in the first protection layer 12, and forming a redistribution layer on the upper surface of the first protection layer 12, the redistribution layer including a first metal line 13 and a second metal line 14; the connection plug is located in the first protection layer 12, the first metal line 13 is electrically connected to the pad 11 via the connection plug; the second metal line 14 is flush with the upper surface of the first metal line 13, and the second metal line 14 is not electrically connected. Figure 6-Figure 7 shown.

[0084] The specific step S3 includes the following steps:

[0085] Step S301: forming a connection opening in the first protective layer 12, wherein the connection opening exposes the pad, such as Figure 6 As shown;

[0086] Step S302: forming a connection plug in the connection opening, such as Figure 7 As shown:

[0087] Step S303: forming a first metal wire 13 and a second metal wire 14 on the upper surface of the first protective layer 12 by electroplating, wherein the first metal wire 13 is connected to the connecting plug. Figure 7 shown.

[0088] In this embodiment, the first metal wire 13 and the second metal wire 14 may be formed of copper. The second metal wire 14 does not contact the first metal wire 13 , and a buffering gap exists between the second metal wire 14 and the first metal wire 13 .

[0089] Step S4: forming a second protective layer 15 on the upper surface of the first protective layer 12, such as Figure 8 As shown;

[0090] Step S5 : forming a first opening and a second opening in the second protection layer 15 , wherein the first opening exposes the first metal line 13 , and the second opening exposes the second metal line 14 .

[0091] Specifically, Figure 8-Figure 9 As shown, in an optional embodiment, step S5 includes:

[0092] Step S501: Open the first opening and the second opening on the second protective layer 15 by exposure and development. Figure 8As shown;

[0093] Step S502: forming an under bump metallization layer 17 on the second protection layer 15 and the inner surface of the first opening and the inner surface of the second opening by sputtering. Fig. 9 As shown;

[0094] Step S503: coating a photoresist layer 19 on the under bump metal layer 17, and opening a first opening and a second opening in the photoresist layer 19 by exposure and development. Fig. 9 shown.

[0095] In this embodiment, the width of the second opening is smaller than the width of the second metal wire 13, the distance between the edge of the second opening and the edge of the second metal wire 13 is 2.5um~7um, the inner surface of the first opening includes the side wall and the bottom wall of the first opening, the inner surface of the second opening includes the side wall and the bottom wall of the second opening, and the thickness of the photoresist layer 19 is 50-60um, which can be 55um.

[0096] Step S6 : forming a bump 20 on the upper surface of the first metal wire 13 , and forming a bump 21 on the upper surface of the second metal wire 14 .

[0097] Specifically, Figure 10-11 As shown, in an optional embodiment, step S6 includes the following steps:

[0098] Step S601: electroplating the metal bump 201 and the metal bump 211 in the first opening and the second opening, forming a solder layer 202 on the metal bump 201, and forming a solder layer 212 on the metal bump 211, such as Fig.10 As shown;

[0099] Step S602: remove the photoresist layer 19, and etch the under bump metallization layer 17 sputtered on the second protective layer 15. Fig.11 As shown;

[0100] Step S603: reflow to make the solder layer 202 and the solder layer 212 into a ball shape, such as Fig.11 shown.

[0101] In this embodiment, the thickness of the second protection layer 15 is between 3-7um, and may be 5um. The metal bumps 201 and 211 may be formed of copper, and the solder layers 202 and 212 may be formed of tin or tin-silver alloy, etc. The height of the metal bumps 201 and 211 is between 25-40um, and may be 30um. The height of the solder layers 202 and 212 is between 15-30um, and may be 20um. The height of the bumps 20 and 21 may be 50um.

[0102] Since the second metal wire 14 and the first metal wire 13 are of the same height, the bumps 20 and 21 are formed in the same layer, so that the coplanarity of the bumps 20 and 21 is relatively high. The present application can eliminate the adverse effect of the second protective layer 15 on the coplanarity of the bumps 20 and 21. When the thickness of the second protective layer 15 is 5um and the height of the bumps 20 and 21 can be 50um, the coplanarity can be improved by 10%. The probability of poor wetting when the chip is flipped onto the substrate is reduced, and the reliability of the entire package is improved.

[0103] like Figure 12-13 As shown, in other optional embodiments, step S3 specifically includes the following steps:

[0104] Step S301: forming a connection opening and a through hole in the first protective layer 12, wherein the connection opening exposes the pad 11, such as Fig.12 As shown;

[0105] Step S302: forming a connection plug in the connection opening and forming a plug 18 in the through opening, such as Fig.13 As shown;

[0106] Step S303: forming a first metal line 13 and a second metal line 14 on the upper surface of the first protection layer 12; the first metal line 13 is connected to the connecting plug and part of the plug 18; the second metal line 14 is connected to the remaining plug 18, and the width of the first metal line 13 and the width of the second metal line 14 are both greater than the width of the plug 18, such as Fig.13 shown.

[0107] This embodiment obtains the following through the same steps as other embodiments: Fig.14 The semiconductor package structure shown has a plug 18, and the plug 18 makes the connection between the first metal wire 13 and the second metal wire 14 and the first protective layer 12 more stable and reliable and not easy to fall off. The cross section of the plug 18 is smaller than the cross section of the second metal wire 14, so when the bump 21 on the second metal wire 14 is subjected to stress, the stress can be better transferred to the first protective layer 12.

[0108] In summary, by forming the first metal wire 13 and the second metal wire 14 synchronously, the bump 20 and the bump 21 are equivalent to being formed on the same layer, the coplanarity of the bump 20 and the bump 21 is relatively high, and the second metal wire 14 is insulated from the pad 11. Therefore, the bump 21 formed on the second metal wire 14 does not play a conductive role. When the chip warps and generates stress, the stress is transferred to the first protective layer 12. In the flip chip of the present application, the bump 21 and the bump 20 have good coplanarity, which reduces the probability of poor wetting when flipping onto the substrate, thereby improving the reliability of the entire package.

[0109] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0110] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for those of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A pad located on the substrate; a first protective layer, covering a portion of the pad, the first protective layer comprising a polymer layer and a passivation layer, the passivation layer is located on an upper surface of the substrate, and the polymer layer is located on an upper surface of the passivation layer; a connecting plug, wherein the connecting plug is located in the first protective layer; A plurality of plugs, wherein the plugs penetrate the polymer layer along the thickness direction of the first protective layer; A redistribution layer is located on the first protective layer; the redistribution layer includes a first metal wire and a second metal wire; the first metal wire is connected to the connection plug and part of the plug, and the first metal wire is electrically connected to the pad via the connection plug; the second metal wire is connected to the remaining plugs; the second metal wire is flush with the upper surface of the first metal wire; the first metal wire is integrally arranged with the plug fixedly connected to the first metal wire, and the second metal wire is integrally arranged with the plug fixedly connected to the second metal wire; A second protection layer is located on an upper surface of the first protection layer and covers the redistribution layer; a first opening and a second opening are formed in the second protection layer, the first opening exposes the first metal line, and the second opening exposes the second metal line; The bump is located on the upper surface of the first metal wire and the second metal wire.

2. The semiconductor structure according to claim 1, characterized in that: It also includes an under-bump metallization layer, which is located on the inner surfaces of the first opening and the second opening and is in contact with the bump, the first metal wire and the second metal wire.

3. The semiconductor structure according to claim 1, characterized in that: A gap exists between the second metal line and the first metal line.

4. The semiconductor structure according to claim 1, characterized in that: The width of the second opening is smaller than the width of the second metal line, and the distance between the edge of the second opening and the edge of the second metal line is 2.5 um to 7 um.

5. The semiconductor structure according to claim 1, characterized in that: The width of the first metal line and the width of the second metal line are both greater than the width of the plug.

6. A method for preparing a semiconductor structure, characterized in that: The steps include: Providing a substrate, wherein a pad is formed on the substrate; forming a first protective layer on the substrate to cover a portion of the pad; A connection opening and a through opening are formed in the first protective layer, the connection opening exposes the pad, a connection plug is formed in the connection opening, a plug is formed in the through opening, and a redistribution layer is formed on the upper surface of the first protective layer, the redistribution layer includes a first metal wire and a second metal wire; the first metal wire is connected to the connection plug and part of the plug, the first metal wire is electrically connected to the pad via the connection plug; the second metal wire is connected to the remaining plugs, the second metal wire is flush with the upper surface of the first metal wire; the first metal wire is integrally arranged with the plug fixedly connected to the first metal wire, and the second metal wire is integrally arranged with the plug fixedly connected to the second metal wire; forming a second protective layer on the upper surface of the first protective layer; forming a first opening and a second opening in the second protection layer, wherein the first opening exposes the first metal line, and the second opening exposes the second metal line; Bumps are formed on upper surfaces of the first metal line and the second metal line.

7. The preparation method according to claim 6, characterized in that: Forming a first protective layer on the substrate comprises: forming a passivation layer on the upper surface of the substrate; A polymer layer is formed on the passivation layer.

8. The preparation method according to claim 7, characterized in that: The width of the second opening is smaller than the width of the second metal line, and the distance between the edge of the second opening and the edge of the second metal line is 2.5 um to 7 um.

9. The preparation method according to claim 7, characterized in that: After forming the first opening and the second opening in the second protective layer and before forming the bump, the method further includes the following steps: An under-bump metallization layer is formed on the inner surfaces of the first opening and the second opening, and the under-bump metallization layer is in contact with both the first metal line and the second metal line; the bump is formed on the surface of the under-bump metallization layer.

10. The preparation method according to claim 6, characterized in that: The width of the first metal line and the width of the second metal line are both greater than the width of the plug.

11. A semiconductor packaging structure, characterized in that: The semiconductor package structure comprises the semiconductor structure according to claims 1-5.

12. The semiconductor package structure according to claim 11, characterized in that: The semiconductor structure is flipped on a substrate, the bump is attached to the substrate, a plastic sealing layer is formed on the periphery of the semiconductor structure, and the plastic sealing layer wraps the bump.

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