Method for forming a semiconductor device

Abstract

The present invention is titled "Method of forming a semiconductor device". In one embodiment, a method of forming a neural network circuit may include forming a dielectric layer over a semiconductor substrate having active devices formed in the semiconductor substrate. An opening may be formed in the dielectric layer, and a resistor and a diode connected in series may be formed within the opening.

Description

Technical Field

[0001] The present invention generally relates to electronic devices, and more particularly, to semiconductors, semiconductor structures, and methods of forming semiconductor devices. Background Art

[0002] In the past, various methods and structures have been utilized to form neuromorphic systems. These neuromorphic systems typically include digital processing computers, memory storage devices such as random access memories, neural networks, and other associated computer architecture components. The digital processing computer accesses the memory storage device to retrieve setup information. The digital computer also reads information from the neural network and processes the information using computer algorithms and other information from the memory storage device.

[0003] Due to the computing time required for the computer to access the memory storage device and access the neural network, as well as the time required for the computer to execute algorithms using the information from the neural network, these neuromorphic systems typically respond slowly to input signals.

[0004] Neuromorphic systems are also expensive due to the space required to form a digital computer architecture including a memory storage device and a digital processing computer.

[0005] Accordingly, there is a desire for a neuromorphic system that processes information faster, is less costly, or occupies less space on a semiconductor device. Brief Description of the Drawings

[0006] Figure 1 An example of a portion of a neuromorphic system including a neural network circuit in accordance with the present invention is shown in a general manner;

[0007] Figure 2 An example of a portion of an embodiment of a neural network circuit in accordance with the present invention is schematically shown, which neural network circuit can have an embodiment that can be an alternative embodiment of the Figure 1 neural network circuit;

[0008] Figure 3 An enlarged cross-sectional portion showing an example of an embodiment of a semiconductor device in accordance with the present invention, which semiconductor device includes an example of an embodiment of a neural network circuit that can have an embodiment that can be an alternative embodiment of the Figure 2 neural network circuit;

[0009] Figure 4 An enlarged cross-sectional portion showing an example of an embodiment of a via that can be a portion of a circuit in accordance with the present invention and can be Figure 3 ; and

[0010] Figure 5An enlarged cross-sectional portion showing an example of an embodiment of a semiconductor device according to the present invention, the semiconductor device may have an embodiment that may be an alternative embodiment of a device as Figure 2 or Figure 3 ; an embodiment of the device;

[0011] For clarity and conciseness of the drawings, the elements in the figures are not necessarily drawn to scale, some elements may be exaggerated for illustrative purposes, and like reference numerals in different figures indicate like elements unless otherwise specified. In addition, to simplify the description, the description and details of well-known steps and elements may be omitted. As used herein, a current-carrying element or current-carrying electrode means an element of a device that carries the current passing through the device, such as the source or drain of a MOS transistor or the emitter or collector of a bipolar transistor or the cathode or anode of a diode, while a control element or control electrode means an element of a device that controls the current passing through the device, such as the gate of a MOS transistor or the base of a bipolar transistor. Additionally, one current-carrying element may carry a current passing through the device in one direction, such as a current entering the device, while a second current-carrying element may carry a current passing through the device in the opposite direction, such as a current leaving the device. Although the device may be described herein as certain N-channel or P-channel devices or certain N-type or P-type doped regions, one of ordinary skill in the art will understand that complementary devices according to the present invention are also possible. One of ordinary skill in the art understands that the conduction type refers to the mechanism by which conduction occurs, such as through holes or electron conduction, and thus, the conduction type does not refer to the doping concentration but to the doping type, such as P-type or N-type. Those skilled in the art should understand that the terms "during", "simultaneously with", and "when" used herein in relation to circuit operation do not exactly mean that an action occurs immediately after the triggering action, but rather that there may be some small but reasonable delays between the reactions triggered by the initial action, such as various propagation delays. Additionally, the term "simultaneously with" means that an action occurs at least for a period of time during the duration of the triggering action. The use of the words "about" or "substantially" means that the value of an element has a parameter that is expected to be close to the stated value or position. However, as is well known in the art, there are always minor differences that prevent the value or position from being exactly the stated value or position. It is recognized in the art that a deviation of up to at least ten percent (10%) (and for some elements including semiconductor doping concentrations, up to twenty percent (20%)) is a reasonable deviation from the ideal target as exactly described. When used in relation to signal states, the term "active" means the active state of a signal, while the term "inactive" means the inactive state of a signal. The actual voltage value or logical state of a signal (such as "1" or "0") depends on whether positive logic or negative logic is used. Thus, if positive logic is used, a high voltage or high logic may be active, and if negative logic is used, a low voltage or low logic may be active; and if positive logic is used, a low voltage or low state may be inactive, and if negative logic is used, a high voltage or high logic may be inactive. In this document, a positive logic convention is used, but those skilled in the art understand that a negative logic convention may also be used.The terms "first", "second", "third", etc. (as used in a part of an element name) in the claims and / or the detailed description are used to distinguish between similar elements and do not necessarily describe an order in time, space, rank, or any other manner. It should be understood that the terms used in this way are interchangeable where appropriate, and the embodiments described herein are capable of operating in an order other than that described or illustrated herein. Referring to "an embodiment" means that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the present invention. Thus, the phrase "in an embodiment" that appears in different places throughout this specification does not necessarily refer to the same embodiment, but in some cases, it may refer to the same embodiment. Additionally, as will be apparent to those of ordinary skill in the art, in one or more embodiments, the specific features, structures, or characteristics may be combined in any suitable manner. For clarity of illustration in the drawings, the doped regions of the device structure are shown as having substantially straight edges and corners of precise angles. However, those skilled in the art understand that due to the diffusion and activation of dopants, the edges of the doped regions are generally not straight and the corners are not of precise angles.

[0012] The embodiments described and illustrated below may lack any element not specifically disclosed herein and / or may be practiced in the absence of any element not specifically disclosed herein. Detailed Description

[0013] Figure 1 An example of a portion of a neuromorphic system 10 including a neural network circuit 14 is shown in a general manner. The system 10 includes a signal device or signal circuit 12 that receives an external stimulus such as light or sound, for example, and generates an electrical signal representative of the external stimulus. The signal circuit 12 provides the electrical signal to the circuit 14, which processes the electrical signal to form an electrical output signal that identifies the information formed by the external stimulus. An interpretation circuit 15 receives the electrical output signal from the circuit 14 and forms an image or signal that can be understood by a user of the system 10.

[0014] Figure 2 An example of a portion of an embodiment of a neural network or neural network circuit 17 is schematically shown, which may have an embodiment that can be an alternative embodiment of the Figure 1 circuit 14. The circuit 17 includes a plurality of input portions 18 - 24 that are configured to receive electrical signals from a signal transmitting device, such as, for example, from Figure 1The circuit 12 receives an electrical signal. Circuit 17 also includes a first synaptic stage 25, which includes a first plurality of synaptic units or synaptic circuits 26 - 41. At least some of the circuits 26 - 41 may be configured to receive one of the input signals, and one embodiment may include each of the circuits 26 - 41 being configured to receive an input signal from one or more of the input units 18 - 24. Circuit 17 also includes a first multiply-accumulate (MAC) stage 65, which includes a plurality of MAC circuits 67 - 72. Each of the circuits 67 - 72 is configured to receive an output from one or more of the circuits 26 - 41, and some of the circuits 67 - 72 may be configured to receive outputs from two or more of the circuits 26 - 41.

[0015] An embodiment of circuit 17 may include a second synaptic stage 75, which includes a plurality of synaptic units or synaptic circuits 78 - 86, each synaptic unit or synaptic circuit being configured to receive an input from the output of circuits 67 - 72.

[0016] In one embodiment, circuit 17 may also include a second multiply-accumulate (MAC) stage 90, which includes a plurality of MAC circuits 93 - 95. Circuits 93 - 95 may be configured to receive an output from one of the circuits 78 - 86, and one embodiment may include at least one of the circuits 93 - 95 being configured to receive outputs from two or more of the circuits 78 - 86.

[0017] Each of the synaptic circuits 26 - 41 and 78 - 86 includes a resistor connected in series with a diode. For example, circuit 26 may include a resistor 44 connected in series with a diode 45, and circuit 27 may include a resistor 47 connected in series with a diode 48. As will be seen further below, one embodiment may include each of the resistors in circuits 26 - 41 and 78 - 86 having a substantially fixed value, but the value of any one resistor may be different from the value of another resistor. For example, resistor 44 may have a fixed resistance different from the fixed resistance of resistor 47. One embodiment may include some of the resistors having substantially the same value. One embodiment may include each of the circuits 67 - 72 and 93 - 95 being a conductor that connects the output of two or more of the corresponding circuits 26 - 41 and 78 - 86 together. For example, circuit 68 may have an embodiment as a conductor that directly connects the outputs of circuits 27, 29, and 31 to each other.

[0018] In one embodiment, each synaptic portion or synaptic circuit at synapse levels 25 and 75 receives a signal and multiplies the signal by the weight of that synaptic portion. One embodiment may include that the weight of the synaptic portion or synaptic weight may be the conductance coefficient due to the elements therein. One embodiment may include that the weight of each synaptic portion is the reciprocal of the resistance of the resistor of the synaptic portion. For example, the weight of synaptic portion or synaptic circuit 26 may be the value 1 divided by the value of resistor 44 (1 / R44).

[0019] In one embodiment, each of circuits 67 - 72 and 93 - 95 may be configured to sum together the values of the signals connected to the output portions of circuits 67 - 72 and 93 - 95. For example, assume that each of input portions 18 - 24 receives an electrical signal. In some embodiments, the input signal may be an analog signal from circuit 12( Figure 1 ). Input portion 18 is connected to the input portion of circuit 26 and to the input portion of circuit 27. Synaptic portion 26 multiplies the input signal by the weight of synaptic portion 26, and synaptic circuit 27 multiplies the input signal by the weight of synaptic portion 27. The value of the signal on input portion 18 causes a current to flow through resistor 44 and diode 45 to circuit 67. The input signal also causes another current to flow through resistor 47 and diode 48 to circuit 68. In one embodiment, the value of resistor 44 may be different from the value of resistor 47, and thus, different current values may flow through circuits 26 and 27.

[0020] Similarly, the signal received on input portion 19 causes a current to flow through circuit 28 to circuit 67, causes another current to flow through circuit 29 to circuit 68, and causes a third current to flow through circuit 30 to circuit 69.

[0021] The current from circuit 26 and the current from circuit 28 are summed together by circuit 67, and the currents from circuits 27, 29, and 31 are summed together at circuit 68. Thus, circuit 68 sums the currents from circuits 27, 29, and 31, circuit 69 sums the currents from circuits 30, 32, and 33, circuit 70 sums the currents from circuits 34, 35, and 37, circuit 71 sums the currents from circuits 36, 38, and 40, and circuit 72 sums the currents from circuits 39 and 41. Thus, circuits 67 - 72 accumulate the results of multiplying the input signals by the weights of the corresponding synaptic portions.

[0022] The output signal formed by circuits 67 - 72 becomes the input signal to circuits 78 - 86. Circuit 78 receives the output signal from circuit 67, circuits 79 - 80 receive the output signal from circuit 68, circuits 81 - 82 receive the output signal from circuit 69, circuits 83 - 84 receive the output signal from circuit 70, circuit 85 receives the output signal from circuit 71, and circuit 86 receives the output signal from circuit 72.

[0023] Circuits 93 - 95 receive output signals such as, for example, current from circuits 78 - 86 and form corresponding output signals at output portions 97 - 99. Circuit 93 receives outputs such as, for example, current from circuits 78 - 79 and 81 and sums them together to form an output signal at output portion 97. Circuit 94 sums together output signals such as, for example, current from circuits 80 and 82 - 83 to form an output signal at output portion 98, and circuit 95 sums together output signals such as, for example, current from circuits 84 - 86 to form an output signal at output portion 99. Thus, circuits 93 - 95 accumulate the results of multiplying the input signals to synaptic portions 78 - 86 by the weights of the corresponding synaptic portions.

[0024] Those skilled in the art will understand that the input signals received at input portions 18 - 24 may be analog signals, and the signals formed by the circuits of circuit 17 may also be analog signals. However, some embodiments may include that the signals received at input portions 18 - 24 may be digital signals, and the signals formed by circuit 17 may represent digital signals. For example, the current formed by the circuits of circuit 17 may represent a digital value.

[0025] Figure 3 An example of an enlarged cross - sectional portion showing an embodiment of a semiconductor device 102 including a neural network circuit 104, which neural network circuit may have an embodiment that may be a physical implementation of circuit 17 as Figure 2 an example of an embodiment. Device 102 includes a semiconductor substrate 106 having a doped region or doped layer 107 formed on or in the substrate 106. Doped regions 109 and 110 may be formed within region 107 to form active regions of active semiconductor devices such as transistors or diodes or alternative portions of passive semiconductor elements and circuits. Embodiments of device 102 may also include isolation regions 111 formed in region 107 to isolate certain portions of the active regions and active elements from each other. The neural network circuit 104 is formed on or alternatively covers the substrate 106 and region 107. In one embodiment, the output signal from circuit 104 may be coupled to different active portions of device 102.

[0026] The circuit 104 includes input portions 115-119, which may have embodiments that can be alternative embodiments of the corresponding input portions 18-22 as Figure 2 . The circuit 104 also includes a first synaptic stage 133, which may have an embodiment that can be substantially similar to Figure 2 stage 25. The first synaptic stage 133 includes a dielectric layer 124 and synaptic vias 135-145, which are formed within the layer 124 and, in one embodiment, are formed to pass through the layer 124. One or more dielectric layers and the openings for the vias 135-145 therein can be formed using well-known semiconductor manufacturing techniques. Each of the vias 135-145 may have a synaptic circuit formed therein. For example, circuits 26-27 may be formed within the corresponding vias 135-136, circuits 28-30 may be formed within the corresponding vias 138, 137, and 139, circuits 31-32 may be formed within the corresponding vias 141 and 140, circuits 33-34 may be formed within the corresponding vias 142-143, and circuits 35-36 may be formed within the corresponding vias 144-145. Those skilled in the art will understand that, for simplicity of the drawings, Figure 3 all the synaptic circuits not shown in Figure 2 . Thus, circuits 37-41 ( Figure 3 ) are not shown in Figure 2 .

[0027] An embodiment of the circuit 104 may further include an input layer 120 for routing input signals from the input portions 115-119 to the synaptic circuits formed in the vias 135-145. The layer 120 includes dielectric layers 122-123 and routing conductors 126-130. The conductors 126-130 are used to connect the synaptic circuits to receive input signals from the input portions 115-119. For example, the input portion 115 is connected to the routing conductor 126, which is connected to the input portions of the synaptic circuits within the vias 135 and 136. Similarly, the input portion 116 is connected to the routing conductor 127, which is connected to the input portions of the synaptic circuits within the vias 137-139 to connect the synaptic circuits to receive input signals. In a similar manner, the input portion 117 is connected to the routing conductor 128, which is connected to the input portions of the synaptic circuits within the vias 140 and 141. Additionally, the input portion 118 is connected to the routing conductor 129, which is connected to the input portions of the synaptic circuits within the vias 142-143 to connect the synaptic circuits to receive input signals from the input portion 118. Furthermore, the input portion 119 is connected to the routing conductor 130, which is connected to the input portions of the synaptic circuits within the vias 144-145 to connect the synaptic circuits to receive input signals from the input portion 119.

[0028] Those skilled in the art will understand that in other embodiments, fewer dielectric layers and conductors may be required to route the input signal from the input section to the synaptic circuits within vias 135 - 145.

[0029] Circuit 104 also includes a MAC stage 148, which may have embodiments that are alternative embodiments of stage 65 as Figure 2 shown. Stage 148 may include MAC circuits 155, 160, 169, and 175, which may have embodiments that are alternative embodiments of circuits 67, 68, 69, and 70, respectively. Stage 148 includes a dielectric layer or alternatively a plurality of dielectric layers, on which conductors are formed to interconnect the output portions of circuits 26 - 41. In one embodiment, circuits 67 - 72 may each be independent conductors. The conductor may be a metal conductor, a doped polysilicon conductor, or a conductor of silicide or silicide material, or other well-known conductor materials. One or more dielectric layers and conductors for circuits 155, 160, 169, and 175 may be formed using well-known semiconductor manufacturing techniques.

[0030] Those skilled in the art will understand that, for purposes of showing routing and interconnectivity, stage 148 is shown as a plurality of dielectric layers 149 - 153 on which conductors are formed to show the routing and interconnectivity to the circuits within the vias to stage 133. However, those skilled in the art will understand that routing may be achieved using one dielectric layer in which the conductors are routed across the dielectric layer. Thus, layers 149 - 153 may be considered as one dielectric layer having a plurality of independent conductors.

[0031] Accordingly, to illustrate routing and interconnectivity, circuit 155 is shown as including a vertical conductor portion 156 and having a horizontal conductor portion 157. The vertical conductor portion is connected to via 135 and to the output of circuit 26, and the horizontal conductor portion routes circuit 155 to connect to via 138 and to the output of circuit 28, thereby connecting the outputs of vias 135 and 138 (and the outputs of circuits 26 and 28) together. Similarly, circuit 160 includes a vertical connector portion 161 and a lateral routing conductor portion 162. The vertical connector portion is electrically connected to vias 136 - 137 and to the outputs of respective circuits 27 and 29, and the lateral routing conductor portion provides interconnectivity with via 141 and with the output of circuit 31, thereby connecting the outputs of vias 136, 137, and 141 (and the outputs of circuits 27, 29, and 31) together. Circuit 160 is also shown as including a via portion 164 that has a dielectric within the via that isolates circuit 160 from the routing portion 157 of circuit 155. Similarly, circuit 169 is shown as having a vertical connector portion 170 and a lateral routing conductor portion 171. The vertical connector portion is connected to vias 139 and 140 and to the outputs of circuits 30 and 32, and the lateral routing conductor portion is connected to via 142 and to the output of circuit 33, thereby connecting the outputs of circuits 30 and 32 - 33 together. Circuit 169 is also shown as including a via portion 172 that has a dielectric within the via that isolates circuit 169 from the routing portion 162 of circuit 160. Circuit 175 includes a conductor 176 that is connected to vias 143 - 144 and to the outputs of circuits 34 - 35, thereby connecting the outputs of vias 143 - 144 (and the outputs of circuits 34 - 35) together. Those skilled in the art will understand that multiple dielectric layers are shown to illustrate the interconnectivity, and in other embodiments, a single dielectric layer rather than multiple dielectric layers 149 - 153 may be used to achieve this connection.

[0032] An embodiment of circuit 104 may also include a second synaptic stage 180, which may have Figure 2An embodiment of an alternative embodiment of stage 75. The second synaptic stage 180 includes a dielectric layer 179 and synaptic vias 181-188 that are formed within layer 179 and, in one embodiment, are formed to pass through layer 179. Each of the vias 181-188 may have synaptic circuitry formed within the via. For example, circuitry 78 may be formed within via 181, circuitry 79-80 may be formed within respective vias 182-183, circuitry 81-82 may be formed within respective vias 184-185, circuitry 83-85 may be formed within respective vias 186-188, etc. One or more dielectric layers and the openings therein for vias 181-188 may be formed using well-known semiconductor manufacturing techniques. Those skilled in the art will understand that, for simplicity of the drawings, not all synaptic circuitry of stage 75 in stage 180 is shown Figure 2 and thus Figure 3 circuitry 86 is not shown in Figure 2 ).

[0033] In one embodiment, circuitry 104 may further include a second MAC stage 190 that may have an embodiment that is an alternative embodiment of stage 90 as Figure 2 . Stage 190 may include MAC circuits 194, 198, and 204 that may have embodiments that are alternative embodiments of circuits 93-95, respectively. Stage 190 includes a dielectric layer or alternatively includes a plurality of dielectric layers on which conductors are formed to interconnect the outputs of circuits 78-86. In one embodiment, circuits 93-95 or alternatively respective circuits 194, 198, and 204 may each be independent conductors. The conductor may be a metal conductor or a doped polysilicon conductor, or a conductor of silicide or silicide material, or other well-known conductor materials. One or more dielectric layers and the conductors for circuits 93-95 or alternatively respective circuits 194, 198, and 204 may be formed using well-known semiconductor manufacturing techniques.

[0034] Those skilled in the art will understand that, for purposes of showing routing and interconnectivity, stage 190 is shown as a plurality of dielectric layers 191-193 on which conductors are formed to show the routing and interconnect to the circuitry within the vias of stage 190. However, those skilled in the art will understand that routing may be achieved using one dielectric layer in which the conductors are routed across the dielectric layers. Thus, layers 191-193 may be considered to be one dielectric layer having a plurality of independent conductors.

[0035] Accordingly, to illustrate the routing and interconnectivity provided by stage 190, circuit 194 is shown as including a vertical conductor portion 195 and a horizontal conductor portion 196. The vertical conductor portion is connected to the outputs of vias 181 and 182 and the outputs of circuits 78 - 79. The horizontal conductor portion routes circuit 194 to the output of via 184 and to the output of circuit 81, thereby connecting the outputs of vias 181 - 182 and 184 (and the outputs of circuits 78 - 79 and 81) together. Similarly, circuit 198 includes a vertical connector portion 199 and a lateral routing conductor portion 200. The vertical connector portion is electrically connected to the output of via 183 and to the output of circuit 80. The lateral routing conductor portion provides interconnectivity with the outputs of vias 185 and 186 and with the outputs of circuits 82 - 83, thereby connecting the outputs of vias 183 and 185 - 186 (and the outputs of circuits 80 and 82 - 83) together. Circuit 198 is also shown as including a via portion 197 that has a dielectric within portion 197 that isolates circuit 198 from the routing portion 196 of circuit 194. Similarly, circuit 204 is shown as having a vertical connector portion 205 that connects to the outputs of vias 187 - 188 and the outputs of circuits 84 - 85, thereby connecting the outputs of vias 187 - 188 (and the outputs of circuits 84 - 85) together. Those skilled in the art will understand that multiple dielectric layers are shown to illustrate routing interconnects, and in other embodiments, a single dielectric layer rather than multiple dielectric layers 191 - 193 may be used to implement the routing connectors.

[0036] In one embodiment, circuits 194, 198, and 204 may form the output signals of circuit 104. Accordingly, circuits 194, 198, and 204 may be connected to the active and / or passive circuits of device 102. For example, one or more of circuits 194, 198, and 204 may be connected to the active circuits of layer 107 to provide input signals to the active devices of layer 107, as generally shown by the dashed lines.

[0037] Those skilled in the art will understand that a digital computer processor or digital arithmetic unit is not required or used to form the output signal of circuit 17, so circuit 17 has a very fast response time to the input signal received at the input section. Since a digital computer is not used, a computer memory circuit is not required to store synaptic weights or data or programs, thereby further reducing costs and improving the response time. Not using a digital computer also reduces the amount of area used on semiconductor devices, thus reducing costs. Additionally, the synaptic circuits of circuit 17 are not formed in an X-Y matrix, so no selection transistors or switching elements are required to select the row lines and column lines of the X-Y matrix. This also reduces the cost of circuit 17. Since each synaptic circuit has a resistor with a fixed resistance, a digital computer is not required to read data from the synaptic circuit, which also improves the response time and reduces costs.

[0038] Since the weight of each synaptic section is a fixed value, once circuit 17 has been physically created, the weight cannot be changed. Thus, circuit 17 is suitable for inference applications, but circuit 17 cannot be used for backpropagation.

[0039] Figure 4 An enlarged cross-sectional portion showing an example of an embodiment of via 135 and circuit 26 formed therein. Layer 124 may be formed on or alternatively cover substrate 106. An opening may be formed through layer 124. Diode 45 may be formed within the opening. For example, a layer 210 of doped polysilicon may be formed within the opening, and another layer 212 of doped polysilicon may be formed on layer 210. Layers 210 and 212 may be doped with opposite conduction types so as to form a junction 211 near or at the interface of layers 210 and 212. Resistor 44 may also be formed within the opening of via 135. For example, an additional layer 214 of doped polysilicon may be formed on layer 212 to form resistor 44. Layer 212 may be doped with the same conduction type as layer 212 and a doping concentration providing the resistance required for resistor 44. In one embodiment, conductor materials 217 and 216 may be formed at opposite ends of the opening of via 135 to provide a simple electrical connection to circuit 26. The dielectric layer of device 102 and the materials within the opening may be formed by well-known semiconductor manufacturing techniques including atomic layer deposition.

[0040] Those skilled in the art will understand that resistor 44 and diode 45 may be formed of other materials. For example, an embodiment of diode 45 may be formed of silicon nitride in contact with a conductor. The conductor may be tantalum nitride (Ta x N y) or other known materials that form a diode junction. One embodiment may include forming diode 45 from zinc oxide (ZnO) in contact with a conductor. The conductor may be silver (Ag), gold (Au), or a combination of gold and titanium (AuTi). In one embodiment, the material of diode 45 may form a Schottky diode. Resistor 44 may have an embodiment formed from nickel oxide (NiO) in contact with a conductor. The conductor may be gold (Ag), platinum (Pt), or other well-known materials that form a diode with nickel oxide. The resistor embodiment may be formed from tantalum oxide (TaO x ) or other equivalent materials. Examples of embodiments may include NiO or TaO x that may be placed between two conductors. In one embodiment, materials and methods used therein in a semiconductor backend of line (BEOL) processing facility may be used to form circuit 17. One embodiment may include that some of the resistor materials may individually or in combination have a variable state. However, embodiments of circuit 10 and / or circuit 17 may be formed to not have (or lack) a circuit for programming or changing the material state. Thus, the state is set or established or programmed once during the manufacturing process. Thus, the value of the resistor remains fixed. For example, current or voltage pulses may be applied by BEOL methods or manufacturing processes.

[0041] Figure 5 An enlarged cross-sectional portion showing an example of an embodiment of semiconductor device 302, which includes at least a portion of a neural network circuit that may have an embodiment as an alternative embodiment of device 102 that may be used as Figure 2 Device 302 has a single synaptic stage 133 and a single accumulation stage 148, rather than multiple synaptic and accumulation stages of device 102. In one embodiment, circuits 155, 160, 169, and 175 may form the output signal of circuit 302. Thus, circuits 155, 160, 169, and 175 may be connected to the active and / or passive circuits of device 302. For example, one or more of circuits 155, 160, 169, and 175 may be connected to the active circuit of layer 107 to provide an input signal to the layer, as generally shown by lines from circuit 155 to region 107, from circuit 164 to regions 109 and 107, from circuit 169 to region 110, and from circuit 175 to region 110.

[0042] Those skilled in the art will understand that embodiments of methods of forming a semiconductor device having a neural network may include:

[0043] Provide a semiconductor substrate such as substrate 106 on which a doped layer such as layer 107 is formed, the doped layer having a plurality of doped regions such as regions 109 / 110, the plurality of doped regions being part of the active region of a semiconductor device;

[0044] Form a first dielectric layer covering the doped layer, such as layer 134;

[0045] Form a plurality of first synaptic circuits in the first dielectric layer, including: forming a plurality of vias in the first dielectric layer and forming a first synaptic circuit in each first via, such as one of the circuits 135 - 145, wherein each first synaptic circuit includes a first diode connected in series with a resistor having a substantially fixed resistance;

[0046] Form an input portion of each first synaptic circuit to receive an input signal among a plurality of input signals;

[0047] Form a second dielectric layer under the first dielectric layer, such as layers 149 - 152, the second dielectric layer including a plurality of first accumulation nodes such as nodes 155 / 160 / 169, wherein each first accumulation node is connected to receive output signals from two or more of the first synaptic circuits; and

[0048] Form a third dielectric layer under the second dielectric layer, such as layer 179; and

[0049] Form a plurality of second vias such as vias 181 - 188 in the third dielectric layer and form a second synaptic circuit in each second via, such as one of the circuits in vias 181 - 188, wherein each second synaptic circuit includes a second diode directly connected in series with a second resistor having another substantially fixed resistance, and each first accumulation node is connected to the input portions of two or more second synaptic circuits.

[0050] One embodiment may include that forming the second dielectric layer includes forming each first accumulation node as a conductor.

[0051] The method may have an embodiment that may include forming a first conductor that is connected to the output portion of the first of the plurality of first synaptic circuits and is connected to the output portion of the second of the plurality of first synaptic circuits.

[0052] In one embodiment, the method may include forming a second conductor that is generally directly connected to the output portion of the third of the plurality of first synaptic circuits and is connected to the output portion of the fourth of the plurality of first synaptic circuits.

[0053] An embodiment may include forming a first metal conductor and forming a second metal conductor, the first metal conductor being directly connected to the output portions of two or more of a plurality of first synaptic circuits, and the second metal conductor being directly connected to the output portions of a different two or more of the plurality of first synaptic circuits.

[0054] The method may have an embodiment that may include forming a first resistor from doped polysilicon.

[0055] An embodiment may include forming a diode from a doped polysilicon material.

[0056] In one embodiment, atomic layer deposition may be used to form the diode.

[0057] Another embodiment may include forming a conductor within one of a plurality of first vias, wherein the conductor is directly connected to a first synaptic circuit to receive an input signal.

[0058] Those skilled in the art will also understand that embodiments of a neural network circuit may include:

[0059] Two or more input portions, such as, for example, input portions 19 - 20, wherein a first input portion receives a first input signal and a second input portion receives a second input signal;

[0060] A first set of two or more synaptic circuits, such as, for example, circuits 29 - 31, and a second set of two or more synaptic circuits, such as, for example, circuits 36 - 37, the first set of two or more synaptic circuits being connected to receive the first input signal and the second set of two or more synaptic circuits being connected to receive the second input signal, wherein each of the first set of two or more synaptic circuits and the second set of two or more synaptic circuits includes a resistor of a substantially fixed value connected in series with a diode;

[0061] A first accumulation node, such as, for example, node 68, the first accumulation node being connected to receive a first output signal from a first synaptic circuit, such as, for example, circuit 30, of the first set of two or more synaptic circuits and a second output signal from a second synaptic circuit, such as, for example, circuit 36, of the second set of two or more synaptic circuits, the first accumulation node being configured to add the first output signal to the second output signal to form a first accumulation signal, wherein the first accumulation node is a conductor; and

[0062] A second summing node, such as node 69 for example, is connected to receive a third output signal from a third synaptic circuit, such as circuit 31 for example, among the first set of two or more synaptic circuits, and to receive a fourth output signal from a fourth synaptic circuit, such as circuit 37 for example, among the second set of two or more synaptic circuits. The second summing node is configured to add the third output signal to the fourth output signal to form a second summing signal.

[0063] One embodiment may include a third set of two or more synaptic circuits, such as circuits 79 - 80 for example, and a fourth set of two or more synaptic circuits, such as circuits 81 - 82 for example. The third set of two or more synaptic circuits is connected to receive a first summing signal, and the fourth set of two or more synaptic circuits is connected to receive a second summing signal. Each of the third set of two or more synaptic circuits and the fourth set of two or more synaptic circuits includes a resistor of a substantially fixed value connected in series with a diode.

[0064] In one embodiment, the circuit may include a third summing node, such as node 93 for example, which is connected to receive a fifth output signal from a fifth synaptic circuit, such as at node 79 for example, among the third set of two or more synaptic circuits, and to receive a sixth output signal from a sixth synaptic circuit, such as circuit 81 for example, among the fourth set of two or more synaptic circuits. The third summing node is configured to add the fifth output signal to the sixth output signal to form a third summing signal.

[0065] One embodiment may include a fourth summing node, such as node 94 for example, which is connected to receive a seventh output signal from a seventh synaptic circuit, such as circuit 80 for example, among the third set of two or more synaptic circuits, and to receive an eighth output signal from an eighth synaptic circuit, such as circuit 82 for example, among the fourth set of two or more synaptic circuits. The third summing node is configured to add the seventh output signal to the eighth output signal to form a fourth summing signal.

[0066] In one embodiment, the circuit may include forming the first set of two or more synaptic circuits and the second set of two or more synaptic circuits within vias in a first dielectric layer.

[0067] In one embodiment, the first summing node and the second summing node may be formed on a second dielectric layer below the first dielectric layer.

[0068] One embodiment may include forming the third synaptic circuit and the fourth synaptic circuit within vias in a third dielectric layer located below the second dielectric layer.

[0069] Those skilled in the art will understand that embodiments of a method of forming a neural network may include:

[0070] Form a first dielectric layer, such as layer 191, over a semiconductor substrate such as, for example, substrate 106 and / or layer 107, the semiconductor substrate having a plurality of active semiconductor devices formed therein;

[0071] Form a first plurality of accumulation node conductors on the first dielectric layer, such as conductors 193 / 199;

[0072] Form a second dielectric layer over the first dielectric layer, such as layer 179;

[0073] Form a plurality of first vias in the second dielectric layer, such as vias 182 - 185; and

[0074] Form a first circuit in each of the plurality of first vias, including forming each first circuit to include a diode in series with a resistor, such as the diode of synaptic section 78, and forming each resistor having a substantially fixed resistance.

[0075] The method may have an embodiment that may include forming a first diode and a first resistor, such as the resistor in via 181, in a first via, such as via 181, of the plurality of first vias, and forming a second diode and a second resistor, such as the resistor in via 183, in a second via, such as via 183, of the plurality of first vias, wherein the first resistor has a value different from that of the second resistor.

[0076] The method may have an embodiment that may include forming one of a first resistor or a first diode directly connected to a first accumulation node conductor, such as conductor 193 or 93, of the first plurality of accumulation node conductors, and forming one of a second resistor or a second diode directly connected to a second accumulation node conductor, such as conductor 199 or 98, of the first plurality of accumulation node conductors.

[0077] One embodiment may include forming a first accumulation node conductor to receive output signals from a first group of two or more first circuits substantially simultaneously, and forming a second accumulation node conductor to receive different output signals from a second group of two or more first circuits.

[0078] In view of all of the above, it is apparent that a novel device and method are disclosed. Among other features, it includes forming a neural network and its synaptic circuits, directly accumulating the output signals of the synaptic circuits. Additionally, each synaptic circuit receives input signals and directly forms corresponding output signals, which helps reduce the response time of the neural network circuit. Not using a digital computer or a digital arithmetic unit reduces cost and improves the response time of the neural network.

[0079] While the subject matter of this specification has been described by way of specific preferred and exemplary embodiments, the foregoing drawings and description of the specification depict only typical and non - limiting examples of the embodiments of the subject matter, and thus the foregoing drawings and description are not to be regarded as limiting its scope. For those skilled in the art, many alternatives and variations will be obvious.

[0080] As reflected in the claims below, aspects of the invention may have less than all of the features of a single embodiment disclosed above. Accordingly, the claims set forth below are hereby expressly incorporated into the description of the drawings, and each claim by itself represents a separate embodiment of the invention. Moreover, although some embodiments described herein include some features contained in other embodiments, but not other features contained therein, those skilled in the art should understand that combinations of features of different embodiments are intended to be within the scope of the invention and are intended to form different embodiments.

Claims

1. A semiconductor device having a neural network, the semiconductor device comprising: A semiconductor substrate having a doped layer formed on the semiconductor substrate, the doped layer having a plurality of doped regions that are part of the active region of the semiconductor device; A first dielectric layer covering the doped layer; A first plurality of vias through the first dielectric layer; A first synaptic circuit within the first plurality of vias, the first synaptic circuit including a first diode serially connected to a first resistor having a substantially fixed resistance; An input portion of each first synaptic circuit is formed to receive an input signal among a plurality of input signals; A second dielectric layer below the first dielectric layer; A second plurality of vias within the second dielectric layer; A first conductor within the second plurality of vias to form a plurality of first accumulation nodes, wherein at least one of the first conductors is connected to receive output signals from two or more of the first synaptic circuits; A third dielectric layer below the second dielectric layer; A third plurality of vias in the third dielectric layer; and A second synaptic circuit within each of the third plurality of vias, the second synaptic circuit including a second diode and a second resistor, wherein the second resistor has another substantially fixed value and wherein the second diode is directly serially connected to the second resistor, and wherein one of the first conductors is connected to input portions of two or more of the second synaptic circuits.

2. The semiconductor device according to claim 1, wherein the first conductor includes a first metal conductor directly connected to output portions of two or more of the first synaptic circuits and a second metal conductor directly connected to output portions of two or more different first synaptic circuits.

3. The semiconductor device according to claim 1, wherein the first resistor includes doped polysilicon.

4. A neural network circuit, the neural network circuit comprising: Two or more input portions, wherein a first input portion receives a first input signal and a second input portion receives a second input signal; A first group of two or more synaptic circuits and a second group of two or more synaptic circuits, the first group of two or more synaptic circuits being connected to receive the first input signal, the second group of two or more synaptic circuits being connected to receive the second input signal, wherein each of the first group of two or more synaptic circuits and the second group of two or more synaptic circuits includes a resistor having a substantially fixed value serially connected to a diode; A first dielectric layer having two or more openings formed therethrough and a first conductor formed by filling a first opening of the two or more openings to provide a conduction path through the first dielectric layer, the first conductor forming a first accumulation node, the first accumulation node being connected to receive a first output signal from a first synaptic circuit of the first set of two or more synaptic circuits and a second output signal from a second synaptic circuit of the second set of two or more synaptic circuits, the first accumulation node being configured to add the first output signal to the second output signal to form a first accumulation signal, wherein the first accumulation node is a conductor; and A second conductor formed by filling a second opening of the two or more openings to provide a conduction path through the first dielectric layer, the second conductor forming a second accumulation node, the second accumulation node being connected to receive a third output signal from a third synaptic circuit of the first set of two or more synaptic circuits and a fourth output signal from a fourth synaptic circuit of the second set of two or more synaptic circuits, the second accumulation node being configured to add the third output signal to the fourth output signal to form a second accumulation signal.

5. The neural network circuit according to claim 4, the neural network circuit further comprising a third set of two or more synaptic circuits and a fourth set of two or more synaptic circuits, the third set of two or more synaptic circuits being connected to receive the first accumulation signal, the fourth set of two or more synaptic circuits being connected to receive the second accumulation signal, wherein each of the third set of two or more synaptic circuits and the fourth set of two or more synaptic circuits includes a substantially fixed value resistor connected in series with a diode.

6. The neural network circuit according to claim 5, the neural network circuit further comprising a third accumulation node, the third accumulation node being connected to receive a fifth output signal from a fifth synaptic circuit of the third set of two or more synaptic circuits and a sixth output signal from a sixth synaptic circuit of the fourth set of two or more synaptic circuits, the third accumulation node being configured to add the fifth output signal to the sixth output signal to form a third accumulation signal.

7. The neural network circuit according to claim 4, wherein the first set of two or more synaptic circuits and the second set of two or more synaptic circuits are formed within openings located in a third dielectric layer.

8. A neural network, comprising: A first dielectric layer covering a semiconductor substrate having a plurality of active semiconductor devices in the semiconductor substrate; A first plurality of accumulation node conductors in the first dielectric layer; A second dielectric layer covering the first dielectric layer; A plurality of first vias in the second dielectric layer; and The first circuit within each of the plurality of first through-holes, the first circuit including a first diode in series with a first resistor within a first through-hole of the plurality of first through-holes and a second diode in series with a second resistor within a second through-hole of the plurality of first through-holes, and wherein each resistor has a substantially fixed resistance, and wherein the first resistor has a value different from that of the second resistor.

9. The neural network according to claim 8, wherein one of the first resistor or the first diode is directly connected to a first accumulation node conductor of the first plurality of accumulation node conductors, and one of the second resistor or the second diode is directly connected to a second accumulation node conductor of the first plurality of accumulation node conductors.

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