High Throughput Digital Filter Architecture for Processing Unary Coded Data

Abstract

Embodiments of the present disclosure relate to a high throughput digital filter architecture for processing unary coded data. Individual bits of a K-bit unary data word are applied to K polyphase finite impulse response filter circuits, where K is greater than 1. Each polyphase finite impulse response filter circuit receives a different bit and operates with a single bit precision to generate a filtered output data word from each received bit. A gain adjustment is applied to each filtered output data word by a gain stage circuit to generate a corresponding gain-adjusted output data word. The gain-adjusted output data words from the gain stage circuits are summed to generate an output data word. The unary data word can be output from a source such as a data encoder or quantizer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Application No. 62 / 931,461, filed on November 6, 2019, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present invention relates generally to digital filters and, more particularly, to digital filters configured for high throughput processing of unary encoded data. Background Art

[0004] Systems for generating unary coded data are common. As is known in the art, unary coding (also known as unary number system or thermometer coding) is an entropy coding scheme that represents a natural number of value J as a K-bit data word formed by J ones and KJ zeros. Thus, as an example, for J=1, K=8, the unary coding of J would be <1,0,0,0,0,0,0,0>; for J=5, K=8, the unary coding of J would be <1,1,1,1,1,0,0,0>.

[0005] There is a need in the art for filtering unary encoded data produced by a system. Summary of the invention

[0006] In an embodiment, a circuit includes: an input configured to receive a K-bit unary data word, where K is greater than 1; K polyphase finite impulse response filter circuits, each polyphase finite impulse response filter circuit configured to receive a unary data word of a different bit of the K-bit unary data word and to generate a filtered output data word therefrom, each polyphase finite impulse response filter circuit having a single bit accuracy; K gain stage circuits, each gain stage circuit configured to apply a gain adjustment to the filtered output data word from a corresponding polyphase finite impulse response filter circuit to generate a gain adjusted output data word; and a summing circuit configured to sum the gain adjusted output data words from the K gain stage circuits to generate the output data word.

[0007] In an embodiment, a method includes: receiving a K-bit unary data word, where K is greater than 1; performing polyphase finite impulse response filtering for each bit of the K-bit unary data word to generate a filtered output data word from each bit, wherein performing the polyphase finite impulse response filtering includes: performing single bit accuracy filtering; applying gain adjustment to each filtered output data word from a corresponding polyphase finite impulse response filtering to generate a gain adjusted data word; and summing the gain adjusted output data words to generate the output data word. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] For a better understanding of the present embodiments, reference will now be made, by way of example only, to the accompanying drawings, in which:

[0009] Figure 1 is a block diagram of a filter circuit for filtering unary coded data;

[0010] Figure 2 is a block diagram of a filter circuit for filtering unary coded data;

[0011] Figure 3 is Figure 2 a block diagram of a polyphase finite impulse response filter used within a circuit of; and

[0012] Figure 4 is to use Figures 2 to 3 Basic block diagram of a filter Delta-Sigma ADC circuit. DETAILED DESCRIPTION

[0013] Reference now Figure 1 , which shows a block diagram of a filter circuit 10 for filtering unary encoded data. A source 12, such as a data encoder or quantizer (e.g., as used in a Delta-Sigma analog-to-digital converter, see Figure 4 ), generating a stream of unary coded data words U at a rate Fs i , where i represents the index of the word in the data word stream. Each unary coded data word U has K bits i Encodes a natural number of value J, where J can be any integer greater than or equal to 0 and less than or equal to K. Source 12 outputs each unary encoded data word U in parallel format on K-bit data bus 14. i , so as to be input to the filter circuit 10.

[0014] Unary coded data word U i The bits U(0)-U(K-1) of the data word U are input to a gain adjustment circuit 20 formed of K gain stages 22. Each gain stage 22 has an input coupled to a bit line 16 of the data bus 14, and each gain stage 22 is configured to receive a unary encoded data word U i Thus, gain stage 22(0) receives bit U(0), gain stage 22(1) receives bit U(1), ..., gain stage 22(K-1) receives bit (K-1). Each gain stage 22 applies a gain adjustment specified by the m-bit gain value g for the unary coded data word U i For example, gain stage 22(0) applies a gain adjustment of g0 to bit U(0), gain stage 22(2) applies a gain adjustment of g2 to bit U(2), and so on. Gain stage 22(K-1) applies a gain adjustment of g0 to bit U(0). (K-1)The gain circuit 20 generates a plurality of (i.e., K) m-bit gain-adjusted output data words G0 to G(K-1) from the gain stages 22(0) to 22(K-1) for the corresponding data buses 24(0) to 24(K-1), respectively.

[0015] The summing circuit 30 performs binary addition of the gain adjusted output data words G0 to G(k-1) to generate a binary coded data word B i Here, the binary coded data word B output from circuit 30 is i The data stream is encoded as a unary data word U i The data stream is generated at the same rate Fs, where i represents the index of the word in the stream. Each binary coded data word B transmitted on the data bus 32 i There are x digits in .

[0016] In an embodiment, all gain values ​​g may be set to be identical. In this configuration, the data buses 24(0) to 24(k-1) will be single bit buses (i.e., bit lines where M=1), and the gain adjusted output data words G0 to G(k-1) will each have a value corresponding to (i.e., equal to) the unary encoded data word U i The single data bit of bits U(0) to U(k-1).

[0017] Note that in the case where all gain values ​​g are set to be consistent, the summing circuit 30 acts as a unary (thermometer) to binary conversion circuit. The value of x will be equal to the number of bits required to encode the binary code K bits of the unary encoded data (i.e., 2 x >=K).

[0018] However, more often, the gain values ​​are not consistent in order to encode the unary data word U i As an example, each gain stage 22 may apply m>1-bit gain adjustment, so the gain-adjusted output data words G0 to G(K-1) (with the unary coded data word U i The non-uniform gain adjustment applied by each gain stage 22 provides a fractional correction for differences between the natural number representation of the unary coded data word and the actual non-integer value represented by the coded value (e.g., a natural number value of 1 in unary programming representing an actual non-integer value of 1.05 would use m bits with a value g1 equal to 1.05 (so as to produce a binary coded data word B i has a value of 1.05) and a natural value of 2 to represent the actual non-integer value 1.95 would use m bits with a value g2 equal to 0.90 (so as to produce a binary coded data word B iHaving the value 1.05+0.90=1.95)).

[0019] The filter circuit 10 also includes a polyphase finite impulse response (PP-FIR) filter 40 which receives the binary coded data word B from the circuit 30. i The polyphase finite impulse response filter 40 operates at a rate Fs / N, where N is the number of partial filter computation (e.g., multiply and accumulate - MAC) circuits 42 within the polyphase finite impulse response filter 40. More generally, N is equal to the number of individual phases of the polyphase finite impulse response filter implementation. The N partial polyphase filter computation circuits 42(0) to 42(N-1) respectively receive a binary coded data word B supplied by a commutation circuit 50 coupled to the output of the summing circuit 30. i For example, the commutation circuit 50 converts the binary coded data word B i The i-th sample of is latched and provided to the partial polyphase filter calculation circuit 42(0) as the x bit on the data bus 34(0), the (i+1)-th sample is latched and provided to the partial polyphase filter calculation circuit 42(1) as the x bit on the corresponding data bus, ..., and the (i+N-1)-th sample is latched and provided to the partial polyphase filter calculation circuit 42(N-1) as the x bit on the data bus 34(N-1). Thus, the polyphase finite impulse response filter 40 generates a filtered output data word Out at a rate of Fs / N. j A sample of , , where j represents the index of the word in the stream.

[0020] Each partial polyphase filter calculation circuit 42 outputs a partial filter data word F having y bits on a corresponding data bus 52(0) to 52(N-1), where y is generally greater than x. A summing circuit 54 performs a binary addition of the partial filter data words F0 to FN-1 to generate a filtered output data word Out j In addition, the filtered output data word Out from circuit 54 j The stream is generated at the same rate as for the operation of the polyphase finite impulse response filter 40. j has z bits, where z is usually greater than y, and the filtered output data word Out j is output on data bus 58 .

[0021] Each partial polyphase filter calculation circuit 42 can be generally represented as a multi-tap filter including a delay circuit 44, a gain stage 46, and a summing circuit 48. In the illustrated example, the partial polyphase filter calculation circuit 42 includes three taps per polyphase bank (i.e., per partial polyphase filter calculation circuit 42). The first delay circuit 44(1) receives the binary coded data word B from the commutation circuit 50 on the data bus 34. i The second delay circuit 44(2) receives the binary coded data word B output from the delay circuit 44(1). i The first gain stage 46 (1) applies a first gain factor C1 to the binary coded data word B. i The second gain stage 46 (2) applies a second gain factor C2 to the binary coded data word B i The first delay of the received samples of the stream of , and the third gain stage 46 (3) applies the third gain coefficient C3 to the binary coded data word B i Summing circuit 48 sums the gain adjusted data words output from gain stage 46 to generate a partial filter data word F.

[0022] The gain coefficient C used in each partial polyphase filter calculation circuit 42 will generally be different from each other, with the gain coefficient C having a value that depends on the specifications of the filter and the decimation rate. Those skilled in the art know how to determine and set the gain coefficient C used in each partial polyphase filter calculation circuit 42.

[0023] It should be noted that in Figure 1 The schematic diagram of the partial polyphase filter calculation circuit 42 shown in FIG. 4 is only an example. Any suitable configuration known in the art can be used for the partial polyphase filter calculation circuit 42.

[0024] The data bus used within circuit 10 may be configured in series or in parallel. In a preferred embodiment, the bus is implemented in parallel.

[0025] Existence relative to Figure 1The implementation of the invention is disadvantageous. The summing circuit 30 operates at a rate Fs. While this may not be a problem when the gain values ​​g for the gain stage 22 are set to be consistent, this does present a problem when inconsistent gain values ​​are used. The number of bits x can be large and the rate Fs can be high, such as mathematical operations that need to be performed at gigahertz speeds. Moreover, the number of bits x has a direct impact on the accuracy required by the polyphase finite impulse response filter 40, and it can be challenging to perform the mathematical operations required by the partial polyphase filter calculation circuit 42 with x-bit accuracy at the Fs / N rate. It should also be noted that the x-bit accuracy within the polyphase finite impulse response filter 40 requires the use of an x-bit delay circuit 44 in each partial polyphase filter calculation circuit 42. In order to apply the gain coefficient C to the x-bit data word at the rate Fs / N, a large number of multiplications of bits must be performed. This requires a non-negligible amount of circuit area and power consumption.

[0026] Reference now Figure 2 , which shows a block diagram of a filter circuit 110 for filtering unary encoded data. A source 112, such as a data encoder or quantizer (e.g., as used in a Delta-Sigma analog-to-digital converter, see Figure 4 ), generating a unary coded data word U at rate Fs i where i represents the index of the word in the stream. Each unary encoded data word U i The source 112 transmits each unary encoded data word U in parallel format on the K-bit data bus 114. i Output to be input to the filter circuit 110.

[0027] Unary coded data word U i The bits U(0)-U of the data word U are input to a filter bank circuit 118 consisting of K polyphase finite impulse response (PP-FIR) filter circuits 140(0) through 140(K-1). Each polyphase finite impulse response filter circuit 140 has an input coupled to a bit line 116 of the data bus 114, and each polyphase finite impulse response filter circuit 140 is configured to receive a unary encoded data word U iThe corresponding bit U(bit) of the multi-phase finite impulse response filter circuit 140(0) receives bit U(0), the multi-phase finite impulse response filter circuit 140(1) receives bit U(1), ..., the multi-phase finite impulse response filter circuit 140(K-1) receives bit U(K-1). This process of allocating data to multiple filter banks in this manner is generally referred to in the art as "commutation". Each multi-phase finite impulse response filter circuit 140 operates at a rate Fs / N, where N is the number of partial multi-phase filter calculation circuits in each multi-phase finite impulse response filter 140, which operates at a rate Fs / N to generate a filtered output data word Fout. j , where j is the index of the generated stream. Each filtered output data word Fout j is an x-bit word (where x is greater than 1), ie, output on the corresponding data bus 108(0) to 108(K-1).

[0028] The filtered output data word Fout j 0 to Fout j K-1 is input to a gain adjustment circuit 120 formed of K gain stages 122. Each gain stage 122 has an input coupled to the data bus 108, and each gain stage 122 is configured to receive a corresponding filtered output data word Fout j Thus, gain stage 122(0) receives the filtered output data word Fout0, gain stage 122(1) receives the filtered output data word Fout1, ..., gain stage 122(K-1) receives the filtered output data word Fout j Each gain stage 122 applies a gain adjustment specified by an m-bit gain value g for the unary coded data word U i Each unary coded data word U i For example, gain stage 122(0) applies a gain adjustment of g0 to the filtered output data word Fout. j 0 (from bit U(0)), gain stage 122(2) applies a gain adjustment of g2 to the filtered output data word Fout j 2 (from bit U(2)), ..., gain stage 122(K-1) converts g (K-1) The gain adjustment is applied to the filtered output data word Fout j K-1 (from bit U(K-1)). Gain circuit 120 generates gain-adjusted output data words G0 to G(K-1) from gain stages 122(0) to 122(K-1), respectively, as y-bit data for output on corresponding y data buses 124(0) to 124(K-1).

[0029] The summing circuit 130 performs binary addition of the gain-adjusted output data words G0 to G(K-1) to generate the output data word Out j Here, the output data word Out from circuit 130 is j The stream of output data word Out is generated at the same rate Fs / N as the operating rate for the polyphase finite impulse response filter 140, where j represents the index of the word in the stream. j There are z bits in each output data word Out, where z is usually greater than y. j is transmitted on data bus 132 .

[0030] In an embodiment, all gain values ​​g may be set to be identical. In this configuration, x=y, and the gain-adjusted output data words G0 to G(K-1) will each match the corresponding filtered output data word Fout j 0 to Fout j K-1.

[0031] However, more often, the gain values ​​are not consistent in order to correspond to the unary coded data word U i The corresponding filtered output data word Fout j Fractional correction is applied. As an example, each gain stage 122 may apply m>1 bit gain adjustment, so the gain adjusted output data words G0 to G(K-1) will each be a y bit data word, where y is generally greater than x. The non-uniform gain adjustment applied by each gain stage 122 provides for processing the unary coded data word U i The fractional correction for the difference between the limits of the natural number representation of and the actual non-integer value represented by the encoded value (see discussion above).

[0032] Reference now Figure 3 , which shows that in Figure 2 1. The filter 140 receives the K-bit unary encoded data word U from the bit line 116. i The single bit is received in the stream at a rate Fs. The polyphase finite impulse response filter 140 operates at a rate Fs / N, where N is the number of partial filter computation (e.g., multiply and accumulate - MAC) circuits 142 within the polyphase finite impulse response filter 140. More generally, N is equal to the number of individual phases of the polyphase finite impulse response filter implementation. The N partial polyphase filter computation circuits 142(0) to 142(N-1) each receive a binary coded data word B supplied from a commutation circuit 150 coupled to receive the single bit U(bit) from the source 112. iN consecutive samples of the stream of bits. For example, the commutation circuit 150 latches the i-th sample of bit U(bit) on the one-bit data bus 106(0) and provides it to the partial polyphase filter calculation circuit 142(0), latches the (i+1)th sample of bit U(bit) on the one-bit data bus and provides it to the partial polyphase filter calculation circuit 142(1), ..., latches the (i+N-1)th sample of bit U(bit) on the one-bit data bus 106(N-1) and provides it to the partial polyphase filter calculation circuit 142(N-1). Thus, the polyphase finite impulse response filter 140 generates a sample of the filtered output data word F having p bits on the data bus 152 at a rate Fs / N, where p is greater than 1.

[0033] The summing circuit 154 performs binary addition of the partial filter data words F0 to F(N-1) to generate a filtered output data word Fout. j Here, the filtered output data word Fout from circuit 154 is j The stream of Fout is generated at the same rate Fs / N as the rate at which the polyphase finite impulse response filter 140 operates, where j represents the index of the word in the stream. j There are x bits in (where x is usually greater than p) and are output on the data bus 108.

[0034] Each partial polyphase filter calculation circuit 142 can be generally represented as a multi-tap filter including a delay circuit 144, a gain stage 146, and a summing circuit 148. In the illustrated example, the partial polyphase filter calculation circuit 142 includes three taps per partial polyphase filter calculation circuit 142. The first delay circuit 144(1) receives a K-bit unary encoded data word U i The second delay circuit 144(2) receives the K-bit unary coded data word U received from the delay circuit 144(1). i The delay circuit 144 can be implemented using a single-bit shift register or a flip-flop. The first gain stage 146 (1) applies a first gain factor C1 to the received K-bit unary encoded data word U i The second gain stage 146 (2) applies the second gain coefficient C2 to the K-bit unary coded data word U i The third gain stage 46(3) applies the third gain coefficient C3 to the K-bit unary coded data word U i Summing circuit 148 sums the gain adjustment data words from gain stage 146 to generate a partial filter data word F.

[0035] The gain coefficient C used in each partial polyphase filter calculation circuit 142 will generally be different from each other, with the gain coefficient C having a value that depends on the specifications of the filter and the decimation rate. Those skilled in the art know how to determine and set the gain coefficient C used in each partial polyphase filter calculation circuit 142.

[0036] It should be noted that in Figure 3 The schematic diagram of the partial polyphase filter calculation circuit 42 shown in FIG. 1 is only an example. Any suitable configuration known in the art can be used for the partial polyphase filter calculation circuit 142.

[0037] Figure 3 Also shown is a truth table for the operation of the partial polyphase filter calculation circuits 142. Because each partial polyphase filter calculation circuit 142 operates on only a single bit (i.e., single bit precision), the partial filter data word F is composed of the K-bit unary encoded data word U being processed. i The sum of the gain coefficients C selected by the logic value of a single bit. Therefore, assuming a K-bit unary coded data word U i Three consecutive samples of a single bit of have logical values ​​0, 0, 0. The output from gain stage 146 will be 0*C1=0, 0*C2=0, and 0*C3=0. The sum of the partial filter data word F obtained by summing circuit 148 will be a p-bit data word with a value of C=0. Conversely, assuming a K-bit unary encoded data word U i Three consecutive samples of a single bit of have logic values ​​0, 1, 1. The output from gain stage 146 will be 0*C1=0, 1*C2=C2, and 1*C3=C3. The sum of the partial filter data word F by summing circuit 148 will be a p-bit data word having a value of C=C2+C3.

[0038] The data bus used within circuit 110 can be configured in series or in parallel. In a preferred embodiment, the bus is implemented in parallel.

[0039] Figures 2 to 3 The implementation of filter 110 provides Figure 1 The filter 10 has several advantages over the conventional filter 10. The filtering operation is performed directly on the unary data, which eliminates the need to perform unary to binary conversion at high (e.g., Fs) data rates. The key calculations are reduced to single-bit operations, allowing very fast implementations. There is a corresponding reduction in required power (e.g., at least 20%). In addition, the critical path for processing is independent of the unary encoded data word U. iThe filter design is also scalable (to multi-GHz operation) with immunity to unary-to-binary conversion and gain of the FIR coefficients.

[0040] Reference now Figure 4 , which shows a basic block diagram of a Delta-Sigma analog-to-digital converter circuit utilizing filter 110. It is noted that filter 110 operates a filter and extracts a thermometer (unary) coded data word output from the quantizer. The quantizer output is also passed through a digital-to-analog converter in a feedback loop to generate an analog feedback signal reduced by a summing circuit from the analog input signal. The resulting different signals are filtered in a loop filter circuit (e.g., using an integrator) and applied to the input of a register that generates a thermometer (unary) coded data word.

[0041] Although the present invention has been illustrated and described in detail in the drawings and the foregoing description, such illustration and description are illustrative or exemplary and non-restrictive; the present invention is not limited to the disclosed embodiments. Other variations of the disclosed embodiments can be understood and realized by those skilled in the art in the process of practicing the claimed invention by studying the drawings, the disclosure and the appended claims.

Claims

1. A circuit comprising: an input configured to receive a K-bit unary encoded data word, where K is greater than 1; K polyphase finite impulse response filter circuits, each polyphase finite impulse response filter circuit configured to receive a different bit of the K-bit unary encoded data word and generate a filtered output data word therefrom, each polyphase finite impulse response filter circuit having a single bit accuracy; K gain stage circuits, each gain stage circuit configured to apply a gain adjustment to the filtered output data word from a corresponding polyphase finite impulse response filter circuit to generate a gain adjusted output data word; as well as A summing circuit is configured to sum the gain-adjusted output data words from the K gain stage circuits to generate an output data word.

2. The circuit of claim 1 , wherein the input receives the K-bit unary encoded data words at a rate Fs, and each polyphase finite impulse response filter circuit generates a stream of the filtered output data words at a rate Fs / N, where N is greater than 1.

3. The circuit of claim 2, wherein N is the number of partial polyphase filter calculation circuits in each polyphase finite impulse response filter circuit.

4. The circuit of claim 3, wherein each partial polyphase filter calculation circuit is a multiply and accumulate circuit MAC.

5. The circuit of claim 4, wherein each MAC includes a delay circuit, and wherein the delay circuit is a single-bit delay element. The circuit of claim 5 , wherein the single-bit delay element is a flip-flop.

7. The circuit of claim 2, wherein N is the number of phases used in the implementation of the polyphase finite impulse response filter circuit.

8. The circuit of claim 1, wherein the gain adjustment for each gain stage circuit provides a fractional correction of the unary encoded data word.

9. The circuit of claim 1, further comprising a source circuit configured to supply the K-bit unary encoded data word.

10. The circuit of claim 9, wherein the source circuit is a quantizer.

11. The circuit of claim 10, wherein the quantizer is part of a Delta-Sigma analog-to-digital converter.

12. The circuit of claim 9, wherein the source circuit is a data encoder.

13. A method for processing a unary coded data word, comprising: receiving a K-bit unary encoded data word, where K is greater than 1; performing polyphase finite impulse response filtering for each bit of the K-bit unary encoded data word to generate a filtered output data word from each bit, wherein performing polyphase finite impulse response filtering includes performing the filtering with single bit accuracy; applying a gain adjustment to each filtered output data word from a corresponding polyphase finite impulse response filter to generate a gain adjusted output data word; as well as The gain adjusted output data words are summed to generate an output data word.

14. The method of claim 13, wherein receiving comprises: The stream of K-bit unary encoded data words is received at a rate Fs, and wherein the polyphase finite impulse response filtering generates the stream of filtered output data words at a rate Fs / N, where N is greater than one.

15. The method of claim 14, wherein N is the number of partial filter calculations performed for each polyphase finite impulse response filtering.

16. The method of claim 14, wherein each partial filter calculation comprises performing a multiply and accumulate operation.

17. The method of claim 14, wherein N is the number of phases used for the implementation of the polyphase finite impulse response filtering.

18. The method of claim 13, wherein applying the gain adjustment comprises: A fractional correction of the unary encoded data word is implemented.

19. The method according to claim 13, further comprising: The K-bit unary encoded data word is supplied from a source circuit.

20. The method of claim 19, wherein the source circuit is a quantizer.

21. The method of claim 20, wherein the quantizer is part of a Delta-Sigma analog-to-digital converter.

22. The method of claim 19, wherein the source circuit is a data encoder.

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