Gate drivers and protection systems for solid-state switches

Abstract

A gate driver and protection system for a solid-state switch. The present invention discloses a circuit system, the circuit system comprising: an electronic solid-state switch, the electronic solid-state switch comprising a first power supply terminal and a second power supply terminal; and a driver and switch protection system, the driver and switch protection system being electrically connected to the electronic solid-state switch. The driver and switch protection system comprises: an isolated bias power supply circuit, the isolated bias power supply circuit being configured to output a DC voltage of at least fifteen volts; a current buffer circuit, the current buffer circuit being electrically connected between the isolated bias power supply circuit and the electronic solid-state switch; and a buffer circuit, the buffer circuit being electrically connected to the first power supply terminal and the second power supply terminal.

Description

Technical Field

[0001] The present disclosure relates to electronic components, and more particularly, to gate drivers and protection for electronic solid-state switches. Background Art

[0002] Existing gate driver circuits, designed for inverter applications, consume high power, are bulky, and are not suitable for integration with solid-state switches. If the power supply has significant inductance, solid-state switches cannot absorb the high energy during turn-off under short-circuit or overload conditions. Therefore, there is a need to develop low-power, compact gate drivers and protection circuits for solid-state switches. Summary of the Invention

[0003] The present disclosure relates to gate drivers and protection for electronic solid-state switches. In one aspect of the disclosure, a circuit system includes an electronic solid-state switch comprising a first power supply terminal and a second power supply terminal; and a driver and switch protection system electrically connected to the electronic solid-state switch. The driver and switch protection system includes an isolated bias power supply circuit configured to output a DC voltage of at least fifteen volts; a current buffer circuit electrically connected between the isolated bias power supply circuit and the electronic solid-state switch; and a buffer circuit electrically connected across the first power supply terminal and the second power supply terminal.

[0004] The current buffer circuit may be configured to source and sink an output current of at least one ampere. The output resistance of the current buffer circuit may be less than two ohms.

[0005] The isolated bias power supply circuit can be configured as a printed circuit board. The isolated bias power supply circuit can be configured as an on-chip integrated transformer-based power supply having an output power of approximately one watt + / - 0.5 watts. The on-chip integrated transformer-based power supply includes a plurality of transformer windings.

[0006] The circuit system may further include a signal processing and diagnostic controller and an external controller each electrically connected to the electronic solid-state switch. The signal processing and diagnostic controller may include a plurality of comparators, and the external controller is configured to command the electronic solid-state switch to transition between an off state and an on state.

[0007] The external controller may be configured to command the electronic solid-state switch to transition to the off state. In response to transitioning to the off state, the signal processing and diagnostic controller may be configured to read a gate-source voltage, a gate-source amperage, a temperature, an amperage of a current flowing between the first power terminal and the second power terminal, and a voltage between the first power terminal and the second power terminal of the electronic solid-state switch. The signal processing and diagnostic controller may be configured to compare the gate-source voltage to a predetermined off gate-source voltage threshold.

[0008] The signal processing and diagnostic controller may be configured to determine that the gate-source voltage is less than the predetermined turn-off gate-source voltage threshold. In response to determining that the gate-source voltage is less than the predetermined turn-off gate-source voltage threshold, the signal processing and diagnostic controller may be configured to compare the voltage between the first power terminal and the second power terminal with a predetermined turn-off voltage threshold. The signal processing and diagnostic controller may be configured to determine that the voltage between the first power terminal and the second power terminal is greater than the predetermined turn-off voltage threshold. In response to determining that the voltage between the first power terminal and the second power terminal is greater than the predetermined turn-off voltage threshold, the signal processing and diagnostic controller may be configured to compare the amperage of the current between the first power terminal and the second power terminal with a predetermined turn-off amperage threshold.

[0009] The signal processing and diagnostic controller may be configured to determine that the amperage of the current between the first power terminal and the second power terminal is less than the predetermined shutdown amperage threshold. In response to determining that the amperage of the current between the first power terminal and the second power terminal is less than the predetermined shutdown amperage threshold. The signal processing and diagnostic controller may be configured to compare the gate-source amperage with a predetermined shutdown gate-source amperage threshold. The signal processing and diagnostic controller may be configured to determine that the gate-source amperage is less than the predetermined shutdown gate-source amperage threshold. In response to determining that the gate-source amperage is less than the predetermined shutdown gate-source amperage threshold. The signal processing and diagnostic controller may be configured to set a fault output signal to pass the shutdown state test, thereby indicating that the electronic solid-state switch is operating normally in the shutdown state.

[0010] The external controller is configured to command the electronic solid-state switch to transition to the on-state. In response to transitioning to the on-state, the signal processing and diagnostic controller may be configured to read a gate-source voltage, a gate-source amperage, a temperature, an amperage of the current flowing between the first power terminal and the second power terminal, and a voltage between the first power terminal and the second power terminal of the electronic solid-state switch. The signal processing and diagnostic controller may be configured to compare the gate-source voltage to a predetermined on-gate-source voltage threshold. The signal processing and diagnostic controller may be configured to determine that the gate-source voltage is greater than the predetermined on-gate-source voltage threshold. In response to determining that the gate-source voltage is greater than the predetermined on-gate-source voltage threshold.

[0011] The signal processing and diagnostic controller may be configured to compare the voltage between the first power terminal and the second power terminal to a predetermined turn-on voltage threshold. The signal processing and diagnostic controller may be configured to determine that the voltage between the first power terminal and the second power terminal is less than the predetermined turn-on voltage threshold. In response to determining that the voltage between the first power terminal and the second power terminal is less than the predetermined turn-on voltage threshold.

[0012] The signal processing and diagnostic controller may be configured to compare the amperage of the current between the first power terminal and the second power terminal with a predetermined on-amperage threshold. The signal processing and diagnostic controller may be configured to determine that the amperage of the current between the first power terminal and the second power terminal is greater than the predetermined on-amperage threshold. In response to determining that the amperage of the current between the first power terminal and the second power terminal is greater than the predetermined on-amperage threshold, the signal processing and diagnostic controller may be configured to compare the gate-source amperage with a predetermined on-gate-source amperage threshold. The signal processing and diagnostic controller may be configured to determine that the gate-source amperage is less than the predetermined on-gate-source amperage threshold. In response to determining that the gate-source amperage is less than the predetermined on-gate-source amperage threshold, the signal processing and diagnostic controller may be configured to set a fault output signal to a passed on-state test, thereby indicating that the electronic solid-state switch is operating normally in the on-state.

[0013] The external controller is configured to command the electronic solid-state switch to transition to the off state. In response to transitioning to the off state, the signal processing and diagnostic controller may be configured to read a gate-source voltage, a gate-source amperage, a temperature, an amperage of the current flowing between the first power terminal and the second power terminal, and a voltage between the first power terminal and the second power terminal of the electronic solid-state switch. The signal processing and diagnostic controller may be configured to compare the amperage of the current flowing between the first power terminal and the second power terminal to a first predetermined degradation current threshold. The signal processing and diagnostic controller may be configured to determine that the amperage of the current flowing between the first power terminal and the second power terminal is greater than the first predetermined degradation current threshold.

[0014] In response to determining that the amperage of the current flowing between the first power terminal and the second power terminal is greater than the first predetermined degradation current threshold, the signal processing and diagnostic controller may be configured to compare the amperage of the current flowing between the first power terminal and the second power terminal to a second predetermined degradation current threshold. The signal processing and diagnostic controller may be configured to determine that the amperage of the current flowing between the first power terminal and the second power terminal is greater than the second predetermined degradation current threshold, wherein the second predetermined degradation current threshold is greater than the first predetermined degradation current threshold. In response to determining that the amperage of the current flowing between the first power terminal and the second power terminal is greater than the second predetermined degradation current threshold, the signal processing and diagnostic controller may be configured to transmit a fault output signal, thereby setting the degradation level of the electronic solid-state switch to degradation level two.

[0015] The external controller is configured to command the electronic solid-state switch to transition to the on-state. In response to transitioning to the on-state, the signal processing and diagnostic controller may be configured to read a gate-source voltage, a gate-source amperage, a temperature, an amperage of the current flowing between the first power terminal and the second power terminal, and a voltage between the first power terminal and the second power terminal of the electronic solid-state switch. The signal processing and diagnostic controller may be configured to calculate a drain-source resistance of the electronic solid-state switch by dividing the voltage between the first power terminal and the second power terminal by the amperage of the current flowing between the first power terminal and the second power terminal.

[0016] In response to calculating the drain-source resistance of the electronic solid-state switch, the signal processing and diagnostic controller may be configured to compare the drain-source resistance to a predetermined on-resistance threshold. The signal processing and diagnostic controller may be configured to determine that the drain-source resistance is greater than the predetermined on-resistance threshold.

[0017] In response to determining that the drain-source resistance is greater than the predetermined on-resistance threshold, the signal processing and diagnostic controller may be configured to compare the gate-source amperage to a predetermined gate-source amperage threshold. The signal processing and diagnostic controller may be configured to determine that the gate-source amperage is greater than the predetermined gate-source amperage threshold. In response to determining that the gate-source amperage is greater than the predetermined gate-source amperage threshold, the signal processing and diagnostic controller may be configured to send a fault output signal to set the degradation level of the electronic solid-state switch to degradation level four.

[0018] The present invention also provides the following technical solutions:

[0019] 1. A circuit system comprising:

[0020] an electronic solid-state switch comprising a first power terminal and a second power terminal;

[0021] a driver and switch protection system electrically connected to the electronic solid-state switch, wherein the driver and switch protection system comprises:

[0022] an isolated bias power supply circuit configured to output a DC voltage of at least fifteen volts;

[0023] a current buffer circuit electrically connected between the isolated bias power supply circuit and the electronic solid-state switch; and

[0024] A buffer circuit is electrically connected to the first power terminal and the second power terminal.

[0025] 2. The circuit system of claim 1 , wherein the current buffer circuit is configured to provide and sink an output current of at least one ampere.

[0026] 3. The circuit system according to technical solution 2, wherein the output resistance of the current buffer circuit is less than two ohms.

[0027] 4. A circuit system according to technical solution 3, wherein the isolated bias power supply circuit is configured as a printed circuit board.

[0028] 5. A circuit system according to technical solution 3, wherein the isolated bias power supply circuit is an on-chip integrated transformer-based power supply with an output power of one watt + / - 0.5 watts, and the on-chip integrated transformer-based power supply includes multiple transformer windings.

[0029] 6. The circuit system according to technical solution 1 further includes a signal processing and diagnostic controller and an external controller, each electrically connected to the electronic solid-state switch, wherein the signal processing and diagnostic controller includes a plurality of comparators, and the external controller is configured to command the electronic solid-state switch to transition between an off state and an on state.

[0030] 7. The circuit system according to technical solution 6, wherein the external controller is configured to command the electronic solid-state switch to transition to the off state;

[0031] In response to transitioning to the off state, the signal processing and diagnostic controller is configured to:

[0032] reading a gate-source voltage, a gate-source amperage, a temperature, an amperage of a current flowing between the first power terminal and the second power terminal, and a voltage between the first power terminal and the second power terminal of the electronic solid-state switch;

[0033] comparing the gate-source voltage to a predetermined turn-off gate-source voltage threshold;

[0034] determining that the gate-source voltage is less than the predetermined turn-off gate-source voltage threshold;

[0035] in response to determining that the gate-source voltage is less than the predetermined turn-off gate-source voltage threshold, comparing the voltage between the first power terminal and the second power terminal to a predetermined turn-off voltage threshold;

[0036] determining that the voltage between the first power terminal and the second power terminal is greater than the predetermined turn-off voltage threshold;

[0037] in response to determining that the voltage between the first power terminal and the second power terminal is greater than the predetermined off-voltage threshold, comparing the amperage of the current between the first power terminal and the second power terminal to a predetermined off-amperage threshold;

[0038] determining that the amperage of the current between the first power terminal and the second power terminal is less than the predetermined shutoff amperage threshold;

[0039] in response to determining that the amperage of the current between the first power terminal and the second power terminal is less than the predetermined turn-off amperage threshold, comparing the gate-source amperage to a predetermined turn-off gate-source amperage threshold;

[0040] determining that the gate-source amperage is less than the predetermined off gate-source amperage threshold; and

[0041] In response to determining that the gate-source amperage is less than the predetermined off gate-source amperage threshold, a fault output signal is set to pass the off state test, thereby indicating that the electronic solid-state switch is operating normally in the off state.

[0042] 8. The circuit system according to technical solution 6, wherein the external controller is configured to command the electronic solid-state switch to change to the on state;

[0043] In response to transitioning to the on state, the signal processing and diagnostic controller is configured to:

[0044] reading a gate-source voltage, a gate-source amperage, a temperature, an amperage of the current flowing between the first power terminal and the second power terminal, and a voltage between the first power terminal and the second power terminal of the electronic solid-state switch;

[0045] comparing the gate-source voltage to a predetermined turn-on gate-source voltage threshold;

[0046] determining that the gate-source voltage is greater than the predetermined turn-on gate-source voltage threshold;

[0047] in response to determining that the gate-source voltage is greater than the predetermined turn-on gate-source voltage threshold, comparing the voltage between the first power terminal and the second power terminal to a predetermined turn-on voltage threshold;

[0048] determining that the voltage between the first power terminal and the second power terminal is less than the predetermined switch-on voltage threshold;

[0049] in response to determining that the voltage between the first power terminal and the second power terminal is less than the predetermined turn-on voltage threshold, comparing the amperage of the current between the first power terminal and the second power terminal to a predetermined turn-on amperage threshold;

[0050] determining that the amperage of the current between the first power terminal and the second power terminal is greater than the predetermined switch-on amperage threshold;

[0051] in response to determining that the amperage of the current between the first power terminal and the second power terminal is greater than the predetermined turn-on amperage threshold, comparing the gate-source amperage to a predetermined turn-on gate-source amperage threshold;

[0052] determining that the gate-source amperage is less than the predetermined turn-on gate-source amperage threshold; and

[0053] In response to determining that the gate-source amperage is less than the predetermined on-state gate-source amperage threshold, a fault output signal is set to pass the on-state test, thereby indicating that the electronic solid-state switch is operating normally in the on-state.

[0054] 9. The circuit system according to technical solution 6, wherein the external controller is configured to command the electronic solid-state switch to transition to the off state;

[0055] In response to transitioning to the off state, the signal processing and diagnostic controller is configured to:

[0056] reading a gate-source voltage, a gate-source amperage, a temperature, an amperage of the current flowing between the first power terminal and the second power terminal, and a voltage between the first power terminal and the second power terminal of the electronic solid-state switch;

[0057] comparing the amperage of the current flowing between the first power terminal and the second power terminal to a first predetermined degradation current threshold;

[0058] determining that the amperage of the current flowing between the first power terminal and the second power terminal is greater than the first predetermined degradation current threshold;

[0059] in response to determining that the amperage of the current flowing between the first power terminal and the second power terminal is greater than the first predetermined degradation current threshold, comparing the amperage of the current flowing between the first power terminal and the second power terminal to a second predetermined degradation current threshold;

[0060] determining that the amperage of the current flowing between the first power terminal and the second power terminal is greater than a second predetermined degradation current threshold, wherein the second predetermined degradation current threshold is greater than the first predetermined degradation current threshold; and

[0061] In response to determining that the amperage of the current flowing between the first power terminal and the second power terminal is greater than the second predetermined degradation current threshold, a fault output signal is sent to set the degradation level of the electronic solid-state switch 102 to degradation level two.

[0062] 10. The circuit system according to technical solution 6, wherein the external controller is configured to command the electronic solid-state switch to change to the on state;

[0063] In response to transitioning to the on state, the signal processing and diagnostic controller is configured to:

[0064] reading a gate-source voltage, a gate-source amperage, a temperature, an amperage of the current flowing between the first power terminal and the second power terminal, and a voltage between the first power terminal and the second power terminal of the electronic solid-state switch;

[0065] calculating a drain-source resistance of the electronic solid-state switch by dividing the voltage between the first power terminal and the second power terminal by the amperage of the current flowing between the first power terminal and the second power terminal;

[0066] responsive to calculating the drain-source resistance of the electronic solid-state switch, comparing the drain-source resistance to a predetermined on-resistance threshold;

[0067] determining that the drain-source resistance is greater than the predetermined on-resistance threshold;

[0068] responsive to determining that the drain-source resistance is greater than the predetermined on-resistance threshold, comparing the gate-source amperage to a predetermined gate-source amperage threshold;

[0069] determining that the gate-source amperage is greater than the predetermined gate-source amperage threshold; and

[0070] In response to determining that the gate-source amperage is greater than the predetermined gate-source amperage threshold, a fault output signal is sent, thereby setting the degradation level of the electronic solid-state switch to degradation level four.

[0071] 11. A circuit system comprising:

[0072] an electronic solid-state switch comprising a first power terminal and a second power terminal;

[0073] an external controller electrically connected to the electronic solid-state switch, wherein the external controller is configured to command the electronic solid-state switch to transition between an OFF state and an ON state;

[0074] a driver and switch protection system electrically connected to the electronic solid-state switch, wherein the driver and switch protection system comprises:

[0075] signal processing and diagnostic controllers;

[0076] an isolated bias power supply circuit electrically connected to the signal processing and diagnostic controller; and

[0077] A buffer circuit is electrically connected to the first power terminal and the second power terminal.

[0078] 12. A circuit system according to technical solution 11, wherein the signal processing and diagnostic controller includes a current buffer circuit, which is electrically connected between the isolated bias power supply circuit and the electronic solid-state switch, and the current buffer circuit is configured to provide and absorb an output current of at least one ampere.

[0079] 13. A circuit system according to technical solution 12, wherein the output resistance of the current buffer circuit is less than two ohms.

[0080] 14. A circuit system according to technical solution 13, wherein the isolated bias power supply circuit is configured as a printed circuit board.

[0081] 15. A circuit system according to technical solution 13, wherein the isolated bias power supply circuit is an on-chip integrated transformer-based power supply with one watt output power, and the on-chip integrated transformer-based power supply includes multiple transformers.

[0082] 16. A circuit system according to technical solution 11, wherein the signal processing and diagnostic controller includes multiple comparators.

[0083] 17. The circuit system according to technical solution 16, wherein the external controller is configured to command the electronic solid-state switch to transition to the off state;

[0084] In response to transitioning to the off state, the signal processing and diagnostic controller is configured to:

[0085] reading a gate-source voltage, a gate-source amperage, a temperature, an amperage of a current flowing between the first power terminal and the second power terminal, and a voltage between the first power terminal and the second power terminal of the electronic solid-state switch;

[0086] comparing the gate-source voltage to a predetermined turn-off gate-source voltage threshold;

[0087] determining that the gate-source voltage is less than the predetermined turn-off gate-source voltage threshold;

[0088] in response to determining that the gate-source voltage is less than the predetermined turn-off gate-source voltage threshold, comparing the voltage between the first power terminal and the second power terminal to a predetermined turn-off voltage threshold;

[0089] determining that the voltage between the first power terminal and the second power terminal is greater than the predetermined turn-off voltage threshold;

[0090] in response to determining that the voltage between the first power terminal and the second power terminal is greater than the predetermined off-voltage threshold, comparing the amperage of the current between the first power terminal and the second power terminal to a predetermined off-amperage threshold;

[0091] determining that the amperage of the current between the first power terminal and the second power terminal is less than the predetermined shutoff amperage threshold;

[0092] in response to determining that the amperage of the current between the first power terminal and the second power terminal is less than the predetermined turn-off amperage threshold, comparing the gate-source amperage to a predetermined turn-off gate-source amperage threshold;

[0093] determining that the gate-source amperage is less than the predetermined off gate-source amperage threshold; and

[0094] In response to determining that the gate-source amperage is less than the predetermined off gate-source amperage threshold, a fault output signal is set to pass the off state test, thereby indicating that the electronic solid-state switch is operating normally in the off state.

[0095] 18. The circuit system according to technical solution 16, wherein the external controller is configured to command the electronic solid-state switch to change to the on state;

[0096] In response to transitioning to the on state, the signal processing and diagnostic controller is configured to:

[0097] reading a gate-source voltage, a gate-source amperage, a temperature, an amperage of a current flowing between the first power terminal and the second power terminal, and a voltage between the first power terminal and the second power terminal of the electronic solid-state switch;

[0098] comparing the gate-source voltage to a predetermined turn-on gate-source voltage threshold;

[0099] determining that the gate-source voltage is greater than the predetermined turn-on gate-source voltage threshold;

[0100] in response to determining that the gate-source voltage is greater than the predetermined turn-on gate-source voltage threshold, comparing the voltage between the first power terminal and the second power terminal to a predetermined turn-on voltage threshold;

[0101] determining that the voltage between the first power terminal and the second power terminal is less than the predetermined switch-on voltage threshold;

[0102] in response to determining that the voltage between the first power terminal and the second power terminal is less than the predetermined turn-on voltage threshold, comparing the amperage of the current between the first power terminal and the second power terminal to a predetermined turn-on amperage threshold;

[0103] determining that the amperage of the current between the first power terminal and the second power terminal is greater than the predetermined switch-on amperage threshold;

[0104] in response to determining that the amperage of the current between the first power terminal and the second power terminal is greater than the predetermined turn-on amperage threshold, comparing the gate-source amperage to a predetermined turn-on gate-source amperage threshold;

[0105] determining that the gate-source amperage is less than the predetermined turn-on gate-source amperage threshold; and

[0106] In response to determining that the gate-source amperage is less than the predetermined on-state gate-source amperage threshold, a fault output signal is set to pass the on-state test, thereby indicating that the electronic solid-state switch is operating normally in the on-state.

[0107] 19. The circuit system according to technical solution 16, wherein the external controller is configured to command the electronic solid-state switch to transition to the off state;

[0108] In response to transitioning to the off state, the signal processing and diagnostic controller is configured to:

[0109] reading a gate-source voltage, a gate-source amperage, a temperature, an amperage of a current flowing between the first power terminal and the second power terminal, and a voltage between the first power terminal and the second power terminal of the electronic solid-state switch;

[0110] comparing the amperage of the current flowing between the first power terminal and the second power terminal to a first predetermined degradation current threshold;

[0111] determining that the amperage of the current flowing between the first power terminal and the second power terminal is greater than the first predetermined degradation current threshold;

[0112] in response to determining that the amperage of the current flowing between the first power terminal and the second power terminal is greater than the first predetermined degradation current threshold, comparing the amperage of the current flowing between the first power terminal and the second power terminal to a second predetermined degradation current threshold;

[0113] determining that the amperage of the current flowing between the first power terminal and the second power terminal is greater than a second predetermined degradation current threshold, wherein the second predetermined degradation current threshold is greater than the first predetermined degradation current threshold; and

[0114] In response to determining that the amperage of the current flowing between the first power terminal and the second power terminal is greater than the second predetermined degradation current threshold, a fault output signal is sent to set the degradation level of the electronic solid-state switch to degradation level two.

[0115] 20. The circuit system according to technical solution 16, wherein the external controller is configured to command the electronic solid-state switch to change to the on state

[0116] In response to transitioning to the on state, the signal processing and diagnostic controller is configured to:

[0117] reading a gate-source voltage, a gate-source amperage, a temperature, an amperage of a current flowing between the first power terminal and the second power terminal, and a voltage between the first power terminal and the second power terminal of the electronic solid-state switch;

[0118] calculating a drain-source resistance of the electronic solid-state switch by dividing the voltage between the first power terminal and the second power terminal by the amperage of the current flowing between the first power terminal and the second power terminal;

[0119] responsive to calculating the drain-source resistance of the electronic solid-state switch, comparing the drain-source resistance to a predetermined on-resistance threshold;

[0120] determining that the drain-source resistance is greater than the predetermined on-resistance threshold;

[0121] responsive to determining that the drain-source resistance is greater than the predetermined on-resistance threshold, comparing the gate-source amperage to a predetermined gate-source amperage threshold;

[0122] determining that the gate-source amperage is greater than the predetermined gate-source amperage threshold; and

[0123] In response to determining that the gate-source amperage is greater than the predetermined gate-source amperage threshold, a fault output signal is sent, thereby setting the degradation level of the electronic solid-state switch to degradation level four.

[0124] The above features and advantages and other features and advantages of the present teachings are readily apparent from the following detailed description of some of the best modes and other embodiments for carrying out the teachings as defined in the appended claims when taken in connection with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0125] Figure 1 is a schematic diagram of a circuit system including an electronic solid-state switch and a gate driver and a protection system electrically connected to the electronic solid-state switch.

[0126] Figure 2 is a flow chart of the first diagnostic method.

[0127] Figure 3 is a flow chart of the second diagnostic method.

[0128] Figure 4 This is a flow chart of the third diagnostic method.

[0129] Figure 5 is a flow chart of the fourth diagnostic method. DETAILED DESCRIPTION

[0130] The following detailed description is merely exemplary in nature and is not intended to limit the application and uses. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding background, summary, or the following detailed description.

[0131] Embodiments of the present disclosure may be described herein in terms of functional and / or logical block components and various processing steps. It should be understood that such block components may be implemented by a variety of hardware, software, and / or firmware components configured to perform specified functions. For example, embodiments of the present disclosure may employ various integrated circuit components, such as memory elements, digital signal processing elements, logic elements, lookup tables, and the like, which may perform various functions under the control of one or more microprocessors or other control devices. Furthermore, those skilled in the art will recognize that embodiments of the present disclosure may be practiced in conjunction with many systems, and the systems described herein are merely exemplary embodiments of the present disclosure.

[0132] For the sake of brevity, technologies related to signal processing, data fusion, signaling, control, and other functional aspects of the system (as well as the individual operating components of the system) may not be described in detail herein. Furthermore, the connecting lines shown in the various figures included herein are intended to represent exemplary functional relationships and / or physical connections between the various elements. It should be noted that alternative or additional functional relationships or physical connections may exist in embodiments of the present disclosure.

[0133] Figure 1 A circuit system 100 is shown that includes an electronic solid-state switch 102 and a gate driver and protection system 200. The electronic solid-state switch 102 has an off state and an on state. The electronic solid-state switch 102 is capable of withstanding at least 650 volts (and more preferably at least 1200 volts) during the off state and carrying a continuous current of at least 400 amperes during the on state. Due to the configuration described below, the gate driver and protection system 200 consumes less than one watt of power and is compact enough for integration in close proximity to the terminals of the electronic solid-state switch 102. The dimensions of the gate driver and protection system 200 do not exceed 55 mm in length, 25 mm in width, and 10 mm in height.

[0134] The electronic solid-state switch 102 includes a substrate 106 having mounting holes 105 on opposite sides of the substrate 106. The substrate 106 has a planar shape (and therefore a flat configuration) to minimize the overall size of the electronic solid-state switch 102. Furthermore, the substrate 106 can be made, in whole or in part, of a thermally conductive material, such as a metal, a metal alloy, or a metal matrix composite. For example, the substrate 106 can be made, in whole or in part, of copper, aluminum, aluminum silicon carbide (AlSiC), copper-infused graphite, graphene, copper foam, etc., and can be mounted to a heat sink.

[0135] The electronic solid-state switch 102 includes an electrically insulating and thermally conductive layer 110 disposed on (though not directly on) a substrate 106. The electrically insulating and thermally conductive layer 110 may be made entirely or partially of a ceramic material. Suitable ceramic materials for the electrically insulating and thermally conductive layer 110 include, but are not limited to, aluminum oxide (Al2O3), aluminum nitride (AlN), aluminum silicon carbide (AlSiC), silicon nitride (Si3N4), and the like. The electronic solid-state switch 102 includes a solder layer disposed between the substrate 106 and the electrically insulating and thermally conductive layer 110 to connect the substrate 106 to the electrically insulating and thermally conductive layer 110. The term "solder" refers to a low-melting-point alloy, particularly one based on lead and tin or (for higher temperatures) brass or silver, which is used to bond less fusible metals. The electronic solid-state switch 102 also includes a metal sheet directly coupled to the electrically insulating and thermally conductive layer 110 to form a direct-bonding substrate. The metal sheet may be made entirely or partially of aluminum to form a direct bonded aluminum (DBA) substrate in conjunction with the electrically insulating and thermally conductive layer 110 . The metal sheet may be directly coupled to (and disposed directly on) the solder layer to enhance the structural integrity of the electronic solid-state switch 102 .

[0136] Electronic solid-state switch 102 also includes a first conductive trace 116 disposed directly on electrically insulating and thermally conductive layer 110 to minimize the size occupied by electronic solid-state switch 102. First conductive trace 116 is disposed directly on (and directly bonded to) electrically insulating and thermally conductive layer 110 to enhance the structural integrity of electronic solid-state switch 102. First conductive trace 116 has a planar shape to minimize its size and forms a positive terminal. Furthermore, first conductive trace 116 is made, in whole or in part, of a metallic material, such as copper.

[0137] Electronic solid-state switch 102 also includes a second conductive trace 118 disposed directly on electrically insulating and thermally conductive layer 110 to minimize the space occupied by electronic solid-state switch 102 . For example, second conductive trace 118 is disposed directly on (and directly bonded to) electrically insulating and thermally conductive layer 110 . Second conductive trace 118 has a planar shape to minimize its size and forms a negative terminal. Furthermore, second conductive trace 118 is made of a metallic material, such as copper or aluminum.

[0138] The electronic solid-state switch 102 also includes a plurality of signal conductors 120 (e.g., a first signal conductor 120a and a second signal conductor 120b) disposed directly on the electrically insulating and thermally conductive layer 110. A first conductive trace 116 is substantially U-shaped and partially surrounds the signal conductors 120. In this disclosure, the term "substantially U-shaped" refers to a shape comprising two parallel legs directly connected to another leg perpendicular to the two parallel legs. A second conductive trace 118 is also substantially U-shaped and partially surrounds the first conductive trace 116. The substantially U-shape of the first and second conductive traces 116, 118, helps minimize the size of the electronic solid-state switch 102. The first and second signal conductors 120a, 120b are made entirely or partially of a metallic material, such as copper or aluminum, and are directly bonded to the electrically insulating and thermally conductive layer 110 (e.g., a ceramic layer). The first signal conductor 120a may be referred to as a source conductor (S), and the second signal conductor 120b may be referred to as a gate conductor. The control input carried by the signal conductor 120 consumes near zero power (ie, less than one watt) to keep the electronic solid-state switch 102 on or off.

[0139] The electronic solid-state switch 102 includes a plurality of semiconductor dies 122, each disposed directly on the first conductive trace 116 to facilitate the flow of power. Although the depicted embodiment shows eight semiconductor dies 122, the electronic solid-state switch 102 includes four to sixteen semiconductor dies 122 (each having a voltage rating of 650 volts to 1200 volts) electrically connected in parallel to each other to carry a current of at least 400 A and enhance scalability. Each semiconductor die in the plurality of semiconductor dies 122 forms a metal oxide semiconductor field effect transistor (MOSFET) and includes a source terminal, a gate terminal, and a drain terminal. Each semiconductor die 122 has a minimum area of ​​20 square millimeters to carry a total current of at least 400 A.

[0140] Each of the plurality of semiconductor dies 122 comprises a semiconductor material such as silicon, silicon carbide, gallium oxide, and gallium nitride. The semiconductor dies 122 are arranged in a predetermined pattern atop a direct-bond substrate to maintain substantially equal current and temperature distribution. The die pitch and terminal positions are selected to maintain substantially equal current and temperature distribution between the electrically connected semiconductor dies 122 and minimize package size. The bottom side of each semiconductor die 122 is directly coupled to the first conductive trace 116. The placement of the semiconductor dies 122 and the direct-bond substrate pattern achieve equal current distribution and low parasitic inductance. The electronic solid-state switch 102 includes a plurality of damping resistors 121, each electrically connected in series to the gate terminal of a corresponding MOSFET to prevent or at least minimize power oscillations. The plurality of semiconductor dies 122 are electrically connected in parallel to achieve a scalable current rating (e.g., multiples of 100A).

[0141] The electronic solid-state switch 102 includes a first plurality of electrical bonds, each electrically connected to a respective semiconductor die in the plurality of semiconductor dies 122. Specifically, each electrical bond in the first plurality of electrical bonds electrically connects a source terminal of a respective MOSFET to the second conductive trace 118. Each electrical bond in the first plurality of electrical bonds electrically interconnects the plurality of semiconductor dies 122 and the second conductive trace 118. Each electrical bond in the first plurality of electrical bonds can be a high current lead bond, a ribbon bond, or a foil bond to minimize parasitic inductance and resistance.

[0142] The electronic solid-state switch 102 also includes a second plurality of electrical bondings, each of which electrically connects the plurality of signal conductors 120 to the plurality of semiconductor dies 122. Specifically, each of the second plurality of electrical bondings electrically connects the gate terminal and the source terminal of a corresponding MOSFET to the first signal conductor 120a and the second signal conductor 120b, respectively. The second plurality of electrical bondings can be low-current lead bondings to minimize parasitic inductance and resistance.

[0143] The electronic solid-state switch 102 may include a plurality of power terminals 132 (e.g. ， A first power terminal 132a and a second power terminal 132b are provided. The first power terminal 132a is directly coupled to (and electrically connected to) the first conductive trace 116. The second power terminal 132b is directly coupled to (and electrically connected to) the second conductive trace 118. The power terminals 132 are electrically isolated from the substrate 106. The electronic solid-state switch 102 may optionally include one or more current sensors electrically or magnetically connected to the second power terminal 132b to measure the current (e.g., in amperes) of the electronic solid-state switch 102.

[0144] The electronic solid-state switch 102 may optionally include one or more thermistors 134 disposed on the electrically insulating and thermally conductive layer 110 to measure (with optimal accuracy) the temperature of the electronic solid-state switch 102. The thermistors 134 may be directly coupled to the signal conductors 120 to measure and monitor the temperature of the electronic solid-state switch 102. One terminal of the thermistor 134 may be directly coupled to the first signal conductor 120a, and another terminal of the thermistor 134 may be directly coupled to the second signal conductor 120d. Alternatively, the thermistor 134 may be embedded as a chip adjacent to the bare semiconductor die 122. The thermistor 134 helps detect and prevent thermal overload.

[0145] Circuit system 100 also includes a gate driver and protection system 200 to protect electronic solid-state switch 102. Circuit system 100 also includes a voltage source 202 configured to output a supply voltage Vcc. Gate driver and protection system 200 also includes an isolated bias power supply circuit 204 electrically connected to voltage source 202. Thus, isolated bias power supply circuit 204 is configured to receive supply voltage Vcc from voltage source 202. Isolated bias power supply circuit 204 is configured to output a fixed DC voltage of at least 15 volts. Isolated bias power supply circuit 204 is configured as a printed circuit board to minimize the size of gate driver and switch protection system 200. Alternatively, isolated bias power supply circuit 204 can be configured as an on-chip integrated transformer-based power supply to minimize the size of circuit 10. Thus, isolated bias power supply circuit 204 can include one or more transformers 205 to provide a DC bias voltage of at least 15 volts. Therefore, the isolated bias power supply circuit 204 can convert and isolate the power supply voltage Vcc supplied by the voltage source 202 and output a DC bias voltage of at least 15V through the transformer 205. The isolated bias power supply circuit 204 has a minimum input of 1500V to output an isolation voltage withstand rating, and a minimum creepage distance of 9mm.

[0146] The gate driver and protection system 200 also includes a current buffer circuit 206 electrically connected to the isolated bias power supply circuit 204. Specifically, the current buffer circuit 206 is electrically connected between the gate terminal of the electronic solid-state switch 102 and the isolated bias power supply circuit 204. The current buffer circuit 206 is configured to source and sink an output current of at least 1 ampere and have an output resistance of less than 2 ohms. It is contemplated that the current buffer circuit 206 is configured to source and sink an output current of at least 1 ampere and have an output resistance of less than 2 ohms. The current buffer circuit 206 is configured to cause the electronic solid-state switch 102 to transition between an on state and an off state in less than five microseconds under non-inductive load operation. For example, the current buffer circuit 206 is configured to cause the electronic solid-state switch 102 to transition between an on state and an off state in less than two microseconds under non-inductive load operation. The current supplied to the electronic solid-state switch 102 by the isolated bias power supply circuit 204 through the current buffer circuit 206 has a gate-source voltage V GS and gate-source amperage I GS . Gate-source voltage V GS is the control voltage supplied to the electronic solid-state switch 102. Gate-source amperage I GS is the amperage of the control current supplied to the electronic solid-state switch 102 .

[0147] Circuit system 100 also includes an external controller 208 configured to provide control inputs. External controller 208 includes at least one processor and a non-transitory computer-readable storage device or medium. The processor can be a custom or commercially available processor, a central processing unit (CPU), a graphics processing unit (GPU), a secondary processor among several processors associated with external controller 208, a semiconductor-based microprocessor (in the form of a microchip or chipset), a macroprocessor, a combination thereof, or generally a device for executing instructions. For example, the computer-readable storage device or medium can include volatile and non-volatile storage devices such as read-only memory (ROM), random access memory (RAM), and keep-alive memory (KAM). KAM is a permanent or non-volatile memory that can be used to store various operating variables when the processor loses power. The computer-readable storage device or medium may be implemented using any of a number of memory devices, such as a PROM (Programmable Read Only Memory), an EPROM (Electrical PROM), an EEPROM (Electrically Erasable PROM), flash memory, or other electrical, magnetic, optical, or combination memory devices capable of storing data, some of which represent executable instructions used by the external controller 208 in controlling the gate driver and protection system 200.

[0148] The gate driver and protection system 200 also includes a first digital logic isolator circuit 210 and a second digital logic isolator circuit 212, each electrically connected to the isolated bias power supply circuit 204. Thus, each of the first digital logic isolator circuit 210 and the second digital logic isolator circuit 212 receives a bias voltage from the isolated bias power supply circuit 204. Each of the first digital logic isolator circuit 210 and the second digital logic isolator circuit 212 is packaged as a chip scale package to minimize the gate driver and protection system 200. The first digital logic isolator circuit 210 is electrically coupled to the external controller 208 and is thus configured to isolate and control inputs received from the external controller 208. The second digital logic isolator circuit 212 is configured to control the fault output signal FO. The first digital logic isolator circuit 210 and the current buffer circuit 206 together form a gate driver 211. In this disclosure, the term "gate driver" refers to a power amplifier that accepts a relatively low-power input from a controller (e.g., the external controller 208) and generates a high-current drive input for the gate of a high-power transistor (e.g., the electronic solid-state switch 102). The time rate of change of current (di / dt) and voltage (dv / dt) are controlled to minimize transient voltage and current overshoots to less than 10% of the operating voltage and current.

[0149] The gate driver and protection system 200 also includes a snubber control and fault logic circuit 214 electrically connected to the electronic solid-state switch 102. As such, the snubber control and fault logic circuit 214 receives a signal from the thermistor 134 (which indicates the temperature of the electronic solid-state switch 102) and a voltage V between the first power supply terminal 132a and the second power supply terminal 132b. 1-2 The current sensor 133 may be electrically coupled to the electronic solid-state switch 102. The current sensor 133 is configured to measure the amperage I of the current flowing between the first power terminal 132a and the second power terminal 132b. 1-2 The current sensor 133 may be a fast current sensor and / or a switch-on voltage sensor to limit short-circuit or overload current to less than 120% of the rated current with a delay of less than 2 microseconds. The current sensor 133 allows for detection of overcurrent and safe shutdown of the electronic solid-state switch 102. The snubber control and fault logic circuit 214 is electrically connected to the current sensor 133. Thus, the snubber control and fault logic circuit 214 is configured to receive an amperage I from the current sensor 133 indicative of the current flowing between the first power terminal 132a and the second power terminal 132b. 1-2signal. Buffer control and fault logic circuit 214 and second digital logic isolator circuit 212 together form a signal processing and diagnostic controller 213. Signal processing and diagnostic controller 213 may include multiple comparators 215, such as operational amplifier voltage comparators, for comparing two voltages or currents. In this disclosure, the term "comparator" refers to a circuit that compares two voltages or currents and outputs a signal indicating which is greater. Buffer control and fault logic circuit 214 may include comparators 215 (i.e., current comparators and / or voltage comparators) to compare two voltages or currents and output a signal indicating which is greater.

[0150] The gate driver and protection system 200 also includes a snubber circuit 216 electrically connected in close proximity to the first power supply terminal 132a and the second power supply terminal 132b of the electronic solid-state switch 102 to allow the rated current of a voltage source (having a predetermined inductance) connected in series with the switch to be switched in less than 0.5 milliseconds (e.g., less than 0.2 milliseconds) while minimizing transient voltages across the electronic solid-state switch 102. The snubber circuit 216 may include one or more transient voltage suppressors (TVS) 218 ​​(such as Zener diodes) electrically connected (e.g., in parallel) to a damping resistor-capacitor circuit (RC circuit) 220 of a predetermined threshold. The breakdown voltage of the TVS 218 is at least 125% of the maximum operating input voltage but less than approximately 90% of the rated voltage of the electronic solid-state switch 102. The energy rating of the TVS 218 is greater than 0.5L. s I pk 2 , where L s is the total inductance (i.e., the inductance of the voltage source and the load), and I pk is the worst-case current interrupted by the electronic solid-state switch 102. Alternatively, the snubber circuit 216 includes a series RC circuit 220 electrically connected across the first power terminal 132a and the second power terminal 132b of the electronic solid-state switch 102. The resistance of the resistor and the capacitance of the RC circuit 220 are predetermined to limit the voltage across the electronic solid-state switch 102 to less than approximately 90% of the rated voltage and to achieve load current interruption in less than a predetermined amount of time at a predetermined total source and load inductance.

[0151] Figure 2 is a flow chart of a first diagnostic method 300. The first diagnostic method 300 begins at block 302, where the external controller 208 sets the control input signal CI to the OFF state. In other words, the external controller 208 commands the electronic solid-state switch 102 to transition to the OFF state. The first diagnostic method 300 then proceeds to block 304.

[0152] At block 304 , the signal processing and diagnostic controller 213 reads the gate-source voltage V GS , Gate-Source Amperage IGS , temperature T, ampere I of the current flowing between the first power terminal 132a and the second power terminal 132b 1-2 , and the voltage V between the first power supply terminal 132a and the second power supply terminal 132b 1-2 . V GS is the control voltage supplied to the electronic solid-state switch 102 between the gate-source terminals. Amperage I GS is the amperage of the current supplied through the gate-source terminals to the electronic solid-state switch 102. Temperature T is the temperature of the electronic solid-state switch 102. The first diagnostic method 300 then continues to block 306.

[0153] At block 306 , the signal processing and diagnostic controller 213 converts the gate-source voltage V GS With the predetermined turn-off gate-source voltage threshold V gsoff The predetermined turn-off gate-source voltage threshold V gsoff is the maximum setting voltage that can be supplied to the electronic solid-state switch 102, which can keep the electronic solid-state switch 102 in the off state. If the gate-source voltage V GS Not less than the predetermined turn-off gate-source voltage threshold V gsoff , the first diagnostic method 300 proceeds to box 315. At box 315, the signal processing and diagnostic controller 213 outputs the fault output signal FO. At box 315, the signal processing and diagnostic controller 213 sets the fault output signal FO to an off-state abnormality, thereby indicating that the electronic solid-state switch 102 is operating abnormally in the off state. If the gate-source voltage V GS is less than the predetermined turn-off gate-source voltage threshold V gsoff , the first diagnostic method 300 proceeds to block 308 .

[0154] At block 308 , the signal processing and diagnostic controller 213 converts the voltage V between the first power supply terminal 132 a and the second power supply terminal 132 b to 1-2 With the predetermined shutdown voltage threshold V off The predetermined turn-off voltage threshold V off is the minimum set voltage that should be output from the electronic solid-state switch 102 when transitioning to the off state. If the voltage V 1-2 Not greater than the predetermined turn-off voltage threshold V off , the first diagnostic method 300 proceeds to box 315. At box 315, the signal processing and diagnostic controller 213 outputs the fault output signal FO. At box 315, the signal processing and diagnostic controller 213 sets the fault output signal FO to the off state abnormality, thereby indicating that the electronic solid-state switch 102 is operating abnormally in the off state. If the voltage V 1-2 Greater than the predetermined turn-off voltage threshold Voff , the first diagnostic method 300 proceeds to box 310 .

[0155] At block 310, the signal processing and diagnostic controller 213 calculates the amperage I of the current flowing between the first power supply terminal 132a and the second power supply terminal 132b. 1-2 With the predetermined shutoff amperage threshold I off The predetermined cut-off ampere threshold I off is the maximum set ampere that can be output from the electronic solid-state switch 102 when transitioning to the OFF state. If the ampere I 1-2 Not less than the predetermined shutoff ampere threshold I off , the first diagnostic method 300 proceeds to box 315. At box 315, the signal processing and diagnostic controller 213 outputs the fault output signal FO. At box 315, the signal processing and diagnostic controller 213 sets the fault output signal FO to the off-state abnormality, thereby indicating that the electronic solid-state switch 102 is operating abnormally in the off state. If the amperage I 1-2 Less than the predetermined shutoff ampere threshold I off , the first diagnostic method 300 proceeds to block 312 .

[0156] At block 312, the signal processing and diagnostic controller 213 converts the gate-source amperage I GS and the predetermined turn-off gate-source amperage threshold I gsoff The predetermined turn-off gate-source amperage threshold I gsoff is the maximum set current that can be supplied to the electronic solid-state switch 102 to turn the electronic solid-state switch 102 into the off state. If the gate-source amperage I GS Not less than the predetermined turn-off gate-source amperage threshold I gsoff , the first diagnostic method 300 proceeds to block 315. At block 315, the signal processing and diagnostic controller 213 outputs the fault output signal FO. At block 315, the signal processing and diagnostic controller 213 sets the fault output signal FO to an off-state abnormality, thereby indicating that the electronic solid-state switch 102 is operating abnormally in the off state. If the gate-source amperage I GS Less than the predetermined turn-off gate-source amperage threshold I gsoff , the first diagnostic method 300 proceeds to block 314. At block 314, the signal processing and diagnostic controller 213 sets the fault output signal FO to pass the off-state test, thereby indicating that the electronic solid-state switch 102 is operating normally in the off-state.

[0157] Figure 34 is a flow chart of a second diagnostic method 400 that can be combined with the first diagnostic method 300. The second diagnostic method 400 begins at block 402, where the external controller 208 sets the control input signal CI to the on state. In other words, the external controller 208 commands the electronic solid-state switch 102 to transition to the on state. The second diagnostic method 400 then proceeds to block 304.

[0158] At block 404 , the signal processing and diagnostic controller 213 reads the gate-source voltage V GS , Gate-Source Amperage I GS , temperature T, ampere I of the current flowing between the first power terminal 132a and the second power terminal 132b 1-2 , and the voltage V between the first power supply terminal 132a and the second power supply terminal 132b 1-2 Voltage V GS is the voltage supplied to the electronic solid-state switch 102 between the gate-source terminals. Amperage I GS is the amperage of the current supplied through the gate-source terminals to the electronic solid-state switch 102. Temperature T is the temperature of the electronic solid-state switch 102. The second diagnostic method 400 then continues to block 406.

[0159] At block 406 , the signal processing and diagnostic controller 213 converts the gate-source voltage V GS With the predetermined gate-source voltage threshold V gson The predetermined gate-source voltage threshold V gson is the minimum set voltage that should be supplied to the electronic solid-state switch 102 to turn the electronic solid-state switch 102 into the on state. If the gate-source voltage is not greater than the predetermined turn-on gate-source voltage threshold V gso , the second diagnostic method 400 proceeds to box 415. At box 415, the signal processing and diagnostic controller 213 outputs the fault output signal FO. At box 415, the signal processing and diagnostic controller 213 sets the fault output signal FO to an ON state abnormality, thereby indicating that the electronic solid-state switch 102 is operating abnormally in the ON state. If the gate-source voltage is greater than the predetermined ON gate-source voltage threshold V gso , the second diagnostic method 400 proceeds to block 408 .

[0160] At block 408 , the signal processing and diagnostic controller 213 converts the voltage V between the first power supply terminal 132 a and the second power supply terminal 132 b to 1-2 With the predetermined turn-on voltage threshold V on The predetermined turn-on voltage threshold V on is the maximum set voltage that may exist across the electronic solid-state switch 102 when transitioning to the on state. If the voltage V1-2 If the voltage V is not less than the predetermined ON voltage threshold, the second diagnostic method 400 proceeds to block 415. At block 415, the signal processing and diagnostic controller 213 outputs the fault output signal FO. At block 415, the signal processing and diagnostic controller 213 sets the fault output signal FO to ON state abnormality, thereby indicating that the electronic solid-state switch 102 is operating abnormally in the ON state. 1-2 is less than the predetermined key-on voltage threshold, the second diagnostic method 400 proceeds to block 410 .

[0161] At block 410, the signal processing and diagnostic controller 213 calculates the amperage I of the current flowing between the first power supply terminal 132a and the second power supply terminal 132b. 1-2 With the predetermined amperage threshold I on The predetermined on-ampere threshold I on is the minimum set ampere that should be output from the electronic solid-state switch 102 when transitioning to the on state. If the ampere I 1-2 Not greater than the predetermined on-ampere threshold I on , the second diagnostic method 400 proceeds to box 415. At box 415, the signal processing and diagnostic controller 213 outputs the fault output signal FO. At box 415, the signal processing and diagnostic controller 213 sets the fault output signal FO to ON state abnormality, thereby indicating that the electronic solid-state switch 102 is operating abnormally in the ON state. If the amperage I 1-2 Greater than the predetermined amperage I on , the second diagnostic method 400 proceeds to block 412 .

[0162] At block 412, the signal processing and diagnostic controller 213 converts the gate-source amperage I GS With the predetermined gate-source amperage threshold I gson The predetermined turn-off gate-source amperage threshold I gson is the maximum set voltage that should be supplied to the electronic solid-state switch 102 in order to turn the electronic solid-state switch 102 into the on state. GS Not less than the predetermined gate-source amperage threshold I gson , the second diagnostic method 400 proceeds to block 415. At block 415, the signal processing and diagnostic controller 213 outputs the fault output signal FO. At block 415, the signal processing and diagnostic controller 213 sets the fault output signal FO to ON-state abnormality, thereby indicating that the electronic solid-state switch 102 is operating abnormally in the ON state. GS Less than the predetermined gate-source amperage threshold I gson, the second diagnostic method 400 proceeds to block 414. At block 414, the signal processing and diagnostic controller 213 sets the fault output signal FO to pass the on-state test, thereby indicating that the electronic solid-state switch 102 is operating normally in the on-state.

[0163] Figure 4 is a flow chart of a third diagnostic method 500 for determining a degradation level of an electronic solid-state switch 102. The third diagnostic method 500 begins at block 502, where the external controller 208 sets the control input signal CI to the OFF state. In other words, the external controller 208 commands the electronic solid-state switch 102 to transition to the OFF state. The third diagnostic method 500 then proceeds to block 504.

[0164] At block 504 , the signal processing and diagnostic controller 213 reads the gate-source voltage V GS , Gate-Source Amperage I GS , temperature T, ampere I of the current flowing between the first power terminal 132a and the second power terminal 132b 1-2 , and the voltage V between the first power supply terminal 132a and the second power supply terminal 132b 1-2 Voltage V GS is the voltage supplied to the electronic solid-state switch 102 between the gate-source terminals. Amperage I GS is the amperage of the current supplied through the gate-source terminals to the electronic solid-state switch 102. Temperature T is the temperature of the electronic solid-state switch 102. The third diagnostic method 500 then continues to block 506.

[0165] At block 506 , the signal processing and diagnostic controller 213 compares the temperature T of the electronic solid-state switch 102 and the voltage V between the first power supply terminal 132 a and the second power supply terminal 132 b . 1-2 The function checks the amperage I of the current flowing between the first power supply terminal 132a and the second power supply terminal 132b. 1-2 This function may be in a lookup table developed through testing. After block 506 , the third diagnostic method 500 continues to block 508 .

[0166] At block 508, the signal processing and diagnostic controller 213 sets the amperage I of the current flowing between the first power supply terminal 132a and the second power supply terminal 132b. 1-2 and the first predetermined degradation current threshold I off1 If the ampere of the current flowing between the first power supply terminal 132a and the second power supply terminal 132b is 1-2 Not greater than the first predetermined degradation current threshold I off1, the third diagnostic method 500 proceeds to block 516. At block 516, the third diagnostic method 500 returns to the remaining control steps. 1-2 Greater than the first predetermined degradation current threshold I off1 , the third diagnostic method 500 proceeds to block 510 .

[0167] At block 510, the signal processing and diagnostic controller 213 sets the amperage I of the current flowing between the first power terminal 132a and the second power terminal 132b. 1-2 and the second predetermined degradation current threshold I off2 The second predetermined degradation current threshold I off2 Greater than the first predetermined degradation current threshold I off1 If the ampere of the current flowing between the first power terminal 132a and the second power terminal 132b is I 1-2 Not greater than the second predetermined degradation current threshold I off2 , the third diagnostic method 500 proceeds to block 512. At block 512, the signal processing and diagnostic controller 213 sends a fault output signal FO, thereby setting the degradation level of the electronic solid-state switch 102 to degradation level 1. After block 512, the third diagnostic method 500 proceeds to block 516. If the amperage I of the current flowing between the first power supply terminal 132a and the second power supply terminal 132b is 1-2 Greater than the second predetermined degradation current threshold I off2 , the third diagnostic method 500 proceeds to block 514. At block 514, the signal processing and diagnostic controller 213 sends a fault output signal FO, thereby setting the degradation level of the electronic solid-state switch 102 to degradation level 2. After block 514, the third diagnostic method 500 proceeds to block 516.

[0168] Figure 5 6 is a flow chart of a fourth diagnostic method 600 for determining a degradation level of an electronic solid-state switch 102. The fourth diagnostic method 600 begins at block 602, where the external controller 208 sets the control input signal CI to the on state. In other words, the external controller 208 commands the electronic solid-state switch 102 to transition to the on state. The fourth diagnostic method 600 then proceeds to block 604.

[0169] At block 604 , the signal processing and diagnostic controller 213 calculates the drain-source resistance R dson, which is the total resistance between the drain and source in the electronic solid-state switch 102 when the electronic solid-state switch 102 is in the on state. To this end, when the electronic solid-state switch 102 is in the on state, the signal processing and diagnostic controller 213 converts the voltage V between the first power supply terminal 132a and the second power supply terminal 132b to 1-2 Divide by the ampere I of the current flowing between the first power terminal 132a and the second power terminal 132b 1-2 (i.e. R dson = V 1-2 / I 1-2 ). Also, at block 606, the amperage I of the current flowing between the first power terminal 132a and the second power terminal 132b is compared to the temperature T. 1-2 and the gate-source voltage V GS Check the drain-source resistance R dson This function may be in a lookup table developed through testing. It also references the temperature T and gate-source voltage V of the electronic solid-state switch 102. GS Check the gate-source amperage I GS This function may be in a lookup table developed through testing. The fourth diagnostic method 600 then proceeds to block 608 .

[0170] At block 608 , the signal processing and diagnostic controller 213 sets the drain-source resistance R dson With the predetermined on-resistance threshold R on1 For comparison, if the drain-source resistance R dson Not greater than the predetermined on-resistance threshold R on1 , the fourth diagnostic method 600 proceeds to block 616. At block 616, the fourth diagnostic method 600 returns to block 602. If the drain-source resistance R dson Greater than the predetermined on-resistance threshold R on1 , the fourth diagnostic method 600 proceeds to block 610 .

[0171] At block 610, the signal processing and diagnostic controller 213 converts the gate-source amperage I GS With the predetermined gate-source amperage threshold I gson1 For comparison, if the gate-source amperage I GS Not greater than a predetermined gate-source amperage threshold I gson1 , the fourth diagnostic method 600 proceeds to block 612. At block 612, the signal processing and diagnostic controller 213 sends a fault output signal FO, thereby setting the degradation level of the electronic solid-state switch 102 to degradation level 3. After block 612, the fourth diagnostic method 600 proceeds to block 616. If the gate-source amperage I GS Greater than a predetermined gate-source amperage threshold Igson1 , the fourth diagnostic method 600 proceeds to block 614. At block 614, the signal processing and diagnostic controller 213 sends a fault output signal FO, thereby setting the degradation level of the electronic solid-state switch 102 to degradation level 4. After block 614, the fourth diagnostic method 600 proceeds to block 616.

[0172] The detailed description and the diagrams or drawings support and describe the present teachings, but the scope of the present teachings is limited only by the claims. Although some best modes and other embodiments for carrying out the present teachings have been described in detail, there are various alternative designs and embodiments for practicing the present teachings defined in the appended claims.

Claims

1. A circuit system, comprising: an electronic solid-state switch, the electronic solid-state switch comprising a first power terminal and a second power terminal; A driver and switch protection system electrically connected to the electronic solid-state switch, wherein the driver and switch protection system comprises: an isolated bias power supply circuit configured to output a DC voltage of at least fifteen volts; a current buffer circuit electrically connected between the isolated bias power supply circuit and the electronic solid-state switch; and a buffer circuit electrically connected to the first power terminal and the second power terminal; a signal processing and diagnostic controller and an external controller each electrically connected to the electronic solid-state switch, wherein the signal processing and diagnostic controller includes a plurality of comparators and the external controller is configured to command the electronic solid-state switch to transition between an OFF state and an ON state; wherein the external controller is configured to command the electronic solid-state switch to transition to the off state; In response to transitioning to the off state, the signal processing and diagnostic controller is configured to: reading a gate-source voltage, a gate-source amperage, a temperature, an amperage of a current flowing between the first power terminal and the second power terminal, and a voltage between the first power terminal and the second power terminal of the electronic solid-state switch; comparing the gate-source voltage to a predetermined turn-off gate-source voltage threshold; determining that the gate-source voltage is less than the predetermined turn-off gate-source voltage threshold; in response to determining that the gate-source voltage is less than the predetermined turn-off gate-source voltage threshold, comparing the voltage between the first power supply terminal and the second power supply terminal to a predetermined turn-off voltage threshold; determining that the voltage between the first power terminal and the second power terminal is greater than the predetermined turn-off voltage threshold; in response to determining that the voltage between the first power terminal and the second power terminal is greater than the predetermined off voltage threshold, comparing the amperage of the current between the first power terminal and the second power terminal to a predetermined off amperage threshold; determining that the amperage of the current between the first power terminal and the second power terminal is less than the predetermined shutoff amperage threshold; in response to determining that the amperage of the current between the first power terminal and the second power terminal is less than the predetermined turn-off amperage threshold, comparing the gate-source amperage to a predetermined turn-off gate-source amperage threshold; determining that the gate-source amperage is less than the predetermined off gate-source amperage threshold; and In response to determining that the gate-source amperage is less than the predetermined off gate-source amperage threshold, a fault output signal is set to pass an off state test, thereby indicating that the electronic solid-state switch is operating normally in the off state. 2 . The circuit system of claim 1 , wherein the current buffer circuit is configured to source and sink an output current of at least one ampere.

3. The circuit system of claim 2, wherein the output resistance of the current buffer circuit is less than two ohms. 4 . The circuit system of claim 3 , wherein the isolated bias power supply circuit is configured as a printed circuit board.

5. The circuit system of claim 3, wherein the isolated bias power supply circuit is an on-chip integrated transformer-based power supply having an output power of one watt + / - 0.5 watts, and the on-chip integrated transformer-based power supply includes a plurality of transformer windings.

6. The circuit system of claim 1, wherein the external controller is configured to command the electronic solid-state switch to transition to the on-state; In response to transitioning to the on state, the signal processing and diagnostic controller is configured to: reading a gate-source voltage, a gate-source amperage, a temperature, an amperage of the current flowing between the first power terminal and the second power terminal, and a voltage between the first power terminal and the second power terminal of the electronic solid-state switch; comparing the gate-source voltage to a predetermined turn-on gate-source voltage threshold; determining that the gate-source voltage is greater than the predetermined turn-on gate-source voltage threshold; in response to determining that the gate-source voltage is greater than the predetermined turn-on gate-source voltage threshold, comparing the voltage between the first power supply terminal and the second power supply terminal to a predetermined turn-on voltage threshold; determining that the voltage between the first power terminal and the second power terminal is less than the predetermined switch-on voltage threshold; in response to determining that the voltage between the first power terminal and the second power terminal is less than the predetermined turn-on voltage threshold, comparing the amperage of the current between the first power terminal and the second power terminal to a predetermined turn-on amperage threshold; determining that the amperage of the current between the first power terminal and the second power terminal is greater than the predetermined switch-on amperage threshold; in response to determining that the amperage of the current between the first power terminal and the second power terminal is greater than the predetermined turn-on amperage threshold, comparing the gate-source amperage to a predetermined turn-on gate-source amperage threshold; determining that the gate-source amperage is less than the predetermined turn-on gate-source amperage threshold; and In response to determining that the gate-source amperage is less than the predetermined on gate-source amperage threshold, a fault output signal is set to pass an on-state test, thereby indicating that the electronic solid-state switch is operating normally in the on-state.

7. The circuit system of claim 1, wherein the external controller is configured to command the electronic solid-state switch to transition to the off state; In response to transitioning to the off state, the signal processing and diagnostic controller is configured to: reading a gate-source voltage, a gate-source amperage, a temperature, an amperage of the current flowing between the first power terminal and the second power terminal, and a voltage between the first power terminal and the second power terminal of the electronic solid-state switch; comparing the amperage of the current flowing between the first power terminal and the second power terminal to a first predetermined degradation current threshold; determining that the amperage of the current flowing between the first power terminal and the second power terminal is greater than the first predetermined degradation current threshold; in response to determining that the amperage of the current flowing between the first power terminal and the second power terminal is greater than the first predetermined degradation current threshold, comparing the amperage of the current flowing between the first power terminal and the second power terminal to a second predetermined degradation current threshold; determining that the amperage of the current flowing between the first power terminal and the second power terminal is greater than a second predetermined degradation current threshold, wherein the second predetermined degradation current threshold is greater than the first predetermined degradation current threshold; as well as In response to determining that the amperage of the current flowing between the first power terminal and the second power terminal is greater than the second predetermined degradation current threshold, a fault output signal is sent to set the degradation level of the electronic solid-state switch to degradation level two.

8. The circuit system of claim 1, wherein the external controller is configured to command the electronic solid-state switch to transition to the on-state; In response to transitioning to the on state, the signal processing and diagnostic controller is configured to: reading a gate-source voltage, a gate-source amperage, a temperature, an amperage of the current flowing between the first power terminal and the second power terminal, and a voltage between the first power terminal and the second power terminal of the electronic solid-state switch; calculating a drain-source resistance of the electronic solid-state switch by dividing the voltage between the first power terminal and the second power terminal by the amperage of the current flowing between the first power terminal and the second power terminal; responsive to calculating the drain-source resistance of the electronic solid-state switch, comparing the drain-source resistance to a predetermined on-resistance threshold; determining that the drain-source resistance is greater than the predetermined on-resistance threshold; in response to determining that the drain-source resistance is greater than the predetermined on-resistance threshold, comparing the gate-source amperage to a predetermined gate-source amperage threshold; determining that the gate-source amperage is greater than the predetermined gate-source amperage threshold; and In response to determining that the gate-source amperage is greater than the predetermined gate-source amperage threshold, a fault output signal is sent to set the degradation level of the electronic solid-state switch to degradation level four.

9. A circuit system comprising: an electronic solid-state switch, the electronic solid-state switch comprising a first power terminal and a second power terminal; an external controller electrically connected to the electronic solid-state switch, wherein the external controller is configured to command the electronic solid-state switch to transition between an OFF state and an ON state; A driver and switch protection system electrically connected to the electronic solid-state switch, wherein the driver and switch protection system comprises: signal processing and diagnostic controllers; an isolated bias power supply circuit electrically connected to the signal processing and diagnostic controller; and a buffer circuit electrically connected to the first power terminal and the second power terminal; wherein the signal processing and diagnostic controller includes a plurality of comparators; wherein the external controller is configured to command the electronic solid-state switch to transition to the off state; In response to transitioning to the off state, the signal processing and diagnostic controller is configured to: reading a gate-source voltage, a gate-source amperage, a temperature, an amperage of a current flowing between the first power terminal and the second power terminal, and a voltage between the first power terminal and the second power terminal of the electronic solid-state switch; comparing the gate-source voltage to a predetermined turn-off gate-source voltage threshold; determining that the gate-source voltage is less than the predetermined turn-off gate-source voltage threshold; in response to determining that the gate-source voltage is less than the predetermined turn-off gate-source voltage threshold, comparing the voltage between the first power supply terminal and the second power supply terminal to a predetermined turn-off voltage threshold; determining that the voltage between the first power terminal and the second power terminal is greater than the predetermined turn-off voltage threshold; in response to determining that the voltage between the first power terminal and the second power terminal is greater than the predetermined off voltage threshold, comparing the amperage of the current between the first power terminal and the second power terminal to a predetermined off amperage threshold; determining that the amperage of the current between the first power terminal and the second power terminal is less than the predetermined shutoff amperage threshold; in response to determining that the amperage of the current between the first power terminal and the second power terminal is less than the predetermined turn-off amperage threshold, comparing the gate-source amperage to a predetermined turn-off gate-source amperage threshold; determining that the gate-source amperage is less than the predetermined off gate-source amperage threshold; and In response to determining that the gate-source amperage is less than the predetermined off gate-source amperage threshold, a fault output signal is set to pass an off state test, thereby indicating that the electronic solid-state switch is operating normally in the off state.

10. The circuit system of claim 9, wherein the signal processing and diagnostic controller includes a current buffer circuit electrically connected between the isolated bias power supply circuit and the electronic solid-state switch, and the current buffer circuit is configured to source and sink at least one ampere of output current.

11. The circuit system of claim 10, wherein the output resistance of the current buffer circuit is less than two ohms.

12. The circuit system of claim 11, wherein the isolated bias power supply circuit is configured as a printed circuit board.

13. The circuit system of claim 11, wherein the isolated bias power supply circuit is an on-chip integrated transformer-based power supply having a one-watt output power, and the on-chip integrated transformer-based power supply comprises a plurality of transformers.

14. The circuit system of claim 9, wherein the external controller is configured to command the electronic solid-state switch to transition to the on-state; In response to transitioning to the on state, the signal processing and diagnostic controller is configured to: reading a gate-source voltage, a gate-source amperage, a temperature, an amperage of a current flowing between the first power terminal and the second power terminal, and a voltage between the first power terminal and the second power terminal of the electronic solid-state switch; comparing the gate-source voltage to a predetermined turn-on gate-source voltage threshold; determining that the gate-source voltage is greater than the predetermined turn-on gate-source voltage threshold; in response to determining that the gate-source voltage is greater than the predetermined turn-on gate-source voltage threshold, comparing the voltage between the first power supply terminal and the second power supply terminal to a predetermined turn-on voltage threshold; determining that the voltage between the first power terminal and the second power terminal is less than the predetermined switch-on voltage threshold; in response to determining that the voltage between the first power terminal and the second power terminal is less than the predetermined turn-on voltage threshold, comparing the amperage of the current between the first power terminal and the second power terminal to a predetermined turn-on amperage threshold; determining that the amperage of the current between the first power terminal and the second power terminal is greater than the predetermined switch-on amperage threshold; in response to determining that the amperage of the current between the first power terminal and the second power terminal is greater than the predetermined turn-on amperage threshold, comparing the gate-source amperage to a predetermined turn-on gate-source amperage threshold; determining that the gate-source amperage is less than the predetermined turn-on gate-source amperage threshold; and In response to determining that the gate-source amperage is less than the predetermined on gate-source amperage threshold, a fault output signal is set to pass an on-state test, thereby indicating that the electronic solid-state switch is operating normally in the on-state.

15. The circuit system of claim 9, wherein the external controller is configured to command the electronic solid-state switch to transition to the off state; In response to transitioning to the off state, the signal processing and diagnostic controller is configured to: reading a gate-source voltage, a gate-source amperage, a temperature, an amperage of a current flowing between the first power terminal and the second power terminal, and a voltage between the first power terminal and the second power terminal of the electronic solid-state switch; comparing the amperage of the current flowing between the first power terminal and the second power terminal to a first predetermined degradation current threshold; determining that the amperage of the current flowing between the first power terminal and the second power terminal is greater than the first predetermined degradation current threshold; in response to determining that the amperage of the current flowing between the first power terminal and the second power terminal is greater than the first predetermined degradation current threshold, comparing the amperage of the current flowing between the first power terminal and the second power terminal to a second predetermined degradation current threshold; determining that the amperage of the current flowing between the first power terminal and the second power terminal is greater than a second predetermined degradation current threshold, wherein the second predetermined degradation current threshold is greater than the first predetermined degradation current threshold; as well as In response to determining that the amperage of the current flowing between the first power terminal and the second power terminal is greater than the second predetermined degradation current threshold, a fault output signal is sent to set the degradation level of the electronic solid-state switch to degradation level two.

16. The circuit system of claim 9, wherein the external controller is configured to command the electronic solid-state switch to transition to the on-state; In response to transitioning to the on state, the signal processing and diagnostic controller is configured to: reading a gate-source voltage, a gate-source amperage, a temperature, an amperage of a current flowing between the first power terminal and the second power terminal, and a voltage between the first power terminal and the second power terminal of the electronic solid-state switch; calculating a drain-source resistance of the electronic solid-state switch by dividing the voltage between the first power terminal and the second power terminal by the amperage of the current flowing between the first power terminal and the second power terminal; responsive to calculating the drain-source resistance of the electronic solid-state switch, comparing the drain-source resistance to a predetermined on-resistance threshold; determining that the drain-source resistance is greater than the predetermined on-resistance threshold; in response to determining that the drain-source resistance is greater than the predetermined on-resistance threshold, comparing the gate-source amperage to a predetermined gate-source amperage threshold; determining that the gate-source amperage is greater than the predetermined gate-source amperage threshold; and In response to determining that the gate-source amperage is greater than the predetermined gate-source amperage threshold, a fault output signal is sent to set the degradation level of the electronic solid-state switch to degradation level four.

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