Reference Voltage Buffer

Abstract

The present invention provides a reference voltage buffer, which includes a reference voltage generator for generating a reference voltage, a first operational amplifier, a first transistor, a first group of resistors, a first load, a second transistor, a second group of resistors and a second load. The first operational amplifier receives a reference voltage and a feedback signal and generates a control signal. The first and second transistors are controlled by the control signal. The first group of resistors is coupled to the first transistor and the first load, wherein the feedback signal is generated from an internal node of the first group of resistors. The second group of resistors is coupled to the second transistor and the second load. The reference voltage generator, the first load and the second load have the same characteristics in response to temperature changes. The present invention can provide a suitable output reference voltage for subsequent circuits with a faster stabilization time.

Description

Technical Field

[0001] The present invention relates generally to reference voltage buffers and, more particularly, to reference voltage buffers having faster settling times and greater full-scale ranges. Background Art

[0002] Analog-to-digital converters (ADCs) usually have reference voltage buffers to provide multiple reference voltages to comparators in quantizers. With the development of advanced semiconductor processes and faster clock signals, reference voltage buffers have encountered many design problems, such as stability issues, signal quality, and process-voltage-temperature (PVT) changes. Specifically, when the comparator in the quantizer starts to sample the input signal using the reference voltage, the reference voltage may drop suddenly, and the reference voltage buffer requires a settling time to return the reference voltage to its original level. As the frequency and sampling rate of the clock signal become faster, the settling time of the reference voltage buffer needs to be designed to be shorter to provide a stable reference voltage. In addition, considering the noise margin of the signal processed by the quantizer, the full scale of the reference voltage buffer should preferably be designed to be larger, that is, the difference between the highest reference voltage and the lowest reference voltage should be designed to be as large as possible. However, a larger full scale design may cause the reference voltage to be unstable. Furthermore, if the reference voltage buffer uses an active device as a load to generate the reference voltage, the reference voltage buffer may suffer from PVT problems and the reference voltage becomes unstable, thereby causing problems for the quantizer. Summary of the invention

[0003] Therefore, an object of the present invention is to provide a reference voltage buffer having a faster settling time and a larger full-scale range, and even when the level of the reference voltage changes due to PVT problems, the reference voltage buffer can provide a suitable reference voltage to the quantizer to solve the above problems.

[0004] According to one embodiment of the present invention, a reference voltage buffer includes a reference voltage generator for generating a reference voltage, a first operational amplifier, a first transistor, a first group of resistors, a first load, a second transistor, a second group of resistors, and a second load. The first operational amplifier is configured to receive a reference voltage and a feedback signal to generate a control signal. The first transistor is configured to be controlled by a control signal. The first group of resistors is coupled to the first transistor, wherein the feedback signal is generated from an internal node of the first group of resistors. The first load is coupled to the first group of resistors. The second transistor is configured to be controlled by a control signal. The second group of resistors is coupled to the second transistor. The second load is coupled to the second group of resistors. In addition, the reference voltage generator, the first load, and the second load have the same characteristics in response to temperature changes.

[0005] According to another embodiment of the present invention, a reference voltage buffer includes a reference voltage generator, a first operational amplifier, a first transistor, a first group of resistors, a first load, a second transistor, a second group of resistors, and a second load. The reference voltage generator is configured to generate a reference voltage. The first operational amplifier is configured to receive the reference voltage and a feedback signal to generate a control signal. The first transistor is configured to be controlled by the control signal. The first group of resistors is coupled to the first transistor, wherein the feedback signal is generated from an internal node of the first group of resistors. The first load is coupled to the first group of resistors. The second transistor is configured to be controlled by the control signal. The second group of resistors is coupled to the second transistor. The second load is coupled to the second group of resistors. In addition, the first load and the second load both include active devices.

[0006] The reference voltage buffer of the present invention can provide a suitable output reference voltage for subsequent circuits with a faster stabilization time.

[0007] These and other objects of the present invention will no doubt become apparent to those skilled in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various drawing figures. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In the following detailed description, for the purpose of explanation, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, it is apparent that one or more embodiments may be practiced without these specific details. In other cases, well-known structures and devices are schematically shown to simplify the drawings.

[0009] Figure 1 is a schematic diagram showing a reference voltage buffer according to one embodiment of the present invention.

[0010] Figure 2 FIG. 4 is a detailed schematic circuit diagram of a reference voltage buffer according to an embodiment of the present invention.

[0011] Figure 3 is a schematic diagram showing a quantizer according to an embodiment of the present invention. DETAILED DESCRIPTION

[0012] Figure 1 FIG. 1 is a schematic diagram showing a reference voltage buffer 100 according to an embodiment of the present invention. Figure 1 As shown, the reference voltage buffer 100 includes a reference voltage generator 110, an operational amplifier 120, a first transistor MN1, a first group of resistors including resistors R11 to R1N, a load 130, a second transistor MN2, a second group of resistors including resistors R21 to R2N, and a load 140. The operational amplifier 120 has a positive input terminal, a negative input terminal, and an output terminal, wherein the positive input terminal is coupled to the reference voltage generator 110, the negative input terminal is coupled to a node in the first group of resistors (in this embodiment, the negative input terminal is coupled to a node between resistors R13 and R14, i.e., receives a feedback signal), and the output terminal is configured to output a control signal Vc to the first transistor MN1 and the second transistor MN2. The transistor MN1 is implemented by using an N-type metal-oxide-semiconductor (NMOS) having a drain, a source, and a gate, wherein the drain is coupled to the power supply voltage VDD, the source is coupled to the resistor R11, and the gate receives the control signal Vc generated by the operational amplifier 120. Resistors R11 to R1N are connected in series, wherein resistor R11 is coupled to the source of transistor MN1, and resistor R1N is coupled to load 130. Transistor MN2 is implemented by using an NMOS having a drain, a source, and a gate, wherein the drain is coupled to power supply voltage VDD, the source is coupled to resistor R21, and the gate receives control signal Vc generated by operational amplifier 120. Resistors R21 to R2N are connected in series, wherein resistor R21 is coupled to the source of transistor MN2, and resistor R2N is coupled to load 140.

[0013] During operation of the reference voltage buffer 100, the reference voltage generator 110 generates a reference voltage Vref to the positive input terminal of the operational amplifier 120, and the operational amplifier 120 compares the reference voltage Vref with the signal from the first group of resistors to generate a control signal Vc to the gates of the transistors MN1 and MN2. By using the closed-loop structure of the operational amplifier 120 and the transistor MN1, the voltage level at the node between the resistors R13 and R14 can be controlled to be equal to the reference voltage Vref. In addition, the transistor MN2, the second group of resistors, and the load 140 are copies of the transistor MN1, the first group of resistors, and the load 130, respectively, and as shown in FIG. Figure 1As shown, the second set of resistors is configured to generate a plurality of output reference voltages, eg, Vrp[m], Vrp[m-1], ... Vrn[m].

[0014] exist Figure 1 In the reference voltage buffer 100 shown, since the operational amplifier 120, the transistor MN1 and the first group of resistors form a closed loop, the transistor MN2 and the second group of resistors are used to provide the output reference voltages Vrp[m], Vrp[m-1]...Vrn[m] to the subsequent circuits, so that the generation of the output reference voltages Vrp[m], Vrp[m-1]...Vrn[m] will be more stable. Specifically, when the subsequent circuits use the output reference voltages Vrp[m], Vrp[m-1]...Vrn[m], the output reference voltages Vrp[m], Vrp[m-1]...Vrn[m] may suddenly drop. At this time, since the operational amplifier 120 still provides a stable control signal Vc to the gate electrode of the transistor MN2, the output reference voltages Vrp[m], Vrp[m-1]...Vrn[m] will immediately return to the original level, that is, the reference voltage buffer 100 has a better stabilization time. In addition, when the reference voltage buffer 100 is used in an ADC with a fast sampling rate, the stabilization time needs to be designed to be shorter to stabilize the output reference voltage. In this embodiment, the loads 130 and 140 use active devices such as NMOS or PMOS to make the stabilization time shorter.

[0015] Although the settling time of the reference voltage buffer 100 can be improved by using the loads 130 and 140 having active devices, the active devices may be susceptible to PVT problems, that is, the output reference voltages Vrp[m], Vrp[m-1], ..., Vrn[m] are susceptible to PVT variations. To solve this problem, the loads 130, 140, and the reference voltage generator 110 are designed to have the same characteristics for PVT variations, that is, if the temperature variation causes the loads 130 / 140 to have a larger dropout voltage (e.g., the voltage at the node between the resistor R1N and the load 130 becomes higher), the temperature variation also causes the reference voltage generator 110 to generate a reference voltage Vref having a higher level. For example, the loads 130 and 140 are both loads that are inverse proportional to absolute temperature (inversePTAT) (i.e., inverse PTAT), and the reference voltage generator 110 is an inverse PTAT reference voltage generator.

[0016] By designing the loads 130 and 140 and the reference voltage generator 110 to have the same characteristics in response to PVT changes, the output reference voltages Vrp[m], Vrp[m-1]...Vrn[m] are suitable for the comparators of the quantizer even if the absolute values ​​of the output reference voltages Vrp[m], Vrp[m-1]...Vrn[m] change. Specifically, each comparator in the quantizer receives two output reference voltages generated by the reference voltage buffer 100, for example, one comparator uses the output reference voltages Vrp[m] and Vrn[m], another comparator uses the output reference voltages Vrp[m-1] and Vrn[m-1]...and so on. When the temperature change causes the load 140 to have a larger voltage difference (i.e., the voltage level of the output reference voltage Vrn[m] increases), the reference voltage Vref provided by the reference voltage generator increases, so that the node between the resistors R13 and R14 has a higher voltage level, and the node between the resistors R23 and R24 also has a higher voltage level accordingly. Therefore, since all the output reference voltages have an increased voltage level, the voltage difference between the two output reference voltages (eg, Vrp[m] and Vrn[m]) will remain stable and the comparator can operate normally.

[0017] Figure 2 FIG. 2 shows a detailed schematic circuit diagram of a reference voltage buffer 100 according to an embodiment of the present invention. Figure 2As shown, the load 130 is implemented by a PMOS MP1 having a gate, a source and a drain, wherein the source is coupled to a resistor R1N, and the drain and the gate are coupled to a ground voltage. The load 140 is implemented by a PMOS MP2 having a gate, a source and a drain, wherein the source is coupled to a resistor R2N, and the drain and the gate are coupled to a ground voltage. The reference voltage generator 110 includes a bandgap reference circuit 210, an operational amplifier 220, transistors MP0, MP3 and MP4, and resistors R1, R2 and R3. The operational amplifier 220 has a positive input terminal, a negative input terminal and an output terminal, wherein the negative input terminal receives a bandgap reference voltage Vbg generated by the bandgap reference circuit 210, the positive input terminal is coupled to a node between the transistor MP3 and the resistor R1, and the output terminal is configured to output a control signal Vc' to the transistors MP3 and MP4. The transistor MP3 is implemented by using a PMOS having a drain, a source and a gate, wherein the source is coupled to the power supply voltage VDD, the drain is coupled to the resistor R1, and the gate receives the control signal Vc' generated by the operational amplifier 220. The transistor MP4 is implemented by using a PMOS having a drain, a source and a gate, wherein the source is coupled to the power supply voltage VDD, the drain is coupled to the resistor R2, and the gate receives the control signal Vc' generated by the operational amplifier 220. The transistor MP0 is implemented by using a PMOS having a drain, a source and a gate, wherein the source is coupled to the resistor R3, and the drain and the gate are connected to the ground voltage. In addition, the node between the resistors R2 and R3 is used to generate a reference voltage Vref to the operational amplifier 120.

[0018] In other embodiments, the transistors MP3 and MP4 may be implemented by NMOS, and / or another resistor may be inserted between the transistor MP3 and the resistor R1.

[0019] exist Figure 2 In the illustrated embodiment, since the load 130 and the transistor MP0 have the same characteristics (for example, both are implemented by PMOS), the voltage change at the source of the transistor MP1 is very similar to the voltage change at the source of the transistor MP0 in response to temperature changes, that is, the voltage change at the source of the transistor MP1 is very similar to the voltage change of the reference voltage Vref. Therefore, the voltage difference between the two output reference voltages (for example, Vrp[m-2] and Vrn[m-2]) will remain stable.

[0020] In addition, in order to improve the noise tolerance, preferably, the output reference voltage has a large full scale, that is, the difference between the highest output reference voltage Vrp[m] and the lowest output reference voltage Vrn[m] should be designed to be as large as possible. In this embodiment, in order to reduce the voltage of the output reference voltage Vrn[m], the load 130 / 140 is implemented by a PMOS MP1 / MP2 with an open-loop design. By using the open-loop design of the load 130 / 140, that is, not setting an operational amplifier to receive the voltage at the source to control the gate, when the PMOS MP1 / MP2 operates in the saturation region, its source can have a lower voltage level.

[0021] Figure 3 FIG. 3 is a schematic diagram showing a quantizer 300 according to an embodiment of the present invention. Figure 3 As shown, the quantizer 300 includes a plurality of comparators (e.g., 310, 320, and 330), a plurality of capacitors (e.g., C1 to C6), and a plurality of switches. In this embodiment, the switches of the quantizer 300 are controlled by control signals and Control, comparator 310 is configured to receive input signals Vin and Vip, common mode signal Vcm and two output reference voltages Vrp[m] and Vrn[m] via capacitors C1 and C2 and multiple switches, and generate a digital output bit Dout[n]. Comparator 320 is configured to receive input signals Vin and Vip, common mode signal Vcm and two output reference voltages Vrp[m-1] and Vrn[m-1] via capacitors C3 and C4 and multiple switches, and generate a digital output bit Dout[n-1]..., and comparator 330 is configured to receive input signals Vin and Vip, common mode signal Vcm and two output reference voltages Vrn[m] and Vrp[m] via capacitors C5 and C6 and multiple switches, and generate a digital output bit Dout[1], where m can be, for example, n / 2. When the switch is turned on and comparator 310 / 320 / 330 starts to use the output reference voltage, the output reference voltage may drop suddenly. By using Figure 1 or Figure 2 In the illustrated embodiment with a faster settling time design, the output reference voltage can return to the original voltage level immediately, and the quantizer 300 can always work well.

[0022] Please note that the quantizer 300 is only used for illustration purposes, and the internal circuit of the quantizer 300 may have a different design as long as each comparator in the quantizer 300 uses two output reference voltages. In addition, because the present invention focuses on the reference voltage buffer 100 providing the output reference voltage, further description of the quantizer 300 is omitted here.

[0023] Briefly summarized, in the reference voltage buffer of the present invention, the reference voltage buffer uses an active load to reduce the stabilization time, the load and the reference voltage generator of the reference voltage buffer are designed to have the same characteristics in response to temperature changes to overcome the PVT problem, and the load of the reference voltage buffer uses an open-loop design to make the output reference voltage have a larger full scale. Therefore, the reference voltage buffer can provide a suitable output reference voltage for subsequent circuits with a faster stabilization time.

[0024] Those skilled in the art will readily recognize that various modifications and variations can be made to the apparatus and method while maintaining the teachings of the present invention. Therefore, the above disclosure should be interpreted as being limited only by the appended claims.

Claims

1. A reference voltage buffer, comprising: a reference voltage generator configured to generate a reference voltage; A first operational amplifier configured to receive the reference voltage and a feedback signal to generate a control signal; a first transistor configured to be controlled by the control signal; a first set of resistors coupled to the first transistor, wherein the feedback signal is derived from an internal node of the first set of resistors; a first load coupled to the first set of resistors; a second transistor configured to be controlled by the control signal; a second set of resistors coupled to the second transistor, wherein the second set of resistors is configured to generate a plurality of output reference voltages; as well as a second load coupled to the second set of resistors, wherein the reference voltage generator, the first load and the second load have the same characteristics in response to temperature changes; Wherein, the first load includes a first P-type metal oxide semiconductor (PMOS), and the second load includes a second PMOS; or The first load includes a first N-type metal oxide semiconductor (NMOS), and the second load includes a second NMOS.

2. The reference voltage buffer according to claim 1, characterized in that: The first load and the second load both include active devices.

3. The reference voltage buffer according to claim 1, wherein: The first load is a load inversely proportional to absolute temperature, the second load is a load inversely proportional to absolute temperature, and the reference voltage generator is a reference voltage generator inversely proportional to absolute temperature.

4. The reference voltage buffer according to claim 1, wherein: When the first load includes a first PMOS and the second load includes the second PMOS, a source of the first PMOS is coupled to the first group of resistors, and a drain and a gate of the first PMOS are coupled to a ground voltage; A source of the second PMOS is coupled to the second group of resistors, and a drain and a gate of the second PMOS are coupled to a ground voltage.

5. The reference voltage buffer according to claim 1, wherein: The reference voltage generator comprises: a bandgap reference generator configured to generate a bandgap reference voltage; A second operational amplifier is configured to receive the bandgap reference voltage and another feedback signal to generate another control signal; a third transistor configured to be controlled by the another control signal; a first resistor coupled to the first transistor, wherein the other feedback signal is from a node between the third transistor and the first resistor; a fourth transistor configured to be controlled by the another control signal; a second resistor coupled to the fourth transistor; a third resistor coupled to the second resistor; and a third load coupled to the third resistor; The first load, the second load and the third load have the same characteristics in response to temperature changes.

6. The reference voltage buffer according to claim 5, characterized in that: The first load, the second load, and the third load are all loads inversely proportional to absolute temperature.

7. The reference voltage buffer according to claim 6, wherein: The third load includes a third PMOS, or the third load includes a third NMOS.

8. The reference voltage buffer according to claim 7, characterized in that: When the first load includes a first PMOS, the second load includes the second PMOS, and the third load includes the third PMOS, the source of the first PMOS is coupled to the first group of resistors, and the drain and gate of the first PMOS are coupled to a ground voltage; the source of the second PMOS is coupled to the second group of resistors, and the drain and gate of the second PMOS are coupled to a ground voltage; A source of the third PMOS is coupled to the third resistor, and a drain and a gate of the third PMOS are coupled to a ground voltage.

9. A reference voltage buffer, comprising: a reference voltage generator configured to generate a reference voltage; a first operational amplifier, configured to receive the reference voltage and a feedback signal to generate a control signal; a first transistor configured to be controlled by the control signal; a first set of resistors coupled to the first transistor, wherein the feedback signal is generated by an internal node of the first set of resistors; a first load coupled to the first set of resistors; a second transistor configured to be controlled by the control signal; a second set of resistors coupled to the second transistor, wherein the second set of resistors is configured to generate a plurality of output reference voltages; as well as a second load coupled to the second set of resistors, Wherein, the first load and the second load both include active devices; Wherein, the first load includes a first P-type metal oxide semiconductor (PMOS), and the second load includes a second PMOS; or The first load includes a first N-type metal oxide semiconductor (NMOS), and the second load includes a second NMOS.

10. The reference voltage buffer according to claim 9, wherein: When the first load includes a first PMOS and the second load includes the second PMOS, a source of the first PMOS is coupled to the first group of resistors, and a drain and a gate of the first PMOS are coupled to a ground voltage; A source of the second PMOS is coupled to the second group of resistors, and a drain and a gate of the second PMOS are coupled to a ground voltage.

11. The reference voltage buffer according to claim 10, characterized in that: The reference voltage generator comprises: a bandgap reference generator configured to generate a bandgap reference voltage; A second operational amplifier is configured to receive the bandgap reference voltage and another feedback signal to generate another control signal; a third transistor configured to be controlled by the another control signal; a first resistor coupled to the first transistor, wherein the other feedback signal is from a node between the third transistor and the first resistor; a fourth transistor configured to be controlled by the another control signal; a second resistor coupled to the fourth transistor; a third resistor coupled to the second resistor; and a third load coupled to the third resistor; The first load, the second load and the third load all include active devices.

12. The reference voltage buffer according to claim 11, characterized in that: The third load includes a third PMOS, or the third load includes a third NMOS.

13. The reference voltage buffer according to claim 12, characterized in that: When the first load includes the first PMOS, the second load includes the second PMOS, and the third load includes the third PMOS, the source of the first PMOS is coupled to the first group of resistors, and the drain and gate of the first PMOS are coupled to a ground voltage; the source of the second PMOS is coupled to the second group of resistors, and the drain and gate of the second PMOS are coupled to a ground voltage; A source of the third PMOS is coupled to the third resistor, and a drain and a gate of the third PMOS are coupled to a ground voltage.

Images