Circuit for digital signal encryption and decryption

Abstract

A circuit for digital signal encryption and decryption, which relates to information electronics technology. It mainly provides a digital circuit to realize synchronous and delay-free encryption / decryption of continuous data streams. In the present invention, "encrypted data" and "time code" are used as "public keys", and the "public keys" and "private keys" are transformed into continuous data code streams through a digital circuit to form a "variable key". The transformation process is realized through means such as a "code bit mutual control circuit" and a "multi-cycle shift circuit". Finally, through the "exclusive OR" with the "variable key", the continuous data stream signal is encrypted / decrypted. The present invention combines the randomness and infinity of the "public key", the secrecy of the "private key", and the non-repeatability of the "time code", so that the "variable key" can be infinite, random, secret, and non-repeating. The technology of the present invention can be widely applied to the encryption in various data storage or transmission processes.

Description

Technical Field

[0001] The present invention relates to a digital signal encryption technology, in particular to a data encryption and decryption circuit composed of a hardware circuit, belonging to the field of information electronics technology. Background Art

[0002] The current era is the era of the information society. The pillar of the information society is information security; the cornerstone of information security is encryption technology.

[0003] With the emergence and development of computer technology, encryption technology has also evolved from classical encryption technology to modern encryption technology. The encryption methods used by people include symmetric encryption and asymmetric encryption. Symmetric encryption technology has also developed from DES (Data Encryption Standard) to AES (Advanced Encryption Standard).

[0004] Although various countries have developed their own unique encryption technologies for reasons such as security, their fundamental principles are similar. Their encryption and decryption transformations are based on the complexity of algorithms to ensure the security of encryption technology.

[0005] Obviously, based on the complexity of algorithms, their encryption and decryption transformations must be implemented through software. When the software runs, it necessarily involves resource overhead and time overhead. The higher the security level, the greater the overhead. In order to keep up with the data stream during encryption, high-speed computing means are required.

[0006] With the development of society, there is an increasing need for information that needs to be encrypted and protected, especially audio and video information with extremely large amounts of data. There is an urgent need for a more efficient and secure encryption technology. Summary of the Invention

[0007] In order to overcome the problem of the operation speed of encryption technology, the present invention provides a new data encryption technology that can achieve real-time synchronous encryption and decryption of data streams through a hardware circuit without relying on program operations.

[0008] To achieve the above object, the technical solution adopted by the present invention to solve this problem is:

[0009] Store the key through a storage circuit, use the "recycled" encrypted data as a random code, and perform a mixed transformation through time sequence information data to generate a random, unpredictable, and non-repeating "variable key" (code stream) to encrypt or decrypt the data synchronously.

[0010] That is to say, the technology of the present invention uses the encrypted data (which has been used previously) as the "plain key", and transforms the "plain key", "secret key" and "time code" into a continuous or cyclic data code stream through a digital circuit, transforms these serial data code streams into parallel data code bits, and then performs "code bit mutual control" on these parallel data code bits to generate a streaming "variable key". Finally, through the "exclusive OR" of the "variable key", the continuous data stream signal is encrypted / decrypted.

[0011] The working principle of the encryption and decryption of digital signals is as follows:

[0012] 1. During encryption, the "exclusive OR circuit" has

[0013] 2. During decryption, the "exclusive OR circuit" has

[0014] Among them, A is the data code stream to be encrypted, B is the code stream of the "variable key" generated inside the circuit, and C is the information data code stream after encryption.

[0015] Since the "variable key" (i.e., the intermediate process B) generated by the encrypting party and the encrypting party is exactly the same and completely unknown to the outside world, encryption and decryption are feasible and secure.

[0016] The specific method is as follows:

[0017] Both the encryption circuit and the decryption circuit have a "digital encryption / decryption transformation circuit" (1) and a "secret key storage circuit" (2).

[0018] The "digital encryption / decryption transformation circuit" (1) has a "plain key transformation circuit" (12), a "secret key transformation circuit" (13), a "hybrid transformation circuit" (15) and a "final transformation circuit" (29).

[0019] The "plain key transformation circuit" (12) is for the transformation of the "plain key", and the "secret key transformation circuit" (13) is for the transformation of the "secret key".

[0020] The so-called "secret key" is a group of exactly the same digital codes that are held in advance and jointly by the encrypting party and the decrypting party, not publicly disclosed, and are stored in the "secret key storage circuit" (2) respectively.

[0021] The so-called "plain key" is a data string or data code stream that is generated in real time by one party, sent to the other party, and used jointly by both parties and publicly disclosed.

[0022] The outputs of the "plain key transformation circuit" (12) and the "key transformation circuit" (13) are both sent to the "hybrid transformation circuit" (15). The output of the "hybrid transformation circuit" (15) finally selects one of the data signals for output to form the "variant key", which is sent to the "last-stage transformation circuit" (29).

[0023] Among them, the "plain key transformation circuit" (12) and the "key transformation circuit" (13) are composed of shift register circuits.

[0024] The "hybrid transformation circuit" (15) is composed of logic gate circuits, combinational logic circuits and sequential logic circuits and has multiple inputs.

[0025] The logic gate circuits include "AND", "OR", "NOT" gate circuits; the combinational logic circuits include encoders, decoders, data distributors, data selectors, numerical comparators, adders, exclusive-OR circuits, etc.; the sequential logic circuits include flip-flops, counters, digital registers, shift registers, etc.

[0026] The so-called transformation in these "transformation circuits" means that the circuits have changes in the input and output data values and the number of input and output ports. For these transformations, the change relationships between their inputs and outputs are not restricted and can be irregular. However, the only and necessary requirement is that such transformations are exactly the same in the paired encryption circuit and decryption circuit. Under the input of the same data, their output changes are also the same. For example, the "key transformation circuits" in the encryption circuit and the decryption circuit are exactly the same, and the "plain transformation circuits" in the encryption circuit and the decryption circuit are exactly the same, and so on. However, the "key transformation circuit" and the "plain transformation circuit" are different.

[0027] In other words, the composition of such circuits is exactly the same in the paired encryption circuit and decryption circuit.

[0028] This combinational circuit composed of logic gate circuits, combinational logic circuits and sequential logic circuits and having multiple inputs has multiple or single outputs. A part of the multiple inputs can be artificially regarded as input data lines, and the other part as control lines. That is to say, a part of the input of this circuit is equivalent to a "control code", and the other part is equivalent to a "controlled code". Therefore, it can be called a "code position mutual control transformation circuit", abbreviated as "code control transformation circuit" (16). This circuit makes the input signals interact and control each other through the combinational logic circuit and the sequential logic circuit, that is, forms a "code control transformation". The input-output relationship of the "code control transformation circuit" (16) is determined by the control code of the control line.

[0029] Digital circuits include: basic logic gate circuits, combinational logic circuits, sequential logic circuits.

[0030] Generally, a combinational logic circuit has several input variables I0, I1, I2, …, I n-1 ; and several output variables Y0, Y1, Y2, …, Y m-1 . Each output function is a function of all or some of the input variables: Y(t n ) = F[I(t n )], that is

[0031] Y0 = F0(I0, I1, I2, …, I n-1 )

[0032] Y1 = F1(I0, I1, I2, …, I n-1 )

[0033] Y2 = F2(I0, I1, I2, …, I n-1 )

[0034] …

[0035] Y m-1 = F m-1 (I0, I1, I2, …, I n-1 )

[0036] The schematic block diagram of the combinational logic circuit is shown in Figure 10 .

[0037] The “code control transformation circuit” (16) is similar to the above-mentioned multi-input and multi-output, and is an extended combinational circuit, but various circuits including sequential logic circuits can be included inside.

[0038] The “code control transformation circuit” (16) is a combinational circuit with multi-terminal input and multi-terminal output (or single-terminal output), and has one or more of basic logic gate circuits, combinational logic circuits, and sequential logic circuits inside.

[0039] The “code control transformation circuit” (16) is connected in series, parallel, or in a mixed connection by these circuits (this method of mutual connection has no restrictions and no rules, as long as the circuits of the encryption party and the decryption party are the same).

[0040] One part of the input terminal is used as the input data terminal, and the other part is used as the control terminal. That is to say, one part of the input of this circuit is used as the “control code”, and the other part is used as the “controlled code”.

[0041] The input-output relationship is determined by the control code (data change) of the control terminal, that is, the so-called “code control transformation circuit” is formed.

[0042] Essentially, the control terminal and the signal input terminal of the input line in the circuit are both input terminals, and they can be interchanged in terms of working principle.

[0043] Inside the "hybrid transformation circuit" (15), or composed of multiple "code-controlled transformation circuits", each "code-controlled transformation circuit" is arranged in parallel with each other, or connected in series, or cross-connected. (Similar to the series and parallel connection of resistors).

[0044] Form nesting, cascading, or feedback.

[0045] The so-called nesting means that the internal modules that make up the code-controlled transformation circuit also have code-controlled transformation circuits.

[0046] The so-called cascading means that after the output of the code-controlled transformation, the data is rearranged, or new data is inserted, and a new code-controlled transformation is performed.

[0047] The so-called feedback refers to the output data, which is fed back to the input end of this stage, or the previous stage or several previous stages through a latch circuit in the middle.

[0048] Such combinations and repeated combinations make the input-output relationship of the code-controlled transformation circuit more unpredictable to the outside world. And the corresponding encryption circuit and decryption circuit are exactly the same as each other, and the transformation results are also exactly the same.

[0049] The "public key transformation circuit" (12) and the "private key transformation circuit" (13) may also have a "code-controlled transformation circuit" (16).

[0050] The "final stage transformation circuit" (29) is composed of an "exclusive OR" circuit.

[0051] For the encryption circuit, the data information to be encrypted is "exclusive OR" with the "variable key" (generated by the "hybrid transformation circuit" (15)) in the "final stage transformation circuit" (29) to form encrypted data information.

[0052] For the decryption circuit, the encrypted data information is "exclusive OR" with the "variable key" (generated by the "hybrid transformation circuit" (15)) in the "final stage transformation circuit" (29) to form decrypted data information.

[0053] This "exclusive OR" is performed in the form of a data stream.

[0054] For the data to be encrypted or decrypted, the pulse frequency of its digital signal constitutes the reference frequency of the pulse clock, and the pulse reference frequency controls the synchronous change of the timing circuit.

[0055] For each timing circuit in the transformation circuit, the clock signal for pulse triggering is either the same frequency and synchronous with the reference signal.

[0056] For each timing circuit in the transformation circuit, the clock signal for pulse triggering is either the same frequency and synchronous with the reference signal, or frequency-divided.

[0057] Alternatively, the pulse clock frequencies of each sequential circuit are code-controlled. Through the combination of a selector and a frequency division circuit, the reference clock is "code-controlled" divided to form pulse clock signals of different frequencies. Each sequential circuit has its own different control, resulting in different variations, but the reference frequency must be an integer multiple of the division.

[0058] This "determining the variation by the value of the code bit" is called "code bit control", abbreviated as "code control", the same below.

[0059] The digital signal encryption and decryption circuit may also have a "data format recognition and separation circuit" (3) and a "data format reconstruction circuit" (4). After the digital signal to be encrypted / decrypted is input through the circuit port (of the "digital signal encryption and decryption circuit"), it first passes through the "data format recognition and separation circuit" (3) to separate the non-format signal, and then is input to the "digital encryption and decryption transformation circuit" (1) for corresponding encryption or decryption transformation. The transformed signal is input to the "data format reconstruction circuit" (4), and the "data format reconstruction circuit" (4) combines the transformed signal with the format signal to reconstruct the format signal and outputs it from the circuit output port (of the "digital signal encryption and decryption circuit").

[0060] Because, general digital signals all have a common dedicated format for identification by relevant digital devices. For example, videos, audios, pictures, etc. all have their own unique formats. If these format data directly participate in the transformation, the devices (especially network devices) will not be able to recognize these formats. Therefore, separation is required, and after encryption / decryption, reconstruction is carried out.

[0061] The so-called "data format recognition and separation circuit" (3) refers to a comparison circuit that compares whether the data format is the same as the format pre-recorded and stored. Once they are the same, separation is performed.

[0062] The so-called "data format reconstruction circuit" (4) refers to the corresponding one that restores the corresponding data format after encryption is completed.

[0063] The digital signal encryption and decryption circuit may also have an "A / D conversion circuit" and a "D / A conversion circuit". In the encryption circuit, there is an "A / D conversion circuit" before the "digital encryption and decryption transformation circuit" (1). In the decryption circuit, there is a "D / A conversion circuit" after the "digital encryption and decryption transformation circuit" (1).

[0064] In this way, the encryption circuit can directly access analog signals and directly perform data encryption after analog-to-digital conversion; the decryption circuit directly performs digital-to-analog conversion after decrypting the received encrypted signal to restore the analog signal. Such a circuit enables the two communication parties to directly perform encrypted video or intercom.

[0065] For the above object, the technical method adopted by the present invention may also be as follows:

[0066] The "code control transformation circuit" (16) has a "multi-cycle shift circuit" (17), or is called a "group of cycle shift circuits".

[0067] The said "multi-cycle shift circuit" (17) is composed of more than one cycle shift register circuit. Each cycle shift circuit is arranged in parallel with each other (to form more input bits and output bits), or is connected in series or in a mixed connection. (Similar to the series and mixed connection of resistors).

[0068] For each cycle shift register circuit, its serial input end and output end are connected to each other, so that the data of the register circuit circulates and shifts according to the clock beat of the data stream (for encrypting or decrypting the data signal), and after shifting, it is output from the parallel data end.

[0069] For each cycle shift register circuit, its shift direction may be the same or different, (for example, either all shift to the left or to the right, or some shift to the left and some shift to the right).

[0070] For each cycle shift register circuit, its moving direction may be fixed or determined by "code bit control", (for example, some are fixed to shift to the left and some are fixed to shift to the right, or the moving direction of each cycle shift register circuit is determined to shift to the left or to the right according to the value of the key, plain key or the mixed code bit. For example, when different potentials (different values of the code bit) are connected to the 9th and 10th pins S0 and S1 of the integrated shift register 74194, corresponding left shift or right shift can be formed). This kind of "change determined by the value of the code bit" is called "code bit control", abbreviated as "code control".

[0071] After the circuit starts or is reset, the data of the shift register circuit is input from the data end and output from the parallel data end each time, and then circulates and shifts according to the clock beat of the data stream (synchronized with the encryption and decryption data stream).

[0072] Before the encryption or decryption work (preparation and initialization after starting or resetting), each cycle shift register circuit may perform "pre-shifting". The so-called "pre-shifting" means performing cycle shifting for initialization, rather than performing cycle shifting according to the clock beat of the data stream (for encrypting or decrypting the data signal). It is the preparatory shift before the formal encryption or decryption work, a kind of preparation and initialization of the circuit, and is automatically performed after the circuit starts or is reset.

[0073] After waiting for the "pre-shifting" to be completed, then circulate and shift according to the clock beat of the data stream (synchronized with the encryption and decryption data stream). The purpose is to increase the complexity of the circuit change and improve the difficulty of breaking the encryption.

[0074] This "pre-shift", the displacement length of its movement, is either fixed or determined by code control. (For example, in each cyclic shift register circuit, some are fixed to shift 3 bits, some are fixed to shift 7 bits; or, it is determined by the control code. If the control code is 4, it shifts 4 bits, if the control code is 6, it shifts 6 bits, etc.)

[0075] This "pre-shift" is carried out during the encryption and decryption process. Due to the individual shifts of multiple cyclic shift register circuits, errors may occur. If one circuit has a deviation, all subsequent ones will be incorrect. The intermediate process is resynchronized through plaintext correction to ensure that subsequent data transformations are no longer incorrect.

[0076] The bit lengths of each cyclic shift register circuit are either equal to each other or not equal to each other.

[0077] The unequal bit lengths are either non-multiple relationships with each other.

[0078] (This "unequal" relationship, for example, some bit lengths are 7 bits, some are 9 bits, some are 10 bits, and so on. By analogy, the lengths are 7, 9, 10, 11, 13, 17, 19, 23, 31,... respectively, or they are distributed according to prime numbers, such as 2, 3, 5, 7, 9, 11, 13, 17, 19, 23, 31,...)

[0079] If the key and the plain key have a total of 18 bytes, 18 * 8 = 144 bit. Taking 140 bits of them, after pre-stage transformation processing, they are respectively sent to 9 (unequal-length) cyclic shift register circuits, making their bit lengths 7, 9, 10, 11, 13, 17, 19, 23, 31 respectively. (The total bit length = 7 + 9 + 10 + 11 + 13 + 17 + 19 + 23 + 31 = 140 bit).

[0080] Then, the combined number of their respective cycles = 7 * 9 * 10 * 11 * 13 * 17 * 19 * 23 * 31 = 20747636910, with more than 20 billion combinations. (Similar to the traditional chronology method, the ten Heavenly Stems such as Jia, Yi, Bing, Ding, etc. and the twelve Earthly Branches such as Zi, Yin, Mao, etc. form a cycle of sixty units for rotation.)

[0081] In other words, for each change in the key or the plain key, 2.59 billion non-repeating outputs can be continuously generated according to the clock beats. Through subsequent transformations, a "variable key" with a bit length of 2.59 billion bits can be generated.

[0082] If it is a multi-level nesting, there will be even more results.

[0083] In the "multi-cyclic shift circuit" (17) of the "code control transformation circuit" (16), either its input end or output end is nested with a "code control transformation circuit".

[0084] This kind of nesting is hierarchical nesting or layered nesting.

[0085] The so-called hierarchical nesting means that the "code control transformation circuit" (16) and the "multi-cycle shift circuit" (17) are alternately combined to form multi-level nesting.

[0086] The so-called layered nesting means that there are a "multi-cycle shift circuit" and a "code control transformation circuit" in the "code control transformation circuit" (16), and there are again a "multi-cycle shift circuit" and a "code control transformation circuit" in the embedded "code control transformation circuit", forming multi-level nesting.

[0087] For the above purposes, the technical method adopted by the present invention can also be as follows:

[0088] The shift register circuit in the "key transformation circuit" (13) enables the key to be input from a serial or parallel port after the circuit starts or is reset, and is fixedly output from the parallel port and sent to the next-level circuit.

[0089] Or, after the circuit starts or is reset, the key is input from a serial or parallel port. After the parallel port output is completed, according to the reference frequency (synchronized with the clock beat of the encryption / decryption data stream), cyclic shift is performed, and after the shift, it is output from the parallel data terminal and sent to the next-level circuit.

[0090] Or, after the circuit starts or is reset, the key is input from a serial or parallel port. After the parallel port output is completed, it is sent to the "multi-cycle shift circuit", and then according to the reference frequency (synchronized with the clock beat of the encryption / decryption data stream), cyclic shift is performed respectively, and after the shift, it is output from the parallel data terminal and sent to the next-level circuit.

[0091] In other words, after the "key transformation circuit" (13) reads the "key" data from the "key storage circuit", it either transforms into fixed static data or performs cyclic shift to form a cyclic code stream and sends it to the next-level circuit.

[0092] For the above purposes, the technical method adopted by the present invention can also be as follows:

[0093] The shift register circuit in the "public key transformation circuit" (12) enables the public key to be input from a serial or parallel port after the circuit starts or is reset, and is fixedly output from the parallel port and sent to the next-level circuit.

[0094] Or, after the circuit starts or is reset, the public key is input from a serial or parallel port. After the parallel port output is completed, according to the reference frequency (synchronized with the clock beat of the encryption / decryption data stream), cyclic shift is performed, and after the shift, it is output from the parallel data terminal and sent to the next-level circuit.

[0095] Alternatively, after the circuit is started or reset, the public key is input from the serial or parallel port, and after the parallel port output is completed, it is sent to the "multi-cyclic shift circuit", and then according to the reference frequency (synchronized with the clock beat of the encryption and decryption data stream), each is cyclically shifted, and after the shift, it is output from the parallel data end and sent to the next level circuit.

[0096] The clear key signal in the "clear key conversion circuit" (12) is either input once or continuously.

[0097] The "one-time" means that after a public key of a specific length is input once, the public key is no longer added in the subsequent encryption and decryption process, but the previously input public key is transformed with the secret key to generate a constantly changing "variable key".

[0098] The term "continuous" means that during the encryption and decryption process, the public key is continuously added and changes synchronously with the encrypted and decrypted data stream.

[0099] This continuously added data stream may be a time code, an "old" encrypted signal, or an "old" "variable key", or a mixture of these (added data stream, "old" encrypted signal, variable key, etc.) signals.

[0100] The "time code" mentioned above refers to the signal digital information converted from time date or time sequence, which is a numerical code generated by the change of time or data segment sequence or data code flow. The "time code" is generated independently by both parties, or generated by the other party and sent to the other party for joint use by both parties.

[0101] The "old" encryption code refers to the encrypted digital information, which is the "old" encrypted data from the past.

[0102] The "old" variable key is the "old key in the past".

[0103] "Old" encryption code and "old" variable key are to "recycle" old encrypted data and old variable keys and reuse them. In other words, the encrypted data (or "variable key") of the previous segment is used as the "plain key" of this segment, and the encrypted data (or "variable key") of this segment is used as the "plain key" of the next segment. In this way, no additional resources are needed to transmit signals.

[0104] When the public key signal is continuously input, the "digital encryption and decryption conversion circuit" (1) may also have a "boot code generation circuit" (21), and the "boot code generation circuit" (21) generates "boot code" data and sends it to the "public key conversion circuit" (12).

[0105] The "boot code" is used as a guiding "public key" in the initial stage of the encryption circuit operation.

[0106] "Pilot code" is the necessary guiding "plain key" at the initial stage of the operation of the encryption circuit when there is no "old" signal available from the encrypted data feedback circuit (22) or the "variant key data feedback circuit" (24).

[0107] The "pilot code" can be either a fixed value, a random value, or a data value of time, traffic, or sequence information.

[0108] The "pilot code" can be obtained directly from the "time code" of the "key transformation circuit" (13) by both the encrypting party and the decrypting party respectively, or it can be generated by one of the encrypting party and the decrypting party and sent to the other party. Generally, it is generated by the encrypting party and sent to the encrypting party together with the encrypted data.

[0109] The digital code of the "pilot" code can be indicative information or a random code without meaning.

[0110] Generally, pilot code = timing code + identification code + redundancy.

[0111] Introducing the timing code and the identification code can prevent the same encrypted text from having the same encryption result. Additionally, rotating the key transformation can also prevent this.

[0112] For the above purposes, the technical method adopted by the present invention can also be as follows:

[0113] The encryption circuit and the decryption circuit internally have a "digital code encryption and decryption transformation circuit" (1) and a "key storage circuit" (2). The "digital code encryption and decryption transformation circuit" (1) has a "plain key transformation circuit" (12), a "key transformation circuit" (13), a "hybrid transformation circuit" (15), and a "final transformation circuit" (29), and also has a "code control transformation circuit" (16) and a "multi-cycle shift circuit" (17).

[0114] These overall circuits or partial circuits in the above (the "digital code encryption and decryption transformation circuit" (1) and the "key storage circuit" (2)) are either implemented by a programmable logic chip PLD or by a computer, which includes a general-purpose computer, a single-chip microcomputer, and a data processor (DSP).

[0115] Because the development of digital circuits has evolved step by step from gate circuits, to combinational gate circuits, to sequential circuits, to register circuits, and then to computers. Therefore, the functions of various gate circuits, combinational gate circuits, sequential circuits, and register circuits can all be implemented by a computer. After software compilation and running on hardware, it is essentially the operation of gate circuits and sequential circuits.

[0116] The encryption circuit, decryption circuit, and internal component circuits provided by the present invention are all combinations of gate circuits and sequential circuits, so they can be easily implemented by software programs.

[0117] In other words, various transformation circuits and signal transformation processes can be implemented by software programs according to the circuit block diagrams and run on a general-purpose computer.

[0118] For example, a single-chip microcomputer can implement the encryption circuit and decryption circuit as a whole, or can separately implement the "code control transformation circuit" (16) and "multi-cycle shift circuit" (17), that is, the single-chip microcomputer can replace the local "code control transformation circuit" (16) and "multi-cycle shift circuit" (17).

[0119] In short, encryption and decryption can be implemented through software.

[0120] For the above purposes, the technical methods adopted by the present invention can also be as follows:

[0121] The "plain key transformation circuit" (12), "key transformation circuit" (13), "mixed code transformation circuit" (15), "final stage transformation circuit" (29) in the encryption and decryption circuits, and the "code control transformation circuit" (16), "multi-cycle shift circuit" (17), "XOR circuit" that make up these circuits (such as the "plain key transformation circuit" (12), "key transformation circuit" (13), "mixed code transformation circuit" (15), "final stage transformation circuit" (29), etc.) are implemented by integrated circuits.

[0122] The "key transformation circuit" (13), "plain key transformation circuit" (12), and "time code transformation circuit" (11) in the encryption and decryption circuits are composed of "shift registers", "counters" circuits or corresponding integrated circuits.

[0123] The above-mentioned various transformation circuits are either formed by parallel connection, series connection, or mixed connection of multiple "shift registers", "counters", and "gate circuits" integrated circuits.

[0124] In other words, according to the circuit architecture provided by the technology of the present invention, we can purchase corresponding various integrated circuits on the market to form the encryption circuit and decryption circuit.

[0125] The above-mentioned various transformation circuits can be formed by parallel connection, series connection, or mixed connection of multiple "shift registers", "counters", "data selectors", "data distributors", and "gate circuits".

[0126] These transformation circuits (in the "key transformation circuit" (13), "public key transformation circuit" (12), and "time code transformation circuit" (11)) can be directly spliced by integrated circuits. For example, they can be spliced by integrated circuits such as 74HC164 (an 8-bit serial-in parallel-out shift register) and 74HC92 (a 12-frequency division counter), or by similar circuits.

[0127] The "code control transformation circuit" (16) is composed of a "data selector" circuit or a corresponding integrated circuit. For example, it can be spliced by circuits such as integrated 74LS151 (an 8-to-1 data selector) and 74HC150 (a 16-to-1 data selector), or by similar circuits.

[0128] The "multi-cycle shift circuit" (17) can be composed of the integrated shift register 74194 of general integrated circuits. For example, the serial inputs and outputs of multiple 74194s are connected end to end, and one output port in the parallel port of the last 74194 is connected to the serial input port of the first 74194 to form a cyclic shift register of any bit length (if 4 74194s can form a cyclic shift register of 9 - 12 bits); multiple groups of cyclic shift registers with different bit lengths can form the "multi-cycle shift circuit" (17).

[0129] In the "data format recognition and separation circuit" (3) in the encryption and decryption circuit, its data recognition is realized by a "numerical comparator" circuit, such as the integrated circuit 74LS85 (numerical comparator).

[0130] In short, the encryption and decryption circuit can be built with common integrated circuits or discrete components.

[0131] For the above purposes, the technical method adopted by the present invention can also be as follows:

[0132] The encryption and decryption circuit has a dip switch or a keyboard.

[0133] The "dip switch" is either the key in the "key storage circuit" (2) or a part of the key. There will be other storage methods or storage circuits for the key.

[0134] The "dip switch" is either the control code in the "code control transformation circuit" (16).

[0135] The "dip switch" is either the connection switch inside the transformation circuit or between circuits.

[0136] In other words, through the dip switch, the key data, the control code, and the circuit connection method can be set manually.

[0137] Alternatively, through the keyboard, change the encryption key, change the control code, or control and change the circuit connection method (i.e., change the transformation method).

[0138] In an actual encryption and decryption device, beneficial effects can be achieved through manual dialing or keyboard control: 1. In case of concern or leakage of the encryption key, the user can temporarily supplement and change the transformation method. 2. If the device is stolen by others, it can protect the encryption and decryption from being used normally. 3. When encryption and decryption are used collectively by a group with multiple members, the members can temporarily change the encryption method and encrypt independently.

[0139] For the above purposes, the technical method adopted by the present invention can also be as follows:

[0140] In the encryption and decryption circuit, the "digital encryption and decryption transformation circuit" (1) and the "encryption key storage circuit" (2) directly form independent circuits. That is, there are no other auxiliary circuits such as "A / D, D / A conversion" and "data format identification, separation, and reconstruction" in the circuit, and only the core transformation system is available.

[0141] The "digital encryption and decryption transformation circuit" (1) and the "encryption key storage circuit" (2) are combined in other circuits and become part of other circuits.

[0142] The "digital encryption and decryption transformation circuit" (1) and the "encryption key storage circuit" (2) directly form an integrated circuit (chip), or are combined in other integrated circuits and become part of the integrated circuit (chip).

[0143] The "encryption key storage circuit" (2) is either directly fixed in the encryption / decryption chip, or there are multiple encryption keys that can be selected in the chip circuit. Two or more encryption / decryption chips are paired for use. They can be used and discarded immediately.

[0144] Such a digital signal encryption and decryption circuit is either embedded in the data storage circuit, or embedded in the signal path of the electronic device, or embedded in the circuits of Internet of Things (IoT) terminals or node devices. For example, directly at the interface of the memory (hard disk) circuit of a computer, in front of the transmitting and receiving ends of a remote control device.

[0145] For the above purposes, the technical method adopted by the present invention can also be as follows:

[0146] The "digital encryption and decryption transformation circuit" (1) has one or more of the transformation circuits including the "encryption key transformation circuit" (13), the "public key transformation circuit" (12), the "time code transformation circuit" (11), and the "hybrid transformation circuit" (15).

[0147] In other words, parts of the "key transformation circuit" (13), "public key transformation circuit" (12), "time code transformation circuit" (11), and "hybrid transformation circuit" (15) are default. The key, public key, and time code can be mixed and do not necessarily all have independent transformation circuits.

[0148] Moreover, among the three data of key, public key, and time code, one of them can be default, leaving only two, constituting a simplified encryption and decryption circuit.

[0149] The "digital encryption and decryption transformation circuit" (1) has a "circuit for returning encrypted data" (22) and a "circuit for returning key-varied data" (24), or has one of these two circuits.

[0150] In other words, one of the "circuit for returning encrypted data" (22) and the "circuit for returning key-varied data" (24) is default, especially there is no circuit for returning key-varied data.

[0151] Alternatively, the public key directly serves as the control code of the "code control transformation circuit" (16), and the key directly serves as the controlled code of the "code control transformation circuit" (16). (Or vice versa, the control code and the controlled code are only relative, and they are both inputs of the code control transformation circuit without substantial difference), constituting the encryption and decryption circuit of the minimum system.

[0152] For the above purposes, the technical method adopted by the present invention can also be as follows:

[0153] The input ends of the "digital encryption and decryption transformation circuit" (1) and the "key storage circuit" (2) each have independent external connection lines.

[0154] The output end of the "digital encryption and decryption transformation circuit" (1) has an independent external connection line, while the output of the "key storage circuit (2)" is directly sent to the "digital encryption and decryption transformation circuit" (1).

[0155] The "digital encryption and decryption transformation circuit" (1) and the "key storage circuit" (2) are fixedly connected or connected by plugging and unplugging.

[0156] For the chip composed of the "digital encryption and decryption transformation circuit" (1) and the "key storage circuit" (2), the interface between the key storage and the encryption circuit is separated, and the chips of the key storage and the encryption circuit are separated and can be plugged and unplugged.

[0157] The separation of the input ends of the "digital encryption and decryption transformation circuit" (1) and the "key storage circuit (2)" makes it impossible for the two to be simultaneously connected to the same peripheral circuit, which can ensure that the key data is not stolen. For security, in the actual circuit, the input end can be made to only be unidirectionally input (written) and cannot be reversely output (maliciously read).

[0158] The encryption and decryption circuit for digital signals is either integrated into the overall circuit, or an independent board circuit, or an integrated circuit chip.

[0159] Advantages of the present invention:

[0160] Due to the present invention integrating the randomness and infinity of the "public key", the secrecy of the "secret key", and the non-repetitiveness of the "time code", the "variable key" and the encryption result can be infinite, random, secret, and non-repetitive.

[0161] Since the "public key" used in the encryption process is the encryption signal of the previous time period, this not only saves the resource overhead of transmitting the "public key", but also can prevent others from tampering. It is anti-tampering encryption and can achieve the credibility, confidentiality, reliability, and integrity of encryption.

[0162] Since the "secret key" participates in the transformation in the form of a code stream, theoretically, as long as the storage circuit permits, the "secret key" can be infinitely long. The longer the "secret key" length, the more difficult it is to break. And these transformations are directly implemented by digital circuits, so the encryption / decryption speed is not affected. This is impossible to achieve with existing encryption technologies.

[0163] Since the time value and sequence value in the "time code" are increasing and non-repetitive, the encryption results of the same text are different.

[0164] Since the generation of the "variable key" is realized through a pure hardware circuit, the process does not involve regular mathematical operations, but only a combination of various independent logic gate circuits. Under repeated transformations, it is impossible for the outside world to reverse the secret key from the encryption result.

[0165] Moreover, the more input bits participate in the "code control transformation circuit", the more difficult it is to break. Theoretically, it can be arbitrarily complex without affecting the transformation speed.

[0166] Since the entire transformation is realized by a hardware circuit, the encryption / decryption process is completely real-time, without any time delay, and changes immediately with transmission. Description of the Drawings

[0167] The present invention will be further described below in conjunction with the drawings and embodiments.

[0168] Figure 1 It is an overall block diagram and component appearance schematic diagram with data format processing of the "encryption and decryption circuit for digital signals".

[0169] Figure 2 It is an overall flow block diagram of the "encryption and decryption circuit for digital signals".

[0170] Figure 3 It is an overall flowchart with data format processing for the "Encryption and Decryption Circuit of Digital Signals".

[0171] Figure 4 It is a schematic diagram showing the changing trend of the data flow of the "Encryption and Decryption Circuit of Digital Signals".

[0172] Figure 5 It is a circuit block diagram of the "Code Control Transformation Circuit" in the encryption and decryption circuit.

[0173] Figure 6 It is an electrical principle schematic block diagram of a working process of the "Code Control Transformation Circuit" in the encryption and decryption circuit.

[0174] Figure 7 It is a schematic diagram of the "Code Control Transformation Circuit" in the encryption and decryption circuit having a "Multi-Cycle Shift Circuit".

[0175] Figure 8 It is an electrical principle schematic block diagram of a working process of the "Encryption and Decryption Circuit of Digital Signals".

[0176] Figure 9 It is a simplified electrical principle schematic diagram of another working process of the "Encryption and Decryption Circuit of Digital Signals".

[0177] Figure 10 It is a schematic block diagram of a combinational logic circuit, which is the "Combinational Logic Circuit Block Diagram" described above.

[0178] In the figure, 1. Digital Signal Encryption and Decryption Transformation Circuit, 2. Key Storage Circuit, 3. Data Format Identification and Separation Circuit, 4. Data Format Reconstruction Circuit, 5. Encryption / Decryption Device, 6. Memory, 11. Time Code Transformation Circuit, 12. Public Key Transformation Circuit, 13. Key Transformation Circuit, 14. Code Bit Allocation Circuit, 15. Hybrid Code Transformation Circuit, 16. Code Control Transformation Circuit, 17. Multi-Cycle Shift Circuit, 18. Date and Clock Circuit, 19. Counting Circuit, 20. Time Code Generation Circuit, 21. Pilot Code Generation Circuit, 22. Encrypted Data Return Circuit, 23. Code Stream Delay Circuit (Shift Circuit), 24. Variant Key Data Return Circuit, 29. Final Stage Transformation Circuit, 31. Encryption and Decryption Selection (Conversion) Circuit, 32. Pre-Shift Circuit, 33. Data Format Processing Circuit, 34. Data Format Code Storage Circuit, 35. Data Format Code Comparison Circuit, 36. Trigger Circuit, 37. Format Control Switch, 38. Synchronization Circuit. Specific Embodiments

[0179] In Figure 1In Figure (a), it is an overall block diagram with data format processing. The "digital encryption and decryption transformation circuit" (1) reads the key from the "key storage circuit" (2). The data to be encrypted (decrypted) is input from end B. After encryption (decryption) transformation, it becomes the encrypted (decrypted) data and is output from end C.

[0180] If it is data to be encrypted (decrypted) with a data format, it is input from end D, processed by the "data format recognition and separation circuit" (3), sent to the "digital encryption and decryption transformation circuit" (1), and after encryption (decryption), it is output from the "data format reconstruction circuit" (4).

[0181] In the figure, if the "data format recognition and separation circuit" (3) and the "data format reconstruction circuit" (4) are respectively changed to A / D and D / A circuits, then this circuit becomes an encryption and decryption processing circuit for analog signals (input from end D and output from end E).

[0182] Figure (b) is a schematic diagram of the appearance of the components of this circuit. The "key storage circuit" (2) is located in the "memory" (6), and the "digital encryption and decryption transformation circuit" (1) is located in the "encryptor / decryptor" (5). The "memory" (6) has an independent data input line A, and the "encryptor / decryptor" (5) has an input line B, an output line C, and (capable of processing data with a data format) an input line D and an output line E.

[0183] The "memory" (6) can be inserted and removed in the "encryptor / decoder" (5).

[0184] In Figure 2 In it, the "key transformation circuit" (13) in the "digital encryption and decryption transformation circuit" (1) reads the key from the "key storage circuit" (2). The output of the "key transformation circuit" (13) is sent to the "code bit allocation circuit" (14).

[0185] 1. When this "encryption and decryption circuit" is used as "encryption" therein, the input end of the "encrypted data feedback circuit" (22) is connected to end C to receive the encrypted data (generated by itself) output from end C.

[0186] 2. When this "encryption and decryption circuit" is used as "decryption" therein, the input end of the "encrypted data feedback circuit" (22) is connected to end B to receive the encrypted data (generated by the other party) input from end B.

[0187] The output of the "encrypted data feedback circuit" (22) is sent to the "code stream delay circuit" (23) for delay (for example, by shifting in a shift register) and synthesized into a "public key". Then it is sent to the "public key transformation circuit" (12).

[0188] The "clear key transformation circuit" (12) can also accept the "variant key" sent back by the "variant key data feedback circuit" (24).

[0189] The "clear key transformation circuit" (12) also accepts the output of the "pilot code generation circuit" (21). During the initial stage of encryption, the "pilot code" is used as the "clear key", and in subsequent stages, the delayed and feedback encrypted data is used as the "clear key".

[0190] The "pilot code generation circuit" (21) reads the time, flow, and sequence information of the "time code generation circuit" (20), or reads the stored "key", and transforms and generates the "pilot code".

[0191] 1. If it is a circuit for "encryption", the "pilot code generation circuit" (21) can generate a random code as the "pilot code". While inputting to the "clear key transformation circuit" (12), it also outputs from the C end and sends it to the "decryption party".

[0192] 2. If it is a circuit for "decryption", correspondingly, the "pilot code generation circuit" (21) inputs the data sent by the "decryption party" from the B end and separates the "pilot code" therein.

[0193] The "counting circuit" (19) calculates and statistics information such as the length and flow of the "digital code to be encrypted (decrypted)", and outputs the statistical data to the next stage.

[0194] The "time code generation circuit" (20) reads the data of the "counting circuit" (19) and the "date and clock circuit" (18), and sends it to the "time code transformation circuit" (11) for transformation.

[0195] The outputs of the "time code transformation circuit" (11), the "clear key transformation circuit" (12), and the "key transformation circuit" (13) are sent to the "code position allocation circuit" (14) together, and then through the "hybrid transformation circuit" (15). The "hybrid transformation circuit" (15) has a "code control transformation circuit" (16) and outputs to form the "variant key".

[0196] The data to be encrypted (decrypted) input from the B end is subjected to an "exclusive OR" operation with the "variant key" in the "final stage transformation circuit" (29) to generate the encrypted (decrypted) data and output it from the C end.

[0197] In Figure 3 In addition to being the same as the main circuit of Figure 2 it also has an "encryption / decryption selection (conversion) circuit" (31) and a "data format processing circuit" (33).

[0198] When the change-over switch of the "Encryption / Decryption Selection (Conversion) Circuit" (31) is connected to point a, the output data at the C terminal is sent back to the "Encrypted Data Return Circuit" (22) through the switch, and thus this circuit becomes the "Signal Encryption Circuit".

[0199] When the change-over switch of the "Encryption / Decryption Selection (Conversion) Circuit" (31) is connected to point b, the input data at the B terminal is sent back to the "Encrypted Data Return Circuit" (22) through the switch, and thus this circuit becomes the "Signal Decryption Circuit".

[0200] The "Data Format Code Storage Circuit" (34) in the "Data Format Processing Circuit" (33) stores general data format flag codes (such as general data formats like sound and video). When the data input at the B terminal passes through the "Data Format Code Comparison Circuit" (35), if it is consistent with the stored data format flag code, it will trigger and control the "Format Control Switch" (37) after a delay through the "Trigger Circuit" (36), causing the control switch to connect to point q (normally connected to point p), so that the signal at the output C terminal is switched to unencrypted format data and directly output.

[0201] In order to enable the "Data Format Code Comparison Circuit" (35) to have a comparison process, other parts of the circuit first undergo a delay process through the "Pre-shift Circuit" (32) so that the "Trigger Circuit" (36) can trigger correctly.

[0202] In Figure 4 is a schematic diagram showing the data flow change trend of a "Digital Signal Encryption / Decryption Circuit".

[0203] The dotted lines in the figure respectively represent the data flow changes and trends in each main circuit. The data flow of the "secret key" is hidden and circularly shifted; the data flow of the "public key" which is the "old" encryption key and the variable key sent back for "recovery" changes irregularly; the data flow of the "time code" in the "public key" is circularly shifted and at the same time the digital value continuously accumulates as time changes.

[0204] In the middle, the "Multi-circular Shift Circuit" divides the data into multiple paths for circular shift, enabling continuous changes.

[0205] In actual work, either "recover" the "old" encryption key and the variable key as the "plain code"; or let the "Multi-circular Shift Circuit" change the data, and either one can be chosen.

[0206] The data flow of the "variable key" generated by the above data flow transformation is hidden, irregularly changing, and non-repeating.

[0207] Therefore, after the data flow of the (encryption / decryption) input data is subjected to an exclusive OR operation bit by bit with the data flow of the "variable key", the data flow of the (encryption / decryption) output data is irregular.

[0208] In Figure 5 , in Figure (a), it is the circuit block diagram of the "code position mutual control transformation circuit", abbreviated as the "code control transformation circuit". One part of the input end serves as the input data line, and the other part serves as the control line. That is to say, one part of the input of this circuit serves as the "control code", and the other part serves as the "controlled code". Essentially, they are the same and can be interchanged, but are artificially distinguished.

[0209] In Figure (b), it is a schematic block diagram of an internal circuit structure of the "code control transformation circuit". It is a combination of a combinational logic circuit and a sequential logic circuit, and the output data can be re-fed back to the input after passing through the latch circuit.

[0210] In Figure (c), it is another schematic block diagram of the internal circuit structure of the "code control transformation circuit". It is a combination of a combinational logic circuit and a sequential logic circuit. There are multiple "code control transformation circuits" inside, and they are nested and cascaded with each other, and there is internal feedback within the stage and feedback between stages. Between the internal "code control transformation circuits", there is a data distribution circuit to rearrange the data and insert new data.

[0211] In Figure 6 , it is a schematic diagram of the electrical principle of the "code position mutual control transformation circuit", abbreviated as the "code control transformation circuit". It is composed of a data distribution circuit, an OR gate circuit, an AND gate circuit, a NOT gate circuit, an exclusive OR gate circuit, etc.

[0212] The circuits among them can be integrated circuits. For example, the "data distribution circuit" can be 74LS538 (3 / 8 multiplexer), and the "exclusive OR gate" is 74HC386 (quadruple exclusive OR circuit), etc.

[0213] In Figure 7 , the "code control transformation circuit" in the encryption and decryption circuit has a schematic diagram of nesting and a "multi-cycle shift circuit".

[0214] After the public key and the private key are mixed, they form multiple outputs through the "code control transformation circuit" (16) and are sent to the "multi-cycle shift circuit" (17), and then form multiple outputs through the second-stage "code control transformation circuit" and are sent to the second-stage "multi-cycle shift circuit", and then through the third-stage "code control transformation circuit", and finally one output is selected to form the "transformed key".

[0215] In the second-stage and third-stage "code control transformation circuits", the public key and the private key can be inserted and mixed.

[0216] The "multi-cycle shift circuit" (17) is composed of more than one cyclic shift register circuit. Each cyclic shift circuit is arranged in parallel with each other to form more input bits and output bits.

[0217] The "multi-cycle shift circuit" at the second level is connected in series and in a mixed connection.

[0218] The bit lengths of the respective cycle shift register circuits are not equal to each other.

[0219] The unequal bit lengths are either non-multiple relationships with each other. For example, some bit lengths are 7 bits, some are 9 bits, some are 10 bits, and so on. By analogy, the lengths are taken as 7, 9, 10, 11, 13, 17, 19, 23, 31, ……, or are distributed according to prime numbers, such as 2, 3, 5, 7, 9, 11, 13, 17, 19, 23, 31, …….

[0220] If the key and the plain key have a total of 18 bytes, 18×8 = 144 bit. Taking 140 bits of them, after the pre-stage transformation process, they are respectively sent to 9 (unequal-length) cycle shift register circuits, so that their bit lengths are 7, 9, 10, 11, 13, 17, 19, 23, 31 respectively. (The total bit length = 7 + 9 + 10 + 11 + 13 + 17 + 19 + 23 + 31 = 140 bit).

[0221] Then, the combination of each cycle = 7×9×10×11×13×17×19×23×31 = 20747636910, with more than 20 billion combinations. (Similar to the traditional chronology method, the ten Heavenly Stems such as Jia, Yi, Bing, Ding, etc. and the twelve Earthly Branches such as Zi, Yin, Mao, etc. form a cycle of sixty units for rotation.)

[0222] In other words, for each change of the key or the plain key, 2.59 billion groups of non-repeating outputs can be continuously generated according to the clock beat. Through subsequent transformation, a "variant key" with a bit length of 2.59 billion bits can be generated.

[0223] In Figure 8 is a schematic diagram of the electrical principle of another working process of the "digital signal encryption and decryption circuit".

[0224] It is a simplified encryption / decryption circuit.

[0225] The "key storage circuit" (2) is composed of a DIP switch and a non-volatile memory, and can manually set and transform the key.

[0226] The "key transformation circuit" (13) is composed of a shift register.

[0227] The "plain key transformation circuit" (12) adds the control of the "key". The "key" and the "old ciphertext" are pre-transformed through an "exclusive OR" circuit.

[0228] The "mixed code transformation circuit" (15) is composed of a data selection circuit.

[0229] The circuit therein may be an integrated circuit. For example, the "shift register" may be 74HC164 (8-bit shift register), 74HC166 (8-bit shift register with serial input and serial output), and the "data selection circuit" may be 74LS151 (8-to-1 data selector), 74HC150 (16-to-1 data selector).

[0230] Others are similar to the foregoing.

[0231] In Figure 9 is a schematic block diagram of the electrical principle of one kind of "digital signal encryption and decryption circuit".

[0232] The "key transformation circuit" (13) is composed of circuits such as a shift register and a data selector. Multiple shift registers are connected in series to form a cyclic shift circuit, and are sent to the "hybrid transformation circuit" (15) through the data selector.

[0233] The "hybrid transformation circuit" (15) is composed of circuits such as a data selector.

[0234] The "code control transformation circuit" (16) has a dip switch and can manually control the next-level transformation.

[0235] The circuit therein may be an integrated circuit. For example, the "shift register" may be 74HC164 (8-bit shift register), and the "data selection circuit" may be 74LS151 (8-to-1 data selector), 74HC150 (16-to-1 data selector), and so on.

[0236] After the "key transformation circuit" (13) reads from the "key storage circuit" (2), it is distributed into multiple paths and performs cyclic shifting. The lengths of the code streams of each cyclic rotation are different, and the ways of sending to the next level are different.

[0237] The "key transformation circuit" (13) transforms from a single-path input to a multi-path output; the "hybrid transformation circuit" (15) transforms from a multi-path input to a single-path output.

[0238] The input data at terminal B1 is the "pilot code", the input data at terminal B2 is the data to be encrypted (or the data to be decrypted), and the output at terminal C is the encrypted data (or the decrypted data).

[0239] The synchronous clock signal is generated by phase-locking by the "synchronization circuit" (38) according to the signal input at terminal B, and is sent directly or through a frequency division circuit to each timing circuit.

Claims

1. Circuit for digital signal encryption and decryption, characterized in that: It is an encryption and decryption circuit using symmetric keys, which includes a "digital signal encryption circuit" and a "digital signal decryption circuit". These two are corresponding to each other and need to be used in pairs, and they are collectively called a "digital signal encryption and decryption circuit". Both the encryption circuit and the decryption circuit have a "digital code encryption and decryption transformation circuit" (1) and a "key storage circuit" (2). The "digital code encryption and decryption transformation circuit" (1) has a "plain key transformation circuit" (12), a "key transformation circuit" (13), a "hybrid transformation circuit" (15), and a "final stage transformation circuit" (29). The so-called "key" is a group of digital codes that are pre-held jointly by the encrypting party and the decrypting party in advance, not publicly disclosed, and are exactly the same, and are stored in the "key storage circuit" (2) respectively. The so-called "plain key" is a data string or data code stream that is generated in real time by one party, sent to the other party, and used jointly by both parties and is publicly disclosed. The outputs of the "plain key transformation circuit" (12) and the "key transformation circuit" (13) are both sent to the "hybrid transformation circuit" (15). The output of the "hybrid transformation circuit" (15) forms a "transformed key" and is sent to the "final stage transformation circuit" (29). Among them, The "plain key transformation circuit" (12) and the "key transformation circuit" (13) are composed of shift register circuits. The "hybrid transformation circuit" (15) is composed of logic gate circuits, combinational logic circuits, and sequential logic circuits, and has multiple inputs. This combination circuit composed of logic gate circuits, combinational logic circuits, and sequential logic circuits is called a "code bit mutual control transformation circuit", abbreviated as a "code control transformation circuit" (16). The "code control transformation circuit" (16) is a combinational circuit with multiple inputs, and internally has one or more of basic logic gate circuits, combinational logic circuits, and sequential logic circuits. The "code control transformation circuit" (16) is formed by connecting in series, in parallel, or in a mixed connection basic logic gate circuits, combinational logic circuits, and sequential logic circuits. One part of the input terminals is used as input data terminals, and the other part is used as control terminals. That is, one part of the input of the "code control transformation circuit" (16) is used as a "control code", and the other part is used as a "controlled code". The control code at the control terminal determines the input-output relationship. Inside the "hybrid transformation circuit" (15), it is composed of multiple "code control transformation circuits". Each "code control transformation circuit" is arranged in parallel with each other, or is connected in series or cross-connected in a mixed manner to form nesting, cascading, or feedback. The so-called nesting means that the internal module that makes up the code control transformation circuit also has a code control transformation circuit. The so-called cascading means that after the output of the code control transformation, the data is rearranged, or new data is inserted, and a new code control transformation is performed. The so-called feedback means that the output data, through a latch circuit in the middle, is fed back to the input terminal of this stage, or the previous stage, or the previous several stages. The "plain key transformation circuit" (12) and the "key transformation circuit" (13) have a "code control transformation circuit" (16). The "final stage transformation circuit" (29) is composed of an "exclusive OR" circuit. For the encryption circuit, the data information to be encrypted is "exclusive-ORed" with the "variant key" in the "final transformation circuit" (29) to form the encrypted data information. For the decryption circuit, the encrypted data information is "exclusive-ORed" with the "variant key" in the "final transformation circuit" (29) to form the decrypted data information. This "exclusive-OR" is performed in the form of a data stream. For the data to be encrypted or decrypted, the pulse frequency of its digital signal constitutes the reference frequency of the pulse clock. For each timing circuit in the "digital encryption and decryption transformation circuit", the pulse-triggered clock signal is of the same frequency and synchronized with the reference signal, or is frequency-divided. Alternatively, the pulse clock frequencies of each timing circuit are selected by code control, and through the combination of a selector and a frequency-divider circuit, "code-controlled" frequency division of the reference clock is performed to form pulse clock signals of different frequencies. The circuit for digital signal encryption and decryption also has a "data format identification and separation circuit" (3) and a "data format reconstruction circuit" (4). After the digital signal to be encrypted / decrypted is input through the circuit port, it first passes through the "data format identification and separation circuit" (3) to separate the non-format signal, and then is input to the "digital encryption and decryption transformation circuit" (1) for corresponding encryption or decryption transformation. The transformed signal is input to the "data format reconstruction circuit" (4), and the "data format reconstruction circuit" (4) combines the transformed signal with the format signal to reconstruct the format signal and outputs it from the circuit output port. The described "data format identification and separation circuit" (3) refers to a comparison circuit that compares whether the data format is the same as the format pre-recorded and stored. Once they are the same, separation is performed. The described "data format reconstruction circuit" (4) refers to the corresponding one that, after encryption is completed, restores the corresponding data format. The circuit for digital signal encryption and decryption also has an "A / D conversion circuit" and a "D / A conversion circuit". In the encryption circuit, there is an "A / D conversion circuit" before the "digital encryption and decryption transformation circuit" (1), and in the decryption circuit, there is a "D / A conversion circuit" after the "digital encryption and decryption transformation circuit" (1).

2. The circuit for digital signal encryption and decryption according to claim 1, wherein: The "code-controlled transformation circuit" (16) has a "multi-cycle shift circuit" (17). The described "multi-cycle shift circuit" (17) is composed of a combination of one or more cycle shift register circuits. Each cycle shift circuit is arranged in parallel with each other, or connected in series, or connected in a mixed manner. For each cycle shift register circuit, its serial input terminal and output terminal are connected to each other, so that the data of the register circuit is cyclically shifted according to the clock beat of the data stream and output from the parallel data terminal after shifting. For each cycle shift register circuit, its shift direction is the same or different. For each cycle shift register circuit, its moving direction is fixed or determined by "code bit control". After the circuit starts or is reset, the data of the shift register circuit is input from the data terminal and output from the parallel data terminal, and then cyclically shifted according to the clock beat of the data stream. Before encryption or decryption, each circular shift register circuit performs "pre-shift". The so-called "pre-shift" means initialization and circular shift. The displacement length of this "pre-shift" is fixed or determined by the code control. This "pre-shift" is performed during the encryption and decryption process. The bit lengths of the circular shift register circuits are equal to each other or unequal to each other. The "multi-circular shift circuit" (17) in the "code-controlled conversion circuit" (16) has a "code-controlled conversion circuit" embedded in its input or output end. This kind of nesting is hierarchical or layered. The so-called hierarchical nesting refers to the alternating combination of "code control conversion circuit" (16) and "multi-cyclic shift circuit" (17) to form a multi-level nesting. The so-called hierarchical nesting means that there are "multi-cyclic shift circuits" and "code-controlled conversion circuits" in the "code-controlled conversion circuit" (16), and the embedded "code-controlled conversion circuit" has "multi-cyclic shift circuits" and "code-controlled conversion circuits", forming multi-level nesting.

3. The digital signal encryption and decryption circuit according to claim 1, characterized in that: The shift register circuit in the "key conversion circuit" (13) allows the key to be input from the serial or parallel port after the circuit is started or reset, and is fixedly output from the parallel port to the next level circuit. Alternatively, after the circuit is started or reset, the key is input from the serial or parallel port, and after the parallel port output is completed, it is cyclically shifted according to the reference frequency, and then output from the parallel data terminal after the shift to the next level circuit. Alternatively, after the circuit is started or reset, the key is input from the serial or parallel port, and after the parallel port output is completed, it is sent to the "multi-cyclic shift circuit", and then circularly shifted according to the reference frequency. After the shift, it is output from the parallel data terminal and sent to the next level circuit.

4. The digital signal encryption and decryption circuit according to claim 1, characterized in that: The shift register circuit in the "public key conversion circuit" (12) allows the public key to be input from the serial or parallel port after the circuit is started or reset, and is fixedly output from the parallel port to the next level circuit. Alternatively, after the circuit is started or reset, the key is input from the serial or parallel port, and after the parallel port output is completed, it is cyclically shifted according to the reference frequency, and then output from the parallel data terminal after the shift to the next level circuit. Alternatively, after the circuit is started or reset, the public key is input from the serial or parallel port, and after the parallel port output is completed, it is sent to the "multi-circular shift circuit", and then according to the reference frequency, each is circularly shifted, and after the shift, it is output from the parallel data terminal and sent to the next level circuit. The clear key signal in the "clear key conversion circuit" (12) is input once or continuously. The "one-time" means that after the public key is input once, in the subsequent encryption and decryption process, the public key is no longer added, but the previously input public key is transformed with the secret key to generate a constantly changing "variable key". The "continuous" mentioned above means that during the encryption and decryption process, the public key is continuously added. This continuously added data stream is a time code, or an "old" encrypted signal, or an "old" variant key, or a mixture of the added data stream, the "old" encrypted signal, and the "old" variant key signal. When the clear key signal is continuously input, in the "digital encryption and decryption transformation circuit" (1), there may also be a "pilot code generation circuit" (21). The "pilot code generation circuit" (21) generates "pilot code" data and sends it to the "clear key transformation circuit" (12). The "pilot code" is a fixed value or a random value. The "pilot code" is obtained directly from the "key transformation circuit" (13) "time code" by both the encrypting party and the decrypting party, or is generated by one party and sent to the other party.

5. The digital signal encryption and decryption circuit according to any one of claims 1-4, characterized in that: The encryption circuit and the decryption circuit internally have a "digital encryption and decryption transformation circuit" (1) and a "key storage circuit" (2). The "digital encryption and decryption transformation circuit" (1) has a "clear key transformation circuit" (12), a "key transformation circuit" (13), a "hybrid transformation circuit" (15), and a "final transformation circuit" (29), and also has a "code control transformation circuit" (16) and a "multi-cycle shift circuit" (17). The overall circuit or part of the circuit in the "digital encryption and decryption transformation circuit" (1) and the "key storage circuit" (2) is implemented by a programmable logic chip PLD or a computer, and the computer includes a general-purpose computer, a single-chip microcomputer, and a data processor.

6. The digital signal encryption and decryption circuit according to any one of claims 1-4, characterized in that: The "clear key transformation circuit" (12), "key transformation circuit" (13), "hybrid code transformation circuit" (15), and "final transformation circuit" (29) in the encryption and decryption circuit, and the "code control transformation circuit" (16), "multi-cycle shift circuit" (17), and "XOR circuit" that make up these circuits are implemented by integrated circuits. The "key transformation circuit" (13), "clear key transformation circuit" (12), and "time code transformation circuit" (11) in the encryption and decryption circuit are composed of "shift registers", "counters" circuits or corresponding integrated circuits. Each transformation circuit in the "key transformation circuit" (13), "clear key transformation circuit" (12), and "time code transformation circuit" (11) is formed by parallel connection, series connection, and mixed connection of multiple "shift registers", "counters", and "gate circuits" integrated circuits.

7. The digital signal encryption and decryption circuit according to any one of claims 1-4, characterized in that: The digital signal encryption and decryption circuit has a DIP switch or a keyboard. The "toggle switch" serves as the key in the "key storage circuit" (2), either as the whole key or a part of the key, or as the control code in the "code control transformation circuit" (16), or as the connection switch for the internal lines of the transformation circuit or between circuits. Through the keyboard, the key or the control code is changed, or the connection mode of the lines is controlled and changed.

8. The digital signal encryption and decryption circuit according to any one of claims 1-4, characterized in that: In the digital signal encryption and decryption circuit, the "digital encryption and decryption transformation circuit" (1) and the "key storage circuit" (2) directly form independent circuits, or become part of a circuit, or directly form an integrated circuit, or become part of an integrated circuit. The "key storage circuit" (2) is directly fixed inside the encryption / decryption chip, or there are multiple stored keys in the chip circuit. This digital signal encryption and decryption circuit is embedded in the data storage circuit, or in the signal path of the electronic device, or in the circuit of the Internet, Internet of Things terminal or node device.

9. The digital signal encryption and decryption circuit according to any one of claims 1-4, characterized in that: The "digital encryption and decryption transformation circuit" (1) has one or more of the transformation circuits including the "key transformation circuit" (13), the "public key transformation circuit" (12), the "time code transformation circuit" (11) and the "hybrid transformation circuit" (15). The "digital encryption and decryption transformation circuit" (1) has an "encrypted data feedback circuit" (22) and a "variable key data feedback circuit" (24), and has one of the "encrypted data feedback circuit" (22) and the "variable key data feedback circuit" (24). The public key directly serves as the control code of the "code control transformation circuit" (16), and the key directly serves as the controlled code of the "code control transformation circuit" (16).

10. The digital signal encryption and decryption circuit according to any one of claims 1-4, characterized in that: The input ends of the "digital encryption and decryption transformation circuit" (1) and the "key storage circuit" (2) each have independent external connection lines. The output end of the "digital encryption and decryption transformation circuit" (1) has an independent external connection line, while the output of the "key storage circuit (2)" is directly sent to the "digital encryption and decryption transformation circuit" (1). The "digital encryption and decryption transformation circuit" (1) and the "key storage circuit" (2) are fixedly connected or connected by plugging and unplugging. For the chip of this circuit composed of the "digital encryption and decryption transformation circuit" (1) and the "key storage circuit" (2), the interface of the key storage and the encryption circuit is separated, and the chips of the key storage and the encryption circuit are separated. The digital signal encryption and decryption circuit is combined in the overall circuit, or is an independent board circuit, or is an integrated circuit chip.

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