Image Sensor

Abstract

The present disclosure provides an image sensor, which includes a first layer, the first layer including pixels in a pixel array, and a first logic circuit configured to control the pixel array. Each pixel includes at least one photodiode configured to generate an electric charge in response to light and a pixel circuit configured to generate a pixel signal corresponding to the electric charge. The second layer includes a second logic circuit connected to the pixel array and the first logic circuit, and is on the first layer. The third layer includes a storage element electrically connected to at least one of the pixels and the first logic circuit, and an insulating layer including the storage element therein. The lower surface of the insulating layer is attached to the upper portion of the first layer, and the upper surface of the insulating layer is attached to the lower portion of the second layer.

Description

Technical Field

[0001] The inventive concept relates to an image sensor and a method of manufacturing the same. Background Art

[0002] An image sensor is a semiconductor-based device that can receive light and generate an electrical signal therefrom. An image sensor may include a pixel array having a plurality of pixels, a logic circuit for driving the pixel array and generating an image, and the like. The plurality of pixels may include a photodiode that generates a charge in response to light, and a pixel circuit that uses the charge generated by the photodiode to output a pixel signal. In order to improve the performance of image sensors, research is being conducted on image sensors to which various elements are added. Summary of the invention

[0003] An aspect of the present inventive concept is to provide an image sensor in which a pixel array, a logic circuit, and a memory device are formed in separate layers stacked on each other, in which a semiconductor substrate is removed from a layer disposed in the middle of the stack, and in which the image sensor can simplify the manufacturing process and realize a global shutter operation and a high dynamic range (HDR) function.

[0004] According to one aspect of the inventive concept, an image sensor includes a first layer including pixels arranged in a pixel array and a first logic circuit configured to control the pixel array. Each pixel includes at least one photodiode configured to generate an electric charge in response to light and a pixel circuit configured to generate a pixel signal corresponding to the electric charge. The image sensor also includes: a second layer including a second logic circuit electrically connected to the pixel array and the first logic circuit, wherein the second layer is on the first layer; a third layer including a storage element and an insulating layer including the storage element therein, the storage element being electrically connected to at least one of the pixel and the first logic circuit. The lower surface of the insulating layer is attached to the upper portion of the first layer, and the upper surface of the insulating layer is attached to the lower portion of the second layer.

[0005] According to one aspect of the present invention, an image sensor includes: a pixel array including pixels in a first semiconductor substrate, each pixel including a photodiode configured to generate an electric charge in response to light, and a pixel circuit configured to generate a pixel voltage based on the electric charge; a first logic circuit including a first element on the first semiconductor substrate, wherein the first logic circuit is configured to control the pixel and is in a first insulating layer on the first semiconductor substrate or covered by the first insulating layer; a second logic circuit including a second element in a second semiconductor substrate different from the first semiconductor substrate, wherein the second logic circuit is configured to drive the pixel array and the first logic circuit, and is in a second insulating layer on the second semiconductor substrate or covered by the second insulating layer; and a capacitor between the first insulating layer and the second insulating layer, wherein the capacitor is in a third insulating layer different from the first insulating layer and the second insulating layer and is connected to at least one of the pixel array and the first logic circuit.

[0006] According to one aspect of the present invention, an image sensor includes: a first layer, including a first semiconductor substrate, a pixel array in a first area of ​​the first semiconductor substrate, and a first logic circuit in a second area around the first area and configured to drive the pixel array; a second layer, stacked on the first layer in a direction perpendicular to an upper surface of the first semiconductor substrate, the second layer including a second semiconductor substrate and a second logic circuit on the second semiconductor substrate; a third layer, between the first layer and the second layer, including a storage element; and a logic path, extending through the third layer and connecting the first logic circuit to the second logic circuit, wherein the logic path does not extend through the semiconductor material.

[0007] According to one aspect of the present invention, a method for manufacturing an image sensor includes: forming a first layer, the first layer including a first semiconductor substrate, a pixel array and a first logic circuit on the first semiconductor substrate, and a first insulating layer on the pixel array and the first logic circuit; forming a second layer, the second layer including a second semiconductor substrate different from the first semiconductor substrate, a second logic circuit on the second semiconductor substrate and different from the first logic circuit, and a second insulating layer on the second logic circuit; forming a third layer, the third layer including a third semiconductor substrate different from the first semiconductor substrate and the second semiconductor substrate, a storage element on the third semiconductor substrate, and a third insulating layer on the storage element; attaching the first layer to the third layer so that a first surface of the third insulating layer faces the first insulating layer; removing the third semiconductor substrate to expose a second surface of the third insulating layer; and attaching the third layer to the second layer so that the second surface of the third insulating layer faces the second insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figures 1 to 3 is a schematic diagram illustrating an image sensor according to an example embodiment of the present disclosure;

[0010] Figure 4 is a schematic block diagram illustrating an image sensor according to an example embodiment of the present disclosure;

[0011] Figure 5 is a schematic circuit diagram showing a pixel circuit of an image sensor according to an example embodiment of the present disclosure;

[0012] Figure 6 is a diagram illustrating the operation of an image sensor according to an example embodiment of the present disclosure;

[0013] Figure 7 and Figure 8 is a schematic circuit diagram showing a pixel circuit of an image sensor according to an exemplary embodiment of the present disclosure;

[0014] Fig. 9 and Fig.10 are diagrams respectively illustrating an image sensor according to a comparative example and an image sensor according to an exemplary embodiment of the present disclosure;

[0015] Figures 11 to 15 is a diagram showing a vertical structure of an image sensor according to an example embodiment of the present disclosure;

[0016] Fig.16 and Fig.17 is a diagram showing a memory element included in an image sensor according to an example embodiment of the present disclosure;

[0017] Fig.18 is a flow chart illustrating a method of manufacturing an image sensor according to an example embodiment of the present disclosure;

[0018] Fig.19 is a diagram illustrating a method of manufacturing an image sensor according to an example embodiment of the present disclosure;

[0019] Figures 20 to 27 is a diagram illustrating a method of manufacturing an image sensor according to an example embodiment of the present disclosure; and

[0020] Fig.28 is a schematic block diagram illustrating an electronic device including an image sensor according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals are used for the same constituent elements, and repeated description of the same constituent elements will be omitted.

[0022] Figures 1 to 3 is a schematic diagram illustrating an image sensor according to an example embodiment of the present disclosure.

[0023] First, refer to Figure 1 , an image sensor 1 according to an exemplary embodiment of the present disclosure includes a first layer 10, a second layer 20, and a third layer 30. The first to third layers 10, 20, and 30 may be stacked in a vertical direction. For example, the third layer 30 may be disposed between the first layer 10 and the second layer 20. The terms first, second, third, etc. are used herein only to distinguish one element or layer from another element or layer.

[0024] For example, the first layer 10 may include a pixel array 11 and a first logic circuit 12. The pixel array 11 includes a plurality of pixels connected to row lines extending in a first direction and column lines extending in a second direction intersecting the first direction and may be arranged in a matrix form. Each pixel may include at least one photodiode generating charges in response to light, and a pixel circuit generating a pixel voltage using the charges generated by the photodiode.

[0025] The first logic circuit 12 may include a circuit for driving the pixel array 11. In one example, the first logic circuit 12 may include a row driver for driving the row lines, a readout circuit for acquiring pixel voltages from pixels through column lines, control logic for controlling the row driver and the readout circuit, etc. In one embodiment, the pixel array 11 is disposed in a first region of the first layer 10, and the first logic circuit 12 is disposed in a second region surrounding the first region.

[0026] The second layer 20 may include a second logic circuit 21. The second logic circuit 21 may include a circuit for driving the pixel array 11 and the first logic circuit 12. In an example, the second logic circuit 21 may include a power supply circuit, an input / output interface, an image signal processor, and the like.

[0027] The third layer 30 may include a storage element array 31. The storage element array 31 may include storage elements, and the storage elements may be implemented as at least one of a metal-insulator-metal (MIM) capacitor, a charge trap element, a magnetic tunnel junction (MTJ) element, and a germanium (Ge)-antimony (Sb)-tellurium (Te) (GST) element. The storage element may be connected to the pixel and / or the first logic circuit 12 formed in the first layer 10. In addition, the storage element may be connected to the second logic circuit 21 formed in the second layer 20.

[0028] Next, refer to Figure 2 , an image sensor 1A according to an example embodiment of the present disclosure may include a first layer 10A, a second layer 20A, and a third layer 30 stacked in a vertical direction.

[0029] exist Figure 2 In the illustrated example embodiment, the first layer 10A may include a pixel array 11A, and all of the first logic circuit 21A and the second logic circuit 22A may be disposed in the second layer 20A. The first logic circuit 21A may include a row driver, a readout circuit, a control logic, etc., and the second logic circuit 22A may include a power supply circuit, an input / output interface, an image signal processor, etc. The third array 30 may include a storage element array 31 in which storage elements are disposed.

[0030] according to Figure 3 The image sensor 1B of the example embodiment shown may include a first layer 10, a second layer 20B, and a third layer 30 stacked in a vertical direction. The first layer 10 and the third layer 30 may be connected to the first layer 10B according to the embodiment of the present invention. Figure 1 The first and third layers of the image sensor 1 of the illustrated example embodiment are identical.

[0031] exist Figure 3 In the example embodiment shown, the second layer 20B may include an analog-to-digital converter (ADC). The analog-to-digital converter may be disposed in an ADC array 21B, and the second logic circuit 22B may be disposed around the ADC array 21B.

[0032] In an example, the area of ​​the second layer 20B in which the ADC array 21B is disposed may correspond to the area of ​​the first layer 10 in which the pixel array 11 is disposed. In other words, the ADC array 21B may be disposed below the pixel array 11. In an example embodiment, the pixels of the pixel array 11 may be connected to the analog-to-digital converter of the ADC array 21B through the storage elements of the storage element array 31. The pixel signal output from the pixel may be an analog signal, and the analog-to-digital converter may output the pixel signal by converting the analog signal into a digital pixel signal.

[0033] Figure 4 is a schematic block diagram illustrating an image sensor according to an example embodiment of the present disclosure.

[0034] Reference Figure 4 , the image sensor 100 may include a pixel array 110 , a logic circuit 120 , and the like.

[0035] The pixel array 110 may include a plurality of pixels PX arranged in an array along a plurality of rows and a plurality of columns. Each of the plurality of pixels PX may include at least one photodiode that generates a charge in response to light, a pixel circuit that generates a pixel signal corresponding to the charge generated by the photodiode, and the like. In one example, the pixel circuit may include a floating diffusion, a transfer transistor, a reset transistor, a drive transistor, a selection transistor, and the like. According to example embodiments, the configuration of the pixel PX may vary. In one example, each pixel PX may include an organic photodiode containing an organic material, or may be implemented as a digital pixel. When the pixel PX is implemented as a digital pixel, each pixel PX may include an analog-to-digital converter for outputting a digital pixel signal. That is, each pixel PX may include at least one photodiode and an additional circuit.

[0036] The logic circuit 120 may include a circuit for controlling the pixel array 110. In an example, the logic circuit 120 may include a row driver 121, a readout circuit 122, a column driver 123, a control logic 124, etc. The row driver 121 may drive the pixel array 110 in units of row (ROW) lines. For example, the row driver 121 may generate a transfer control signal that controls a transfer transistor of a pixel circuit, a reset control signal that controls a reset transistor thereof, and a selection control signal that controls a selection transistor thereof, and may input the transfer control signal, the reset control signal, and the selection control signal to the pixel array 110.

[0037] The readout circuit 122 may include a correlated double sampler (CDS), an analog-to-digital converter (ADC), etc. The correlated double sampler may be connected to the pixel PX through a column line. The correlated double sampler may read a pixel signal from the pixel PX connected to a row line selected by a row line selection signal of the row driver 121 through a column line. The analog-to-digital converter may convert the pixel signal detected by the correlated double sampler into a digital pixel signal, and may send the digital pixel signal to the column driver 123.

[0038] The column driver 123 may include a latch, a buffer circuit, an amplification circuit, etc. for temporarily storing a digital pixel signal, and may process the digital pixel signal received from the readout circuit 122. The row driver 121, the readout circuit 122, and the column driver 123 may be controlled by the control logic 124. The control logic 124 may include a timing controller for controlling the operation timing of the row driver 121, the readout circuit 122, and the column driver 123.

[0039] Figure 5 is a schematic circuit diagram illustrating a pixel circuit of an image sensor according to an example embodiment of the present disclosure.

[0040] Reference Figure 5According to an exemplary embodiment of the present disclosure, a pixel may include a pixel circuit PC having a plurality of transistors and a photodiode PD. A signal generated by the transistor using charges generated by the photodiode PD may be output through a column line COL.

[0041] The pixel circuit PC may include a transfer transistor TX, a reset transistor RX, a drive transistor DX, a selection transistor SX, etc. The reset transistor RX may be turned on and off by a reset control signal RG. When the reset transistor RX is turned on, the voltage of the floating diffusion FD may be reset to a power supply voltage VDD. In an example, when the voltage of the floating diffusion FD is reset, the selection transistor SX is turned on by a selection control signal SG, so that the reset voltage may be output to the column line COL.

[0042] In an example embodiment, the photodiode PD generates electrons or holes as main charge carriers in response to light. When a reset voltage is output to the column line COL and then the transfer transistor TX is turned on, the charge generated by the photodiode PD being exposed to light can be moved to the floating diffusion FD. The drive transistor DX can be used as a source follower amplifier that amplifies the voltage of the floating diffusion FD. When the selection transistor SX is turned on by the selection control signal SG, the pixel voltage corresponding to the charge generated by the photodiode PD can be output to the column line COL.

[0043] Figure 6 is a diagram illustrating the operation of an image sensor according to an example embodiment of the present disclosure.

[0044] For the sake of convenience, the following will refer to Figure 4 The operation of the image sensor 100 is described below. Figure 6 In the example embodiment shown, the image sensor 100 may operate in a global shutter method in which the pixels PX are simultaneously reset and simultaneously exposed to light (eg, simultaneously active to generate charge in response to light incident thereon).

[0045] Reference Figure 6 , at reset time T RS During this time, the photodiodes of the pixels PX included in the pixel array 110 may be reset simultaneously. In an example, a reset transistor included in a pixel circuit is turned on to connect the photodiode to a predetermined power supply voltage, and thus the photodiode may be reset.

[0046] When the photodiode is reset or after the photodiode is reset, the photodiode included in the pixel PX is exposed for a period of time T EXDuring this period, the image sensor is activated and exposed to light, so that a charge can be generated. In one example, the exposure time T can be determined by the operating environment of the image sensor, the shutter speed, the aperture value, etc. EX .

[0047] After the exposure time T EX When or after exposure time T EX After that, the row driver 121 may scan each row line. The readout circuit 122 may perform a readout operation on each pixel PX in the order in which the row driver 121 scans the row lines. The readout circuit 122 may perform a readout operation on each pixel PX in the readout time T RO During this period, a pixel signal is read from each of the plurality of pixels PX.

[0048] The readout circuit 122 can read the pixel signal of the pixel PX in units of row lines. Therefore, the pixel PX connected to the row line that is not activated by the row driver 121 can store the charge generated by the photodiode. Alternatively, the charge can be stored until the pixel signal generated by the pixel PX is output through the column line. Therefore, in order for the image sensor 100 to operate in a global shutter method, a device for storing the charge generated by the photodiode and / or the pixel signal generated by the pixel circuit may be required.

[0049] Figure 7 and Figure 8 is a schematic circuit diagram illustrating a pixel circuit of an image sensor according to an example embodiment of the present disclosure.

[0050] In one example, Figure 7 and Figure 8 is a circuit diagram showing a pixel circuit of an image sensor operating in a global shutter method. Figure 7 and Figure 8 , a pixel of an image sensor according to an example embodiment of the present disclosure may include a photodiode PD and a pixel circuit PC.

[0051] First, in Figure 7 In the example embodiment shown, the pixel circuit PC may include a transfer transistor TX, a reset transistor RX, a first drive transistor DX1, a first switch element SW1, a second switch element SW2, a second drive transistor DX2, a select transistor SX, a current source transistor CX, etc. In addition, the pixel circuit PC may include at least one storage element, such as C1 and C2.

[0052] As previously referenced Figure 6 As described above, in an image sensor operating in a global shutter method, pixels can be reset simultaneously. In the reset operation, the reset transistor RX is reset at the reset time T RSDuring the exposure time T, the reset control signal RG is turned on, so that the charge of the floating diffusion FD can be removed. EX During this time, charge may be generated by the photodiode PD in response to exposure to light.

[0053] In one operation of the global shutter method, pixels are reset at the same time and activated and exposed to light at the same time. In addition, a readout operation for reading pixel signals from pixels can be sequentially performed in units of row lines connected to pixels. Therefore, at least a portion of the pixels can store the charge generated by the photodiode PD and / or the pixel signal corresponding to the charge generated by the photodiode PD until the readout operation is performed. Figure 7 In the example embodiment shown, when the transfer transistor TX is turned on by the transfer control signal TG and the charge generated by the photodiode PD moves to the floating diffusion FD, the first drive transistor DX1 used as a source follower amplifier can output a first pixel signal. Due to the current control signal CG, the current source transistor CX can supply current to the first drive transistor DX1.

[0054] When at least one of the first switching element SW1 and the second switching element SW2 is turned on, the first pixel signal may be stored in at least one of the first capacitor C1 and the second capacitor C2. That is, the first capacitor C1 and the second capacitor C2 provided as storage elements may be programmed by the first pixel signal output by the first driving transistor DX1.

[0055] In at least a portion of the pixel, before performing a readout operation, at least one of the first switch element SW1 and the second switch element SW2 is turned on by the first control signal S1 and the second control signal S2, and the first pixel signal may be stored in the first capacitor C1 and / or the second capacitor C2. When performing a readout operation, the second switch element SW2 and the selection transistor SX are turned on, and the second drive transistor DX2 may amplify the first pixel signal to output a second pixel signal. The second pixel signal may be a pixel signal output by the pixel to the readout circuit through the column line COL.

[0056] Next, in Figure 8 In the example embodiment shown, the pixel 200 may include an analog pixel circuit 201, a comparator 202, a storage circuit 203, etc. The analog pixel circuit 201 may include a photodiode and two or more transistors, and may output a pixel signal corresponding to the charge generated by the photodiode in response to exposure to light.

[0057] The comparator 202 compares the pixel signal with a predetermined reference signal V REF In one example, when the pixel signal is compared with the predetermined reference signal VREF When the magnitude relationship between the pixels 200 and 201 changes, the comparator 202 may invert its output. The storage circuit 203 may include a counter circuit, etc. In an example embodiment, the storage circuit 203 may count the time until the output of the comparator is inverted, and the counting result may be stored as a digital pixel signal. When the readout operation for the pixel 200 starts, the storage circuit 203 may output the digital pixel signal to the column line COL.

[0058] In other words, according to Figure 8 The pixel 200 of the illustrated exemplary embodiment may not output an analog signal but a digital signal. Therefore, noise in a readout operation may be reduced, and a pixel signal is simultaneously inverted into a digital pixel signal in the pixel 200 included in the image sensor, so that a readout speed may be increased.

[0059] However, the area that each pixel of an image sensor can have is limited. Figure 7 Capacitors C1 and C2 are arranged as shown or as Figure 8 The comparator 202 and the storage circuit 203 are arranged as shown, and integration problems may occur. In an exemplary embodiment of the present disclosure, at least a part of the elements included in the pixel are formed in wafers different from each other, and the wafers are stacked to connect the elements. Therefore, an image sensor that operates in a global shutter method and solves the integration problem can be provided.

[0060] In addition, capacitors C1 and C2 and storage circuit 203 can be used for other functions besides the operation of the global shutter method. For example, capacitors C1 and C2 and storage circuit 203 can be used as a memory for storing image data, or can be used to provide a high dynamic range (HDR) function.

[0061] In one example, the first image data generated by the activation and exposure to light of the photodiode PD during the first time may be stored in the capacitors C1 and C2 and / or the storage circuit 203. The photodiode PD may be activated and exposed to light during a second time different from the first time to generate the second image data, and the first image data and the second image data may be used to generate the result image. In an example embodiment, the first time may be longer than the second time in duration. In particular, in the first image data acquired during the relatively long first time, the dark area may be fully represented. In the second image data acquired during the relatively short second time, the bright area may be accurately represented without saturation. The image signal processor included in the image sensor may use both the first image data and the second image data to generate the result image. According to an example embodiment, the pixel signal (rather than the image data) generated in response to the charge generated by the activation and exposure to light of the photodiode PD in each of the first time and the second time may be stored in the capacitors C1 and C2 or the storage circuit 203.

[0062] Fig. 9 and Fig.10 1 and 2 are diagrams respectively illustrating an image sensor according to a comparative example and an image sensor according to an exemplary embodiment of the present disclosure.

[0063] Fig. 9 and Fig.10 is a diagram showing a cross-sectional structure of one of the pixels included in the image sensors 300 and 400. Specifically, Fig. 9 A comparative example provided to describe an image sensor is shown. Fig. 9 According to a comparative example, an image sensor 300 may include a semiconductor substrate 301, a photodiode 305 and a transistor 310 formed on the semiconductor substrate 301, metal wirings 311 and 312 connected to the transistor 310, an insulating layer 320 in which the transistor 310 and the metal wirings 311 and 312 are embedded, and the like.

[0064] The semiconductor substrate 301 may be a substrate including a semiconductor material such as silicon, and the photodiode 305 may be formed in the semiconductor substrate 301. In one example, the photodiode 305 may be formed using a process of implanting impurities into the inside of the semiconductor substrate 301, and the photodiode 305 may be connected to at least one of the transistors 310. Fig. 9 , the vertical separation membrane 303 is formed adjacent to the photodiode 305, and the photodiode 305 may not be formed in or on one side of the vertical separation membrane 303, so that the semiconductor substrate 301 has no photodiode on one side of the vertical separation membrane 303.

[0065] On one surface of the semiconductor substrate 301, a light blocking layer 307 and a micro lens 309 may be formed. In one example, the light blocking layer 307 may be formed on a portion of the semiconductor substrate 301 on a side of the vertical separation diaphragm 303 where there is no photodiode 305, and the micro lens 309 may be formed to overlap with the photodiode 305.

[0066] The transistor 310 may provide a pixel circuit. In one example, the transistor 310 may include a transfer transistor, a reset transistor, a drive transistor, a current source transistor, a switch element, etc. The transistor 310 is connected to the photodiode 305 and may be connected to a storage element 313 embedded in the insulating layer 320 through metal wirings 311 and 312. In a comparative example, the storage element 313 may be a capacitor and may be provided between the lower wiring 311 and the upper wiring 312.

[0067] The process of manufacturing the capacitor may include a process of forming a dielectric film. In order to improve the leakage characteristics of the capacitor, the process of forming the dielectric film may be performed at a relatively high temperature. When the dielectric film is formed at a high temperature, the lower wiring 311 provided before the formation of the capacitor may be formed of tungsten. However, compared with other metals such as copper, tungsten has a relatively high resistivity and a low reflectivity. In this regard, Fig. 9 In the illustrated comparative example, when the lower wiring 311 is formed of tungsten, the characteristics of the image sensor 300 may be reduced or deteriorated compared to the case where the lower wiring 311 is formed of other metals such as copper.

[0068] Reference Fig.10 In an exemplary embodiment of the present disclosure, in order to solve the above problem, the memory element 432 is formed separately to be attached to the pixel. The image sensor 400 according to an exemplary embodiment of the present disclosure may include a lower layer LL including a photodiode 405 and a transistor 410, and an upper layer UL including a memory element 432.

[0069] In one example, the photodiode 405, the vertical separation diaphragm 403, the light blocking layer 407, the microlens 409, the transistor 410, the lower wiring 411 and the lower insulating layer 420 are formed based on one semiconductor substrate 401 to manufacture the lower layer LL, and the upper wiring 431, the storage element 432 and the upper insulating layer 430 are formed based on another semiconductor substrate (different from the substrate 401 of the lower layer LL) to manufacture the upper layer UL. The upper layer UL can be vertically inverted to be attached to the lower layer LL. When the lower layer LL and the upper layer UL are attached to each other, the semiconductor substrate of the upper layer UL and / or the lower layer LL or the semiconductor substrate included in the upper layer UL and / or the lower layer LL can be partially or completely removed therefrom.

[0070] According to an example embodiment, at a boundary B1 between the lower layer LL and the upper layer UL, the lower insulating layer 420 and the upper insulating layer 430 face or oppose each other and may contact each other. At least one of the lower wirings 411 and at least one of the upper wirings 431 may be electrically connected to each other by copper-to-copper (Cu-Cu) bonding at the boundary B1 between the lower layer LL and the upper layer UL. Fig.10 As shown, a connection wiring 440 providing Cu-Cu bonding may be disposed at a boundary B1 between the lower layer LL and the upper layer UL.

[0071] In other words, in an example embodiment of the present disclosure, the storage element 432 can be formed separately based on a separate semiconductor substrate. Therefore, because the high temperature process for forming the dielectric film of the storage element 432 can be performed without restriction (for example, without considering the influence of the high temperature process on the existing wiring or other elements), the leakage current of the storage element 432 can be significantly reduced. In addition, because the lower wiring 411 of the transistor 410 connected to the pixel is not formed of tungsten but of other metals (such as copper) with improved or excellent resistivity and reflectivity, the operating characteristics of the image sensor 400 can be improved.

[0072] Figures 11 to 15 is a diagram illustrating a vertical structure of an image sensor according to an example embodiment of the present disclosure.

[0073] First, refer to Fig.11 and Fig.12 , the image sensor 500 according to an example embodiment of the present disclosure may include a first layer L1, a second layer L2, and a third layer L3. The third layer L3 may be disposed between the first layer L1 and the second layer L2.

[0074] The first layer L1 may include a pixel array having pixels and a first logic circuit for controlling the pixel array. In an example embodiment, the pixel array is disposed in a first region of the first layer L1, and the first logic circuit is disposed in a second region around the first region. The first logic circuit may include a row driver, a readout circuit, a control logic for driving the pixel array, and the like. In an example, Fig.11 may be a diagram showing a cross-sectional structure of a first region of the image sensor 500, Fig.12 It may be a diagram showing a cross-sectional structure of the second region of the image sensor 500 .

[0075] Referring to the first layer L1, a vertical separation diaphragm 503 and a photodiode 505 are formed in a first semiconductor substrate 501, and a light blocking layer 507 and a microlens 509 may be formed on one surface of the first semiconductor substrate 501. In addition, a transistor 510 included in the pixel circuit may be formed on the other surface of the first semiconductor substrate 501, and the transistor 510 and a metal wiring 511 connected to the transistor 510 may be embedded in an insulating layer 520.

[0076] The second layer L2 may be disposed above the first layer L1 and may include a second logic circuit. The second logic circuit may include a circuit for driving the pixel array and the first logic circuit. In one example, the second logic circuit may include a power supply circuit, an input / output interface, an image signal processor, and the like. Referring to the second layer L2, a second semiconductor substrate 550, a circuit element 560 formed on the second semiconductor substrate 550, a metal wiring 561 connected to the circuit element 560, an insulating layer 570 covering the circuit element 560 and the metal wiring 561, and the like may be included.

[0077] The third layer L3 may be disposed between the first layer L1 and the second layer L2. The third layer L3 may include a memory element 532 electrically connected to the pixel array and / or the first logic circuit of the first layer L1, an insulating layer 530 in which the memory element 532 is embedded, and the like. The lower surface of the insulating layer 530 is attached to the first layer L1, and the upper surface of the insulating layer 530 may be attached to the second layer L2. In addition, the lower surface of the insulating layer 530 faces or is opposite to the upper surface of the insulating layer 520 of the first layer L1, and the upper surface of the insulating layer 530 may face or be opposite to the lower surface of the insulating layer 570 of the second layer L2.

[0078] exist Fig.11 In the example embodiment shown, the storage element 532 may be a capacitor. In one example, the storage element 532 may be implemented as a metal-insulator-metal (MIM) capacitor. In one example, each pixel included in the first layer L1 may be connected to at least one of the storage elements 532. The pixels may not share the storage element 532. In other words, the pixels may be connected to different storage elements 532, respectively.

[0079] When the storage element 532 is implemented as a capacitor, the first electrode of the capacitor may be connected to one of the first transistors 510. Figure 7 , for example, one of the first switching element SW1 and the second switching element SW2 can be connected to the first electrode of the capacitor. In addition, the second electrode of the capacitor can be connected to a metal wiring among the second metal wirings 511 to which a predetermined power supply voltage is supplied.

[0080] In other words, according to Figure 7As shown in the circuit diagram, the storage element 532 may be provided as a first capacitor C1 and a second capacitor C2. Therefore, the first pixel signal output by the first drive transistor DX1 may be temporarily stored in the storage element 532. When the readout operation for the pixel starts, the second drive transistor DX2 may output the pixel signal to the column line COL using the voltage of the storage element 532.

[0081] Cu-Cu bonding may be applied to the first boundary B1 between the first layer L1 and the third layer L3. Fig.11 At least one of the metal wirings 511 of the first layer L1 may be connected to at least one of the metal wirings 531 of the third layer L3 through the connection wiring 540 disposed at the first boundary B1.

[0082] In an exemplary embodiment of the present disclosure, the third layer L3 and the second layer L2 may be directly attached to each other. Fig.11 and Fig.12 , the insulating layer 530 of the third layer L3 and the insulating layer 570 of the second layer L2 may be attached to each other by an adhesive layer 580 .

[0083] The image sensor 500 according to an example embodiment of the present disclosure may include a logic path 535 that passes through the third layer L3 and connects the first logic circuit and the second logic circuit to each other. Fig.12 The length of the logic path 535 may be greater than the thickness of the third layer L3 and may extend from the second region in the first layer L1 where the first logic circuit is provided in the stacking direction. The connection wiring 540 connecting the pixel to the storage element 532 may have a shorter length than the logic path 535.

[0084] The logic path 535 may extend from the metal wiring 511 of the first layer L1 to the metal wiring 561 of the second layer L2 and may not pass through a region formed of a semiconductor material, such as a semiconductor substrate. Fig.12 , the logic path 535 may extend into or may pass through the insulating layers 520, 530, and 570 of the first to third layers L1 to L3 and the adhesive layer 580. Therefore, the logic path 535 does not need to be formed by a through silicon via (TSV), so process difficulty, time, and / or cost may be reduced.

[0085] Next, refer to Fig.13 , the image sensor 500A according to an exemplary embodiment of the present disclosure may include a first layer L1, a second layer L2, and a third layer L3 between the first layer L1 and the second layer L2. Fig.11 and Fig.12 Similar parts or can refer to Fig.11 and Fig.12 Description of the component being understood.

[0086] exist Fig.13 In the example embodiment shown, the second layer L2 and the third layer L3 can be connected by a Cu-Cu bonding method. Fig.13 , the metal wiring 561 of the second layer L2 and the metal wiring 531 of the third layer L3 may be electrically connected to each other through the connection wiring 580A. Therefore, the second logic circuit of the second layer L2 may use the memory element 532.

[0087] In one example, the image signal processor of the second logic circuit can store and process the image data received from the first logic circuit connected to the pixel array in the storage element 532. That is, the storage element 532 can be used as a buffer memory for storing image data. Alternatively, data for the operation of the second logic circuit can be stored in the storage element 532.

[0088] Next, refer to Fig.14 , an image sensor 500B according to an exemplary embodiment of the present disclosure may include a first layer L1, a second layer L2, and a third layer L3 between the first layer L1 and the second layer L2. Fig.13 The description of Fig.11 and Fig.12 Similar parts or can refer to Fig.11 and Fig.12 Description of the component being understood.

[0089] exist Fig.14 In the example embodiment shown, the memory elements 532B and 533B may be vertically stacked in the third layer L3. Fig.14 , the first storage element 532B and the second storage element 533B may be stacked inside the insulating layer 530 of the third layer L3. The first storage element 532B and the second storage element 533B may share at least a portion of the metal wiring 531 inside the insulating layer 530, and may be connected to the metal wiring 511 of the first layer L1 through the connection wiring 540.

[0090] In one example, the first storage element 532B and the second storage element 533B can be used for different purposes. The first storage element 532B is connected to the first logic circuit of the first layer L1 for storing image data generated by processing the pixel signal by the first logic circuit. The second storage element 533B is connected to the pixels of the first layer L1 to store the charge generated by the photodiode 505 in each pixel, or can store the pixel signal output by the pixel circuit. The functions of the first storage element 532B and the second storage element 533B are not limited to those in the example embodiments, and can be expanded and / or changed in various ways.

[0091] Next, refer to Fig.15 , an image sensor 500C according to an example embodiment of the present disclosure may include a first layer L1, a second layer L2, and a third layer L3 between the first layer L1 and the second layer L2. Fig.13 and Fig.14 The description of Fig.11 and Fig.12 The same parts or can refer to Fig.11 and Fig.12 Description of the component being understood.

[0092] exist Fig.15 In an example embodiment shown, the memory elements 532C and 533C may be vertically stacked in the third layer L3. In addition, the memory elements 532C and 533C may be connected not only to the pixels and / or the first logic circuit of the first layer L1, but also to the second logic circuit of the second layer L2. Fig.15 , at least one of the metal wirings 531 connected to the storage elements 532C and 533C may be connected to at least one of the metal wirings 561 of the second layer L2 through the connection wiring 580C at the boundary B2 between the second layer L2 and the third layer L3.

[0093] In one example, the first storage element 532C adjacent to the first layer L1 is connected to the pixel of the first layer L1 for global shutter operation or HDR function. Alternatively, the first storage element 532C may be connected to the first logic circuit of the first layer L1. In addition, the second storage element 533C adjacent to the second layer L2 is connected to the second logic circuit to be used as a buffer memory for storing image data, etc. However, according to example embodiments, the connection relationship between the pixel, the storage elements 532C and 533C, the first logic circuit, and the second logic circuit may be modified in various ways.

[0094] Fig.16 and Fig.17 is a diagram illustrating a memory element included in an image sensor according to an example embodiment of the present disclosure.

[0095] First, refer to Fig.16 In an example embodiment of the present disclosure, the pixel circuit PC may include a transfer transistor TX, a reset transistor RX, a first drive transistor DX1, a first switch element SW1, a second switch element SW2, a second drive transistor DX2, a selection transistor SX, a current source transistor CX, etc. In addition, the pixel circuit PC may include at least one storage element ME1 and ME2. The operation of the pixel circuit PC may be similar to that of the above reference Figure 7 The pixel circuit PC may be operated in a global shutter method.

[0096] When at least one of the first switching element SW1 and the second switching element SW2 is turned on, the first pixel signal output by the first driving transistor DX1 may be stored in at least one of the first storage element ME1 and the second storage element ME2. The first storage element ME1 and the second storage element ME2 may be implemented as magnetic tunnel junction (MTJ) elements. Fig.17 The first memory element ME1 is described. The second memory element ME2 can be understood with reference to the following description of the first memory element ME1.

[0097] Reference Fig.17 , the first memory element ME1 may include an MTJ element, and may include a free layer 610, a pinned layer 630, and a tunnel layer 620 disposed therebetween. The magnetization direction of the pinned layer 630 is fixed without changing, and the magnetization direction of the free layer 610 may change in the same or opposite direction as the pinned layer 630 depending on conditions. In order to fix the magnetization direction of the pinned layer 630, an antiferromagnetic layer may be further included in the first memory element ME1.

[0098] In one example, in the first memory element ME1, the fixed layer 630 is connected to the first switch element SW1, and the free layer 610 may be connected to the first metal wiring 601. The first metal wiring 601 may be a wiring to which a predetermined reference voltage (eg, a ground voltage) is input. The first switch element SW1 may be connected to the second metal wiring 602 and the third metal wiring 603. Fig.16 As can be understood from the circuit diagram of FIG. 6 , the first control signal S1 is input through the second metal wiring 602, and the third metal wiring 603 is connected to the output terminal of the first driving transistor DX1.

[0099] The magnetization direction of the free layer 610 may be determined by the current or voltage input by the first switch element SW1 turned on by the first control signal S1 (i.e., the current or voltage generated by the pixel signal output by the first drive transistor DX1). In one example, when the current flows from the free layer 610 to the fixed layer 630 by the first pixel signal, the magnetization direction of the free layer 610 may be the same as that of the fixed layer 630. In addition, when the current flows from the fixed layer 630 to the free layer 610 by the first pixel signal, the magnetization direction of the free layer 610 may be changed to a direction opposite to that of the fixed layer 630.

[0100] Meanwhile, according to an example embodiment of the present disclosure, the storage element ME1 and / or ME2 of the pixel circuit PC may be provided by an element other than the MTJ element. In one example, the storage element ME1 and / or ME2 may be provided by a variable resistance element in which the phase changes according to the temperature. For example, the storage element ME1 and ME2 may be implemented using a germanium (Ge)-antimony (Sb)-tellurium (Te) (GST) element. Alternatively, the storage element ME1 and / or ME2 may be implemented using a charge trap element, which is a storage element including an additional charge storage layer in which charges may be captured. In other words, the storage element ME1 and / or ME2 may be interpreted as conceptually including all types of elements capable of storing data using the first pixel signal output by the first drive transistor DX1. In addition, according to an example embodiment, the storage elements ME1 and ME2 included in the pixel circuit PC may be implemented by different elements.

[0101] Fig.18 is a flow chart showing a method of manufacturing an image sensor according to an example embodiment of the present disclosure. Fig.19 is a diagram illustrating a method of manufacturing an image sensor according to an example embodiment of the present disclosure. Fig.18 and Fig.19 A method of manufacturing an image sensor is described.

[0102] Reference Fig.18 and Fig.19 The method of manufacturing an image sensor according to an exemplary embodiment of the present disclosure may start with preparing a first layer 701, a second layer 702, and a third layer 703 (S10). Each of the first layer 701, the second layer 702, and the third layer 703 may be a separate wafer.

[0103] In an example, according to example embodiments, the first layer 701 may include a first semiconductor substrate and pixels formed on the first semiconductor substrate, and a first logic circuit for driving the pixels may be included in the first layer 701. According to example embodiments, the second layer 702 may include a second semiconductor substrate and a second logic circuit formed in the second semiconductor substrate, and the first logic circuit for driving the pixels may be included in the second layer 702. The third layer 703 may include a storage element such as a MIM capacitor, a MOS capacitor, an MTJ element, a GST element, a charge trap element, etc. Each of the first semiconductor substrate, the second semiconductor substrate, and the third semiconductor substrate may be different from each other (e.g., a separate wafer).

[0104] When preparing the first layer 701 to the third layer 703, the first layer 701 and the third layer 703 can be attached to each other (S20). The first layer 701 and the third layer 703 can be bonded to each other at the wafer level (710). In other words, at the wafer level, which is the level before the laser scribing process is performed on the first layer 701 and the third layer 703 to be separated into semiconductor chips, the first layer 701 and the third layer 703 can be attached to each other. The third layer 703 is vertically inverted to be attached to the first layer 701. Therefore, when the first layer 701 and the third layer 703 are attached to each other, the first semiconductor substrate and the third semiconductor substrate can be exposed below and above, respectively. In an example, in the process of attaching the first layer 701 to the third layer 703, the metal wiring of the first layer 701 and the metal wiring of the third layer 703 can be connected to each other using a Cu-Cu bonding method.

[0105] When the first layer 701 and the third layer 703 are attached to each other, the third semiconductor substrate may be completely removed from the third layer 703 (S30). In an exemplary embodiment, the third semiconductor substrate (720) may be completely removed using an etching process and a chemical mechanical polishing (CMP) process. The third semiconductor substrate is completely removed, and a semiconductor substrate such as a silicon wafer is not provided in the third layer 703. In addition, when the third layer 703 is prepared, an insulating layer formed on the third semiconductor substrate may be exposed to the outside.

[0106] When the third semiconductor substrate is removed, the third layer 703 and the second layer 702 may be attached to each other (S40). Thus, the first layer 701, the second layer 702, and the third layer 703 may be combined into one. The second layer 702 may be bonded to the third layer 703 at the wafer level (730), and in a manner similar to S20, the second layer 702 may be vertically inverted and attached to the third layer 703. When the second layer 702 is attached to the third layer 703, the first logic circuit of the first layer 701 and the second logic circuit of the second layer 702 may be electrically connected to each other (S50). In addition, according to an example embodiment of the present disclosure, at least a portion of the second logic circuit of the second layer 702 may be electrically connected to a storage element of the third layer 703 by a Cu-Cu bonding method.

[0107] When the second layer 702 is attached to the upper portion of the third layer 703, a portion of the first semiconductor substrate (740) may be removed. When a portion of the first semiconductor substrate is removed by the CMP process, an optical layer (750) exposed to the outside may be formed on one surface of the first semiconductor substrate. The optical layer may include a color filter, a microlens, a light blocking layer, etc.

[0108] Figures 20 to 27 is a diagram illustrating a method of manufacturing an image sensor according to an example embodiment of the present disclosure.

[0109] Reference Fig. 20 , a first layer L1 may be prepared to manufacture an image sensor. The first layer L1 includes a first semiconductor substrate 801, and pixels may be disposed in the first semiconductor substrate 801. The pixels may be disposed in a first region of the first semiconductor substrate 801, and a first logic circuit for driving the pixels may be disposed around the first region.

[0110] A photodiode 805 and a vertical separation membrane 803 may be formed inside the first semiconductor substrate 801. Fig. 20 In the illustrated example embodiment, the vertical separation diaphragm 803 is shown to be formed deeper than the photodiode 805, but this is only an example and is not necessarily limited thereto. A transistor 810 and a metal wiring 811 providing a pixel circuit may be formed on one surface of the first semiconductor substrate 801. The transistor 810 and the metal wiring 811 may be in the first insulating layer 820 or covered by the first insulating layer 820.

[0111] Reference Fig.21 , a third layer L3 may be prepared to manufacture an image sensor. The third layer L3 includes a third semiconductor substrate 835, and a metal wiring 831 and a storage element 832 connected to the metal wiring 831 may be formed on an upper portion of the third semiconductor substrate 835. The metal wiring 831 and the storage element 832 may be in a third insulating layer 830 formed on the third semiconductor substrate 835 or covered by the third insulating layer 830. The storage element 832 may be implemented as a capacitor, an MTJ element, a GST element, a charge trap element, etc.

[0112] In an example embodiment of the present disclosure, the first layer L1 including the pixel is formed based on the first semiconductor substrate 801, and the third layer L3 including the storage element 832 can be formed based on the third semiconductor substrate 835 different from the first semiconductor substrate 801. Therefore, when the storage device 832 is a capacitor, the process for forming the dielectric film can be performed at a high temperature, and the leakage current of the capacitor can be significantly reduced. In addition, the metal wiring 811 of the first layer L1 can be formed of a metal with low resistivity and high reflectivity, such as copper, without material restrictions.

[0113] Next, refer to Fig. 22 , the first layer L1 and the third layer L3 may be attached to each other. In one example, the third layer L3 is vertically inverted and attached to the upper portion of the first layer L1, and thus, the upper surface of the first insulating layer 820 may face or oppose the third insulating layer 830. Fig. 22In the illustrated example embodiment, the first layer L1 and the third layer L3 may be attached to each other by a Cu-Cu bonding method using a connection wiring 840 that connects the metal wiring 811 of the first layer L1 to the metal wiring 831 of the third layer L3. However, according to example embodiments, an additional adhesive layer may be provided at a boundary B1 between the first layer L1 and the third layer L3.

[0114] Reference Fig.23 , when the first layer L1 and the third layer L3 are attached to each other, the third semiconductor substrate 835 may be completely removed. When the third semiconductor substrate 835 is completely removed, the third insulating layer 830 may be exposed to the outside.

[0115] When the third semiconductor substrate 835 is completely removed, as shown in FIG. Fig.24 As shown, the second layer L2 may be attached to the third insulating layer 830. The second layer L2 may be vertically inverted and attached to the third layer L3 in a similar manner, and thus, the second semiconductor substrate 850 may be relatively located above the second insulating layer 870. Fig.24 In the example embodiment shown, the second layer L2 and the third layer L3 may be attached to each other by an additional adhesive layer 880 along the boundary B2. Fig.25 As shown, the second layer L2 and the third layer L3 may be attached, for example, without an adhesive layer by providing a connecting wiring 880A of Cu-Cu bonding.

[0116] The second layer L2 may include a second logic circuit for driving the first logic circuit. The second logic circuit may include a power supply circuit, an input / output interface, an image signal processor, etc. In the second layer L2, a circuit element 860 and a metal wiring 861 for providing the second logic circuit may be in the second insulating layer 870 or covered by the second insulating layer 870.

[0117] In order to connect the second logic circuit of the second layer L2 to the first logic circuit of the first layer L1, a logic path may be formed in an operation before attaching the second layer L2. Fig.12 and Fig.23 As described above, the logic path for connecting the first logic circuit to the second logic circuit may pass through the third layer L3.

[0118] In an exemplary embodiment of the present disclosure, before forming the logic path, the third semiconductor substrate 835 included in the third layer L3 may be completely removed using an etching process, a CMP process, etc. The logic path only passes through a layer formed of an insulating material to connect the first logic circuit to the second logic circuit without passing through a substrate including a semiconductor material. Therefore, the difficulty of forming the logic path can be reduced, which can reduce the time and cost required for the process.

[0119] Reference Fig.26 , a portion of the first semiconductor substrate 801 may be removed. When the portion of the first semiconductor substrate 801 is removed, the photodiode 805 may be closer to one surface 801F of the first semiconductor substrate 801. The portion of the first semiconductor substrate 801 may be removed using an etching process and / or a CMP process.

[0120] Next, refer to Fig. 27 , an optical layer may be formed on one surface 801F of the first semiconductor substrate 801. The optical layer may include a light blocking layer 807, a color filter 808, a microlens 809, etc. According to example embodiments, a buffer layer may be further formed between the color filter 808 and the first semiconductor substrate 801 and / or between the color filter 808 and the microlens 809.

[0121] exist Fig. 27 In the illustrated example embodiment, the color filter 808 covers the light blocking layer 807, and the microlens 809 may be formed so as not to overlap with the light blocking layer 807. However, according to another example embodiment, the color filter 808 is first formed on one surface 801F of the first semiconductor substrate 801, and the light blocking layer 807 and the microlens 809 may be formed on the color filter 808.

[0122] Fig.28 is a schematic block diagram illustrating an electronic device including an image sensor according to an example embodiment of the present disclosure.

[0123] according to Fig.28 The electronic device 1000 of the illustrated example embodiment includes a display 1010, a sensor unit 1020, a memory 1030, a communication unit 1040, a processor 1050, and a port 1060. The electronic device 1000 may further include a power supply, input and output devices, etc. Fig.28 Among the components shown, a port 1060 may be provided for the electronic device 1000 to communicate with a video card, a sound card, a memory card, a universal serial bus (USB) device, etc. The electronic device 1000 may be a smart phone, a tablet PC, a smart wearable device, etc., as well as a desktop computer and a laptop computer according to the related art.

[0124] The processor 1050 may be configured to perform certain operations, commands, tasks, etc. The processor 1050 may be a central processing unit (CPU), a microprocessor unit (MPU), a system on a chip (SoC), etc., and may communicate with the display 1010, the sensor unit 1020, the memory 1030, the communication unit 1040, and other devices connected to the port 1060 through the bus 1070.

[0125] The memory 1030 may be a storage medium storing multimedia data or data used for the operation of the electronic device 1000. The memory 1030 may include a volatile memory such as a random access memory (RAM) or a nonvolatile memory such as a flash memory. In addition, the memory 1030 may include at least one of a solid state drive (SSD), a hard disk drive (HDD), and an optical disk drive (ODD) as a storage element.

[0126] The sensor unit 1020 may include an image sensor, a global positioning system (GPS) sensor, an acoustic sensor, etc. In addition, the electronic device 1000 may include two or more image sensors. In this case, at least one of the characteristics such as the total number of pixels, the viewing angle, and the aperture value of the two or more image sensors may have different values. Fig.28 In the example embodiment shown, the image sensor included in the sensor unit 1020 may be a Figures 1 to 27 Various example embodiments of image sensors are described.

[0127] As described above, according to an example embodiment of the inventive concept, a pixel array, a logic circuit, and a storage element are formed on additional or corresponding layers, and these layers are stacked to manufacture an image sensor. In a layer disposed between layers stacked on each other, the semiconductor substrate can be completely removed. Therefore, the process of manufacturing an image sensor can be simplified, and the image sensor can use a storage element to provide various functions.

[0128] For ease of description, spatial relational terms such as "under", "beneath", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature to another element(s) or feature(s) as shown in the figure. It will be understood that in addition to the orientation depicted in the figure, the spatial relational terms are intended to also cover other different orientations of the device in use or operation. For example, if the device in the figure is turned over, the elements described as "under" or "beneath" other elements or features will be oriented "above" the other elements or features.

[0129] When an element is referred to as being "on" or "connected to" another element, it may be directly on or directly connected to the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0130] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the claims.

[0131] This application claims the benefit of priority from Korean Patent Application No. 10-2019-0141207 filed on November 6, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. An image sensor, comprising: A first layer includes pixels in a pixel array and a first logic circuit configured to control the pixel array, each of the pixels including: at least one photodiode configured to generate charge in response to light; and a pixel circuit configured to generate a pixel signal corresponding to the charge; a second layer including a second logic circuit electrically connected to the pixel array and the first logic circuit, wherein the second layer is on the first layer; and a third layer including a storage element electrically connected to at least one of the pixel and the first logic circuit, and further including an insulating layer including the storage element therein, wherein the lower surface of the insulating layer is directly attached to the upper portion of the first layer, and the upper surface of the insulating layer is directly attached to the lower portion of the second layer, and The first layer and the second layer have no semiconductor substrate therebetween. 2 . The image sensor of claim 1 , wherein the first layer comprises a first semiconductor substrate, the second layer comprises a second semiconductor substrate, and the third layer has no through-silicon vias.

3. The image sensor according to claim 1, wherein the pixel circuit of each of the pixels is connected to at least one of the storage elements, and The pixels are respectively connected to different storage elements among the storage elements. 4 . The image sensor of claim 3 , wherein the pixels are configured to be activated simultaneously to generate the charge, and the storage element is configured to be programmed by the pixel signal. 5 . The image sensor according to claim 4 , wherein the storage element is configured to output the pixel signals to the first logic circuit in sequence. 6 . The image sensor according to claim 4 , wherein the pixel circuit of each of the pixels includes a switching element connected between the at least one of the storage elements and the at least one photodiode.

7. The image sensor of claim 1 , wherein the storage element is configured to store first image data, the first logic circuit is configured to generate the first image data by controlling the pixel to be active during a first time, and The first logic circuit is configured to generate a result image using the first image data and second image data, the second image data being acquired by controlling the pixels to be active during a second time different from the first time.

8. The image sensor according to claim 1, wherein the storage element comprises at least one of a metal-insulator-metal capacitor, a charge trap element, a magnetic tunnel junction element, and a germanium (Ge)-antimony (Sb)-tellurium (Te) element. 9 . The image sensor of claim 1 , wherein the pixel and the storage element are connected by a copper-to-copper bond at a boundary between the first layer and the third layer. 10 . The image sensor of claim 1 , wherein the upper surface of the insulating layer is attached to the lower portion of the second layer through an adhesive layer between the second layer and the third layer.

11. The image sensor according to claim 1, wherein the second area of ​​the second layer corresponds to the first area of ​​the first layer, the second logic circuit is arranged in the second area of ​​the second layer, and the pixel array is arranged in the first area of ​​the first layer, and The second logic circuit is electrically connected to at least one of the pixel and the storage element.

12. The image sensor of claim 11, wherein the second logic circuit and the storage element are connected by copper-to-copper bonding at a boundary between the second layer and the third layer, and wherein the boundary is located above the pixel array. 13 . The image sensor according to claim 11 , wherein the second logic circuit comprises an analog-to-digital converter connected to the pixel through the storage element and configured to convert the pixel signal into a digital pixel signal. 14 . The image sensor according to claim 13 , wherein the analog-to-digital converters are connected to the pixels, respectively, and are configured to output the digital pixel signals through column lines. 15 . The image sensor according to claim 1 , wherein the first layer further comprises a metal wiring connected to the pixel circuit of each of the pixels, and wherein the metal wiring comprises copper (Cu).

16. An image sensor, comprising: A pixel array comprising pixels on a first semiconductor substrate, each of the pixels comprising: a photodiode configured to generate charge in response to light; and a pixel circuit configured to generate a pixel voltage based on the charge; a first logic circuit including a first element on the first semiconductor substrate, wherein the first logic circuit is configured to control the pixel and is in a first insulating layer on the first semiconductor substrate; a second logic circuit including a second element on a second semiconductor substrate different from the first semiconductor substrate, wherein the second logic circuit is configured to drive the pixel array and the first logic circuit and is in a second insulating layer on the second semiconductor substrate; and a capacitor between the first insulating layer and the second insulating layer, wherein the capacitor is in a third insulating layer different from the first insulating layer and the second insulating layer and is connected to at least one of the pixel array and the first logic circuit, wherein the lower surface of the third insulating layer is directly attached to the upper portion of the first insulating layer, and the upper surface of the third insulating layer is directly attached to the lower portion of the second insulating layer, and There is no semiconductor substrate between the first insulating layer and the second insulating layer. 17 . The image sensor according to claim 16 , wherein a lower surface of the third insulating layer faces an upper surface of the first insulating layer, and wherein an upper surface of the third insulating layer faces a lower surface of the second insulating layer.

18. The image sensor according to claim 16, wherein the pixel circuit of each of the pixels comprises: a first driving transistor configured to output a first pixel signal based on the charge generated by the photodiode; a switching element connected to an output terminal of the first driving transistor; as well as A second driving transistor is connected to the switching element and configured to output a second pixel signal.

19. An image sensor, comprising: A first layer including a first semiconductor substrate, a pixel array in a first region of the first semiconductor substrate, and a first logic circuit in a second region around the first region and configured to drive the pixel array; a second layer stacked on the first layer in a direction perpendicular to an upper surface of the first semiconductor substrate, the second layer comprising a second semiconductor substrate and a second logic circuit on the second semiconductor substrate; a third layer between the first layer and the second layer and including a storage element and an insulating layer including the storage element therein, wherein a lower surface of the insulating layer is directly attached to an upper portion of the first layer, and an upper surface of the insulating layer is directly attached to a lower portion of the second layer; as well as A logic via extends through the insulating layer of the third layer and connects the first logic circuit to the second logic circuit, wherein the logic via does not extend through semiconductor material.

20. The image sensor of claim 19, wherein a length of the logic via is greater than a thickness of the third layer.

Images