Control systems for medium voltage variable frequency drives

Abstract

A drive system (300) is disclosed herein, comprising a power unit (312) for providing power to one or more output phases (A, B, C), each power unit (312) having a plurality of switching devices (315a-d) including semiconductor switches; and a control system (400) communicating with the plurality of power units (312) and controlling the operation of the plurality of power units (312), wherein the control system (400) comprises a system on chip (410) comprising one or more central processing units (412, 414) and a field programmable gate array (416) communicating with the one or more central processing units (412, 414).

Description

Technical Field

[0001] Aspects of the present disclosure generally relate to control systems for drive systems, and more particularly to control systems for medium voltage variable frequency drives. Throughout the specification, the terms "drive," "drive system," "converter," and "power supply" may be used interchangeably. Background Art

[0002] Because individual power semiconductor devices cannot withstand high voltages, medium voltage (MV) variable frequency drives (e.g., multilevel power converters) are used in applications such as medium voltage alternating current (AC) drives, flexible AC transmission systems (FACTS), and high voltage DC (HVDC) transmission systems. Multilevel power converters typically include multiple power cells for each phase, each power cell including an inverter circuit with semiconductor switches that are capable of varying the voltage output of an individual cell.

[0003] One example of a multilevel power converter is a cascaded H-bridge converter system having multiple H-bridge cells as described, for example, in U.S. Patent No. 5,625,545 to Hammond, which is incorporated herein by reference in its entirety. Another example of a multilevel power converter is a modular multilevel converter system having multiple M2C or M2LC subsystems.

[0004] Medium voltage drives contain purpose-built digital control systems. Currently, digital control systems divide control loop commands and status, power cell control information, and external communication interfaces into three separate components. The three separate major components are: a control processor / host central processing unit for control loop commands, status, and non-drive interfaces; a field programmable gate array (FPGA) for power cell control and communications; and an electronic programmable logic device (EPLD) for external communications. The major components require a dedicated data bus on a printed circuit board (PCB) so that the major components can exchange information between them for the drive system to operate successfully.

[0005] However, current control system architectures require a considerable amount of physical space for the PCB data bus wiring design as well as for the three components themselves, and the PCB wiring needs to be carefully designed in order for the data communication to operate correctly / consistently. In addition, the use of three separate devices increases the possibility of overall system failure due to manufacturing defects or general use. Summary of the invention

[0006] Briefly described, aspects of the present disclosure relate to a drive system, for example, embodied as a medium voltage variable frequency drive, and more specifically to a control system for the drive system. Specifically, aspects of the present disclosure provide a drive system, which includes: a plurality of power cells that provide power to one or more output phases, each power cell including a plurality of switching devices including semiconductor switches; and a control system that communicates with the plurality of power cells and controls the operation of the plurality of power cells, wherein the control system includes a system on chip, the system on chip including one or more central processing units and a field programmable gate array that communicates with the one or more central processing units. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A schematic diagram showing a known basic configuration of a cascaded H-bridge converter system according to an exemplary embodiment of the present disclosure.

[0008] Figure 2 A schematic diagram illustrating another known basic configuration of a cascaded H-bridge converter system in accordance with exemplary embodiments disclosed herein.

[0009] Figure 3 A schematic diagram is shown of a drive system according to an exemplary embodiment disclosed herein.

[0010] Figure 4 A schematic diagram showing the architecture of a control system of a drive system according to an exemplary embodiment disclosed herein.

[0011] Figure 5 Perspective views showing different control system devices according to exemplary embodiments disclosed herein. DETAILED DESCRIPTION

[0012] To facilitate understanding of the embodiments, principles and features of the present invention, they will be explained below with reference to their implementation in illustrative embodiments. In particular, they are described in the context of a control system for a variable frequency drive, in particular a medium voltage (MV) variable frequency drive including a multi-unit power supply (e.g., a modular multilevel converter system and a cascaded H-bridge converter system). However, the embodiments of the present invention are not limited to use in the described devices or methods.

[0013] As used herein, "medium voltage" is a voltage greater than about 690 V and less than about 69 kV, and "low voltage" is a voltage less than about 690 V. One of ordinary skill in the art will appreciate that other voltage levels may be designated as "medium voltage" or "low voltage." For example, in some embodiments, "medium voltage" may be a voltage between about 3 kV and about 69 kV, and "low voltage" may be a voltage less than about 3 KV.

[0014] The components and materials described below as making up the various embodiments are intended to be illustrative rather than limiting. Many suitable components and materials that can perform the same or similar functions as the materials described herein are also intended to be included within the scope of the embodiments of the present invention.

[0015] Figure 1 and Figure 2 Each shows a schematic diagram of a known multi-cell power supply 10, specifically, a cascaded H-bridge converter system that receives three-phase power from an alternating current (AC) source and delivers power to a load 12 (eg, a three-phase AC motor).

[0016] refer to Figure 1 , a multi-cell power supply 10 includes a transformer 14, a power circuit 16, and a controller 18, also referred to herein as a control system. The transformer 14 includes a primary winding that excites nine secondary windings, and the power circuit 16 includes a plurality of printed circuit board (PCB) power cells 26, referred to herein as power cells 26, which are respectively operably coupled to the secondary windings of the transformer 14. Since the power supply 10 includes nine secondary windings, and a power cell 26 is operably coupled to each secondary winding, the power supply 10 includes nine power cells 26. Of course, depending on the type of power supply 10 and / or the type of load 12 coupled to the power supply 10, the power supply 10 may include more or less than nine power cells 26 and / or more or less than nine secondary windings.

[0017] The power cells 26 may be rated for a lower voltage and configured to provide a medium voltage output to the load 12. Each output phase A, B, C of the power circuit 16 is powered by a group of power cells 26 connected in series. The outputs of the power cells 26 are coupled in series in a first phase group 30, a second phase group 32, and a third phase group 34. Each phase output voltage is the sum of the output voltages of the power cells 26 in the respective phase groups 30, 32, and 34. For example, the first phase group includes power cells 26 labeled A1, A2, and A3, where the phase output voltage of output phase A is the sum of the output voltages of power cells A1, A2, and A3. The same applies to output phase B and power cells B1, B2, B3, and output phase C and power cells C1, C2, C3. In this regard, the power circuit 16 uses a power cell 26 rated for a lower voltage to transmit a medium voltage output to the load 12, wherein the power cell includes components rated for a lower voltage standard. Each power cell 26 is coupled (eg, via a fiber optic communication link) to a controller 18 , which may use current feedback and voltage feedback to control operation of the power cell 26 .

[0018] like Figure 2As shown, the multi-unit power supply 10 includes a three-phase AC power supply 20, a power circuit 16, and a controller 18. The three-phase AC power supply 20 includes two diode bridges 22, each of which is connected to the secondary winding of a power converter transformer 24 on the AC voltage side and is electrically connected in series on the direct current (DC) voltage side. The parallel connection of these phase groups provides positive and negative DC voltage buses. The power circuit 16 includes a power cell 28, which is coupled to the DC voltage bus created by the power supply 20. For example, the power cell 28 is rated for a lower voltage and is configured to provide a medium voltage output to the load 12. Although the load 12 can be illustrated as being in the multi-unit power supply 10, the load 12 is not part of the multi-unit power supply 10. Instead, as shown in FIG. Figure 1 As more clearly shown, the load 12 is independent of the multi-unit power supply 10 and is connected thereto.

[0019] Each output phase A, B, C of the power circuit 16 is powered by a series connected group of power cells 28, and the reference output phases are labeled A1-A4, B1-B4, and C1-C4. The power cells 28 are coupled in series in a first phase group 30, a second phase group 32, and a third phase group 34. Each phase output voltage is a reference voltage as previously described. Figure 1 The sum of the output voltages of the power cells 28 in the phase groups 30, 32, and 34 of the power circuit 16. The power circuit 16 uses the power cells 28 rated for lower voltages to deliver the medium voltage output to the load 12, wherein the power cells 28 include components rated for the lower voltage standard. Each power cell 28 is coupled (e.g., via a fiber optic communication link) to the controller 18, which can use current feedback and voltage feedback to control the operation of the power cell 28.

[0020] It should be noted that in Figure 1 and Figure 2 In the embodiment, the number of power cells 26, 28 in each phase group 30, 32, 34 can be between 2 and 12 to provide different medium voltage outputs according to the requirements of the load 12. Figure 1 In the embodiment of FIG. 1 , the number of secondary windings of transformer 14 matches the number of power cells 26. Figure 2 In the embodiment of FIG. 1 , the number of diode bridges and transformer secondary windings may vary from 1 to 6 to allow for harmonic cancellation on the primary side of transformer 24. It will be appreciated by one of ordinary skill in the art that other numbers of units and diode bridges may be used depending on the application and that the configurations shown and described herein are intended to be exemplary in nature.

[0021] Figure 3A schematic diagram of a drive system 300 is shown including a cascaded H-bridge multilevel converter 310 having a seven-level topology, including three phases, each phase having three power cells, and in accordance with one aspect of the present invention, additionally including a control system 400. An example of the cascaded H-bridge multilevel converter 310 is the Perfect Harmony XT manufactured by Siemens Industry, Inc. drive.

[0022] exist Figure 3 In the example of , system 300 is a medium voltage drive, which includes a three-phase power source providing a power input 302 via lines L1, L2 and L3. A multilevel converter 310 is connected to the AC power input 302 and generates a three-phase AC power supply as an output 303 via output phases A, B and C. The AC output 303 can be connected to a load 320, which includes a motor in this example. The motor 320 can be operated by controlling the frequency and / or amplitude of the output voltage generated by the multilevel converter 310.

[0023] Each phase of the multi-level converter 310 includes a respective phase leg formed from a plurality of power cells 312 arranged in a cascaded manner. Figure 1 In the example of FIG. 1 , the same number (i.e., 3) of power cells 312 connected in series each form a phase leg A, a leg B. Each power cell 321 of the phase is connected to the power input 302 via input lines L1, L2, and L3. For example, the power to the input lines L1, L2, and L3 can be provided via a multi-phase winding transformer.

[0024] The three-phase power cells 312 are labeled as cells A1 to A3, cells B1 to B3, and cells C1 to C3, respectively. Each power cell 312 responds to a control signal from the control system 400, which includes, for example, a pulse width modulation (PWM) signal to change the voltage level and / or frequency output to form a multi-level voltage waveform for each phase. The power cell 312 typically includes power semiconductor switching devices, passive components (inductors, capacitors), control circuits, processors, interfaces, and other components for communicating with the control system 400 (i.e., the power cell operates based on signals from the control system 400).

[0025] Each power cell 312 includes a single-phase inverter circuit connected via input lines L1, L2, L3 to an independent direct current (DC) source generated by rectification of the AC power input to each power cell 312. In this example, the rectification is performed by diode rectifiers 313a-f arranged in a bridge rectifier configuration. This example also uses a filtering circuit including, for example, a capacitor 314 for smoothing the output voltage ripple from the rectified DC power.

[0026] The inverter circuit of each cell 312 includes power semiconductor switching devices 315a-d arranged in an H-bridge (also referred to as a full-bridge) configuration. The switching devices 315a-d may include, for example but not limited to, power transistors (e.g., insulated-gate bipolar transistors (IGBTs)). The switching devices 315a, 315b are connected to the cell output line 316a, while the switching devices 315c, 315d are connected to the cell output line 316b. The transistors 315a-d receive a pulse width modulated signal, for example, in the form of a gate input signal 318 controlled by the control system 400 based on pulse width modulation. The control system 400 selects any one of the transistors 315a or 315b to be turned on via the first switch leg 317a, and selects any one of the transistors 315c or 315d to be turned on via the second switch leg 317b, which will allow power to be passed to the load 320 through the line 316a or 316b, respectively. In other words, the controller of the switch pin 317a triggers a switching event so that one of the transistors 315a, 315b is in the on state and the other is in the off state. Similarly, the controller of the switch pin 317b triggers a switching event so that one of the transistors 315c, 315d is in the on state and the other is in the off state. In the illustrated embodiment, the switch pins 317a, 317b of the individual unit 312 are referred to as the switch pin A and the switch pin B of the individual unit 312.

[0027] Although each power cell 312 is included in the medium voltage device drive 300, each power cell 312 can be internally constructed as a low voltage standard. For example, each power cell 312 can have a 600 volt rated voltage. Therefore, the maximum voltage level that can be output by each power cell 312 is about 600VDC. Depending on which transistor is turned on, the output voltage on the unit output line 316a, 316b of each power cell 312 can be polarity or zero. Therefore, each power cell 312 can have three output states: +600VDC, -600VDC or 0VDC. Due to the serial connection between the three power cells 312 in each phase output line (for example, the unit A1, A2, A3 of the output phase A), the maximum output voltage amplitude of about 1800VDC can be generated for the respective phase output lines. Each power cell 312 can operate independently of another. Therefore, at least seven voltage levels per phase can be provided for the motor 320. Approximate values ​​for these line-neutral voltage states include + / -1800 VDC, + / -1200 VDC, + / -600 VDC, and 0 VDC.

[0028] The motor 320 may include any type of AC type motor, for example, synchronous, asynchronous, permanent magnet, and may be rated for low voltage, medium voltage, or high voltage. For example, a medium voltage AC motor (such as those used for industrial process control) may operate in the range of 4.16 kV to 13.8 kV. Larger or smaller voltages may be used. More than one motor 320 may be connected. Other loads may be used in place of the motor 320 or in addition to the motor 320. The motor 320 responds to the voltage applied to the three phases by the multi-level converter, for example, to increase, decrease, or maintain speed or position.

[0029] Figure 4 A schematic diagram showing the architecture of a control system 400 of a drive system according to an exemplary embodiment disclosed herein. The control system 400 will refer to Figure 3 However, it should be noted that other types of drive systems may be used in connection with the control system 400, such as a modular multi-level converter system with an M2C or M2LC subsystem.

[0030] In an example, the drive system 300 including the control system 400 having the SOC 410 may embody a medium voltage variable frequency drive including an output voltage between about 2.3 kV and about 11 kV.

[0031] As mentioned before, the control system of the current drive system divides the control tasks (such as control loop commands and status, power unit control information and external communication interface) into 3 independent components, which require dedicated data buses on the printed circuit board. Figure 4The improved control system 400 is described in detail.

[0032] According to an exemplary embodiment, control system 400 includes a system on chip (SOC) 410 that integrates major control components into a single integrated circuit instead of separate devices. A system on a chip (also known as a chip-level system) is an integrated circuit that integrates all or most components of a computer or other electronic system on a single substrate.

[0033] The SOC 410 includes one or more central processing units (CPUs) 412, 414, and a field programmable gate array (FPGA) 416 that communicates with the one or more central processing units 412, 414. Specifically, the embodiment provides a first central processing unit (CPU1) 412 and a second central processing unit (CPU2) 414, each performing different tasks. However, it should be noted that the first and second central processing units 412, 414 can be combined into a single central processing unit.

[0034] The first central processing unit 412 may be referred to as a “system manager,” wherein the second central processing unit 414 may be referred to as a “controller.” Each central processing unit 412, 414 includes a microprocessor and other circuitry that performs control and processing tasks.

[0035] The first processing unit 412 (system manager) is configured to communicate with an Ethernet interface 420, a file system interface 422, one or more USB interfaces 424, and an analog-to-digital interface 426. The various interfaces may be considered as 'non-driver' interfaces, and the information provided by the interfaces may be considered as 'non-driver' information or command and status information.

[0036] The second processing unit 414 (controller) is configured to receive the power unit control information and generate operating commands for the power unit 312. The second processing unit 414 controls the operation of the power unit 312 together with the FPGA 416, and thus provides functionality to control the load (e.g., the motor 320 of the drive system 300). The second processing unit 414 can be operably coupled to a memory 430, such as a non-volatile random access memory (NVRAM), a keyboard 432 (e.g., for inputting parameters of the drive system), and a MODBUS I / O (input / output) module 434. Modbus is a serial communication protocol used to connect industrial electronic devices.

[0037] The first and second central processing units 412, 414 communicate with each other via an interprocess communication link 436, and the processing units 412, 414 can be configured to communicate with a memory 438, which can be a random access memory. The components described above regarding the first and second central processing units 412, 414 and the FPGA 416 are all included on the SOC 410.

[0038] According to a further embodiment, the SOC includes a dedicated data bus 440, labeled as a parallel interface, which is used for communication purposes between the central processing units 412, 414 and the FPGA 416.

[0039] FPGA 416 is configured to communicate with: one or more analog-to-digital converters (ADCs) 442, a power cell bypass system 444, a plurality of power cells 446 (eg, Figure 3 power unit 312), encoder 448, one or more input / output interfaces (key I / O) 450 and an internal network (drive / actuator) 452.

[0040] One or more analog-to-digital converters 442 may be used to convert multiple analog signals (e.g., voltage amplitude, current amplitude, unit temperature, etc.) into digital signals. A power unit bypass system 444 may be used to bypass one or more failed power units of the drive system. Each power unit 446 sends operating information to the FPGA 416 and receives operational commands via the FPGA 416. An encoder 448 is associated with the motor 320 of the system 300 and converts the rotational motion or position of the motor into a code of electronic pulses and transmits the electronic pulses to the FPGA 416. One or more input / output interfaces 450 may be embodied as, for example, switches, potentiometers, etc., which allow the operator of the drive system to provide a certain parameter. An internal network 452 may be used to facilitate the interconnection of multiple drive systems. The information provided by the devices 442, 444, 446, 448, 450, 452 may be considered as 'drive' information, which includes specific information related to power unit control.

[0041] In operation, the FPGA 416 performs logic operations on the received drive information and then passes the resulting information to the second central processing unit (controller) 414. The second processing unit 414 processes the resulting information and, based on the processed information, generates operational commands for the FPGA 416 to distribute to the appropriate interfaces, such as the power unit 446 and the encoder 448. Basically, the FPGA 416 handles housekeeping and only communications to the appropriate interfaces.

[0042] SOC 410 may include additional components. These components may include, for example: a real-time clock 472; a read-only memory (ROM) 474; one or more sensors 474, 476 (e.g., a temperature sensor, a humidity sensor, or a pressure sensor); and a power management bus (PMBus) 480. Components 472, 474, 476, 478, 480 communicate via an integrated circuit bus (I2C).

[0043] In another exemplary embodiment, Figure 4 As shown, the control system 400 also includes a communication board 460 for external communication. The communication board 460 may be outside the SOC 410, wherein the SOC and the communication board 460 communicate via a data bus (BUS) 462. The communication board 460 may include an additional field programmable gate array 464 configured to perform external communication 466 and communicate with devices external to the SOC (e.g., an interface 468 for connecting a motor module, a terminal module, or a sensor module to a drive system).

[0044] However, by utilizing SOC 410 and FPGA 416 with sufficiently large logic density, external communication functions (communication board 460) may also be included in SOC 410. In this case, FPGA 416 is also configured to communicate with devices or systems external to SOC 410, such as an external network.

[0045] Furthermore, the control system 400 also stores and executes specific instructions to implement pulse width modulation (PWM) control. By pulse width modulating the voltage reference of each phase, the control system 400 (specifically the second processing unit 414) controls each power unit 446 ( Figure 3 The processing unit 414 may control the voltage reference of the power cell 312 and thus control the amplitude and frequency of the voltage output between the output lines 316a, 316b of each power cell 312. A local control circuit or control board in the respective power cell 312 may receive the voltage reference and generate a gating pulse for the power switching device using appropriate vector control and pulse width modulation. Alternatively, the processing unit 414 may output a gating pulse for the cell 312 based on the reference voltage.

[0046] Figure 5 1 shows perspective views of different control system devices according to exemplary embodiments disclosed herein. Specifically, Figure 5An improved control system 400 including a SOC 410 is shown compared to an existing control system 500. The control system 500 includes, for example, a heat sink 510, which is necessary for cooling purposes and transfers heat generated primarily by the internal central processing unit. The control system 400 does not require such a heat sink because it contains the SOC 410 including the central processing unit and many other components.

[0047] The SOC 410 including all its components is etched on a silicon wafer. By utilizing the SOC, a single device is used, which contains one or more central processing units 412, 414 and FPGA logic 416 and a dedicated data bus. Therefore, the physical space used for the control system 400 is reduced. Instead of three or four independent devices, only one device, the SOC 410, is required. The reduced size provides additional space to add electrical features to the existing form factor of the control system 400. Due to the data bus 440 inside the SOC 410, there is no need to carefully design the PCB data bus wiring interconnection. Further, the reduced number of components increases the robustness of the control system to failures.

Claims

1. A drive system (300), comprising: A plurality of power cells (312) providing power to one or more output phases (A, B, C), each power cell (312) comprising a plurality of switching devices (315a-d) including semiconductor switches, and a control system (400) that communicates with the plurality of power units (312) and controls operation of the plurality of power units (312), The control system (400) includes a system on chip (410), which includes: one or more central processing units (412, 414), and a field programmable gate array (416) in communication with the one or more central processing units (412, 414), The system on chip (410) includes first and second central processing units (412, 414) communicating with each other. The second central processing unit (414) is configured to receive power unit control information and generate a first operation command, and The first central processing unit (412) is configured to receive commands and status information, and generate at least one instruction based on the commands and status information, and the at least one instruction is configured to instruct the second central processing unit (414) to generate a second operation command.

2. The drive system (300) according to claim 1, in, The system on chip (410) also includes a dedicated data bus (440) between the one or more central processing units (412, 414) and the field programmable gate array (416).

3. The drive system (300) according to claim 1, in, The field programmable gate array (416) is in communication with the plurality of power units (312) and is configured to receiving the power unit control information from each of the plurality of power units (312), sending the power unit control information to the second central processing unit (414), and The first and second operation commands are received from the second central processing unit (414) for distribution to the plurality of power units (312).

4. The drive system (300) according to claim 1, in, The field programmable gate array (416) is configured to distribute the first and / or second operation commands to at least one of an analog-to-digital converter (442), a power unit bypass system (444), a power unit (312, 446), an encoder (448), an input-output interface (450), and an internal network (452).

5. The drive system (300) according to claim 1, in, The field programmable gate array (416) is also configured to communicate with devices external to the system on chip (410).

6. The drive system (300) according to claim 1, in, One of the central processing units (412, 414) is configured to communicate with at least one of an Ethernet interface (420), a file system interface (422), a universal serial bus interface (424), and an analog-to-digital converter interface (426).

7. The drive system (300) according to claim 1, in, One of the central processing units (412, 414) is operably coupled to a memory (430), a keyboard (432), and a MODBUS input / output module (434).

8. The drive system (300) according to claim 1, in, The system on chip (410) also includes a memory (438), and the first and second central processing units (412, 414) are configured to communicate with the memory (438).

9. The drive system (300) according to claim 1, in, The control system (400) further includes a communication board (460) external to the system-on-chip (410), and the system-on-chip (410) and the communication board (460) communicate via another data bus (462).

10. The drive system (300) according to claim 9, in, The communication board (460) includes an additional field programmable gate array (464) configured to communicate with devices external to the system on chip (410).

11. The drive system (300) according to claim 1, in, The system on chip (410) is etched on a silicon wafer.

12. The drive system (300) according to claim 1, This is embodied as a medium voltage variable frequency drive including output voltages between about 2.3 kV and about 11 kV.

13. The drive system (300) according to claim 1, Also included is a cascaded H-bridge converter system (310).

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