A neuron circuit without power supply using a pnpn diode

Abstract

The present invention relates to a power-free neuron circuit that utilizes a p‑n‑p‑n diode for the purpose of small area and low power consumption. According to one embodiment, the neuron circuit generates an electric potential by charging a current input from a synapse through a capacitor. If the generated electric potential is greater than a threshold value, a pulse voltage corresponding to the generated electric potential can be generated and output by a p‑n‑p‑n diode connected to the capacitor.

Description

Technical Field

[0001] The present invention relates to a neuron simulation device and a power-free neuron circuit using a pnpn diode, and more specifically, to a low-power neuron circuit that uses a metal oxide semiconductor field effect transistor, a capacitor, and a silicon-based pnpn diode nanostructure having a steep switching slope due to a latch-up effect, and is driven only by a synaptic current from the input of the circuit without applying an external bias. Background Art

[0002] Neuromorphic technology is a technology used to mimic the human neural structure into electronic devices and circuits. Previous von Neumann-based computers showed fast working speed in sequential mathematical calculations, but were greatly limited in terms of speed and power consumption when calculating multiple input values ​​and output values ​​at the same time. These limitations are due to the structural characteristics that the memory and processor are separated and connected through a bus. When parallel calculations are performed, the "von Neumann bottleneck" phenomenon occurs, which delays the processing speed.

[0003] Among various neuromorphic technologies, spiking neural network technology can emulate more advanced thinking abilities by imitating the function of the brain's nervous system and brain waves. In order to emulate this spiking neural network, research is being conducted around the world to embody nerves and synapses as electronic devices, especially to embody neurons that generate electrical pulses after being stimulated at the front end through multiple synapses to transmit excitement to the back end synapses.

[0004] The neuron circuit of the prior art is composed of a comparator that integrates the signals generated at the synapse at the front end, generates a pulse if a signal above the threshold is applied, and multiple additional circuits that prevent signal delays and ensure stability. Therefore, the use of multiple transistors will increase the overall area of ​​the neuron circuit and will also face a big problem in power consumption. Due to this structural limitation, there is a problem that the structure of the neural simulation system becomes complicated and the precision will also face limitations. Therefore, research is conducted on neuron simulation devices and circuits with various devices and structures such as variable resistive random-access memory (ReRAM), phase change memory (PCM), and conductive bridge memory (CBRAM). However, this device cannot be applied to the previous complementary metal oxide semiconductor process, so the uniformity and stability of the device will be reduced, and due to the complex process, it is difficult to apply it to real life. Therefore, it is necessary to develop a new neuron circuit based on the complementary metal oxide semiconductor process.

[0005] Prior art literature

[0006] Patent Literature

[0007] Korean Patent Publication No. 2017-0138047 "Neuron Simulation Device and Circuit"

[0008] Korean Patent Publication No. 2018-0127153 "Nervous system simulation integrated circuit combining neuron simulation circuit and synaptic device array and its manufacturing method"

[0009] Non-patent literature

[0010] M. Vardhana, N. Arunkumar, S. Lasrado, E. Abdulhay, and, G. Ramirez. "Convolutional neural network for bio-medical image segmentation with hardwareacceleration." Cognitive Systems, vol.50, pp.10-14, Aug.2018, doi: 10.1016 / j.cogsys.2018.03.005.

[0011] G. Cauwenberghs. "An analog VLSI recurrent neural network learning acontinuous-time trajectory." IEEE Transactions on Neural Networks, vol.7, no.2, pp.346-361, Mar.1996, doi: 10.1109 / 72.485671. Summary of the invention

[0012] An object of the present invention is to develop a simple neuron-mimicking device that can achieve high integration with a smaller number of electrodes than conventional complementary metal oxide semiconductor neuron-mimicking devices.

[0013] An object of the present invention is to develop a circuit and a device that operate based on lower standby power consumption than conventional complementary metal oxide semiconductor neuron circuits.

[0014] An object of the present invention is to develop a neuron-simulating device and circuit that can use conventional complementary metal oxide semiconductor processes.

[0015] An object of the present invention is to develop a circuit that has a smaller number of transistors and is highly integrated compared to conventional complementary metal oxide semiconductor neuron circuits.

[0016] An object of the present invention is to develop a low-power neuron circuit that is driven only by a synaptic current from an input of the circuit without applying an external bias, compared to a conventional complementary metal oxide semiconductor neuron circuit that requires application of an external bias.

[0017] The object of the present invention is to develop a circuit that realizes excitation and resetting within a neuron circuit without an additional current and voltage signal controller.

[0018] An object of the present invention is to develop a neuron simulation device and circuit that can be used in a spiking neural network by taking into account changes in synaptic weight values ​​of synaptic output currents flowing to an input portion of a neuron circuit.

[0019] According to one embodiment, the neuron circuit can generate a potential by charging the current input from the synapse through a capacitor. If the generated potential is greater than a threshold, a pulse voltage corresponding to the generated potential is generated and output by a pnpn diode connected to the capacitor.

[0020] According to an embodiment of the neuron circuit, at least one transistor connected to the pnpn diode may be used to reset the generated pulse voltage.

[0021] In the pnpn diode of one embodiment, the anode terminal may be connected in parallel with the capacitor, and the cathode terminal may be connected with at least one of the transistors.

[0022] In at least one of the above-mentioned transistors in one embodiment, in the first transistor, the gate terminal can be connected to the gate line, the drain terminal is connected in series with the cathode terminal of the above-mentioned pnpn diode, the gate terminal and the drain terminal of the second transistor are simultaneously connected to the drain terminal of the above-mentioned first transistor and the source terminal of the above-mentioned pnpn diode, and in the third transistor, the drain terminal is simultaneously connected to the above-mentioned capacitor and the anode terminal of the above-mentioned pnpn diode, and the gate terminal of the above-mentioned third transistor is simultaneously connected to the gate terminal and the drain terminal of the above-mentioned second transistor.

[0023] In one embodiment, the pulse voltage may be determined by voltage division of the first transistor and the pnpn diode.

[0024] The pnpn diode of one embodiment may generate a pulse voltage corresponding to the generated potential by utilizing an avalanche breakdown phenomenon generated inside the diode device by an anode voltage.

[0025] In one embodiment, the pulse voltage may change frequency according to a change in the duration of the input pulse and a size of the input pulse.

[0026] The pnpn diode of one embodiment has a plurality of potential barriers, and the plurality of potential barriers are used to block injection of charge carriers before the anode voltage is applied.

[0027] In a neuron circuit of one embodiment, when the anode voltage increases to a set reference voltage, the pnpn diode can reduce the heights of the multiple potential barriers in the valence band through the anode voltage, and inject holes into the potential wells where the heights of the multiple potential barriers are reduced.

[0028] In the above-mentioned pnpn diode of one embodiment, the above-mentioned pulse voltage can be reduced by a voltage-induced reset current occurring at the gate terminal of the above-mentioned second transistor, and the pulse voltage can be reset by releasing the charge charged to the capacitor through a voltage-induced discharge current occurring at the gate terminal of the above-mentioned third transistor.

[0029] In a neuron circuit of one embodiment, as the current pulse from the synapse at the front end is integrated in the capacitor, the anode voltage will increase, and as the drain voltage increases, the potential barrier formed by the reverse bias level formed inside the pnpn diode will increase. As the potential barrier increases, if the drain voltage increases to above the threshold voltage for avalanche breakdown, a latch-up effect will occur through the impact ionization mechanism of the pnpn diode.

[0030] In the neuron circuit of one embodiment, due to the current flowing due to the latch effect, the voltage at the output terminal V spike Electrical excitation occurs.

[0031] In a neuron circuit of one embodiment, if at the output terminal V spike When a pulse voltage is generated, the gate voltages of the third transistor and the second transistor are increased, and the third transistor and the second transistor are both turned on and release the charge charged in the capacitor and V spike voltage to perform reset operation.

[0032] The neuron circuit of one embodiment can generate an electric potential by charging the current input from the synapse through a capacitor. If the generated electric potential is greater than a threshold value, a pnpn diode connected to the capacitor is used to generate and output a pulse voltage corresponding to the generated electric potential, and at least one transistor connected to the pnpn diode is used to reset the generated pulse current.

[0033] According to one embodiment, the present invention has the effect of realizing high integration and low power neuron circuit operation using a device with a simple structure that operates with a smaller number of electrodes than conventional neuron simulation devices.

[0034] According to an embodiment, the present invention has the effect of realizing a low-power neuron circuit using a device having a steep switching slope value due to a latch effect, compared with a conventional complementary metal oxide semiconductor neuron analog device.

[0035] According to one embodiment, the present invention has the effect of minimizing the number of transistors compared to conventional neuron circuits, thereby achieving high integration and low power circuit operation.

[0036] According to one embodiment, the present invention has the effect of achieving a self-driven low-power neuron circuit operation without applying an external bias voltage, compared to conventional neuron circuits.

[0037] According to one embodiment, the present invention has the effect of being able to reflect a change in neuron firing frequency characteristics based on a change in the magnitude and application duration of a synaptic current input to a neuron circuit.

[0038] According to one embodiment, the present invention has the effect of being able to apply a neuron circuit that can use a complementary metal oxide semiconductor process to a spiking neural network. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1a and Figure 1b A diagram illustrating a structure of a pnpn diode formed by connecting a diode structure and an access electronic device in series according to an embodiment.

[0040] Figure 2a to Figure 2f A block diagram of a neuron circuit according to an embodiment is shown.

[0041] Figure 3a Energy band diagram illustrating the anode voltage of a pnpn diode.

[0042] Figure 3b A block diagram illustrating the anode voltage-current characteristics of a pnpn diode.

[0043] Figure 4a and Figure 4b A diagram illustrating the pulse and reset mechanism of a neuron circuit including various energy band diagrams of a pnpn diode.

[0044] Figure 4c A diagram illustrating an embodiment of a neuron circuit operating in current mode.

[0045] Figure 4d A timing diagram illustrating a simulation of a neuron circuit according to an embodiment.

[0046] Figure 5a 1 is a timing chart showing changes in output characteristics based on changes in the size of synaptic current pulses applied to a neuron circuit.

[0047] Figure 5b 1 is a timing diagram showing changes in output characteristics based on temporal changes in synaptic current pulses applied to a neuron circuit.

[0048] Figure 5c is a block diagram showing changes in firing frequency based on changes in the size and timing of synaptic current pulses applied to a neuronal circuit.

[0049] Description of Reference Numerals

[0050] 110: Diode structure 120: Access electronic devices DETAILED DESCRIPTION

[0051] For the embodiments based on the concepts of the present invention disclosed in this specification, specific structural or functional descriptions are only used to illustrate the embodiments of the concepts of the present invention. The embodiments of the concepts of the present invention can be implemented in various forms and are not limited to the embodiments described in this specification.

[0052] The embodiments of the concept of the present invention may have various changes and various forms, so the embodiments are illustrated in the drawings and described in detail in this specification. However, this does not limit the embodiments of the concept of the present invention to a specific form, but includes the changes, equivalent technical solutions or alternative technical solutions included in the scope of protection of the present invention and the invention claims.

[0053] The terms "first" or "second" can only be used to describe various structural elements, and the above structural elements are not limited to the above terms. The above terms are only used to distinguish two structural elements. For example, without exceeding the scope of the invention claimed in the concept of the present invention, the first structural element can be named as the second structural element, and similarly, the second structural element can also be named as the first structural element.

[0054] When a structural element is 'connected' or 'coupled' to other structural elements, it can be directly connected or coupled to other structural elements, or other structural elements can exist in between. On the contrary, when a structural element is 'directly connected' or 'coupled' to other structural elements, it can be understood that there are no other structural elements in between. Expressions that describe the relationship between structural elements, such as 'between' and 'directly between' or 'directly adjacent', etc., also need to be interpreted in the same way.

[0055] The terms used in this specification are only used to describe specific embodiments and are not used to limit the present invention. Unless otherwise clearly indicated in the context, the singular includes the plural. In this specification, the terms "including" or "having" are used to specify the existence of the described features, numbers, steps, actions, structural elements, components or combinations thereof, and do not preclude the existence or additional possibility of one or more other features, numbers, steps, actions, structural elements, components or combinations thereof.

[0056] Unless otherwise expressly defined, all terms used herein, including technical or scientific terms, have the same meaning as those generally associated with those of ordinary skill in the art to which the present invention belongs. Terms defined in commonly used dictionaries have the same meaning as they have in the context of the relevant technology and cannot be interpreted in an abnormal or excessive manner unless expressly defined in this specification.

[0057] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. However, the scope of protection of the invention is not limited to these embodiments. The same reference numerals disclosed in the various drawings represent the same components.

[0058] Figure 1a FIG. 4 is a diagram for explaining the structure of a pnpn diode nanostructure having two electrodes as a neuron simulation device according to an embodiment of the present invention.

[0059] and, Figure 1b FIG. 4 is a diagram for explaining the structure of a metal oxide semiconductor field effect transistor constituting a neuron circuit according to an embodiment.

[0060] Reference Figure 1a , a pnpn diode consists of an anode, a cathode and two terminals.

[0061] The neuron simulation device only includes a pnpn diode nanostructure, an anode electrode and a cathode electrode. The anode region is in a p-doped state, and the cathode region is in an n-doped state.

[0062] Reference Figure 1a The anode region of the diode structure 110 is connected to the bit line BL, referring to Figure 1b The source region of the access electronic device 120 is connected to the source line SL. + The doped region and the drain region of the access electronic device 120 may be connected in series to form a device.

[0063] In normal state, it does not conduct electricity, but when a signal is applied to the bit line BL, current will flow from the anode to the cathode. And, as long as the current is applied, it will not be interrupted until the current is turned off.

[0064] Figure 2a A block diagram of an unpowered neuron circuit of one embodiment is shown.

[0065] In the present invention, a power-free neuron circuit is provided which performs integrate-and-fire using only four semiconductor devices including a pnpn diode and a metal oxide semiconductor field effect transistor.

[0066] In particular, pnpn diodes exhibit a latching effect, through which unpowered neuron circuits can provide input pulse integration, spike generation, and reset operations with minimal standby power consumption.

[0067] In particular, the unpowered neuron circuit can automatically perform integration and excitation work within the circuit without an artificial signal controller, and can operate only through synaptic current from the input without additional external devices.

[0068] Figure 2a An unpowered neuron circuit is shown having a basic square neuron block composed of a plurality of synaptic devices 210, 220 and a neuron circuit embodying a hardware-based spiking neural network.

[0069] The neuron circuit 200 without power supply of one embodiment may include a pnpn diode, at least one transistor and a capacitor C for integrated operation. mem .

[0070] As an example, at least one transistor may use three metal oxide semiconductor field effect transistors M1 to M3 . Figure 2a In the embodiment, for the convenience of explanation, three metal oxide semiconductor field effect transistors can be used as at least one transistor, and can also be designed in various forms.

[0071] The examples designed in various forms are as follows Figure 2b to Figure 2f Explain more specifically.

[0072] First, refer to Figure 2a The presynapse 210 receives synaptic output from other connected neuronal cells and converts the response synaptic weight value into current input.

[0073] The synaptic current input may generate a potential by charging a capacitor of the unpowered neuron circuit 200 and thus may be integrated.

[0074] Furthermore, if the charged potential reaches a threshold value, the unpowered neuron circuit 200 of one embodiment may generate an output pulse 201 .

[0075] like Figure 2a As shown, the output pulse 201 of the unpowered neuron circuit 200 can be delivered to the post-synapse 220.

[0076] A pnpn diode for the unpowered neuron circuit 200 may replace the MOSFET.

[0077] like Figure 2aAs shown, in a neuron circuit 200 based on complementary metal oxide semiconductors without power supply, a pnpn diode nanostructure as a neuron simulation device is connected to three metal oxide semiconductor field effect transistors and a battery. In this case, the anode terminal of the pnpn diode nanostructure is connected in parallel with the drain of the metal oxide semiconductor field effect transistor and the battery to receive an input signal from the presynapse. Moreover, the gate of the metal oxide semiconductor field effect transistor M1 connected in series with the cathode terminal of the pnpn diode nanostructure is connected in an open state without applying a bias. The battery connected in parallel with the pnpn diode nanostructure integrates the current signal from the presynapse. If a pulse occurs, the current is made to flow to the metal oxide semiconductor field effect transistor (M3) connected in parallel with the battery. Through the above current, the charge stored in the battery is released. At the same time, the current is made to flow to the metal oxide semiconductor field effect transistor M2 connected in series with the cathode terminal of the pnpn diode to execute the pulse voltage signal V spike The reset action drops to 0V. In addition, the V spike Therefore, the neuron circuit based on the complementary metal oxide semiconductor process performs the integration and firing action only by the current signal occurring before the synapse without additional external bias, and performs the integration and firing action by internal self-drive without the help of external circuit.

[0078] like Figure 2a As shown, in the operation of the neuron circuit 200, as the current pulse generated before the synapse is integrated in the capacitor, the anode voltage V of the pnpn diode nanostructure is mem will increase. In this case, V mem will increase to Figure 2a When the voltage of the pnpn diode reaches the threshold voltage, the neuron circuit 200 performs the excitation operation. If the excitation is performed in the neuron circuit 200, the V mem The voltage returns to the reset operation again at 0 V. The electrical integration and firing operation in this neuron circuit 200 mimics the integration and firing operation of biological neurons from the time integration to the refractory period.

[0079] The operation of each device of the neuron circuit 200 will be performed by Figure 4a and Figure 4b Explain in more detail.

[0080] Figure 2a Using a capacitor C mem, 1 diode (pnpn diode) and 3 transistors (metal oxide semiconductor field effect transistors) are used to implement the neuron circuit 200.

[0081] In the process of implementing the neuron simulation circuit, a capacitor C mem A potential is necessarily required for one diode (pnpn diode), and at least one of the three transistors (metal oxide semiconductor field effect transistor) can be selectively replaced by another device.

[0082] the following, Figure 2b to Figure 2f The diagrams illustrate various embodiments of neuron circuits to which the present invention may be applied.

[0083] first, Figure 2b In place of Figure 2a The neuron circuit 200 uses only one capacitor C mem , a diode (pnpn diode) and a transistor M1 to embody the neuron circuit 202.

[0084] The neuron circuit 202 can input the synaptic current to the capacitor C mem Charging is performed and the potential is integrated.

[0085] And, if the capacitor C mem When the charged potential reaches the threshold, an output pulse can be generated through the output end of a diode (pnpn diode).

[0086] Figure 2c In place of Figure 2a The neuron circuit 200 can use a capacitor C mem , a diode (pnpn diode) and two transistors M1 and M2 to embody the neuron circuit 203.

[0087] The neuron circuit 203 can input the synaptic current to the capacitor C mem Charging is performed and the potential is integrated.

[0088] And, if the capacitor C mem When the charged potential reaches a threshold value, the neuron circuit 203 can generate an output pulse through the output end of a diode (pnpn diode).

[0089] The anode terminal of the pnpn diode nanostructure is connected in parallel with the drain of the metal oxide semiconductor field effect transistor and the accumulator to receive input signals from the presynaptic. Moreover, the gate of the metal oxide semiconductor field effect transistor M2 connected in series with the cathode terminal of the pnpn diode nanostructure is connected in an open state without applying a bias. The accumulator connected in parallel with the pnpn diode nanostructure integrates the current signal from the presynaptic. If a pulse occurs, the current flows to the metal oxide semiconductor field effect transistor M1 connected in parallel with the accumulator. Through the above circuit, the charge stored in the accumulator is released, and the pulse voltage signal V is executed. spike The reset operation is reduced to 0V. In addition, the V spike Therefore, the neuron circuit 203 based on the complementary metal oxide semiconductor process performs integration and excitation work only through the current signal occurring before the synapse without additional external bias, and performs integration and excitation work by self-driving inside the circuit without the help of external circuit.

[0090] Figure 2d In place of Figure 2a The neuron circuit 200 uses a capacitor C mem The neuron circuit 204 is implemented by a diode (pnpn diode) and two transistors M1 and M2.

[0091] The anode terminal of the pnpn diode nanostructure is connected in parallel with the drain terminal of the metal oxide semiconductor field effect transistor and the storage device to receive input signals from the presynaptic. The storage device connected in parallel with the pnpn diode nanostructure integrates the current signal from the presynaptic. If a pulse occurs, the current flows to the metal oxide semiconductor field effect transistor M1 connected in parallel with the storage device. Through the above current, the charge stored in the storage device is released. At the same time, the current flows to the metal oxide semiconductor field effect transistor M2 connected in series with the cathode terminal of the pnpn diode to execute the pulse voltage signal V spike The reset operation is reduced to 0V. In addition, the V spike to the postsynaptic input.

[0092] Figure 2e By will be Figure 2c The metal oxide semiconductor field effect transistor M2 in the embodiment is replaced by a resistor R1 to embody the neuron circuit 205, Figure 2f By Figure 2c The MOSFET M2 in the embodiment of FIG. 1 is replaced by a variable resistor VR1 to embody an embodiment of the neuron circuit 206 .

[0093] Figure 3aEnergy band diagram 310 illustrating the anode voltage of a pnpn diode.

[0094] have Figure 1a The pnpn diode of the structure forms a reverse bias level inside the device, and thus, as shown in the energy band diagram 310, the size of the internal barrier at 5.9V will increase. As a result, the pnpn diode exhibits neuron simulation device characteristics based on the latch effect. Figure 3b As shown in the figure, the neuron-simulating device latches up at a specified voltage as the anode voltage increases. That is, the pnpn diode can operate by a different mechanism from the previous 3-terminal FBFET device.

[0095] Figure 3b FIG3 is a diagram illustrating a current characteristic diagram 320 of an anode voltage of a pnpn diode. As shown in the current characteristic diagram 320, the pnpn diode nanostructure exhibits a latching effect in which the current rises sharply vertically when the device drain voltage is about 2.35 V. The low leakage current based on the latching effect characteristic of the pnpn diode as such a neuron simulation device is used to embody an excitation and integrated neuron circuit with extremely low standby power consumption.

[0096] In the MOSFET neuron circuit, V mem The gate voltage is provided to the transistor, thereby operating as a trigger threshold for turning on a channel associated with the corresponding transistor, and has a magnitude of 2.35V.

[0097] However, at V less than 2.35V mem In the case of threshold swing (SS), it is possible that V spike . Because it is greater than 60mV / dec, it is possible that V spike The problem of time width greater than 20μs.

[0098] Furthermore, for one integrated and activated operation, the MOSFET neuron circuit requires 1.59 mW of power consumption (or 7.62 × 10 -11 J energy consumption).

[0099] When compared to the above-described MOSFET neuron circuit, the unpowered neuron circuit 200 may consume less energy for an integration and firing operation.

[0100] The power consumption, energy consumption and energy efficiency are 0.85mW, 1.72×10 -12j and 99.5%, the excellent energy efficiency of the neuron circuit 200 without power supply can be presented at V spike The latching effect of the anode current and the high ratio of the anode current to the off-current of the pnpn diode are responsible for reducing V spike Therefore, the neuron circuit 200 without power supply using the pnpn diode is superior to the neuron circuit composed of only metal oxide semiconductor field effect transistors in terms of structural simplicity and energy efficiency.

[0101] The current and voltage characteristic diagrams of the pnpn diode during the integration and excitation operation in the neuron circuit 200 without power supply are presented in correspondence with the integration and excitation operation of an actual biological neuron.

[0102] The neuron circuit of the present invention can use the characteristics of the pnpn diode as such a neuron-mimicking device to perform low-power integration and excitation functions.

[0103] In the neuron circuit of the present invention, as the current pulse from the synapse at the front end is integrated on the capacitor, the drain voltage V of the pnpn diode mem The voltage will increase.

[0104] Thus, the potential barrier formed by the reverse bias voltage level formed inside the pnpn diode gradually increases.

[0105] And, as the potential barrier increases, if V mem When the voltage increases to above the threshold voltage for avalanche breakdown, latch-up occurs through the mechanism of the pnpn diode and a rapid current flow occurs.

[0106] In this case, with the voltage division of the pnpn diode and the first transistor, at the output terminal V spike Electrical excitation may occur.

[0107] On the other hand, if the output terminal V spike If a pulse voltage occurs in the circuit, the gate voltages of M3 and M2 are increased, and both M3 and M2 are turned on and release the charge V that charges the capacitors. spike voltage, thereby performing a reset operation.

[0108] Figure 4a To illustrate the V mem FIG410 is an energy band diagram of the pulse mechanism of the neuron circuit.

[0109] Figure 4a and Figure 4bThe pulse and reset mechanisms of the neuron circuit 410 are shown including various energy band diagrams of a pnpn diode.

[0110] The neuron circuit 410 can charge the capacitor 411 by the current input from the synapse and generate a potential. If the generated potential is greater than a threshold value, the neuron circuit 410 can generate and output a pulse voltage corresponding to the generated potential using a pnpn diode 412 connected to the capacitor 411. The neuron circuit 410 can reset the generated pulse voltage using a plurality of transistors 413, 414, and 415 connected to the pnpn diode.

[0111] In the pnpn diode 412 , an anode terminal may be connected in parallel with the capacitor 411 , and a cathode terminal may be connected to three transistors 413 , 414 , and 415 .

[0112] Observe the connection relationship between the multiple transistors 413, 414, and 415. First, in the first transistor M1, 413, the gate terminal can be connected to the gate line V GL The drain terminal may be connected in series with the source terminal of the pnpn diode 412 .

[0113] Furthermore, the gate terminal and the drain terminal of the second transistor M2 , 414 may be connected to the drain terminal of the first transistor M1 , 413 and the cathode terminal of the pnpn diode 412 at the same time.

[0114] Furthermore, in the third transistor M3 , 415 , the drain terminal can be connected to the anode terminal of the capacitor 411 and the pnpn diode 412 at the same time, and the gate terminal of the third transistor M3 , 415 can be connected to the gate terminal and the drain terminal of the second transistor M2 , 414 at the same time.

[0115] On the other hand, the threshold of the anode terminal of the pnpn diode 412 can be defined as V mem .

[0116] The output terminal of the pnpn diode 412 and the gate line V of the first transistor GL The voltage can determine the output voltage V spike Appropriate threshold and pulse voltage.

[0117] Neuronal circuit properties such as the threshold used to trigger this voltage, pulse frequency, etc. can be varied.

[0118] If the output terminal of the pnpn diode 412 and the gate line V GL Apply a specified voltage (e.g., V GL=450mV), the integration and excitation work is based on the synaptic current input I synaptic V mem The increase is reflected.

[0119] If the current input pulse I synaptic Applicable to neuron circuit 410, the sum of the input currents in capacitor 411 increases V mem The potential is integrated.

[0120] Therefore, whenever a current input pulse I is applied synaptic ,like Figure 4a As shown in the reference numeral 416, V mem Will gradually increase.

[0121] If V mem is greater than the threshold, then V spike The pulse voltage can be determined by the voltage division of the pnpn diode 412 and the first transistors M1 and 413.

[0122] Figure 4b For the mem An energy band diagram illustrating the reset operation of a neuronal circuit.

[0123] Figure 4b The neuron circuit 420 operates by resetting to reduce V mem , thereby, the potential barrier of the pnpn diode 422 is regenerated.

[0124] Afterwards, if V spike Increases in a short time, the gate voltage of the second transistor M2, 424 can sense the reset current I Reset And, according to the reset current I Res眦 , V spike On the other hand, the gate voltage of the third transistor M3, 425 connected to the second transistor M2, 424 will also decrease. As the gate voltage of the third transistor M3, 425 decreases, the current used for the discharge of the capacitor 421 can be sensed, and as a result, the V mem Can be reduced.

[0125] Thus, as shown in the energy band diagram 426, the V of the charged pnpn diode mem It gradually decreases along with the discharge.

[0126] After the reset operation, whenever the synaptic input current I synaptic The signal flows through the neuron circuit 420, and a repetitive process of integration and excitation occurs.

[0127] Figure 4c A diagram illustrating an embodiment of a neuron circuit operating in current mode.

[0128] The neuron circuit 430 can charge the capacitor 431 with the current input from the synapse and generate a potential. And, if the generated potential is greater than the threshold, the neuron circuit 430 can generate a pulse current corresponding to the generated potential using the pnpn diode 432 connected to the capacitor 431 to output I OUT Furthermore, the neuron circuit 430 may reset the generated pulse current using a plurality of transistors 433, 434, and 435 connected to a pnpn diode.

[0129] In the pnpn diode 432 , an anode terminal may be connected in parallel with the capacitor 431 , and a cathode terminal may be connected to three transistors 433 , 434 , and 435 .

[0130] Observe the connection relationship between the multiple transistors 433, 434, and 435. First, in the first transistor M1, 433, the gate terminal can be connected to the gate line V GL The drain terminal may be connected in series with the cathode terminal of the pnpn diode 432 .

[0131] Furthermore, the gate terminal and the drain terminal of the second transistor M2 , 434 may be connected to the drain terminal of the first transistor M1 , 433 and the cathode terminal of the pnpn diode 432 at the same time.

[0132] Furthermore, in the third transistor M3 , 435 , the drain terminal can be connected to the capacitor 411 and the anode terminal of the pnpn diode 432 at the same time, and the gate terminal of the third transistor M3 , 435 can be connected to the gate terminal and the drain terminal of the second transistor M2 , 434 at the same time.

[0133] Figure 4d FIG. 4 is a diagram illustrating a simulated timing diagram 440 of a neuron circuit according to an embodiment.

[0134] In order to integrate and excite the neuron circuit, a series of initialization operations may be required in the pnpn diode. After the initialization of the neuron circuit, the input current pulse I with a width of 0.8μs and 9.5μA synaptic The neuron circuit is applied with a period of 10 μs for 250 μs. Whenever an input pulse 411 is applied, V mem 442 will increase by 0.3V. By inputting pulse 411 No. 8, V mem 442 may be greater than the threshold.

[0135] If Vmem442 is greater than the threshold, an output pulse V of 0.0V to 1.1V is generated. spike .

[0136] 9.5μA each I synaptic During the time integration, V mem Increase 0.287V.

[0137] In C mem Reach 8 I synaptic Afterwards, if V mem When the trigger threshold reaches 2.3V, during the depolarization process, V spike can change rapidly from 0 to 1.02V. During subsequent repolarization, V mem and V spike The initial voltage becomes 0V.

[0138] During a period of depolarization and repolarization, the neuron circuit can generate V with an amplitude of 1.02V. spike Pulse. In this I synaptic In the case of V spike It can be repeatedly excited at a frequency of 11.7 kHz. On the other hand, the neuron circuit of the present invention requires initialization of the pnpn diode for integration and excitation.

[0139] If the resetting is completed, then for the repeated work of integration and activation, V spike and V mem Can return to the initial value (V spike =V mem = 0.0V). After that, the next repeated synaptic input pulse can increase V again. mem ,like Figure 4d As shown, this cycle of integration and stimulation will occur normally.

[0140] As a result, the neuron circuit of one embodiment of the present invention can exhibit integration and firing operation at a firing frequency of approximately 20 kHz using only 4 transistors.

[0141] The performance of the neuron circuit of the present invention includes the number of transistors used, device type, synaptic input type, power consumption and excitation frequency, showing a performance higher than that of previous neuron circuits.

[0142] The firing frequency of the neuronal circuit is based on I synaptic The amplitude and duration of the oscillation change. synaptic A larger amplitude or a wider time width can reduce V mem The time at which the trigger threshold is reached.

[0143] In the neuron circuit of the present invention, with I having a time width of 0.8 μs and a period of 10 μs synaptic The amplitude of the I2C is increased from 9.5 μA to 11 μA at a rate of 0.5 μA per time, and the excitation frequency can be increased from 8.1 kHz to 15.6 kHz. Moreover, with an I2C having an amplitude of 10 μA and a period of 10 μs, synaptic The time width t synaptic Each time the period increases by 0.1μs, it changes from 0.6μs to 0.9μs, and the excitation frequency changes from 11.5kHz to 24.0kHz. This means that I synaptic Adjusting the amplitude and duration of the pulse can control the excitation frequency of the neuronal circuit.

[0144] In the past, neuron circuits based on Conductance and Hindmarsh-Rose models showed a form of using a large number of transistors to consume the highest power at a low excitation frequency. In addition, in the case of a neuron circuit based on complementary metal oxide semiconductors, the Izhikevich model that showed an excellent excitation frequency required 14 transistors and a high power consumption of 40μW. In addition, the past neuron circuits required more than 20 transistors in all device types.

[0145] As a result, the neuron circuit of the present invention has a small circuit area, is simplest and most efficient in terms of power consumption and firing frequency.

[0146] Figure 5a 5 is a timing diagram 510 showing changes in output characteristics based on changes in the size of synaptic current pulses applied to a neuron circuit.

[0147] like Figure 5a As shown, the timing diagram 510 shows a characteristic that the excitation time becomes faster as the size of the applied synaptic current pulse increases from 9.5 μA to 10 μA, 10.5 μA, and 11 μA in sequence.

[0148] Figure 5b 5 is a timing diagram 520 showing changes in output characteristics based on temporal changes in synaptic current pulses applied to a neuron circuit.

[0149] like Figure 5b As shown, the timing diagram 520 shows that the size of the applied synaptic current pulse changes over time from 0.6 μS to 0.7 μS, 0.8 μS, and 0.9 μS, and the excitation time becomes faster.

[0150] Figure 5c 5 is a timing diagram 530 showing changes in firing frequency based on changes in the size and timing of synaptic current pulses applied to a neuronal circuit.

[0151] Confirm the change of the excitation frequency characteristics based on the size and time of the synaptic current pulse applied to the neuron circuit. As explained above, the larger the size of the presynaptic current is, the longer the time width of the current is, and the faster the neuron circuit is excited. This is because the longer the size and time of the current are, the more the charge accumulated in the battery per unit time will increase. Therefore, if Figure 5c As shown, the magnitude of the current I synaptic and the occurrence width t synaptic The more it increases, the firing frequency will increase.

[0152] As a result, by utilizing the present invention, it is possible to develop a simple neuron-simulating device that can achieve high integration with a smaller number of electrodes than conventional complementary metal oxide semiconductor neuron-simulating devices.

[0153] Furthermore, if the present invention is utilized, compared to conventional complementary metal oxide semiconductor neuron devices, devices operating based on low standby power consumption can be developed, neuron simulation devices and circuits that can use conventional complementary metal oxide semiconductor processes can be developed, and compared to conventional complementary metal oxide semiconductor neuron circuits, circuits that can simultaneously achieve high integration and low power consumption can be developed.

[0154] Furthermore, by utilizing the present invention, it is possible to develop a circuit that can realize excitation and resetting inside a neuron circuit without an additional controller, and to develop a neuron simulation device and circuit that can be used in a pulse neural network.

[0155] The above-described device may be embodied as a combination of hardware structural elements, software structural elements, and / or hardware structural elements and software structural elements. For example, the device and structural elements described in the embodiments, such as a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor (digital signal processor), a microcomputer, a field programmable array (FPA), a programmable logic unit (PLU), a microprocessor, or any other device that can execute and respond to instructions, can be embodied using one or more conventional computers or special purpose computers. The processing device can execute an operating system (OS) and one or more software applications executed on the above operating system. In addition, the processing device accesses, stores, operates, processes, and generates data in response to the operation of the software. For ease of understanding, the case of using one processing device is described, and a person of ordinary skill in the art of the present invention can know that the processing device may include multiple processing elements and / or multiple types of processing elements. For example, the processing device may include multiple processors or a processor and a controller. Furthermore, other processing configurations such as parallel processors may also be used.

[0156] Software may include a computer program, code, instruction, or a combination of more than one of these, to configure a processing device or to command a processing device independently or collectively in a manner to perform work as required. Software and / or data are permanently or temporarily embodied in a type of machinery, component, physical device, virtual device, computer storage medium or device, or signal wave transmitted by a processing device interpreting or providing instructions or data to the processing device. Software is distributed on a networked computer system so that it can be stored or run by a distributed method. Software and data may be stored on one or more computer-readable recording media.

[0157] As described above, although the embodiments are described by limited drawings, a person skilled in the art of the present invention can make various modifications and variations from the above description. For example, the described techniques can be performed in a different order from the described methods, and / or the structural elements of the described systems, structures, devices, circuits, etc. can be combined or combined in a different form from the described methods, or replaced or replaced by other structural elements or equivalent technical solutions, and appropriate results can also be achieved.

[0158] Therefore, contents equivalent to other examples, other embodiments and the scope of protection of the invention also belong to the scope of protection of the invention described later.

Claims

1. A neuron circuit comprising a capacitor and a pnpn diode connected to the capacitor, It is characterized in that The capacitor is used to charge the current input from the synapse to generate a potential. If the generated potential is greater than a threshold value, a pulse voltage corresponding to the generated potential is generated and outputted by using the pnpn diode connected to the capacitor, wherein: The pnpn diode generates a pulse voltage corresponding to the generated potential by utilizing an avalanche breakdown phenomenon generated inside the diode device by an anode voltage.

2. The neuron circuit according to claim 1, It is characterized in that The neuron circuit resets the generated pulse voltage using at least one transistor connected to the pnpn diode.

3. The neuron circuit according to claim 2, It is characterized in that In the above-mentioned pnpn diode, the anode terminal is connected in parallel with the above-mentioned capacitor, and the cathode terminal is connected to at least one of the above-mentioned transistors.

4. The neuron circuit according to claim 3, It is characterized in that In at least one of the above transistors, In the first transistor, the gate terminal is connected to the gate line, and the drain terminal is connected in series with the cathode terminal of the pnpn diode. The gate terminal and the drain terminal of the second transistor are simultaneously connected to the drain terminal of the first transistor and the source terminal of the pnpn diode. In the third transistor, the drain terminal is connected to the anode terminal of the capacitor and the pnpn diode at the same time, and the gate terminal of the third transistor is connected to the gate terminal and the drain terminal of the second transistor at the same time.

5. The neuron circuit according to claim 4, It is characterized in that The pulse voltage is determined by voltage division of the first transistor and the pnpn diode.

6. The neuron circuit according to claim 4, It is characterized in that The pulse voltage changes frequency according to a change in the time width of the input pulse and the size of the input pulse.

7. The neuron circuit according to claim 1, It is characterized in that The pnpn diode has a plurality of potential barriers, and the plurality of potential barriers are used to block injection of charge carriers before the anode voltage is applied.

8. The neuron circuit according to claim 7, It is characterized in that When the anode voltage increases to a set reference voltage, the pnpn diode reduces the heights of the plurality of potential barriers in the valence band by the anode voltage, and injects holes into the potential wells formed when the heights of the plurality of potential barriers are reduced.

9. The neuron circuit according to claim 4, It is characterized in that In the above pnpn diode, The pulse voltage is reduced by a voltage-induced reset current generated at the gate terminal of the second transistor. The pulse voltage is reset by discharging the charge charged in the capacitor through a voltage-induced discharge current generated at the gate terminal of the third transistor.

10. The neuron circuit according to claim 8, It is characterized in that As the current pulse from the front-end synapse integrates on the capacitor, the voltage above the anode will increase, As the drain voltage increases, the potential barrier formed by the reverse bias level formed inside the above pnpn diode will increase, As the potential barrier increases, if the drain voltage increases above the threshold voltage for avalanche breakdown, a latch-up phenomenon will occur.

11. The neuron circuit according to claim 10, It is characterized in that Due to the current flowing due to the latch effect that occurs, the voltage at the output terminal (V spike ) electrical excitation occurs.

12. The neuron circuit according to claim 11, It is characterized in that If the above output terminal (V spike ) generates a pulse voltage, the gate voltages of the third transistor and the second transistor are increased, and the third transistor and the second transistor are turned on and release the charge charged in the capacitor and (V spike ) voltage to perform reset operation.

13. A neuron circuit comprising a capacitor, a pnpn diode connected to the capacitor, and at least one transistor connected to the pnpn diode, It is characterized in that The capacitor is used to charge the current input from the synapse to generate a potential. If the generated potential is greater than a threshold value, a pulse voltage corresponding to the generated potential is generated and outputted by the pnpn diode connected to the capacitor. The generated pulse voltage is reset by using at least one transistor connected to the pnpn diode, wherein: In the above-mentioned pnpn diode, the anode terminal is connected in parallel with the above-mentioned capacitor, and the cathode terminal is connected to at least one of the above-mentioned transistors. In at least one of the above transistors, In the first transistor, the gate terminal is connected to the gate line, and the drain terminal is connected in series with the cathode terminal of the pnpn diode. The gate terminal and the drain terminal of the second transistor are simultaneously connected to the drain terminal of the first transistor and the source terminal of the pnpn diode. In the third transistor, the drain terminal is connected to the anode terminal of the capacitor and the pnpn diode at the same time, and the gate terminal of the third transistor is connected to the gate terminal and the drain terminal of the second transistor at the same time.

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