Vertical non-volatile memory device and manufacturing method thereof

Abstract

A vertical non-volatile memory device and a manufacturing method thereof are disclosed. The vertical non-volatile memory device comprises: a substrate, comprising a cell array region and an extension region, the extension region extending from the cell array region in a first direction and comprising a contact; a channel structure extending from the substrate in a vertical direction; a first stacking structure, comprising a gate electrode layer and an interlayer insulating layer alternately stacked along the sidewall of the channel structure; a plurality of partitioning regions extending in a first direction and dividing the cell array region and the extension region in a second direction perpendicular to the first direction; in the extension region, two insulating layer dams are arranged between two adjacent partitioning regions; a second stacking structure, comprising a sacrificial layer and an interlayer insulating layer alternately stacked on the substrate between the two insulating layer dams; and an electrode pad connected to the first gate electrode layer in the extension region.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2019-0146171 filed on November 14, 2019 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The inventive concept relates to a nonvolatile memory device and a method of manufacturing the same, and more particularly, to a nonvolatile memory device having a vertical channel structure with increased integration density and a method of manufacturing the same. Background Art

[0003] Non-volatile memory is a computer memory that can retrieve stored information even after it has been power cycled. Devices including non-volatile memory are increasingly being used. For example, MP3 players, digital cameras, mobile phones, camcorders, flash memory cards, and solid-state disks (SSDs) use non-volatile memory for storage. Among non-volatile memories, flash memory can electrically and collectively erase the data of a cell, and is therefore widely used as a storage device in place of a hard disk. However, as the storage capacity of flash memory increases, a method for effectively utilizing the storage space of flash memory is desired. Therefore, a non-volatile memory device including a vertical transistor structure rather than a planar transistor structure can be used. Summary of the invention

[0004] According to an exemplary embodiment of the inventive concept, a vertical non-volatile memory device is provided, which includes: a substrate, including a cell array area and an extension area, the extension area extending from the cell array area along a first direction and including a vertical contact; a vertical channel structure extending from the top surface of the substrate along a vertical direction; a first stacking structure, including gate electrode layers and interlayer insulating layers alternately stacked along the sidewalls of the vertical channel structure; a plurality of partitioning areas extending along the first direction and dividing the cell array area and the extension area into a plurality of cells in a second direction perpendicular to the first direction; in the extension area, two insulating layer dams are arranged between two partitioning areas adjacent to each other along the second direction among the plurality of partitioning areas, wherein the two insulating layer dams extend along the first direction; a second stacking structure, including sacrificial layers and interlayer insulating layers alternately stacked on the substrate between the two insulating layer dams; and an electrode pad connected to the first gate electrode layer among the gate electrode layers in the extension area.

[0005] In addition, according to another exemplary embodiment of the inventive concept, a vertical non-volatile memory device is provided, which includes: a substrate, including a cell array area and an extension area extending from the cell array area along a first direction; a vertical channel structure, extending from the top surface of the substrate along a vertical direction; a first stacking structure, including gate electrode layers and interlayer insulating layers alternately stacked along the side walls of the vertical channel structure; a dividing area, extending along the first direction and dividing the cell array area and the extension area into a plurality of cells in a second direction perpendicular to the first direction; in the extension area, two insulating layer dams are arranged between two dividing areas adjacent to each other along the second direction, wherein the two insulating layer dams extend along the first direction; a second stacking structure, including a sacrificial layer and an interlayer insulating layer alternately stacked on the substrate between the two insulating layer dams; an electrode pad, connected to a first gate electrode layer in the gate electrode layer and arranged in the extension area, the electrode pad including a first pad area located on the first stacking structure and a second pad area located on the second stacking structure; and a vertical direct contact, arranged in the extension area and inserted into the second stacking structure via the second pad area of ​​the electrode pad.

[0006] In addition, according to another exemplary embodiment of the inventive concept, a method for manufacturing a vertical non-volatile memory device is provided, the method comprising: forming a molding structure by alternately stacking interlayer insulating layers and sacrificial layers on a substrate including a cell array region and an extension region; in the extension region, forming an insulating layer dam extending along a first direction on the substrate and separated from each other in a second direction perpendicular to the first direction; forming a step structure exposing the sacrificial layer in the extension region along the first direction by etching the molding structure; forming an additional sacrificial layer on the exposed sacrificial layer in the extension region; forming a vertical channel structure on the substrate for penetrating the molding structure and extending in a direction perpendicular to a top surface of the substrate; forming a vertical channel structure on the substrate extending along the first direction and extending in a second direction perpendicular to the first direction; forming a vertical channel structure on the substrate extending along the first direction and extending in a second direction perpendicular to the first direction; forming a vertical channel structure on the substrate extending along the first direction and extending in a second direction perpendicular to the first direction; forming a vertical channel structure on the substrate extending along the first direction and extending in a second direction perpendicular to the first direction. and a first dividing groove that divides the cell array area and the extension area; forming a first stacking structure by replacing the sacrificial layer and the additional sacrificial layer with the first conductive layer using the first dividing groove, the first stacking structure including gate electrode layers and interlayer insulating layers alternately stacked along the sidewalls of the vertical channel structure; forming a dividing area by forming an insulating layer in the first dividing groove; and forming a vertical direct contact connected to the electrode pad in the extension area, wherein two insulating layer dams are arranged along a second direction from the dividing area, and in the formation of the first stacking structure, the first stacking structure is formed in the cell array area, a second stacking structure substantially identical to the molding structure and located between the two insulating layer dams is maintained, and an electrode pad connected to the gate electrode layer in the extension area is formed.

[0007] According to another exemplary embodiment of the inventive concept, a vertical non-volatile memory device is provided, which includes: a substrate, including a cell array area and an extension area, the extension area extending from the cell array area along a first direction and including a vertical contact; a vertical channel structure extending from the top surface of the substrate along a vertical direction; a first stacking structure, including gate electrode layers and interlayer insulating layers alternately stacked along the sidewalls of the vertical channel structure; a plurality of partitioning areas extending along the first direction and dividing the cell array area and the extension area into a plurality of cells in a second direction perpendicular to the first direction; in the extension area, two insulating layer dams are arranged between two partitioning areas adjacent to each other along the second direction among the plurality of partitioning areas, wherein the two insulating layer dams extend along the first direction; a second stacking structure, including sacrificial layers and interlayer insulating layers alternately stacked on the substrate between the two insulating layer dams; a first electrode pad connected to a first gate electrode layer among the gate electrode layers in the extension area; and a second electrode pad connected to a first sacrificial layer among the sacrificial layers in the extension area. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other features of the inventive concept will be more clearly understood by describing in detail exemplary embodiments of the inventive concept in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is an equivalent circuit of a memory cell array of a vertical type nonvolatile memory device according to an exemplary embodiment of the inventive concept;

[0010] Figure 2 is a plan view illustrating a vertical type nonvolatile memory device according to an exemplary embodiment of the inventive concept;

[0011] Figure 3A It is shown Figure 2 A cross-sectional view of a vertical nonvolatile memory device taken along line II', line II-II' and line III-III';

[0012] Figure 3B It is shown Figure 2 A cross-sectional view of a vertical nonvolatile memory device taken along line IV-IV' and line V-V';

[0013] Figure 4 is a plan view illustrating a vertical type nonvolatile memory device according to an exemplary embodiment of the inventive concept;

[0014] Figure 5 is a plan view illustrating a vertical type nonvolatile memory device according to an exemplary embodiment of the inventive concept;

[0015] Fig. 6A It is shown Figure 5A cross-sectional view of a vertical nonvolatile memory device taken along line II', line VI-VI' and line VII-VII';

[0016] Figure 6B It is shown Figure 5 A cross-sectional view of a vertical nonvolatile memory device taken along line VIII'-VIII';

[0017] Figure 7 is a cross-sectional view illustrating a vertical type nonvolatile memory device according to an exemplary embodiment of the inventive concept; and

[0018] Figure 8 , Fig. 9 , Fig.10 , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig.14 , Fig.15A , Fig. 15B , Fig.16 , Fig.17A and Fig. 17B It shows the manufacturing Figure 2 A cross-sectional view of a method for manufacturing a vertical nonvolatile memory device. DETAILED DESCRIPTION

[0019] Hereinafter, exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. The same reference numerals may be used for the same constituent elements in the accompanying drawings, and thus, repeated description thereof may be omitted.

[0020] Figure 1 1 is an equivalent circuit of a memory cell array of a vertical type nonvolatile memory device 10 according to an exemplary embodiment of the inventive concept.

[0021] Reference Figure 1 , a vertical nonvolatile memory device 10 according to an exemplary embodiment of the inventive concept may include a common source line CSL, a plurality of bit lines (BL0 to BLm), and a plurality of cell strings CSTR. The bit lines (BL0 to BLm) may be arranged two-dimensionally, and a plurality of cell strings CSTR may be connected to each bit line (BL0 to BLm) in parallel. The plurality of cell strings CSTR may be commonly connected to the common source line CSL.

[0022] Each cell string CSTR may include a first string selection transistor SSt1, a second string selection transistor SSt2, a memory cell transistor MCT, and a ground selection transistor GST. Each memory cell transistor MCT may include a data storage element. The first string selection transistor SSt1 and the second string selection transistor SSt2 may be connected in series to each other, the second string selection transistor SSt2 may be connected to a corresponding one of the bit lines (BL0 to BLm), and the ground selection transistor GST may be connected to the common source line CSL. In addition, the memory cell transistor MCT may be connected in series between the first string selection transistor SSt1 and the ground selection transistor GST. In some exemplary embodiments of the inventive concept, one string selection transistor (SSt1 or SSt2) may be arranged in each cell string CSTR. The first string selection transistor SSt1 and the second string selection transistor SSt2 may be connected to the string selection lines SSL1 and SSL2, respectively.

[0023] like Figure 1 As shown in , each cell string CSTR may include a first dummy cell transistor DMC1 connected between a first string selection transistor SSt1 and one of the memory cell transistors MCT and a second dummy cell transistor DMC2 connected between a ground selection transistor GST and one of the memory cell transistors MCT. However, in some exemplary embodiments of the inventive concept, at least one of the first dummy cell transistor DMC1 and the second dummy cell transistor DMC2 may be omitted. The first dummy cell transistor DMC1 and the second dummy cell transistor DMC2 may be connected to dummy selection lines DWL1 and DWL2, respectively. The ground selection line GSL may be provided between a common source line CSL and the dummy selection line DWL2.

[0024] Since one cell string CSTR includes a plurality of memory cell transistors MCT having different distances from a common source line CSL, a multi-layer word line (WL0 to WLn) may be located between the common source line CSL and the bit lines (BL0 to BLm). In addition, gate electrodes of the memory cell transistors MCT arranged at substantially the same distance from the common source line CSL may be commonly connected to one of the word lines (WL0 to WLn), and thus may be in an equipotential state.

[0025] In the vertical nonvolatile memory device 10 of the present embodiment, due to the insulating layer dam (refer to Figure 2 ID) is formed in which electrode pads are formed (refer to Figure 2 The extension region of ELp1 and ELp2 in Figure 2 EA in the vertical contact (refer to Figure 2 VC in the extension area EA) is connected to the electrode pad ( Figure 2The gate electrode layer under ELp1 and ELp2 in Figure 3B A bridge defect of EL1 and EL2 in the vertical nonvolatile memory device may not occur, and thus a vertical nonvolatile memory device with improved reliability may be implemented.

[0026] Figure 2 is a plan view of a vertical type nonvolatile memory device 100 according to an exemplary embodiment of the inventive concept, Figure 3A Shows Figure 2 sectional views of the vertical nonvolatile memory device 100 taken along line II′, line II-II′, and line III-III′, Figure 3B Shows Figure 2 A cross-sectional view of the vertical nonvolatile memory device 100 taken along line IV-IV' and line V-V' is briefly given or omitted. Figure 1 Description given.

[0027] Reference Figures 2 to 3B , the vertical nonvolatile memory device 100 according to the present embodiment may include a cell array region CAA and an extension region EA located on a substrate 101. For reference, Figure 2 is with Figure 3A 1 and 2. The planarization insulating layer 150 is omitted in the extension area EA, and the planarization insulating layer 150 is omitted in the extension area EA.

[0028] The substrate 101 may have a top surface FS extending along a first direction (x direction) and a second direction (y direction). The substrate 101 may include a semiconductor material, for example, a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor. A cell region and a peripheral circuit region arranged outside the cell region may be located on the substrate 101.

[0029] The cell array area CAA and the extension area EA may be located in the cell area of ​​the substrate 101. The cell array area CAA may be where Figure 1 A plurality of bit lines (BL0 to BLm) may be located on the top surface of the cell array area CAA, and an impurity region and a common source line CSL may be under the cell array area CAA.

[0030] The extension area EA may be an area in which electrode pads (ELp1 and ELp2) are arranged, and the electrode pads (ELp1 and ELp2) are formed by extending the gate electrode layers (EL1 and EL2) of the first string selection transistor SSt1, the second string selection transistor SSt2, the memory cell transistor MCT, and the ground selection transistor GST from the cell array area CAA along the first direction (x direction). The electrode pads (ELp1 and ELp2) may be distinguished by the first electrode pad ELp1 and the second electrode pad ELp2, respectively, and the vertical direct contact VC may be connected to each of the first electrode pad ELp1 and the second electrode pad ELp2. In addition, the electrode pads (ELp1 and ELp2) may have a raised pad structure. In the extension area EA, the gate electrode layer (EL1 and EL2) and the first electrode pad ELp1 and the second electrode pad ELp2 may have a step structure in the first direction (x direction). When describing the structure of the insulating layer dam ID located in the extension area EA, a detailed description of the step structure of the gate electrode layers (EL1 and EL2) and the first and second electrode pads ELp1 and ELp2 is provided in more detail.

[0031] The stacked structure SST may be located on the substrate 101. The stacked structure SST may extend from the cell array area CAA to the extension area EA along a first direction (x direction) on the substrate 101. The buffer insulating layer 110 may be located between the stacked structure SST and the substrate 101. The stacked structure SST may be provided in plurality on the substrate 101, and may be arranged to be separated from each other along a second direction (y direction). For example, a partitioning area DA extending along a first direction (x direction) may be provided along a second direction (y direction), and the stacked structures SST may be separated from each other and the partitioning area DA may be located between the stacked structures SST. In this case, the partitioning area DA may be referred to as a word line cutting area, and the insulating spacer IS and the common source plug CSP may be arranged therein.

[0032] like Figure 2 As shown in , at least one additional partition area DAa extending along the first direction (x direction) may be included in the cell array area CAA between two partition areas DA adjacent to each other along the second direction (y direction). The additional partition area DAa may be provided so that a replacement process of the gate electrode layers (EL1 and EL2) may be more easily performed. In some exemplary embodiments of the inventive concept, the additional partition area DAa may be omitted.

[0033] The stacked structure SST may include a first stacked structure SST1 and a second stacked structure SST2. The first stacked structure SST1 may be formed in the cell array area CAA and may be formed between the insulating layer dam ID of the extension area EA and the partition area DA. The second stacked structure SST2 may be formed between two insulating layer dams ID adjacent to each other in the extension area EA.

[0034] The first stacked structure SST1 may include gate electrode layers (EL1 and EL2) and interlayer insulating layers ILD that are alternately and repeatedly stacked along a third direction (z direction) perpendicular to the top surface FS of the substrate 101. The thickness of the gate electrode layers (EL1 and EL2) may be substantially the same. The thickness of the interlayer insulating layer ILD may vary according to the characteristics of the memory device. In addition, the thickness of the interlayer insulating layer ILD may be smaller than the thickness of the gate electrode layers (EL1 and EL2). Each of the gate electrode layers (EL1 and EL2) may be connected to a portion of the first electrode pad ELp1 and the second electrode pad ELp2 in the extension area EA. For example, the first electrode pad ELp1 and the second electrode pad ELp2 may be divided into a first pad area PA1 and a second pad area PA2, respectively, on the side of the insulating layer dam ID in the extension area EA along the second direction (y direction), and the gate electrode layers (EL1 and EL2) may be connected to the first pad area PA1 of the electrode pads (ELp1 and ELp2), respectively.

[0035] The second stacked structure SST2 may include sacrificial layers SL and interlayer insulating layers ILD alternately and repeatedly stacked along a third direction (z direction) perpendicular to the top surface FS of the substrate 101. As described above, the second stacked structure SST2 may be located between two insulating layer dams ID adjacent to each other along the second direction (y direction) in the extension area EA. The second pad region PA2 of the electrode pads (ELp1 and ELp2) may be located on the top surface of the second stacked structure SST2. The first pad region PA1 and the second pad region PA2 of the electrode pads (ELp1 and ELp2) may be connected to each other on the top surface of the insulating layer dam ID.

[0036] The planarization insulating layer 150 may cover the stacked structure SST on the substrate 101. The planarization insulating layer 150 may have a substantially flat top surface. In addition, the planarization insulating layer 150 may cover the electrode pads (ELp1 and ELp2) in the step structure or extension area EA of the stacked structure SST. The planarization insulating layer 150 may include one insulating layer or a plurality of insulating layers.

[0037] A plurality of vertical channel structures VCS having a structure penetrating the stacked structure SST may be formed on the substrate 101. For example, Figure 2 As shown in , the vertical channel structure VCS may be arranged in a zigzag form along the first direction (x direction) in a plan view. The vertical channel structure VCS may be located in the cell array area CAA. However, the arrangement position of the vertical channel structure VCS is not limited thereto. For example, Figure 4 As shown in the vertical type nonvolatile memory device 100 a , the vertical channel structure VCS may be located in the extension area EA.

[0038] The vertical channel structure VCS may include a lower semiconductor pattern LSP, an upper semiconductor pattern USP, a data storage pattern VP, and a buried insulating pattern VI. The lower semiconductor pattern LSP may directly contact the substrate 101 and may include an epitaxial layer in the form of a column grown from the substrate 101. For example, the lower semiconductor pattern LSP may be partially located in the substrate 101. The top surface of the lower semiconductor pattern LSP may be above the top surface of the lowermost gate electrode layer EL1 and may be below the top surface of the lowermost interlayer insulating layer ILD on the lowermost gate electrode layer EL1. The gate insulating layer 115 may be located on a portion of the sidewall of the lower semiconductor pattern LSP.

[0039] The upper semiconductor pattern USP may directly contact the lower semiconductor pattern LSP. The inside of the upper semiconductor pattern USP may be filled with a buried insulating pattern VI including an insulating material. The lower semiconductor pattern LSP may be connected to the upper semiconductor pattern USP, penetrating the data storage pattern VP.

[0040] The data storage pattern VP may be located between the stacked structure SST and the upper semiconductor pattern USP. The data storage pattern VP may extend along a third direction (z direction) and may surround a sidewall of the upper semiconductor pattern USP. The data storage pattern VP may include one thin layer or a plurality of thin layers. In an exemplary embodiment of the inventive concept, the data storage pattern VP may be a data storage layer of a NAND flash memory device and may include a tunnel insulating layer, a charge storage layer, and a blocking insulating layer.

[0041] The bit line electrode pad BP and the bit line contact plug BCP connected to the bit line electrode pad BP may be located on the upper semiconductor pattern USP. The side surface of the bit line electrode pad BP may be surrounded by the data storage pattern VP. For example, the side surface of the bit line electrode pad BP may be in direct contact with the data storage pattern VP. According to an exemplary embodiment of the inventive concept, the bit line electrode pad BP may be located on the top surface of the upper semiconductor pattern USP and the top surface of the data storage pattern VP, and the top surface of the bit line electrode pad BP may be covered by the first upper interlayer insulating layer 160.

[0042] The common source area CSA may be formed by doping an upper portion of the substrate 101 with impurities. The common source area CSA may extend along a first direction (x direction). A common source plug CSP may be formed on and connected to the common source area CSA. An insulating spacer IS may be located between the common source plug CSP and the stacked structure SST, and the common source plug CSP and the insulating spacer IS may constitute a partition area DA. In some exemplary embodiments of the inventive concept, the common source plug CSP may be formed only on a portion of the top surface of the common source area CSA, and a separation insulating layer may be located on the common source plug CSP. In this structure, the common source plug CSP, the insulating spacer IS, and the separation insulating layer may constitute a partition area DA.

[0043] The first upper interlayer insulating layer 160 may be located on the planarization insulating layer 150 in the extension area EA. In addition, the first upper interlayer insulating layer 160 may cover the top surface of the vertical channel structure VCS. The second upper interlayer insulating layer 170 may be located on the first upper interlayer insulating layer 160 and may cover the top surface of the common source plug CSP and the top surface of the insulating spacer IS.

[0044] In the extension area EA, the vertical contact VC may be connected to the corresponding electrode pads (ELp1 and ELp2) by penetrating the first upper interlayer insulating layer 160, the second upper interlayer insulating layer 170, and the planarization insulating layer 150. Figure 3A and Figure 3B As shown in , the vertical length of the vertical direct contact VC, in other words, the length of the vertical direct contact VC along the third direction (z direction) can be reduced as the vertical direct contact VC is closer to the cell array area CAA. For example, as the vertical direct contact VC gets closer to the cell array area CAA, it can be connected to a higher second stack structure SST2 than a vertical direct contact VC that is farther away from the cell array area CAA. In addition, the top surface of the vertical direct contact VC can be substantially coplanar. The vertical direct contact VC can penetrate the electrode pads (ELp1 and ELp2) and be inserted into the second stack structure SST2 under the electrode pads (ELp1 and ELp2).

[0045] In the second stacked structure SST2, a sacrificial layer SL and an interlayer insulating layer ILD may be formed. Therefore, even when the vertical direct contact VC is inserted into the second stacked structure SST2 via the electrode pads (ELp1 and ELp2), the bridging defect with the gate electrode layer (EL1 and EL2) generated in the conventional vertical non-volatile memory device may not occur. For example, in the conventional vertical non-volatile memory device, in the extension region, the gate electrode layer may be under the electrode pad. Therefore, in the case where the vertical direct contact extends downward via the electrode pad, when the vertical direct contact is connected to the gate electrode layer under the electrode pad, a bridging defect may occur. On the contrary, in the vertical non-volatile memory device 100 of the present embodiment, since the second stacked structure SST2 is located under the electrode pads (ELp1 and ELp2) to which the vertical direct contact VC is connected, even if the vertical direct contact VC penetrates the corresponding electrode pads (ELp1 and ELp2) and extends downward, a bridging defect with the gate electrode layer (EL1 and EL2) may not occur.

[0046] In the vertical nonvolatile memory device 100 of the present embodiment, a second stacked structure SST2 may be formed due to the insulating layer dam ID. The second stacked structure SST2 will be described in more detail later when describing the structure of the insulating layer dam ID and the electrode pads (ELp1 and ELp2) in the extension area EA.

[0047] The sub-bit line SBL may be located on the second upper interlayer insulating layer 170 in the cell array area CAA and may be electrically connected to the corresponding vertical channel structure VCS via the bit line contact plug BCP. In the extension area EA, the connection line CL may be located on the second upper interlayer insulating layer 170 and may be connected to the vertical contact VC. The third upper interlayer insulating layer 180 may be located on the second upper interlayer insulating layer 170 and may cover the sub-bit line SBL and the connection line CL. The bit line BL may be located on the third upper interlayer insulating layer 180 and may extend in the second direction (y direction) across the stacked structure SST. The bit line BL may be connected to the sub-bit line SBL via a contact plug.

[0048] In the vertical nonvolatile memory device 100 of the present embodiment, the structures of the insulating layer dam ID and the corresponding electrode pads (ELp1 and ELp2) in the extension area EA are described in more detail below.

[0049] As described above, in the vertical nonvolatile memory device 100 of the present embodiment, as the gate electrode layer (EL1 and EL2) is farther from the substrate 101 in the third direction (z direction) in the extension area EA, the gate electrode layer (EL1 and EL2) may have a step structure whose length decreases in the first direction (x direction). In addition, in the extension area EA, the first electrode pad ELp1 and the second electrode pad ELp2 connected to the gate electrode layer (EL1 and EL2) may have a raised pad structure. In this case, the raised pad structure may be a structure in which the thickness of the electrode pads (ELp1 and ELp2) is greater than the thickness of the corresponding gate electrode layer (EL1 and EL2).

[0050] In addition, if Figure 2 As shown in , the vertical non-volatile memory device 100 of the present embodiment may include two insulating layer dams ID extending in the first direction (x direction) and separated from each other in the second direction (y direction) in the extension area EA. The second stacked structure SST2 may be located between the two insulating layer dams ID. The second stacked structure SST2 may include sacrificial layers SL and interlayer insulating layers ILD arranged alternately. In the extension area EA, the first stacked structure SST1 may be located between the partition area DA and the insulating layer dam ID, and the first stacked structure SST1 may include gate electrode layers (EL1 and EL2) and interlayer insulating layers ILD arranged alternately.

[0051] The gate electrode layers (EL1 and EL2) may be connected to corresponding electrode pads (ELp1 and ELp2) in the extension area EA, and the gate electrode layers (EL1 and EL2) and the first electrode pad ELp1 and the second electrode pad ELp2 may have a step structure that increases or decreases two layers in the extension area EA. In other words, the first electrode pad ELp1 may be separated by two layers in the extension area EA. In the first stacked structure SST1, the gate electrode layers (EL1 and EL2) and the interlayer insulating layers ILD may be alternately stacked along a third direction (z direction), and the gate electrode layers (EL1 and EL2) may include odd-numbered first gate electrode layers EL1 and even-numbered second gate electrode layers EL2. For example, in Figure 3A or Figure 3B , it is shown that the first gate electrode layer EL1 and the second gate electrode layer EL2 are arranged from the first layer to the ninth layer in the cell array area CAA. However, the number of layers of the first gate electrode layer EL1 and the second gate electrode layer EL2 is not limited thereto. For example, the first gate electrode layer EL1 and the second gate electrode layer EL2 may be formed into eight layers or less, or may be formed into ten layers or more.

[0052] The first gate electrode layer EL1 and the second gate electrode layer EL2 and the first electrode pad ELp1 and the second electrode pad ELp2 of the first stacked structure SST1 may have a first step structure STS1 on the left side relative to the first pad gap PG1 in the extension area EA, and may have a second step structure STS2 on the right side of the first pad gap PG1 in the extension area EA. In other words, the first step structure STS1 and the second step structure STS2 may be adjacent to each other in the second direction (y direction) relative to the first pad gap PG1 extending along the first direction (x direction). In addition, the structure of the second stacked structure SST2 may be substantially the same as the step structure of the first stacked structure SST1 in the extension area EA, except that it includes a sacrificial layer SL instead of the gate electrode layers EL1 and EL2. More specifically, the sacrificial layer SL is used in the second stacked structure SST2 to replace the gate electrode layers EL1 and EL2. As Figure 3B As shown in, the sacrificial layer SL and the first and second electrode pads ELp1 and ELp2 of the second stacked structure SST2 may have a first step structure STS1 on the left side of the first pad gap PG1 in the extension area EA, and may have a second step structure STS2 on the right side of the first pad gap PG1 in the extension area EA.

[0053] In the first stepped structure STS1, the length of the first gate electrode layer EL1 and the length of the second gate electrode layer EL2 may decrease in the first direction (x direction) in the order of the first layer, the second layer-third layer, the fourth layer-fifth layer, the sixth layer-seventh layer, and the eighth layer-ninth layer. The first layer and the upper layer of the paired two layers (in other words, the third layer, the fifth layer, the seventh layer, and the ninth layer) may correspond to the first gate electrode layer EL1, and the lower layer of the paired two layers (in other words, the second layer, the fourth layer, the sixth layer, and the eighth layer) may correspond to the second gate electrode layer EL2. In addition, the first gate electrode layer EL1 corresponding to the upper layer may constitute the first electrode pad ELp1 in the extension area EA. In this case, the portion connected by "-" may mean that the first gate electrode layer EL1 and the second gate electrode layer EL2 have the same length in the first direction (x direction). For example, "second layer-third layer" may mean that the second gate electrode layer EL2 of the second layer and the first gate electrode layer EL1 of the third layer have the same length in the first direction (x direction).

[0054] In the second stepped structure STS2, the length of the first gate electrode layer EL1 and the length of the second gate electrode layer EL2 may decrease in the first direction (x direction) in the order of the first layer-the second layer, the third layer-the fourth layer, the fifth layer-the sixth layer, and the seventh layer-the eighth layer. The upper layer of the two layers in a pair (in other words, the second layer, the fourth layer, the sixth layer, and the eighth layer) may correspond to the second gate electrode layer EL2, and the lower layer of the two layers in a pair (in other words, the first layer, the third layer, the fifth layer, and the seventh layer) may correspond to the first gate electrode layer EL1. In addition, the second gate electrode layer EL2 corresponding to the upper layer may constitute the second electrode pad ELp2 in the extension area EA.

[0055] When a block of the cell array area CAA is located between two adjacent partition areas DA, all the first gate electrode layers EL1 and the second gate electrode layers EL2 in the block can be connected to the vertical direct contact VC via the first step structure STS1 and the second step structure STS2 and the first electrode pad ELp1 and the second electrode pad ELp2. In addition, in the extension area EA, by dividing the first electrode pad ELp1 and the second electrode pad ELp2 along the second direction (y direction) relative to the first pad gap PG1 using the first step structure STS1 and the second step structure STS2, the vertical direct contact VC can be arranged in two rows in the first direction (x direction). Therefore, the process margin can be fully ensured by further widening the arrangement interval of the vertical direct contact VC in the first direction (x direction).

[0056] exist Figure 3B, as shown in the portion taken along line IV-IV', the first electrode pad ELp1 may be the ninth layer located on the left side of the first pad gap PG1 among the first electrode pad ELp1 and the second electrode pad ELp2 closest to the cell array area CAA. In addition, the first gate electrode layer EL1 and the second gate electrode layer EL2 of the first to eighth layers may be under the first electrode pad ELp1. However, as the first gate electrode layer EL1 and the second gate electrode layer EL2 of the first to eighth layers are lowered by two layers together with the first electrode pad ELp1, the first gate electrode layer EL1 and the second gate electrode layer EL2 may extend farther from the cell array area CAA in the first direction (x direction). In other words, the second gate electrode layer EL2 of the eighth layer can have the same length in the first direction (x direction) as the length of the first electrode pad ELp1 of the ninth layer and can extend the shortest among the first to ninth layers, the second gate electrode layer EL2 of the sixth layer and the first gate electrode layer EL1 of the seventh layer, the second gate electrode layer EL2 of the fourth layer and the first gate electrode layer EL1 of the fifth layer, the second gate electrode layer EL2 of the second layer and the first gate electrode layer EL1 of the third layer can each have the same length in the first direction (x direction), and as the number of layers decreases, the first gate electrode layer EL1 and the second gate electrode layer EL2 can extend longer in the cell array area CAA, and the first gate electrode layer EL1 of the first layer can extend the farthest among the first to ninth layers.

[0057] In addition, among the first electrode pad ELp1 and the second electrode pad ELp2 closest to the cell array area CAA, the second electrode pad ELp2 may be the eighth layer at the right side of the first pad gap PG1, and the first gate electrode layer EL1 and the second gate electrode layer EL2 of the first to seventh layers may be under the second electrode pad ELp2. In addition, as the first gate electrode layer EL1 and the second gate electrode layer EL2 of the first to seventh layers are lowered by two layers together with the second electrode pad ELp2, the first gate electrode layer EL1 and the second gate electrode layer EL2 may extend farther from the cell array area CAA in the first direction (x direction). In other words, the first gate electrode layer EL1 of the seventh layer can have the same length in the first direction (x direction) as the second electrode pad ELp2 of the eighth layer and can extend the shortest among the first to eighth layers, and each of the first gate electrode layer EL1 of the fifth layer and the second gate electrode layer EL2 of the sixth layer, the first gate electrode layer EL1 of the third layer and the second gate electrode layer EL2 of the fourth layer, and the first gate electrode layer EL1 of the first layer and the second gate electrode layer EL2 of the second layer can have the same length in the first direction (x direction) and can extend longer in the cell array area CAA as the number of layers decreases.

[0058] exist Figure 3BIn the case of the portion intercepted along the line V-V', the first electrode pad ELp1 and the second electrode pad ELp2 may be two layers lower than the first electrode pad ELp1 and the second electrode pad ELp2 in the portion intercepted along the line IV-IV', respectively. In other words, in the first electrode pad ELp1 and the second electrode pad ELp2 that are second closest to the cell array area CAA, the first electrode pad ELp1 may be the seventh layer at the left side of the first pad gap PG1, and the first gate electrode layer EL1 and the second gate electrode layer EL2 of the first to sixth layers may be under the first electrode pad ELp1. In addition, the second electrode pad ELp2 may be the sixth layer at the right side of the first pad gap PG1, and the first gate electrode layer EL1 and the second gate electrode layer EL2 of the first to fifth layers may be under the second electrode pad ELp2.

[0059] The first electrode pad ELp1 and the second electrode pad ELp2 may be separated from each other by a second pad gap PG2 from the side ends (ELe1 and ELe2) of the step structure toward the cell array area CAA in the first direction (x direction). Figure 3A In the embodiment, the first electrode pad ELp1 may be separated from the first side end portion ELe1 of the left side step structure by a second pad gap PG2.

[0060] The first electrode pad ELp1 and the second electrode pad ELp2 may be divided into a first pad area PA1 and a second pad area PA2, respectively, based on the insulating layer dam ID. Figure 3B As shown in , the first pad area PA1 may be thicker than the second pad area PA2 in the third direction (z direction). The lower portion of the first pad area PA1 may be in contact with the side surface of the insulating layer dam ID, and the upper portion of the first pad area PA1 may be connected to the second pad area PA2 on the upper surface of the insulating layer dam ID. For example, the first pad area PA1 and the second pad area PA2 may be connected through the first electrode pad ELp1. In addition, as Figure 3A As shown in the portion taken along line III-III' in FIG. 1 , a lower portion of the first pad area PA1 of the first electrode pad ELp1 may be connected to the first gate electrode layer EL1. In addition, a lower portion of the first pad area PA1 of the second electrode pad ELp2 may be connected to the second gate electrode layer EL2.

[0061] The second gate electrode layer EL2 may be arranged under the first electrode pad ELp1 and the interlayer insulating layer ILD may be placed between the second gate electrode layer EL2 and the first electrode pad ELp1, but the second gate electrode layer EL2 may not be connected to the first electrode pad ELp1. In addition, the first gate electrode layer EL1 may be arranged under the second electrode pad ELp2 and the interlayer insulating layer ILD may be placed between the first gate electrode layer EL1 and the second electrode pad ELp2, but the first gate electrode layer EL1 may not be connected to the second electrode pad ELp2.

[0062] In the vertical nonvolatile memory device 100 of the present embodiment, the first electrode pad ELp1 and the second electrode pad ELp2 which are raised and have a step structure may be formed in the extension area EA in the first direction (x direction). In addition, two insulating layer dams ID which are separated from each other in the second direction (y direction) perpendicular to the first direction (x direction) may be formed. In addition, since the first gate electrode layer EL1 and the second gate electrode layer EL2 are not replaced under the first electrode pad ELp1 and the second electrode pad ELp2 between the two insulating layer dams ID, the second stacked structure SST2 in which the sacrificial layers SL and the interlayer insulating layers ILD are alternately formed may be maintained in its current state. Therefore, in the vertical nonvolatile memory device 100 of the present embodiment, in the process of forming the vertical direct contact VC in the extension area EA, although the vertical direct contact VC is formed by penetrating the first electrode pad ELp1 and the second electrode pad ELp2, a bridging defect of the vertical direct contact VC connected to the first gate electrode layer EL1 and the second gate electrode layer EL2 located under the first electrode pad ELp1 and the second electrode pad ELp2 may not occur, and as a result, a vertical nonvolatile memory device with improved reliability may be realized.

[0063] For reference, in a conventional vertical non-volatile memory device, according to the dispersion associated with forming a raised electrode pad, the pull-back (P / B) etching dispersion of the etchant may increase in the gate electrode layer replacement process. In this case, the connection margin between the pad and the vertical direct contact is reduced. In addition, when the vertical direct contact is formed in the electrode pad portion with the smallest margin, a bridging defect in which the vertical direct contact is connected to the lower gate electrode layer by penetrating the electrode pad portion may occur.

[0064] However, in the vertical nonvolatile memory device 100 of the present embodiment, the insulating layer dam ID is formed in the extension area EA before the gate electrode layer replacement process, and the mold structure is maintained between the insulating layer dam ID in the gate electrode layer replacement process. In this case, the P / B etching of the etching solution for the gate electrode layer of the lower portion can be limited by the insulating layer dam ID, while the P / B etching of the etching solution for the electrode pad of the upper portion is increased regardless of the dispersion caused by the formation of the raised electrode pad. Therefore, the vertical nonvolatile memory device 100 of the present embodiment can improve the connection margin and eliminate the bridging defect.

[0065] Figure 4 is a plan view of a vertical type nonvolatile memory device 100a according to an exemplary embodiment of the inventive concept, and may correspond to Figure 2 Briefly give or omit reference to Figures 1 to 3B Description given.

[0066] Reference Figure 4 The vertical nonvolatile memory device 100a of the embodiment is Figure 2 The vertical nonvolatile memory device 100 of the present embodiment may be different in that the dummy channel structure DCS is arranged in the extension area EA. In the vertical nonvolatile memory device 100a of the present embodiment, the dummy channel structure DCS may be located in a portion where the first stacked structure SST1 is formed in the extension area EA. In the extension area EA, the first stacked structure SST1 may be formed between the insulating layer dam ID and the partition area DA and located in a portion of the extension area EA adjacent to the cell array area CAA.

[0067] The dummy channel structure DCS may be formed to prevent the interlayer insulating layer ILD from being formed on the gate electrode layer (refer to Figure 3A Therefore, the dummy channel structure DCS may be formed in the portion where the first stacked structure SST1 is formed in the replacement process of the gate electrode layer (EL1 and EL2). On the other hand, in the replacement process of the gate electrode layer (EL1 and EL2), since the second stacked structure SST2 is maintained as it is between the two insulating layer dams 1D adjacent to each other along the second direction (y direction), the dummy channel structure DCS may not be arranged in the second stacked structure SST2.

[0068] The dummy channel structure DCS may have a structure similar to the vertical channel structure (refer to Figure 2 The vertical channel structure VCS and the dummy channel structure DCS may be substantially the same structure as the structure of the VCS in the third direction (the z direction). For example, in the third direction (the z direction), the bottom surface of the vertical channel structure VCS and the bottom surface of the dummy channel structure DCS may be at substantially the same level. In addition, the vertical channel structure VCS and the dummy channel structure DCS may have substantially the same length in the third direction (the z direction). This may be because the vertical channel structure VCS and the dummy channel structure DCS are formed simultaneously in the same process.

[0069] Since the dummy channel structure DCS is formed in the extension area EA, unlike the vertical channel structure VCS penetrating the entire first stack structure SST1, the dummy channel structure DCS may have a structure penetrating the planarization insulating layer 150 (refer to Figure 3A ) and the structure of the first stacked structure SST1 under the planarization insulating layer 150. For example, the dummy channel structure DCS may penetrate through the step structure of the first stacked structure SST1, and as the dummy channel structure DCS becomes farther away from the cell array area CAA, the number of gate electrode layers (EL1 and EL2) through which the dummy channel structure DCS passes may decrease.

[0070] The internal structure of the dummy channel structure DCS may be substantially the same as the internal structure of the vertical channel structure VCS. Therefore, the dummy channel structure DCS may include a lower semiconductor pattern (refer to Figure 2 LSP in), upper semiconductor pattern (refer to Figure 2 USP), data storage pattern (refer to Figure 2 VP) and buried insulation pattern (refer to Figure 2 In some exemplary embodiments of the inventive concept, in the dummy channel structure DCS, the upper semiconductor pattern USP may be removed, and the buried insulating pattern VI may be directly disposed on the data storage pattern VP.

[0071] Figure 5 is a plan view of a vertical type nonvolatile memory device 100 b according to an exemplary embodiment of the inventive concept, Fig. 6A Shown along Figure 5 A cross-sectional view of a vertical nonvolatile memory device 100b taken along line II', line VI-VI', and line VII-VII', Figure 6B Shown along Figure 5 A cross-sectional view of a vertical nonvolatile memory device 100b taken along line VIII-VIII' is briefly given or omitted. Figures 1 to 4 Description given.

[0072] Reference Figures 5 to 6B The vertical nonvolatile memory device 100b of the present embodiment may be different from the structure of the gate electrode layer (EL) and the electrode pad ELp in the extension area EA1. Figure 2 In the vertical nonvolatile memory device 100b of the present embodiment, in the extension area EA1, the gate electrode layer (EL) and the electrode pad ELp may have a step structure that increases or decreases one layer in the first direction (x direction). Therefore, the gate electrode layer (EL) in the cell array area CAA of one block between two adjacent division areas DA may be connected to the corresponding electrode pad ELp via a single step structure of the extension area EA1.

[0073] For example, in Fig. 6A and Figure 6B In the embodiment of the present invention, the first to ninth gate electrode layers (EL) may be arranged in the cell array area CAA. The number of layers of the gate electrode layer (EL) is not limited thereto. For example, the gate electrode layer (EL) may be formed into eight layers or less, or ten layers or more. In the step structure of the extension area EA1, the length of the gate electrode layer (EL) may be increased by one layer sequentially along the first direction (x direction). In addition, the gate electrode layer (EL) of each layer may constitute an electrode pad ELp in the extension area EA1, and the vertical direct contact VC may be arranged in a line in the first direction (x direction).

[0074] like Figure 6B As shown in the portion taken along line VIII-VIII' in , the electrode pad ELp may be the eighth layer of the electrode pad ELp that is second closest to the cell array area CAA, and the gate electrode layers (EL) of the first to seventh layers may be under the electrode pad ELp. The gate electrode layers (EL1 and EL2) of the first to seventh layers together with the electrode pad ELp may extend farther from the cell array area CAA in the first direction (x direction) as they are lowered by one layer. In other words, the electrode pad ELp of the eighth layer extends the shortest distance in the first direction (x direction), and as the number of layers of the gate electrode layer (EL) decreases from the seventh layer to the first layer, the gate electrode layer (EL) may extend farther away from the cell array area CAA.

[0075] In the vertical nonvolatile memory device 100b of the present embodiment, two insulating layer dams ID extending in the first direction (x direction) and separated from each other in the second direction (y direction) may be formed between two division areas DA adjacent to each other in the extension area EA1 in the second direction (y direction). Figure 2 In the vertical nonvolatile memory device 100, the second stacked structure SST2 may be arranged between the two insulating layer dams ID. In other words, the first stacked structure SST1 in which the gate electrode layer (EL) and the interlayer insulating layer ILD are alternately arranged may be located in the cell array area CAA and between the insulating layer dam ID and the partition area DA. In addition, the second stacked structure SST2 in which the sacrificial layer SL and the interlayer insulating layer ILD are alternately arranged may be located between the two insulating layer dams ID.

[0076] In the vertical nonvolatile memory device 100b of the present embodiment, the electrode pad ELp may have a raised pad structure. Therefore, the electrode pad ELp may be divided into a first pad area PA1 and a second pad area PA2 based on the insulating layer dam ID. For example, the second pad area PA2 may be disposed between a pair of insulating layer dams ID. Figure 6B As shown in , the first pad area PA1 may be thicker than the second pad area PA2 in the third direction (z direction). The lower portion of the first pad area PA1 may be in contact with the side surface of the insulating layer dam ID, and the upper portion of the first pad area PA1 may be connected to the second pad area PA2 on the upper surface of the insulating layer dam ID. In addition, as Fig. 6A As shown in a portion taken along line VII-VII′ in FIG. 8 , a lower portion of the first pad area PA1 of the electrode pad ELp may be connected to the gate electrode layer (EL).

[0077] In addition, in the vertical nonvolatile memory device 100b of the present embodiment, the dummy channel structure (see Figure 4The DCS in the example may be located in the extension area EA1. Figure 4 As shown in the vertical non-volatile memory device 100a, in the extension area EA1, the dummy channel structure DCS can be arranged in the portion where the first stacked structure SST1 is formed, in other words, arranged in the portion between the insulating layer dam ID and the partition area DA, and arranged in the portion of the extension area EA1 adjacent to the cell array area CAA.

[0078] Figure 7 1 is a cross-sectional view showing a vertical nonvolatile memory device 100c according to an exemplary embodiment of the inventive concept. Figures 1 to 6B Description given.

[0079] Reference Figure 7 The vertical nonvolatile memory device 100c according to the present embodiment may include a cell area CA and a peripheral circuit area PCA. The cell area CA may have, for example, Figure 2 The structure of the cell region of the vertical nonvolatile memory device 100 is basically the same as that of the vertical nonvolatile memory device 100. Figure 7 The portion corresponding to the unit area CA can be Figure 3A The structure of the cell area CA of the vertical nonvolatile memory device 100c of the present embodiment is not limited to Figure 2 For example, the structure of the cell area CA of the vertical nonvolatile memory device 100c of the present embodiment may be: Figure 4 The vertical nonvolatile memory device 100a and Figure 5 1. The structure of a cell region of a vertical nonvolatile memory device 100b.

[0080] In the vertical nonvolatile memory device 100c of the present embodiment, the peripheral circuit area PCA may be below the substrate 101 of the cell area CA. In other words, the cell area CA may be stacked on the peripheral circuit area PCA. Therefore, the peripheral circuit area PCA and the cell area CA may overlap each other in a plan view. For reference, Figure 2 , Figure 4 and Figure 5 In the vertical type nonvolatile memory devices 100 , 100 a , and 100 b , the peripheral circuit area PCA may be arranged around the cell area on the top surface FS of the substrate 101 in a horizontal direction.

[0081] The peripheral circuit area PCA may be formed on a base substrate 201. The base substrate 201 may be similar to Figure 2The base substrate 201 may include an n-well region NW doped with n-type impurities and a p-well region PW doped with p-type impurities. An active region may be defined in the n-well region NW and the p-well region PW by a device isolation layer 215 .

[0082] In the peripheral circuit area PCA, high voltage and / or low voltage transistors and passive elements such as resistors or capacitors may be arranged. The peripheral circuit area PCA may include a peripheral circuit gate electrode PG, a source / drain region S / D, a peripheral circuit plug PCP, a peripheral circuit wiring ICL and a lower buried insulating layer 220. The lower buried insulating layer 220 may include a single layer or multiple layers. A P-type metal oxide semiconductor (PMOS) transistor may be formed in an N-well region NW, and an N-type metal oxide semiconductor (NMOS) transistor may be formed in a P-well region PW. The transistor in the peripheral circuit area PCA is represented, for example, by PTR. In addition, in the extension area EA of the cell area CA, a wiring structure for electrically connecting the cell area CA and the peripheral circuit area PCA may be provided. The wiring structure may include a connection contact plug that penetrates the planarization insulating layer 150 and the substrate 101 and is connected to the peripheral circuit wiring ICL of the peripheral circuit area PCA.

[0083] Figures 8 to 17B It shows the manufacturing Figure 2 A cross-sectional view of a method for manufacturing a vertical nonvolatile memory device. Fig.11A , Fig. 12A , Fig.13A , Fig.15A and Fig.17A Can correspond to Figure 3A Parts I-I' and II-II', Figure 8 , Fig. 9 , Fig.10 , Fig. 11B , Fig. 12B , Fig. 13B , Fig.14 , Fig. 15B , Fig.16 and Fig. 17B Can correspond to Figure 3B . Reference Figures 1 to 3B Give a description together, briefly give or omit the referenced Figures 1 to 3B For example, refer to Figure 8 , Fig. 9 , Fig.10 and Fig.14 ,and Figure 3A The corresponding drawings of the parts taken along lines II' and II-II' in FIG. Figure 3B The drawings of the present invention are the same as those of the present invention or drawings used for the previous process, so their description is omitted.

[0084] Reference Figure 8 , a molding structure 210 may be formed on the substrate 101 of the cell array area CAA and the extension area EA. The molding structure 210 may include sacrificial layers SL and interlayer insulating layers ILD vertically alternately stacked. In the molding structure 210, the sacrificial layer SL may include a material having an etching selectivity relative to the interlayer insulating layer ILD. For example, the sacrificial layer SL may include silicon nitride, and the interlayer insulating layer ILD may include silicon oxide. The materials of the sacrificial layer SL and the interlayer insulating layer ILD are not limited thereto. The sacrificial layer SL may have substantially the same thickness, and the interlayer insulating layer ILD may have different thicknesses in some areas.

[0085] In addition, Figure 7 In the case of the vertical nonvolatile memory device 100c shown in FIG, after the peripheral circuit area PCA is formed under the substrate 101, the molding structure 210 may be formed on the substrate 101. According to an exemplary embodiment of the inventive concept, after the peripheral circuit area PCA and the cell area CA are formed on different wafers from each other, the vertical nonvolatile memory device 100c may be manufactured in a manner of stacking a second wafer on a first wafer and connecting them to each other via a wiring structure.

[0086] Reference Fig. 9 After forming the molding structure 210, first trenches T1 extending in the first direction (x direction) and separated from each other in the second direction (y direction) may be formed in the extension area EA. Figure 2 or Figure 4 As shown in FIG. 1 , the first trench T1 may be formed between two partition areas DA to be formed later or between two second trenches for partitioning areas (see FIG. 1 ). Fig.14 The first trench T1 may be formed to penetrate the molding structure 210 and expose a top surface portion of the substrate 101.

[0087] Reference Fig.10 , the insulating layer dam ID may be formed by filling the first trench T1 with an insulating material. The insulating layer dam ID may include an oxide, for example, silicon oxide. The material of the insulating layer dam ID is not limited thereto. Since the insulating layer dam ID is formed in the first trench T1, the insulating layer dam ID may have a structure extending in the first direction (x direction) in the extension area EA and separated from each other in the second direction (y direction). In the extension area EA, the second stacked structure SST2 may be located between the two insulating layer dams ID in the second direction (y direction).

[0088] Reference Fig.11A and Fig. 11B, a trimming process may be performed on the molding structure 210 to form a step structure in the extension area EA. In this case, although the trimming process includes forming a mask pattern covering the molding structure 210 in the cell array area CAA and the extension area EA, etching a portion of the molding structure 210, and reducing the horizontal area of ​​the mask pattern, the process of etching a portion of the molding structure 210 and the process of reducing the horizontal area of ​​the mask pattern may be repeated alternately. After performing the trimming process, the molding structure 210 may have a step structure in the extension area EA. For example, the second stacked structure SST2 may have a stair shape in the extension area EA.

[0089] In this case, the step structure in the extension area EA may include a first step structure STS1 and a second step structure STS2. Each of the first step structure STS1 and the second step structure STS2 may have a step structure with two layers increased or decreased. In addition, the first step structure STS1 and the second step structure STS2 may have a difference of one layer at the same position in the first direction (x direction). Therefore, the top surface of the odd-numbered sacrificial layer SL may be exposed in the first step structure STS1, and the top surface of the even-numbered sacrificial layer SL may be exposed in the second step structure STS2. Fig.11A A first step structure STS1 is shown, and Fig. 11B In the example, the left part may correspond to the first step structure STS1, and the right part may correspond to the second step structure STS2. Fig. 11B The left half of the structure may correspond to the first step structure STS1, and Fig. 11B The right half of the structure may correspond to the second stepped structure STS2.

[0090] In the trimming process, the upper portion of the insulating layer dam ID may be etched, and in the stepped structure of the extension area EA, the top surface of the insulating layer dam ID may be at the same level as the top surface of the exposed sacrificial layer SL. For example, in the first stepped structure STS1, the top surface of the insulating layer dam ID may be coplanar with the top surface of the odd-numbered sacrificial layer SL, and in the second stepped structure STS2, the top surface of the insulating layer dam ID may be coplanar with the top surface of the even-numbered sacrificial layer SL.

[0091] The step structure of the extension area EA is not limited to a step structure with two layers added or reduced. For example, the step structure of the extension area EA may have a step structure with one layer added or reduced. When the extension area is formed with a step structure, it is possible to manufacture Figure 5 A vertical nonvolatile memory device 100b is provided.

[0092] Reference Fig. 12A and Fig. 12B, an additional sacrificial layer SLa may be formed on the exposed sacrificial layer SL and the insulating layer dam ID in the step structure in the extension area EA. The additional sacrificial layer SLa may include the same material as that of the sacrificial layer SL. For example, the additional sacrificial layer SLa may include silicon nitride. The material of the additional sacrificial layer SLa is not limited thereto. In addition, although the additional sacrificial layer SLa includes the same material as that of the sacrificial layer SL, by providing slight differences, such as changing the component ratio, the additional sacrificial layer SLa may have a higher etching rate than the sacrificial layer SL for the same etching solution. For example, for a phosphoric acid solution (HP), the additional sacrificial layer SLa may be etched faster than the sacrificial layer SL. However, in some exemplary embodiments of the inventive concept, the additional sacrificial layer SLa and the sacrificial layer SL may include substantially the same material.

[0093] The process of forming the additional sacrificial layer SLa is briefly described as follows. First, a first material layer covering the mold structure 210 can be deposited relatively thickly on the entire surface of the substrate 101. The first material layer can be a material layer for the additional sacrificial layer SLa. Next, the first material layer can be thinned by wet etching. In this case, all the first material layers on the side of the step structure in the extension area EA can be removed. Subsequently, a photoresist (PR) pattern covering the extension area EA can be formed, and the first material layer on the cell array area CAA can be removed by using the PR pattern. Next, by removing the PR pattern, an additional sacrificial layer SLa can be formed on the sacrificial layer SL and the insulating layer dam ID exposed in the step structure of the extension area EA.

[0094] like Fig. 12A As shown in , since the additional sacrificial layer SLa is not formed at the side end ELe of the step structure of the extension area EA, a second gap G2 may be formed between the side end ELe of the step structure and the additional sacrificial layer SLa. The sacrificial layer SL under the additional sacrificial layer SLa may be exposed by the second gap G2. For example, more than one sacrificial layer SL under the additional sacrificial layer SLa may be exposed by the second gap G2.

[0095] As described above, the first stepped structure STS1 and the second stepped structure STS2 may have a difference of one layer at the same position in the first direction (x direction). Fig. 11BIn the case where the left side corresponds to the first step structure STS1, the sacrificial layer SL on the ninth layer may be exposed, and where the right side corresponds to the second step structure STS2, the sacrificial layer SL on the eighth layer may be exposed. As described above, since the first step structure STS1 and the second step structure STS2 form different layers at the same position in the first direction (x direction), a first gap G1 may be formed between the side surface of the first step structure STS1 and the additional sacrificial layer SLa. The sacrificial layer SL under the additional sacrificial layer SLa may be exposed by the first gap G1.

[0096] The first gap G1 may extend along the first direction (x direction) on each layer of the step structure. The first gap G1 may be aligned with the aforementioned first pad gap ( Figure 2 The additional sacrificial layer SLa may be divided into a first additional sacrificial layer SLa1 and a second additional sacrificial layer SLa2 by the first gap G1, and thereafter, the first additional sacrificial layer SLa1 and the second additional sacrificial layer SLa2 may be replaced by a portion of the first electrode pad ELp1 and a portion of the second electrode pad ELp2, respectively.

[0097] Reference Fig.13A and Fig. 13B , a second material layer covering the molding structure 210 may be deposited on the entire surface of the substrate 101, and a planarization insulating layer 150 may be formed by planarizing the second material layer. The second material layer may cover the molding structure 210 in the cell array area CAA and the molding structure 210 of the step structure and the additional sacrificial layer SLa in the extension area EA. The second material layer may include an insulating material, for example, an oxide. The material of the second material layer is not limited thereto.

[0098] Next, a vertical hole penetrating the mold structure 210 may be formed in the cell array area CAA. Next, a lower semiconductor pattern LSP filling a lower portion of the vertical hole is formed. The lower semiconductor pattern LSP may be formed by using selective epitaxial growth (SEG) using the substrate 101 exposed by the vertical hole as a seed layer. Subsequently, in the cell array area CAA, a vertical channel structure VCS may be formed by forming a data storage pattern VP, an upper semiconductor pattern USP, and a buried insulating pattern VI in the vertical hole. Thereafter, a bit line pad BP may be formed on the upper semiconductor pattern USP of the vertical channel structure VCS.

[0099] exist Figure 4In the case where the vertical nonvolatile memory device 100a includes a dummy channel structure DCS in the extension area EA, the dummy channel structure DCS in the extension area EA can be formed in the process of forming the vertical channel structure VCS. For example, a vertical hole penetrating the planarization insulating layer 150 and the molding structure 210 can be formed in the extension area EA. As the vertical hole becomes farther away from the cell array area CAA, the number of sacrificial layers SL penetrated by the vertical hole can be reduced. Next, a dummy channel structure DCS can be formed by forming a lower semiconductor pattern LSP, a data storage pattern VP, an upper semiconductor pattern USP, and a buried insulating pattern VI in the vertical hole. In some exemplary embodiments of the inventive concept, in the dummy channel structure DCS, the upper semiconductor pattern USP can be removed, and the buried insulating pattern VI can be formed directly on the data storage pattern VP.

[0100] Reference Fig.14 , a first upper interlayer insulating layer 160 covering the top surface of the vertical channel structure VCS and the planarizing insulating layer 150 may be formed on the entire surface of the substrate 101. Next, by etching the first upper interlayer insulating layer 160, the planarizing insulating layer 150, and the mold structure 210, a second trench T2 exposing the substrate 101 may be formed. A plurality of second trenches T2 may have a line shape extending in the first direction (x direction) and may be separated from each other in the second direction (y direction). The second trenches T2 may be separated from the vertical channel structure VCS and expose the sidewalls of the sacrificial layer SL and the interlayer insulating layer ILD of the mold structure 210. In addition, the second trenches T2 may expose the sidewalls of the additional sacrificial layer SLa arranged on the top portion of the step structure in the extension area EA. The cell array area CAA and the extension area EA may be divided into block units via the second trenches T2. However, when the second trenches T2 are formed, at least one additional second trench T2 extending in the first direction (x direction) may be formed in the cell array area CAA. In the additional second trench T2, an additional partitioning region may be formed later (see Figure 2 DAa in.

[0101] After forming the second trench T2 , a common source area CSA may be formed by doping impurities on the exposed upper region of the substrate 101 .

[0102] Reference Fig.15A and Fig. 15B, the sacrificial layer SL and the additional sacrificial layer SLa exposed through the second trench T2 may be removed. The sacrificial layer SL and the additional sacrificial layer SLa may be removed by isotropic etching using an etching solution having an etching selectivity with respect to the interlayer insulating layer ILD, the vertical channel structure VCS, and the substrate 101. For example, when the sacrificial layer SL and the additional sacrificial layer SLa are silicon nitride layers and the interlayer insulating layer ILD is a silicon oxide layer, the sacrificial layer SL and the additional sacrificial layer SLa may be removed by performing an isotropic etching process using an etching solution containing phosphoric acid.

[0103] By performing a removal process on the sacrificial layer SL and the additional sacrificial layer SLa, the sacrificial layer SL in the cell array area CAA, the sacrificial layer SL between the second trench T2 and the insulating layer dam ID in the extension area EA, and the additional sacrificial layer SLa in the extension area EA can be removed. In addition, the sacrificial layer SL under the additional sacrificial layer SLa between the insulating layer dams ID adjacent to each other in the second direction (y direction) can be retained without being etched. Therefore, the second stacked structure SST2 can be retained between the insulating layer dams ID.

[0104] In addition, as described above, the additional sacrificial layer SLa may be etched faster than the sacrificial layer SL. Therefore, in some exemplary embodiments of the inventive concept, the additional sacrificial layer SLa between the insulating layer dams ID and a portion of the sacrificial layer SL directly under the additional sacrificial layer SLa may be etched and removed.

[0105] Reference Fig.16 After removing the sacrificial layer SL and the additional sacrificial layer SLa, the portion from which the sacrificial layer SL and the additional sacrificial layer SLa have been removed may be filled with a first conductive layer. The first conductive layer may include a barrier layer and a metal layer. The barrier layer may include, for example, TiN, TaN, or WN, and the metal layer may include, for example, W. However, the materials of the barrier layer and the metal layer are not limited thereto.

[0106] Thereafter, the first conductive layer located on the inner wall of the second trench T2 may be removed by anisotropic etching. After the anisotropic etching, the first conductive layer remaining between the interlayer insulating layer ILD may constitute the first gate electrode layer EL1 and the second gate electrode layer EL2. In addition, the first conductive layer remaining in the extension area EA may constitute the electrode pads (ELp1 and ELp2).

[0107] The entire process of removing the sacrificial layer SL and replacing the removed portion with the first gate electrode layer EL1 and the second gate electrode layer EL2 may be referred to as a gate electrode layer replacement process. In the method of manufacturing a vertical non-volatile memory device according to an exemplary embodiment of the inventive concept, by forming the first gate electrode layer EL1 and the second gate electrode layer EL2 using a gate electrode layer replacement process, a first stacked structure SST1 may be formed in a portion of the extension area EA and the cell array area CAA. In addition, when the first gate electrode layer EL1 and the second gate electrode layer EL2 are formed, an electrode pad (ELp1 and ELp2) may be formed on the step structure in the extension area EA. The electrode pad (ELp1 and ELp2) may be formed by replacing a portion of the additional sacrificial layer SLa and the sacrificial layer SL with a first conductive layer, and the first stacked structure SST1 and the second stacked structure SST2 may be arranged together under the electrode pad (ELp1 and ELp2). In other words, the electrode pad (ELp1 and ELp2) may include a first pad area PA1 on the first stacked structure SST1 and a second pad area PA2 on the second stacked structure SST2.

[0108] Next, an insulating spacer IS and a common source plug CSP may be formed in the second trench T2. The common source plug CSP may be connected to the common source area CSA. In some exemplary embodiments of the inventive concept, the common source area CSA may be formed after a replacement process of the first gate electrode layer EL1 and the second gate electrode layer EL2.

[0109] Next, a second upper interlayer insulating layer 170 may be formed on the first upper interlayer insulating layer 160 .

[0110] Reference Fig.17A and Fig. 17B , a first hole H1 penetrating the first upper interlayer insulating layer 160, the second upper interlayer insulating layer 170, and the planarizing insulating layer 150 may be formed in the extension area EA. After an etching mask pattern is formed on the second upper interlayer insulating layer 170, the first hole H1 may be formed by anisotropically etching the first upper interlayer insulating layer 160, the second upper interlayer insulating layer 170, and the planarizing insulating layer 150.

[0111] Next, by burying the first hole H1 with the second conductive layer, a vertical contact VC connected to each of the electrode pads (ELp1 and ELp2) may be formed. Subsequently, the above-described bit line contact plug BCP, sub bit lines SBL, bit lines BL, and connection lines CL may be formed.

[0112] While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concept as set forth in the following claims.

Claims

1. A vertical non-volatile memory device, comprising: a substrate including a cell array region and an extension region, the extension region extending from the cell array region along a first direction and including a vertical contact; A vertical channel structure extending in a vertical direction from a top surface of the substrate; A first stacked structure including gate electrode layers and interlayer insulating layers alternately stacked along a sidewall of the vertical channel structure; a plurality of division regions extending along a first direction and dividing the cell array region and the extension region into a plurality of cells along a second direction perpendicular to the first direction; two insulating layer dams, arranged in the extension region between two division regions adjacent to each other along the second direction among the plurality of division regions, wherein the two insulating layer dams extend along the first direction; a second stacked structure including sacrificial layers and interlayer insulating layers alternately stacked on the substrate between the two insulating layer dams; and an electrode pad connected to a first gate electrode layer in the gate electrode layer in the extension region, The first stacked structure extends from the cell array region to a region between one of the insulating layer dams in the extension region and one of the partition regions, The electrode pad includes a first pad region located on the first stacked structure and a second pad region located on the second stacked structure, and The first vertical contact penetrates the electrode pad and is inserted into the second stack structure, wherein the first pad region and the second pad region are connected to each other on a top surface of one of the insulating layer dams, and The first pad region is connected to the corresponding gate electrode layer.

2. The vertical nonvolatile memory device according to claim 1, wherein: In the vertical direction, the first pad region is thicker than the gate electrode layer in the cell array region.

3. The vertical nonvolatile memory device according to claim 1, wherein: In the vertical direction, the first pad region is thicker than the second pad region, and A lower portion of the first pad region contacts a sidewall of the one insulating layer dam and is connected to at least one of the gate electrode layers.

4. The vertical nonvolatile memory device according to claim 1, wherein: The electrode pad is divided into a first electrode pad and a second electrode pad by a pad gap extending along a first direction between the two insulating layer dams, and The first vertical direct contact is connected to the first electrode pad, and the second vertical direct contact is connected to the second electrode pad.

5. The vertical nonvolatile memory device according to claim 4, wherein: End portions of each of the first electrode pad and the second electrode pad in the first direction have different heights from each other in the vertical direction.

6. The vertical nonvolatile memory device according to claim 4, wherein: The gate electrode layer has a step structure along a first direction in the extension region, The gate electrode layers corresponding to the first electrode pads have a stepped structure every two layers, and a single odd-numbered gate electrode layer constitutes an upper layer. The gate electrode layers corresponding to the second electrode pads have a stepped structure every two layers, and a single even-numbered gate electrode layer constitutes an upper layer. The first electrode pad is connected to the odd-numbered gate electrode layer, and The second electrode pads are connected to the even-numbered gate electrode layers.

7. The vertical nonvolatile memory device according to claim 1, wherein: In the cell array region, another division region extending in the first direction is arranged between the two division regions adjacent to each other in the second direction.

8. The vertical nonvolatile memory device according to claim 1, wherein: The peripheral circuit region is disposed on a lower portion of the substrate.

9. The vertical nonvolatile memory device according to claim 1, wherein: The vertical channel structure has a first vertical channel structure located in the cell array region and a second vertical channel structure located in the extension region, and The second vertical channel structure is arranged in a portion of the extension region in which the first stack structure is formed.

10. A vertical non-volatile memory device, comprising: A substrate including a cell array region and an extension region extending from the cell array region along a first direction; A vertical channel structure extending in a vertical direction from a top surface of the substrate; A first stacked structure including gate electrode layers and interlayer insulating layers alternately stacked along a sidewall of the vertical channel structure; a division region extending along a first direction and dividing the cell array region and the extension region into a plurality of cells along a second direction perpendicular to the first direction; two insulating layer dams, arranged in the extension region between two division regions adjacent to each other along the second direction, wherein the two insulating layer dams extend along the first direction; a second stacked structure, comprising sacrificial layers and interlayer insulating layers alternately stacked on the substrate between the two insulating layer dams; an electrode pad connected to a first gate electrode layer among the gate electrode layers and arranged in the extension region, the electrode pad comprising a first pad region located on the first stacked structure and a second pad region located on the second stacked structure, wherein the electrode pad overlaps at least one of the insulating layer dams in a vertical direction; and The first vertical contact is arranged in the extension area and inserted into the second stack structure via the second pad area of ​​the electrode pad.

11. The vertical nonvolatile memory device according to claim 10, wherein: The electrode pad has a protruding pad structure thicker than each of the gate electrode layers in the cell array region in a vertical direction, A lower portion of the first pad region contacts a side surface of one of the insulating layer dams, and The first pad region is connected to the second pad region on a top surface of the one insulating layer dam.

12. The vertical nonvolatile memory device according to claim 10, wherein: A first stacked structure under the first pad region is located between one of the partition regions and one of the insulating layer dams in the extension region, and At least one of the gate electrode layers is connected to the first pad region.

13. The vertical nonvolatile memory device according to claim 10, wherein: The electrode pad is divided into a first electrode pad and a second electrode pad by a pad gap extending along a first direction between the two insulating layer dams. The first electrode pad and the second electrode pad have side ends located at substantially the same position in the first direction and have different heights from each other in the vertical direction, and The first vertical direct contact is connected to the first electrode pad, and the second vertical direct contact is connected to the second electrode pad.

14. The vertical nonvolatile memory device according to claim 13, wherein: The gate electrode layer has a step structure along a first direction in the extension region, The gate electrode layers corresponding to the first electrode pads have a stepped structure every two layers, and a single odd-numbered gate electrode layer constitutes an upper layer. The gate electrode layers corresponding to the second electrode pads have a stepped structure every two layers, and a single even-numbered gate electrode layer constitutes an upper layer. The first electrode pad is connected to the odd-numbered gate electrode layer, and The second electrode pads are connected to the even-numbered gate electrode layers.

15. The vertical nonvolatile memory device according to claim 10, wherein: In the cell array region, another division region extending in the first direction is arranged between the two division regions adjacent to each other in the second direction, The vertical channel structure includes a first vertical channel structure located in the cell array region and a second vertical channel structure located in the extension region, and The second vertical channel structure is arranged in a portion of the extension region in which the first stack structure is formed.

16. A vertical non-volatile memory device, the device comprising: a substrate including a cell array region and an extension region, the extension region extending from the cell array region along a first direction and including a vertical contact; A vertical channel structure extending in a vertical direction from a top surface of the substrate; A first stacked structure including gate electrode layers and interlayer insulating layers alternately stacked along a sidewall of the vertical channel structure; a plurality of division regions extending along a first direction and dividing the cell array region and the extension region into a plurality of cells along a second direction perpendicular to the first direction; two insulating layer dams, arranged in the extension region between two division regions adjacent to each other along the second direction among the plurality of division regions, wherein the two insulating layer dams extend along the first direction; a second stacked structure including sacrificial layers and interlayer insulating layers alternately stacked on the substrate between two insulating layer dams; and a first electrode pad connected to a first gate electrode layer in the gate electrode layers in the extension region; and a second electrode pad connected to a first sacrificial layer among the sacrificial layers in the extension region, Among them, one of the two insulating layer dams is arranged under the first electrode pad, and the other insulating layer dam is arranged under the second electrode pad.

17. The vertical nonvolatile memory device according to claim 16, wherein: The first electrode pad is higher than the second electrode pad in the vertical direction.

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