Decoding method, system, device and computer readable storage medium

Abstract

The present disclosure provides a decoding method, system, device and computer-readable storage medium, which relate to the field of communication technology. The decoding method includes: a decoding controller inputs first coded information into a first segmented CRC-SCL decoder; the first segmented CRC-SCL decoder decodes the first coded information and outputs the first decoded information; after the first segmented CRC-SCL decoder outputs the first decoded information, the decoding controller inputs the second coded information into the first segmented CRC-SCL decoder; wherein the first coded information and the second coded information are the coding results of different segments of the same transmission information; the first segmented CRC-SCL decoder decodes the second coded information and outputs the second decoded information; the merger merges the first decoded information and the second decoded information to obtain a decoding result. The present disclosure can reduce the resource requirements of the decoder during the decoding process and reduce the decoding cost by reusing the decoder.

Description

Technical Field

[0001] The present disclosure relates to the field of communication technology, and in particular to a decoding method, system, device and computer-readable storage medium. Background Art

[0002] The traditional segmented XOR CRC-SCL (Cyclic Redundancy Check-Successive cancellation List) coding and decoding method uses the XOR CRC code as the CRC code of the segmented information codeword, and uses the XOR CRC code to imply the check information of the two segments of information codewords, achieving a check performance close to twice the length of the CRC code. This coding and decoding method performs full parallel decoding of the segmented information codewords without reducing the coding efficiency and slightly reducing the check performance, which can greatly reduce the decoding delay. Summary of the invention

[0003] A technical problem solved by the present disclosure is how to reduce the resource requirements of the decoder during the decoding process.

[0004] According to one aspect of an embodiment of the present disclosure, a decoding method is provided, including: a decoding controller inputs first coded information into a first segmented CRC-SCL decoder; the first segmented CRC-SCL decoder decodes the first coded information and outputs first decoded information; after the first segmented CRC-SCL decoder outputs the first decoded information, the decoding controller inputs second coded information into the first segmented CRC-SCL decoder; wherein the first coded information and the second coded information are coding results of different segments of the same transmission information; the first segmented CRC-SCL decoder decodes the second coded information and outputs second decoded information; a merger merges the first decoded information and the second decoded information to obtain a decoding result.

[0005] In some embodiments, the decoding method further includes: after the first segment CRC-SCL decoder outputs the second decoding information, the decoding controller sequentially inputs the encoding results of the remaining different segments of the transmission information into the first segment CRC-SCL decoder; the first segment CRC-SCL decoder sequentially decodes the encoding results of the remaining different segments and outputs the decoding information of the encoding results of the remaining different segments; the merger merges the decoding results and the decoding information of the encoding results of the remaining different segments to obtain the transmission information.

[0006] In some embodiments, the decoding method also includes: after the decoding controller inputs the first coded information into the first segmented CRC-SCL decoder, the third coded information is input into the second segmented CRC-SCL decoder; wherein the first coded information, the second coded information, and the third coded information are the coding results of different segments of the same transmission information; the second segmented CRC-SCL decoder decodes the third coded information and outputs the third decoded information; the merger merges the first decoded information and the second decoded information to obtain the decoding result, including: the merger merges the first decoded information, the third decoded information and the second decoded information to obtain the decoding result.

[0007] In some embodiments, the decoding method further includes: when the decoding delay is greater than the first threshold, adding a segmented CRC-SCL decoder to decode the encoding results of the remaining different segments of the transmission information.

[0008] In some embodiments, the decoding method further includes: when the decoding delay is less than a second threshold, deleting the segmented CRC-SCL decoder to use the reserved segmented CRC-SCL decoder to decode the encoding results of the remaining different segments of the transmission information.

[0009] According to another aspect of an embodiment of the present disclosure, a decoding system is provided, including: a decoding controller, configured to: input first coding information into a first segmented CRC-SCL decoder; after the first segmented CRC-SCL decoder outputs the first decoding information, input second coding information into the first segmented CRC-SCL decoder; wherein the first coding information and the second coding information are coding results of different segments of the same transmission information; the first segmented CRC-SCL decoder, configured to: decode the first coding information and output first decoding information; decode the second coding information and output second decoding information; a merger, configured to: merge the first decoding information and the second decoding information to obtain a decoding result.

[0010] In some embodiments, the decoding controller is further configured to: after the first segment CRC-SCL decoder outputs the second decoding information, sequentially input the encoding results of the remaining different segments of the transmission information into the first segment CRC-SCL decoder; the first segment CRC-SCL decoder is further configured to: sequentially decode the encoding results of the remaining different segments, and output the decoding information of the encoding results of the remaining different segments; the merger is further configured to: merge the decoding results and the decoding information of the encoding results of the remaining different segments to obtain the transmission information.

[0011] In some embodiments, the decoding system also includes a second segmented CRC-SCL decoder; the decoding controller is also configured to: after inputting the first encoded information into the first segmented CRC-SCL decoder, input the third encoded information into the second segmented CRC-SCL decoder; wherein the first encoded information, the second encoded information, and the third encoded information are the encoding results of different segments of the same transmission information; the second segmented CRC-SCL decoder is configured to: decode the third encoded information and output the third decoded information; the merger is configured to: merge the first decoded information, the third decoded information and the second decoded information to obtain a decoding result.

[0012] In some embodiments, the decoding system further comprises a segmented CRC-SCL decoder adder configured to: when the decoding delay is greater than a first threshold, add a segmented CRC-SCL decoder to decode the encoding results of the remaining different segments of the transmission information.

[0013] In some embodiments, the decoding system also includes a segmented CRC-SCL decoder deleter, which is configured to: when the decoding delay is less than a second threshold, delete the segmented CRC-SCL decoder to use the retained segmented CRC-SCL decoder to decode the encoding results of the remaining different segments of the transmitted information.

[0014] According to another aspect of an embodiment of the present disclosure, a decoding device is provided, including: a memory; and a processor coupled to the memory, wherein the processor is configured to execute the aforementioned decoding method based on instructions stored in the memory.

[0015] According to another aspect of the embodiments of the present disclosure, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and when the instructions are executed by a processor, the aforementioned decoding method is implemented.

[0016] The present disclosure can reduce the resource requirements of the decoder during the decoding process and reduce the decoding cost by reusing the decoder.

[0017] Other features and advantages of the present disclosure will become apparent from the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0019] Figure 1 A flowchart of a decoding method according to some embodiments of the present disclosure is shown.

[0020] Figure 2 A schematic diagram showing an application example of the decoding method disclosed in the present invention.

[0021] Figure 3 A schematic diagram showing another application example of the decoding method disclosed in the present invention.

[0022] Figure 4 A schematic flow chart of a decoding method according to some other embodiments of the present disclosure is shown.

[0023] Figure 5 A schematic diagram of the structure of a decoding system according to some embodiments of the present disclosure is shown.

[0024] Figure 6 A schematic structural diagram of a decoding device according to some embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0025] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is by no means intended to limit the present disclosure and its application or use. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0026] First combine Figure 1 Some embodiments of the decoding method disclosed herein are described.

[0027] Figure 1 FIG. 1 is a flow chart showing a decoding method according to some embodiments of the present disclosure. Figure 1 As shown, this embodiment includes steps S101 to S105.

[0028] In step S101, the decoding controller inputs the first coded information into the first segmented CRC-SCL decoder.

[0029] The first segmented CRC-SCL decoder may specifically be a segmented XOR CRC-SCL decoder.

[0030] In step S102, the first segmented CRC-SCL decoder decodes the first coded information and outputs first decoded information.

[0031] In step S103, the decoding controller inputs the second coded information into the first segmented CRC-SCL decoder after the first segmented CRC-SCL decoder outputs the first decoded information.

[0032] The first coded information and the second coded information are coding results of different segments of the same transmission information. The first coded information and the second coded information can be continuous coded information or discontinuous coded information.

[0033] In step S104, the first segmented CRC-SCL decoder decodes the second coded information and outputs second decoded information.

[0034] In step S105, the merger combines the first decoding information and the second decoding information to obtain a decoding result.

[0035] By reusing the decoder, this embodiment can reduce the hardware resource requirements of the decoder during the decoding process without reducing the coding rate and the verification capability, thereby reducing the decoding cost.

[0036] In some embodiments, in step S101, after the decoding controller inputs the first coded information into the first segmented CRC-SCL decoder, the third coded information is input into the second segmented CRC-SCL decoder. The first coded information, the second coded information, and the third coded information are the coding results of different segments of the same transmission information; the second segmented CRC-SCL decoder decodes the third coded information and outputs the third decoded information. The second segmented CRC-SCL decoder can specifically be a segmented XOR CRC-SCL decoder. In step S105, the merger merges the first decoding information, the third decoding information, and the second decoding information to obtain a decoding result.

[0037] For ease of understanding, combined Figure 2 Give a specific application example.

[0038] Figure 2 FIG. 1 is a schematic diagram showing an application example of the decoding method disclosed in the present invention. Figure 2 As shown, when the decoding controller detects the complete first and second segments of coded information, the first segment XOR CRC-SCL decoder is started to start decoding, and after the decoding is completed, the result is output to the merger for sequential output. When the decoding controller detects the complete third segment of coded information, the second segment XOR CRC-SCL decoder is started to start decoding, and after the decoding is completed, the decoding result is output to the merger for sequential output, and so on, until the decoding of all segment coded information is completed.

[0039] Those skilled in the art should understand that the first - stage coding information, the second - stage coding information, and the third - stage coding information are consecutive coding information, and the coding information is distributed to each segmented decoder in the order of the first - stage coding information, the second - stage coding information, the third - stage coding information...

[0040] Specifically, when the decoding controller detects that the first XOR CRC - SCL decoder has completed decoding and receives the complete (N + 1) - th segment of coding information, it starts the first XOR CRC - SCL decoder for the second time to perform the decoding of the (N + 1) - th segment of coding information. After the decoding is completed, the decoding result is output to the combiner for sequential output. When the decoding controller detects that the second XOR CRC - SCL decoder has completed decoding and receives the complete (N + 2) - th segment of coding information, it starts the second XOR CRC - SCL decoder for the second time to perform the decoding of the (N + 2) - th segment of coding information, and so on until the decoding of the last segment of coding information is completed. If the decoding delay of a single decoder is small enough, N decoders may participate in the decoding of a complete coding information multiple times, resulting in a significant reduction in the hardware resource requirements of the decoder.

[0041] Assume that the duration of the coding information is t1, and it is divided into m segments for segmented XOR CRC - SCL polarization coding. The segmented XOR CRC - SCL decoder takes t2 time to complete the decoding of one segment of coding information. If t2 is greater than (1 - 3 / m)*t1, (N = m), when the decoding controller detects the complete last segment of coding information, it starts the last segmented XOR CRC - SCL decoder to start decoding. After the decoding is completed, the decoding result is output to the combiner for sequential output. At this time, for m - segment fully parallel segmented XOR CRC - SCL decoding, the decoding delay is (1 + 2 / m)t1 + t2. If t2 is not greater than (1 - 3 / m)*t1, (N < m), when the decoding controller detects the complete (N + 1) - th segment of coding information, it starts the first XOR CRC - SCL decoder for the second time to perform the decoding of the (N + 1) - th segment of coding information. After the decoding is completed, the decoding result is output to the combiner for sequential output. And so on until the decoding of the last segment of coding information is completed. If t2 is small enough, N decoders may participate in the decoding of a complete coding information multiple times, and the complexity of the decoder will be significantly reduced.

[0042] In this embodiment, when a short decoding delay is required and the hardware resource requirements are small, multiple segmented XOR CRC - SCL decoders are reused for parallel / serial hybrid decoding. Compared with the fully parallel segmented XOR CRC - SCL decoder, the hardware resource requirements are less and the decoding cost is lower.

[0043] In some embodiments, the decoding method further includes steps S106 to S108.

[0044] In step S106, after the first segment CRC-SCL decoder outputs the second decoded information, the decoding controller sequentially inputs the encoding results of the remaining different segments of the transmission information into the first segment CRC-SCL decoder.

[0045] In step S107, the first segment CRC-SCL decoder decodes the encoding results of the remaining different segments in turn, and outputs decoding information of the encoding results of the remaining different segments.

[0046] In step S108, the merger combines the decoding result and the decoding information of the encoding results of the other different segments to obtain transmission information.

[0047] For ease of understanding, combined Figure 3 Give a specific application example.

[0048] Figure 3 FIG. 2 is a schematic diagram showing another application example of the decoding method disclosed in the present invention. Figure 3 As shown, when the decoding controller detects the complete first and second segments of coded information, the segmented XOR CRC-SCL decoder is started to start decoding, and the decoding result is output to the shift register after the decoding is completed. When the decoder controller detects the complete third segment of coded information, if the segmented XOR CRC-SCL decoder has completed the decoding of the first segment of coded information, the segmented XOR CRC-SCL decoder is controlled to decode the second segment of coded information, otherwise, the decoding of the second segment of coded information is started after the segmented XOR CRC-SCL decoder completes the decoding of the first segment of coded information; and so on, until the decoding of all segment coded information is completed.

[0049] Assume that the coded information duration is t1, and it is divided into m segments for XOR CRC-SCL polarization coding. The XOR CRC-SCL decoder uses t2 time to complete the decoding of one segment of coded information. When the segment decoding delay is less than the segment coding information duration, the decoding delay is (1+2 / m)t1+t2; when the segment decoding delay is greater than the segment coding information duration, the decoding delay is 2t1 / m+mt2.

[0050] This embodiment repeatedly uses a segmented XOR CRC-SCL decoder for serial decoding while requiring the minimum hardware resource requirements and not requiring high decoding delay. Compared with the full parallel segmented XOR CRC-SCL decoder, it requires the least hardware resources, consumes the least power, and has the lowest cost. Under the premise of not requiring high decoding delay, this embodiment can minimize the hardware resource requirements of the decoder, reduce the power consumption and cost of the decoder, and is suitable for low-cost, low-power, wearable, and micro-terminal channel decoders.

[0051] Combine the following Figure 4Other embodiments of the decoding method disclosed in the present invention are described. These embodiments are applicable to software working scenarios such as cloud computing.

[0052] Figure 4 FIG. 2 is a flow chart showing a decoding method according to another embodiment of the present disclosure. Figure 4 As shown, this embodiment includes steps S401 to S403.

[0053] In step S401, the quantitative relationship between the decoding delay and the first threshold and the second threshold is determined.

[0054] When the decoding delay is greater than the first threshold, step S402 is executed. In step S402, a segmented CRC-SCL decoder is added to decode the encoding results of the remaining different segments of the transmission information.

[0055] When the decoding delay is greater than the first threshold, step S403 is executed. In step S403, the segment CRC-SCL decoder is deleted to use the reserved segment CRC-SCL decoder to decode the encoding results of the remaining different segments of the transmission information.

[0056] The added or deleted segmented CRC-SCL decoder may be a segmented XOR CRC-SCL decoder.

[0057] This embodiment can adaptively adjust the number of segmented CRC-SCL decoders according to the decoding delay, thereby reducing the resource requirements for the decoders while ensuring the decoding delay.

[0058] Combine the following Figure 5 Some embodiments of the disclosed decoding system are described.

[0059] Figure 5 FIG. 2 shows a schematic diagram of the structure of a decoding system in some embodiments of the present disclosure. Figure 5 As shown, the decoding system 50 in this embodiment includes:

[0060] The decoding controller 501 is configured to: input the first coded information into the first segmented CRC-SCL decoder; after the first segmented CRC-SCL decoder outputs the first decoded information, input the second coded information into the first segmented CRC-SCL decoder; wherein the first coded information and the second coded information are the coding results of different segments of the same transmission information; the first segmented CRC-SCL decoder 502 is configured to: decode the first coded information and output the first decoded information; decode the second coded information and output the second decoded information; the merger 503 is configured to: merge the first decoded information and the second decoded information to obtain a decoding result.

[0061] By reusing the decoder, this embodiment can reduce the hardware resource requirements of the decoder during the decoding process without reducing the coding rate and the verification capability, thereby reducing the decoding cost.

[0062] In some embodiments, the decoding controller 501 is further configured to: after the first segment CRC-SCL decoder outputs the second decoding information, sequentially input the encoding results of the remaining different segments of the transmission information into the first segment CRC-SCL decoder; the first segment CRC-SCL decoder 502 is further configured to: sequentially decode the encoding results of the remaining different segments, and output the decoding information of the encoding results of the remaining different segments; the merger 503 is further configured to: merge the decoding results and the decoding information of the encoding results of the remaining different segments to obtain the transmission information.

[0063] This embodiment repeatedly uses a segmented XOR CRC-SCL decoder for serial decoding while requiring the minimum hardware resource requirements and not requiring high decoding delay. Compared with the full parallel segmented XOR CRC-SCL decoder, it requires the least hardware resources, consumes the least power, and has the lowest cost. Under the premise of not requiring high decoding delay, this embodiment can minimize the hardware resource requirements of the decoder, reduce the power consumption and cost of the decoder, and is suitable for low-cost, low-power, wearable, and micro-terminal channel decoders.

[0064] In some embodiments, the decoding system 50 also includes a second segmented CRC-SCL decoder 504; the decoding controller 501 is also configured to: after inputting the first encoded information into the first segmented CRC-SCL decoder, input the third encoded information into the second segmented CRC-SCL decoder; wherein the first encoded information, the second encoded information, and the third encoded information are the encoding results of different segments of the same transmission information; the second segmented CRC-SCL decoder 504 is configured to: decode the third encoded information and output the third decoded information; the merger is configured to: merge the first decoded information, the third decoded information and the second decoded information to obtain a decoding result.

[0065] In this embodiment, when a shorter decoding delay is required and a smaller hardware resource requirement is required, multiple segmented XOR CRC-SCL decoders are repeatedly used to perform parallel / serial mixed decoding. Compared with a fully parallel segmented XOR CRC-SCL decoder, the hardware resource requirement is less and the decoding cost is lower.

[0066] In some embodiments, the decoding system 50 further includes a segmented CRC-SCL decoder adder 505 configured to add a segmented CRC-SCL decoder to decode the encoding results of the remaining different segments of the transmitted information when the decoding delay is greater than the first threshold.

[0067] In some embodiments, the decoding system also includes a segmented CRC-SCL decoder deleter 506, which is configured to: when the decoding delay is less than a second threshold, delete the segmented CRC-SCL decoder to use the retained segmented CRC-SCL decoder to decode the encoding results of the remaining different segments of the transmitted information.

[0068] This embodiment can adaptively adjust the number of segmented CRC-SCL decoders according to the decoding delay, thereby reducing the resource requirements for the decoders while ensuring the decoding delay.

[0069] Combine the following Figure 6 Some embodiments of the decoding device disclosed herein are described.

[0070] Figure 6 FIG. 2 shows a schematic diagram of the structure of a decoding device in some embodiments of the present disclosure. Figure 6 As shown, the decoding device 60 of this embodiment includes: a memory 610 and a processor 620 coupled to the memory 610 , and the processor 620 is configured to execute the decoding method in any of the aforementioned embodiments based on instructions stored in the memory 610 .

[0071] The memory 610 may include, for example, a system memory, a fixed non-volatile storage medium, etc. The system memory may store, for example, an operating system, an application program, a boot loader, and other programs.

[0072] The decoding device 60 may also include an input / output interface 630, a network interface 640, a storage interface 650, etc. These interfaces 630, 640, 650, the memory 610, and the processor 620 may be connected, for example, via a bus 660. The input / output interface 630 provides a connection interface for input / output devices such as a display, a mouse, a keyboard, and a touch screen. The network interface 640 provides a connection interface for various networked devices. The storage interface 650 provides a connection interface for external storage devices such as an SD card and a USB flash drive.

[0073] The present disclosure also includes a computer-readable storage medium on which computer instructions are stored. When the instructions are executed by a processor, the decoding method in any of the aforementioned embodiments is implemented.

[0074] The present disclosure is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present disclosure. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0075] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0076] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0077] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A decoding method, comprising: The decoding controller inputs the first coded information into the first segmented CRC-SCL decoder; The first segmented CRC-SCL decoder decodes the first coded information and outputs first decoded information; The decoding controller inputs the second coded information into the first segmented CRC-SCL decoder after the first segmented CRC-SCL decoder outputs the first decoded information; After the decoding controller inputs the first coded information into the first segment CRC-SCL decoder, the decoding controller inputs the third coded information into the second segment CRC-SCL decoder; wherein the first coded information, the second coded information and the third coded information are the coding results of different segments of the same transmission information; The first segmented CRC-SCL decoder decodes the second coded information and outputs second decoded information; The second segmented CRC-SCL decoder decodes the third coded information and outputs third decoded information; The merger combines the first decoding information, the third decoding information and the second decoding information to obtain a decoding result.

2. The decoding method according to claim 1, further comprising: The decoding controller sequentially inputs the encoding results of the remaining different segments of the transmission information into the first segment CRC-SCL decoder after the first segment CRC-SCL decoder outputs the second decoding information; The first segment CRC-SCL decoder decodes the encoding results of the remaining different segments in sequence, and outputs decoding information of the encoding results of the remaining different segments; The merger combines the decoding result and the decoding information of the encoding results of the remaining different segments to obtain the transmission information.

3. The decoding method according to any one of claims 1 to 2, further comprising: When the decoding delay is greater than the first threshold, a segmented CRC-SCL decoder is additionally provided to decode the encoding results of the remaining different segments of the transmission information.

4. The decoding method according to claim 1, further comprising: When the decoding delay is less than the second threshold, the segment CRC-SCL decoder is deleted to use the reserved segment CRC-SCL decoder to decode the encoding results of the remaining different segments of the transmission information.

5. A decoding system comprising: A decoding controller is configured to: input the first coded information into a first segmented CRC-SCL decoder; After the first segment CRC-SCL decoder outputs the first decoded information, the second coded information is input into the first segment CRC-SCL decoder; after the first coded information is input into the first segment CRC-SCL decoder, the third coded information is input into the second segment CRC-SCL decoder; wherein the first coded information, the second coded information and the third coded information are coding results of different segments of the same transmission information; The first segmented CRC-SCL decoder is configured to: decode the first coded information and output the first decoded information; decode the second coded information and output the second decoded information; A second segmented CRC-SCL decoder is configured to: decode the third coded information and output third decoded information; The merger is configured to merge the first decoding information, the third decoding information and the second decoding information to obtain a decoding result.

6. The decoding system as claimed in claim 5, wherein: The decoding controller is further configured to: after the first segment CRC-SCL decoder outputs the second decoding information, sequentially input the encoding results of the remaining different segments of the transmission information into the first segment CRC-SCL decoder; The first segment CRC-SCL decoder is further configured to: sequentially decode the encoding results of the remaining different segments, and output decoding information of the encoding results of the remaining different segments; The merger is further configured to: merge the decoding result and the decoding information of the encoding results of the remaining different segments to obtain the transmission information.

7. The decoding system according to any one of claims 5 to 6, further comprising a segmented CRC-SCL decoder adder configured to: When the decoding delay is greater than the first threshold, a segmented CRC-SCL decoder is additionally provided to decode the encoding results of the remaining different segments of the transmission information.

8. The decoding system of claim 5, further comprising a segmented CRC-SCL decoder pruner configured to: When the decoding delay is less than the second threshold, the segment CRC-SCL decoder is deleted to use the reserved segment CRC-SCL decoder to decode the encoding results of the remaining different segments of the transmission information.

9. A decoding device, comprising: Memory; as well as A processor coupled to the memory, wherein the processor is configured to execute the decoding method according to any one of claims 1 to 4 based on instructions stored in the memory.

10. A computer-readable storage medium, wherein: The computer-readable storage medium stores computer instructions, and when the instructions are executed by a processor, the decoding method according to any one of claims 1 to 4 is implemented.

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