Depth camera with rotating bin

Abstract

Embodiments of the present disclosure relate to a depth map sensor having bin rotation. A depth map sensor includes: a first array of first pixels, each first pixel having a first photodetector associated with a pixel circuit, the pixel circuit including a plurality of first bins for accumulating events. A clock source is configured to generate a plurality of phase-shifted clock signals. A first circuit has a plurality of first output lines coupled to the first array of first pixels. The first circuit is configured to receive the plurality of phase-shifted clock signals. The first circuit includes a first block and a second block. The first block is configured to propagate the plurality of phase-shifted clock signals to the second block during a first period determined by a first enable signal, and the second block is configured to select which of the plurality of first output lines each of the plurality of phase-shifted clock signals is applied to.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the priority benefit of European Patent Application No. 19306416.9, filed on October 31, 2019, the content of which is hereby incorporated by reference in its entirety to the maximum extent permitted by law. Technical Field

[0003] The present disclosure relates to a depth map sensor with bin rotation. Background Art

[0004] Time-of-flight (ToF) cameras based on single-photon avalanche diodes (SPADs) are favored candidates for depth map sensors due to their ability to provide precise photon arrival times. Such ToF cameras typically include a light source such as a vertical-cavity surface-emitting laser (VCSEL) that emits light pulses or light waveforms into an image scene and an SPAD array for detecting the returned signal.

[0005] In the case of indirect ToF (iToF), the phase of the returned waveform is compared with the phase of the emitted waveform in order to estimate the time of flight, which is then converted into a distance measurement. In existing ToF cameras, circuits that are capable of performing precise time sampling of events within time windows (also known as bins) are typically used to detect the returned waveforms received by the SPAD array. However, any mismatch in these time windows results in non-uniformity in the time sampling, which in turn interferes with the precise detection of the phase of the returned waveforms and thus reduces the accuracy of the distance measurement. Summary of the Invention

[0006] The present disclosure generally relates to the field of time-of-flight (ToF) depth map sensors and, in particular, to a circuit and method for operating such sensors.

[0007] Embodiments can improve the accuracy of distance measurement methods and devices for depth map sensors.

[0008] One embodiment addresses all or some of the needs in the prior art for distance measurement methods and devices for depth map sensors.

[0009] One embodiment provides a depth map sensor that includes: a first array of first pixels, each first pixel including at least one first photodetector associated with a pixel circuit, the pixel circuit including a plurality of first bins for accumulating events. A clock source is configured to generate a plurality of phase-shifted clock signals. A first circuit has a plurality of first output lines coupled to the first array of first pixels and receives the plurality of phase-shifted clock signals. The first circuit includes a first block that propagates the plurality of phase-shifted clock signals to a second block during a first period determined by a first enable signal. The second block is configured to select which of the plurality of first output lines each of the phase-shifted clock signals is applied to.

[0010] According to one embodiment, the depth map sensor includes: a second array of second pixels, each second pixel including at least one second photodetector associated with a pixel circuit, the pixel circuit including a plurality of second bins for accumulating events; and a second circuit having a plurality of second output lines coupled to the second array of second pixels, the second circuit receiving the plurality of phase-shifted clock signals from the clock source. The second circuit includes a third block that propagates the plurality of phase-shifted clock signals to a fourth block during a second period determined by a second enable signal, wherein the duration of the second period is different from the duration of the first period. The fourth block is configured to select which of the plurality of second output lines each of the phase-shifted clock signals is applied to.

[0011] According to one embodiment, the selection performed by the fourth block is different from the selection performed by the second block.

[0012] According to one embodiment, the first array of first pixels is a return pixel array adapted to be illuminated by at least one light source of the depth map sensor, the at least one light source being configured to transmit light into an image scene. The second array of second pixels is a reference array.

[0013] According to one embodiment, a grouping of the first photodetectors of the first array of first pixels of the depth map sensor is illuminated during a first exposure phase. The grouping of the first photodetectors of the first array of first pixels of the depth map sensor is read during a first readout phase after the first exposure phase. The second photodetectors of the second array of second pixels of the depth map sensor are illuminated during a second exposure phase and then read during a second readout phase, the second exposure phase and the second readout phase of the second photodetectors being included in the first exposure phase of the grouping of the first photodetectors.

[0014] According to one embodiment, the first exposure phase includes: a first exposure sub-phase, during which a plurality of phase-shifted clock signals are applied to a plurality of first output lines of a first array of first pixels coupled to the depth map sensor in a first order; and at least one second exposure sub-phase, during which a plurality of phase-shifted clock signals are applied to a plurality of first output lines of a first array of first pixels coupled to the depth map sensor according to a cyclic circular shift.

[0015] According to one embodiment, the second exposure phase includes: a third exposure sub-phase, during which a plurality of phase-shifted clock signals are applied to a plurality of second output lines of a second array of second pixels coupled to the depth map sensor in a second order; and at least one fourth exposure sub-phase, during which a plurality of phase-shifted clock signals are applied to a plurality of second output lines of a second array of second pixels coupled to the depth map sensor according to a cyclic circular shift.

[0016] According to one embodiment, the first duration is less than the second duration.

[0017] According to one embodiment, the first duration is between 10 μs and 20 μs, and the second duration is between 50% and 95% of the first duration.

[0018] One embodiment provides a method of controlling a first array of first pixels of a depth map sensor, including: using a first block to propagate, during a first period determined by a first enable signal, a plurality of phase-shifted clock signals received by a first circuit and generated by a clock source to a second block, the first block being included in a first circuit having a plurality of first output lines coupled to the first array of first pixels. Each first pixel includes at least one first photodetector associated with a pixel circuit, and the pixel circuit includes a plurality of first bins for accumulating events. The second block selects which of the plurality of first output lines each of the plurality of phase-shifted clock signals is applied to.

[0019] According to one embodiment, the method includes: using a third block to propagate, during a second period having a duration different from the duration of the first period and determined by a second enable signal, a plurality of phase-shifted clock signals received by a second circuit from the clock source to a fourth block, the third block being included in a second circuit having a plurality of second output lines coupled to the second array of second pixels, wherein each second pixel includes at least one second photodetector associated with a pixel circuit, and the pixel circuit includes a plurality of second bins for accumulating events; and using the fourth block to select which of the plurality of second output lines each of the plurality of phase-shifted clock signals is applied to.

[0020] According to one embodiment, the selection performed by the fourth block is different from the selection performed by the second block. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The above and other features and advantages, as well as other features, will be described in detail in the following description of specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings, in which:

[0022] Figure 1 A top view of a depth map sensor according to an exemplary embodiment of the present disclosure is schematically illustrated in block form;

[0023] Figure 2 Schematically illustrates a Figure 1 pixel array of the depth map sensor according to an exemplary embodiment;

[0024] Figure 3 An example of a pixel circuit is schematically illustrated in block form;

[0025] Figure 4 is a timing diagram of signals in the Figure 3 pixel circuit;

[0026] Figures 5 to 8 is a timing diagram of signals in the Figure 3 pixel circuit;

[0027] Figure 9 is a timing diagram of operations of a Figure 1 depth map sensor according to an exemplary embodiment;

[0028] Figure 10 A part of a depth map sensor according to an exemplary embodiment is schematically illustrated in block form;

[0029] Figure 11 A Figure 10 pixel circuit associated with a Figure 3 timing generator according to an exemplary embodiment is schematically illustrated in block form;

[0030] Figure 12 is a Figure 11 timing diagram of a phase shift clock signal received by the timing generator;

[0031] Figures 13 to 16 is a timing diagram of signals in the Figure 3 pixel circuit according to an exemplary embodiment;

[0032] Figure 17 A Figure 1 timing generator of a depth map sensor according to an exemplary embodiment is schematically illustrated in block form;

[0033] Figure 18 Schematically illustrates a circuit configured to generate a phase shift signal according to an example embodiment;

[0034] Figure 19 represents according to an example embodiment Figure 18 a timing diagram of the operation of the circuit; and

[0035] Figure 20 illustrates according to an example embodiment Figure 17 a multiplexing circuit of the timing generator. DETAILED DESCRIPTION

[0036] In the various figures, the same features have been designated with the same reference numerals. In particular, structural features and / or functional features common among the various embodiments may have the same reference numerals and may be provided with the same structural characteristics, dimensional characteristics, and material characteristics.

[0037] For clarity, only the operations and elements useful for understanding the embodiments described herein have been described and illustrated in detail.

[0038] Unless otherwise specified, when referring to two elements connected together, this represents a direct connection without any intermediate elements other than conductors; while when referring to two elements coupled together, this means that the two elements may be connected or they may be coupled via one or more other elements.

[0039] In the following disclosure, unless otherwise specified, when referring to absolute positioning qualifiers (such as the terms "front", "rear", "top", "bottom", "left", "right", etc.), or when referring to relative positioning qualifiers (such as the terms "above", "below", "higher", "lower", etc.), or when referring to orientation qualifiers (such as "horizontal", "vertical", etc.), reference is made to the orientation shown in the drawings or to a depth map sensor oriented as during normal use.

[0040] Unless otherwise specified, the expressions "about", "substantially", "essentially", and "approximately" mean within 10%, and preferably within 5%.

[0041] In the following disclosure, example embodiments are described with reference to a depth map sensor using a scanned VCSEL source. However, it will be apparent to those skilled in the art that the principles described herein are equally applicable to depth map sensors using different types of laser light sources, which may or may not be scanned.

[0042] Figure 1 A top view of a depth map sensor 100 according to an example embodiment of the present disclosure is schematically illustrated in block form.

[0043] According to this embodiment, the depth map sensor 100 includes a pixel array (RTN ARRAY) 102. The pixel array 102 is a return array, for example, adapted to be scanned synchronously with the illumination of the image scene. Each pixel of the return array 102 includes at least one photodetector ( Figure 1 not shown in). The photodetectors of the return array 102 can be single photon avalanche diodes (SPADs). In an alternative embodiment, the photodetectors of the return array 102 can be photodiodes, which are, for example, photodiodes manufactured using complementary metal oxide semiconductor (CMOS) technology.

[0044] The image scene is illuminated by an illumination system 104. According to this embodiment, the illumination system 104 includes a plurality of light sources 106. The illumination system 104 is, for example, a scanned array of vertical cavity surface emitting lasers (VCSELs), where each light source 106 corresponds to at least one VCSEL. The depth map sensor 100 can include an optical system ( Figure 1 not shown in), which includes at least one lens and / or diffuser, and the optical system partially or completely covers the illumination system 104.

[0045] In the following disclosure, the letter "N" represents the total number of light sources 106 of the illumination system 104 belonging to the depth map sensor 100. In Figure 1 is presented a four-light-source 106 (106-1, 106-2, 106-3, and 106-4) arranged in a 1×4 array, but this does not imply a limitation on the number and arrangement of the light sources 106 in the illumination system 104. For example, more generally, the array can be an i×j array of light sources 106, where i and j are integers equal to one or more, and i times j is equal to N. In some embodiments, the illumination system 104 is a scanned laser illumination system that includes ten VCSELs arranged in a 1×10 array. In this case, each light source 106 is thus a laser light source 106 including one VCSEL, and N is equal to 10.

[0046] More generally, the illumination system 104 continuously illuminates various regions of the image scene, and these regions potentially partially overlap. In some alternative embodiments ( Figure 1 not shown in), the illumination system 104 includes only one light source 106 (e.g., a single VCSEL) and includes an optical device configured to scan the image scene. Such an optical device can include at least one mirror that is tilted at discrete angles with respect to the light source 106, so as to deflect the emitted light towards a plurality (N) of regions within the image scene, and these regions can in turn partially overlap.

[0047] In some embodiments, the depth map sensor 100 further includes at least one additional pixel array, e.g., two other pixel arrays 108-1 and 108-2 as depicted in Figure 1 . The additional pixel arrays 108-1 and 108-2 can act as reference arrays. In this case, the reference pixel arrays 108-1 and 108-2 are illuminated with light internally emitted by the illumination system 104. For example, the reference pixel arrays 108-1 and 108-2 are illuminated with a portion of the light reflected by an optical system ( Figure 1 , not shown) covering the illumination system 104. Preferably, the reference arrays 108-1 and 108-2 are placed as close as possible to the illumination system 104, since the purpose of these reference arrays is to capture the light immediately after it is emitted by the light source 106 of the illumination system 104.

[0048] According to Figure 1 's orientation, the reference arrays 108-1 and 108-2 are the upper / top reference array and the lower / bottom reference array, respectively. In one embodiment where the illumination system 104 is a vertical 1×N VCSEL array (where N is equal to or greater than 2), the upper reference array 108-1 can be used in association with the upper half of the VCSEL array, while the lower reference array can be used in association with the lower half of the VCSEL array. This enables the reference arrays 108-1 and 108-2 to capture the light emitted from the illumination system 104, which is close to the position where the light is emitted with minimal attenuation.

[0049] In Figure 1 , the return array 102 is separated from the reference arrays 108-1 and 108-2 and the illumination system 104 by an optical barrier 110. The optical barrier 110 prevents the return array 102 from being directly illuminated by the illumination system 104 or a portion of the light that may be reflected by an optical system ( Figure 1 , not shown) covering the illumination system 104. Thus, the light reaching the return array 102 mainly originates from the image scene rather than from the interior of the depth map sensor 100.

[0050] The return array 102 and the reference arrays 108-1 and 108-2 are driven, for example, by a control circuit (CTRL) 112. The light source 106 of the illumination system 104 is also driven, for example, by the control circuit 112. In some embodiments, the control circuit 112 is a microcontroller, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA).

[0051] The depth map sensor 100 may further include several other elements or circuits, which are represented by a single functional block (FCT) 114 in Figure 1 .

[0052] Each light source 106 of the illumination system 104 emits or projects light pulses or a light waveform into the image scene. These light pulses or the light waveform are immediately captured by at least one of the reference arrays 108-1, 108-2 after they are emitted. A return signal caused by the reflection of these light pulses or the light waveform in the image scene is then detected by the return array 102.

[0053] According to one embodiment, the depth map sensor 100 is configured to perform indirect ToF (iToF). In this case, the phase of the returned waveform captured by the return array 102 is compared with the phase of the emitted waveform captured by at least one of the reference arrays 108-1, 108-2 to estimate the time of flight, which is then converted into a distance measurement.

[0054] Figure 2 Schematically illustrate the Figure 1 return array 102 of the depth map sensor 100 according to an example embodiment.

[0055] The return array 102 is an array of pixels 202. In fact, the return array 102 can be a rectangular array which, in one example, includes 332 rows of pixels 202 and 252 columns of pixels 202.

[0056] In some embodiments, the reference arrays 108-1 and 108-2 ( Figure 1 ) are also pixel arrays of pixels 202 similar to the return array 102. The reference arrays 108-1 and 108-2 may each include fewer pixels than the return array 102. In one embodiment, each of the reference arrays 108-1, 108-2 can be a square array including 12 rows of pixels and 12 columns of pixels.

[0057] According to Figure 2 the embodiment, the return array 102 is divided into a number of clusters 204 of pixels 202. The clusters 204 are herein defined as regions of the return array 102 which respectively include at least one pixel 202 and preferably include a group of adjacent pixels 202.

[0058] In Figure 2 the depicted example, only two clusters 204 are shown, each cluster 204 including two adjacent rows of pixels 202. More specifically, the cluster 204-1 includes two adjacent rows 202-1 of pixels, and the other cluster 204-2 includes two adjacent rows 202-2 of pixels.

[0059] In Figure 2Cluster 204 is shown as a rectangular area of return array 102. Each cluster 204 includes the same number of pixels 202, but this does not imply any limitation on the shape of cluster 204 and the number of pixels 202 in each cluster 204. Specifically, each cluster in cluster 204 can have any shape and can include any number of pixels 202, and these pixels can be adjacent or not adjacent. Although two clusters 204 (204-1 and 204-2) are shown in Figure 2 , return array 102 can include any number of clusters 204, such as 10 clusters 204.

[0060] Figure 3 An example of pixel circuit 300 is schematically illustrated in block form. Figure 3 The pixel circuit 300 is similar to the pixel circuit described in U.S. Patent Publication No. 2018 / 0246212, which is assigned to the applicant and is incorporated herein by reference in its entirety.

[0061] As depicted in Figure 3 , pixel circuit 300 is associated with, for example, one pixel 202 (PX) of return pixel array 102. Pixel 202 includes at least one photodetector. For example, pixel 202 includes four photodetectors arranged in a 2×2 arrangement ( Figure 3 not shown in). Each photodetector of pixel 202 is, for example, a SPAD.

[0062] The output signal PS of pixel 202 (which, for example, originates from combining and pulse shaping the output signals of at least some of the photodetectors) can be passed to delay module 304 and clock sampling flip-flop 306. In the example of Figure 3 , delay module 304 includes a pair of delay elements (T) 3040, 3042 and inverter 3044. For example, delay module 304 is configured to receive the PS signal, delay the PS signal and invert the PS signal. Thus, a delayed inverted version PS' of the PS signal is output by delay module 304. Specifically, the delayed signal PS' includes, for example, rising edges generated from the falling edges of each pulse of the PS signal.

[0063] In Figure 3 the example shown, clock sampling flip-flop 306 is configured to sample four phase-shifted clock signals C1, C2, C3 and C4 using the output signal PS of pixel 202. Each of the four phase-shifted clock signals C1, C2, C3, C4 is phase-shifted by, for example, a quarter cycle relative to the next phase-shifted clock signal. In this case, C1 is substantially the inversion of C3, and C2 is substantially the inversion of C4.

[0064] InFigure 3 In [the figure], the clock sampling flip-flop 306 is shown as four D-type flip-flops 306-1, 306-2, 306-3, and 306-4. Each D-type flip-flop 306-1, 306-2, 306-3, 306-4 has a data input (D) coupled to one of the phase-shifted clock signals C1, C2, C3, C4 and a clock input (>) coupled to the PS signal. The output (Q) of each D-type flip-flop 306-1, 306-2, 306-3, 306-4 is coupled to a corresponding input of the gated edge detector decoder 308. For example, if the associated phase-shifted clock signals C1, C2, C3, C4 are high on the rising edge of the SPAD event pulse, output signals are generated from each D-type flip-flop 306-1, 306-2, 306-3, 306-4.

[0065] For example, the output signal PS' of the delay module 304 (which is provided to the gated edge detector decoder 308) is used to time the detection events propagated through the gated edge detector decoder 308 to the phase rotation multiplexer 310. The gated edge detector decoder 308, for example, has four outputs GD1, GD2, GD3, and GD4 as shown in Figure 3 [the figure].

[0066] If a SPAD event is detected during one of four corresponding time windows, then the gated edge detector decoder 308 outputs a high state, for example, on one of its four outputs GD1, GD2, GD3, GD4. These time windows are described in more detail below with respect to Figure 4 [the figure].

[0067] The phase rotation multiplexer 310 is associated, for example, with four ripple counters or bins 314-1 (BIN1), 314-2 (BIN2), 314-3 (BIN3), and 314-4 (BIN4). For example, the phase rotation multiplexer 310 also receives a selection signal SS from the phase rotator / selector (array phase rotation controller) 312. Based on the value of the SS signal, the phase rotation multiplexer 310 selects which of the four ripple counters BIN1, BIN2, BIN3, BIN4 each output GD1, GD2, GD3, GD4 of the gated edge detector decoder 308 will be applied to.

[0068] In other words, the phase rotation multiplexer 310 distributes each of the outputs GD1, GD2, GD3, GD4 to the corresponding ripple counters BIN1, BIN2, BIN3, BIN4 selected by the phase rotator / selector 312 using the SS signal. Thus, the ripple counters BIN1, BIN2, BIN3, and BIN4 are receiving the outputs from the multiplexer 310 as inputs, and the ripple counters BIN1, BIN2, BIN3, and BIN4 are configured to count the events detected by the pixel circuit 300 in order to generate a histogram.

[0069] Figure 4 is a timing diagram of signals in the Figure 3 pixel circuit.

[0070] Figure 4 corresponding to an ideal case where the four phase-shifted clock signals C1, C2, C3, and C4 are, for example, square wave signals that are exactly phase-shifted by a quarter cycle with respect to the next square wave signal. In Figure 4 the phase-shifted clock signals C1 to C4 are phase-shifted with respect to each other such that the phase-shifted clock signals C2, C3, and C4 exhibit phase shifts of 90°, 180°, and 270° respectively compared to the phase-shifted clock signal C1.

[0071] The gated edge detector decoder 308 ( Figure 3 ) is configured, for example, to output a high state:

[0072] on the output GD1 of the gated edge detector decoder 308 if an event is detected in the time window TW1 included between the rising edge of the phase-shifted clock signal C1 and the rising edge of the phase-shifted clock signal C2;

[0073] on the output GD2 of the gated edge detector decoder 308 if an event is detected in another time window TW2 included between the rising edge of the phase-shifted clock signal C2 and the rising edge of the phase-shifted clock signal C3;

[0074] on the output GD3 of the gated edge detector decoder 308 if an event is detected in yet another time window TW3 included between the rising edge of the phase-shifted clock signal C3 and the rising edge of the phase-shifted clock signal C4; and

[0075] on the output GD4 of the gated edge detector decoder 308 if an event is detected in yet another time window TW4 included between the rising edge of the phase-shifted clock signal C4 and the rising edge of the phase-shifted clock signal C1.

[0076] In Figure 4 the example, by the phase rotation multiplexer 310 ( Figure 3)The SPAD events detected within time windows TW1, TW2, TW3, and TW4 are respectively assigned to ripple counters BIN1, BIN2, BIN3, and BIN4. The time windows TW1, TW2, TW3, and TW4 have the same width in the example of Figure 4

[0077] However, different from the situation shown in Figure 4

[0078] To mitigate the impact of possible differences between the phase - shifted clock signals C1, C2, C3, and C4, as will be described now in conjunction with Figures 5 to 8 Figure 3 the pixel circuit 300 of

[0079] Figures 5 to 8 is an additional timing diagram showing the signals in the pixel circuit of Figure 3 Figures 5 to 8 Specifically,

[0080] corresponds to a non - ideal situation where the phase - shifted clock signals C1, C2, C3, and C4 are not separated by equal phase shifts. For example, such differences are caused by the physical implementation of the circuit and conduction paths (not shown) that are configured to propagate the phase - shifted clock signals C1, C2, C3, and C4 from the timing source to the pixel circuit. Figures 5 to 8

[0081] The phase shift between the phase - shifted clock signals C1 and C2 is equal to the phase shift between the phase - shifted clock signals C4 and C1;

[0082] The phase shift between the phase - shifted clock signals C2 and C3 is greater than the phase shift between the phase - shifted clock signals C1 and C2; and

[0083] The phase shift between the phase - shifted clock signals C3 and C4 is less than the phase shift between the phase - shifted clock signals C1 and C2.

[0084] For example, Figure 5 shows Figure 4 ​​​​​A corresponding phase rotation setting, where the phase rotation multiplexer 310 is configured to:

[0085] Couple the output GD1 corresponding to the time window TW1 to the ripple counter BIN1;

[0086] Couple the output GD2 corresponding to the time window TW2 to the ripple counter BIN2;

[0087] Couple the output GD3 corresponding to the time window TW3 to the ripple counter BIN3; and

[0088] Couple the output GD4 corresponding to the time window TW4 to the ripple counter BIN4.

[0089] In Figure 5 the phase rotation setting, for example, a laser pulse (laser start pulse) represented by the vertical arrow in Figures 5 to 8 is emitted by the laser source at the rising edge of the phase shift clock signal C1. However, as mentioned above, the phase shift between the phase shift clock signals C2 and C3 is greater than it should be, and the phase shift between the phase shift clock signals C3 and C4 is less than it should be. This can lead to inaccurate distance measurement. In fact, due to the fact that the time window TW2 is larger than the time windows TW1 and TW4, the probability of detecting an event is higher during the time window TW2, and due to the fact that the time window TW3 is narrower than the time windows TW1 and TW4, the probability of detecting an event is lower during the time window TW3.

[0090] To mitigate this difference in the width of the time windows, the phase rotator / selector 312 is configured to: during consecutive exposure sub - phases, perform histogram generation using each of the time windows TW1 to TW4 to capture events for each of the four bins of the histogram, as will now be described with reference to Figures 6 to 8 .

[0091] For example, Figure 6 shows another phase rotation setting, where the phase rotator / selector 312 is configured to control the emission of the optical pulse (laser start pulse) at the rising edge of the phase shift clock signal C2. The phase rotation multiplexer 310 is configured to:

[0092] Couple the output GD1 corresponding to the time window TW1 to the ripple counter BIN4;

[0093] Couple the output GD2 corresponding to the time window TW2 to the ripple counter BIN1;

[0094] Couple the output GD3 corresponding to the time window TW3 to the ripple counter BIN2; and

[0095] Couple the output GD4 corresponding to the time window TW4 to the ripple counter BIN3.

[0096] For example, Figure 7 Another phase rotation setting is shown, in which the phase rotator / selector 312 is configured to control the emission of an optical pulse (laser start pulse) at the rising edge of the phase-shifted clock signal C3. The phase rotation multiplexer 310 is configured to:

[0097] Couple the output GD1 corresponding to the time window TW1 to the ripple counter BIN3;

[0098] Couple the output GD2 corresponding to the time window TW2 to the ripple counter BIN4;

[0099] Couple the output GD3 corresponding to the time window TW3 to the ripple counter BIN1; and

[0100] Couple the output GD4 corresponding to the time window TW4 to the ripple counter BIN2.

[0101] For example, Figure 8 Another phase rotation setting is shown, in which the phase rotator / selector 312 is configured to control the emission of an optical pulse (laser start pulse) at the rising edge of the phase-shifted clock signal C4. The phase rotation multiplexer 310 is configured to:

[0102] Couple the output GD1 corresponding to the time window TW1 to the ripple counter BIN2;

[0103] Couple the output GD2 corresponding to the time window TW2 to the ripple counter BIN3;

[0104] Couple the output GD3 corresponding to the time window TW3 to the ripple counter BIN4; and

[0105] Couple the output GD4 corresponding to the time window TW4 to the ripple counter BIN1.

[0106] As shown above with reference to Figures 5 to 8 As shown, the phase rotator / selector 312 ( Figure 3 ) can be configured such that the phase rotation multiplexer 310 dispatches the outputs GD1, GD2, GD3, GD4 of the gated edge detector decoder 308 to the selected ripple counters BIN1, BIN2, BIN3, BIN4, which change over time, for example, according to a cyclic circular shift (in other words, rotation). In addition, an opposite phase rotation is applied to the light source so that there is no modification to the relative timing between the optical signal and the bins.

[0107] In Figures 5 to 8In the example, the width of each time window TW1, TW2, TW3, TW4 does not change over time, i.e., it changes from one phase rotation setting to another phase rotation setting.

[0108] After an entire cycle including all four of the above rotation settings, the differences between the phase-shifted clock signals C1, C2, C3, and C4 are considered to reach an average.

[0109] Figure 9 represents according to an exemplary embodiment Figure 1 of the timing diagram of the operation of the depth map sensor 100.

[0110] During Figure 1 the operation of the depth map sensor 100, for example, clusters 204 (see Figure 2 ) of pixels 202 of the return array 102 are illuminated sequentially. When illuminating the clusters 204 of the return array 102 during the scanning operation, the clusters 204 of the return array 102 are, for example, activated to detect illumination from the image scene in a top-to-bottom order.

[0111] According to one embodiment, the sequential activation of the clusters 204 (204-1 and 204-2) is performed synchronously with the illumination of the corresponding or associated light sources 106 (106-1 and 106-2) of the Figure 1 illumination system 104. According to this embodiment, the number of clusters 204 is equal to the number N of light sources 106, where N is equal to two or more. In other words, each light source 106 of the illumination system 104 is configured to illuminate the corresponding cluster 204 of the return array 102.

[0112] In the following disclosure, the period during which the clusters 204 of the return array 102 are illuminated is referred to as the "exposure phase". Assuming that the illumination system 104 includes N light sources 106, there are also N exposure phases of the return array 102. In particular, as depicted in Figure 9 , one exposure phase 402 of the return array 102 is defined by the cluster 204-1 illuminated by the light source 106-1, and another exposure phase 404 of the return array 102 is defined by the cluster 204-2 illuminated by the light source 106-2.

[0113] In the following disclosure, the period during which the pixels 202 of the clusters 204 are read after illumination is referred to as the "readout phase". In the case where there are N exposure phases, there are also N readout phases of the return array 102. In particular, as depicted in Figure 9 , one readout phase (RP) 406 is defined by reading the pixels 202-1 of the cluster 204-1 after the exposure phase 402.

[0114] In some embodiments, one of the two reference arrays 108-1, 108-2 (e.g., the top reference array 108-1) is also illuminated and then read during each exposure phase of the cluster 204 of the return array 102.

[0115] More specifically, as depicted in Figure 9 , the exposure phase 408 of the reference array 108-1, followed by the readout phase (RP) 410 of the reference array 108-1, occurs during the exposure phase 402 of the cluster 204-1, and another exposure phase 412 of the reference array 108-1, followed by the readout phase (RP) 414 of the reference array 108-1, occurs during the exposure phase 404 of the cluster 204-2.

[0116] Thus, the reference array 108-1 is exposed and read during each exposure phase of the cluster 204 of the return array 102. For example, compared to the case where the durations of the exposure phases 408, 412 of the reference array 108-1 would be the same as the exposure phases 402, 404 of the return array 108-1 respectively, this advantageously avoids the need for memory elements configured to store the information captured by the reference array 108-1. The disadvantage of such memory elements is that they would require a large amount of physical space for implementation, resulting in a reduced resolution of the depth map sensor 100 or an increased size of the depth map sensor 100.

[0117] In addition, according to one embodiment, each exposure phase 402, 404 of the return array 102 and each exposure phase 408, 412 of the reference array 108-1 are divided into a plurality of exposure sub-phases (ESP), e.g., four exposure sub-phases. As Figure 9 shown, the exposure 402 of the cluster 204-1 of the return array 102 includes four exposure sub-phases 402-1, 402-2, 402-3, and 402-4, the exposure 404 of the cluster 204-2 of the return array 102 includes four exposure sub-phases 404-1, 404-2, 404-3, and 404-4, the exposure 408 of the reference array 108-1 includes four exposure sub-phases 408-1, 408-2, 408-3, and 408-4, and the exposure 412 of the reference array 108-1 includes four exposure sub-phases 412-1, 412-2, 412-3, and 412-4.

[0118] As Figure 9As shown, the exposure sub - phases of the reference array 108 - 1 are shorter than the exposure sub - phases of the return array 102 to allow for the read - out phase RP of the reference array 108 - 1 to be considered. For example, the duration of each exposure sub - phase 402 - 1, 402 - 2, 402 - 3, 402 - 4 of the return array 102 is between 10 μs and 20 μs (e.g., equal to 17.25 μs), while the duration of each exposure sub - phase 408 - 1, 408 - 2, 408 - 3, and 408 - 4 is between 50% and 95% of the duration of each exposure sub - phase 402 - 1, 402 - 2, 402 - 3, 402 - 4 of the return array 102.

[0119] According to one embodiment, each exposure sub - phase of the same exposure phase corresponds to a different phase - rotation setting. Thus, the phase - rotation setting is changed at a higher frequency during the exposure phases 408, 412 of the reference array 108 - 1 compared to during the exposure phases 402, 404 of the return array 102.

[0120] Thus, Figure 1 this operation of the depth - map sensor 100 requires driving the pixel circuits 300 of the return array 102 ( Figure 3 ) and the pixel circuits 300 of the reference array 108 - 1 with two separate time sources. Using two time sources instead of one is not desirable, especially since time sources typically occupy a relatively large chip area and have a relatively high power consumption.

[0121] Figure 10 A portion of a depth - map sensor according to an example embodiment is schematically illustrated in block form and includes a multi - phase clock generator 1000 and a timing generator 500 associated with a pixel array.

[0122] More specifically, as Figure 10 shown, the timing generator 500 is coupled, for example, to a return array (RTN array) 102 and a reference array (REF array), such as an upper reference array 108 - 1 ( Figure 1 ). In the case where there is more than one reference array, the timing generator 500 is coupled to each reference array, for example.

[0123] The timing generator 500 is configured, for example, to generate phase - shifted clock signals based on signals generated by the multi - phase clock generator 1000, which allow the depth - map sensor 100 to operate generally as described with respect to Figure 9 and to provide these phase - shifted clock signals to each pixel array in the pixel array.

[0124] Figure 11 Schematically illustrated in block form according to an example embodiment is related to Figure 10associated with the timing generator 500 Figure 3 the pixel circuit 300. In the following description, the pixel circuit 300 is considered as the pixel circuit of the return array 102 ( Figure 1 ). However, since the pixel circuits of the reference array 108-1 are also associated with the same timing generator 500, the pixel circuit 300 can equally be the pixel circuit of a reference array (e.g., the upper reference array 108-1).

[0125] According to this embodiment, the timing generator 500 is coupled to the flip-flops 306 (306-1, 306-2, 306-3, and 306-4) of the pixel circuit 300. In particular, the timing generator 500 is configured to provide the phase-shifted clock signals C1, C2, C3, and C4 to the flip-flops 306. As Figure 11 shown, the timing generator 500 receives, for example, four additional phase-shifted clock signals PHI1, PHI2, PHI3, and PHI4 from a polyphase clock generator 1000 ( Figure 11 not shown in the figure).

[0126] Figure 12 is the timing diagram of the phase-shifted clock signals PHI1, PHI2, PHI3, and PHI4 received by Figure 11 the timing generator 500. In particular, Figure 12 corresponds to an example where the phase-shifted clock signals PHI1, PHI2, PHI3, and PHI4 are not separated by equal phase shifts. For example, this difference is caused by the physical implementation of the circuit and the conduction paths (not shown), which are configured to propagate the signals PHI1, PHI2, PHI3, and PHI4 from the timing source to the pixel circuit.

[0127] More specifically, in the example of Figure 12 :

[0128] the phase shift between the signals PHI1 and PHI2 is equal to the phase shift between the signals PHI4 and PHI1;

[0129] the phase shift between the signals PHI2 and PHI3 is greater than the phase shift between the signals PHI1 and PHI2; and

[0130] the phase shift between the signals PHI3 and PHI4 is less than the phase shift between the signals PHI1 and PHI2.

[0131] According to one embodiment, a timing generator 500 provides phase-shifted clock signals C1, C2, C3, and C4 corresponding to one of the signals PHI1, PHI2, PHI3, and PHI4 to D flip-flops 306-1, 306-2, 306-3, and 306-4 of a pixel circuit 300. To mitigate the effects of possible differences between the phase-shifted clock signals PHI1, PHI2, PHI3, and PHI4 (such as Figure 12 the phase-shifted clock signals shown in

[0132] ), the timing generator 500 is further configured such that these signals PHI1, PHI2, PHI3, and PHI4 are assigned to the D flip-flops 306-1, 306-2, 306-3, and 306-4 according to a cyclic ring shift. In other words, the timing generator 500 is configured to perform a phase rotation of the phase-shifted clock signals PHI1, PHI2, PHI3, and PHI4.

[0133] For example, a phase rotation multiplexer 310 controlled by a signal emitted by a phase rotator / selector 312 is configured to assign SPAD events detected within time windows TW1, TW2, TW3, and TW4 to ripple counters BIN1, BIN2, BIN3, and BIN4, respectively. Figures 13 to 16 An example of the phase rotation performed by the timing generator 500 is described below in conjunction with

[0134] Figures 13 to 16 FIG. is an additional timing diagram of signals in the pixel circuit 300 according to an example embodiment of Figure 3

[0135] According to one embodiment, a laser source emits laser pulses (laser start pulses) represented by the vertical arrows in Figures 13 to 16 based on the rising edge of the same signal. For example, in the four phase rotation settings described below in conjunction with Figures 13 to 16 , an optical pulse is emitted based on the rising edge of the signal PHI1. In Figures 13 to 16 , the laser start pulse and the rising edge of the signal PHI1 are shown to occur simultaneously. However, in reality, there may be a time offset between the rising edge of the signal PHI1 and the laser start pulse.

[0136] As shown below with reference to Figures 13 to 16 FIG., the phase rotator / selector 312 ( Figure 11)For example, it is configured such that the selection transmitted by the phase rotation multiplexer 310 of the outputs GD1, GD2, GD3, GD4 of the gated edge detector decoder 308 to each ripple counter BIN1, BIN2, BIN3, BIN4 changes over time according to a cyclic circular shift or rotation. The rotation performed by the phase rotation multiplexer 310 results in no modification of the relative timing between the optical signal and the bins.

[0137] Figure 13 For example, it shows a first phase rotation setting where the phase-shifted clock signals C1, C2, C3, and C4 respectively correspond to the phase-shifted clock signals PHI1, PHI2, PHI3, and PHI4.

[0138] In Figure 13 the example of, the phase rotation multiplexer is configured to:

[0139] Couple the output GD1 corresponding to the time window TW1 to the ripple counter BIN1;

[0140] Couple the output GD2 corresponding to the time window TW2 to the ripple counter BIN2;

[0141] Couple the output GD3 corresponding to the time window TW3 to the ripple counter BIN3; and

[0142] Couple the output GD4 corresponding to the time window TW4 to the ripple counter BIN4.

[0143] Figure 14 For example, it shows a second phase rotation setting where the phase-shifted clock signals C1, C2, C3, and C4 respectively correspond to the phase-shifted clock signals PHI2, PHI3, PHI4, and PHI1.

[0144] The time window TW1 (as described above with reference to Figure 4 which is defined, for example, by the time interval between the rising edge of the phase-shifted clock signal C1 and the rising edge of the phase-shifted clock signal C2) corresponds to the time interval between the rising edge of the signal PHI1 and the rising edge of the signal PHI2 in the first phase rotation setting illustrated in Figure 13 and corresponds to the time interval between the rising edge of the signal PHI2 and the rising edge of the signal PHI3 in the second phase rotation setting illustrated in Figure 14 ).

[0145] In Figure 14 the example of, the phase rotation multiplexer is configured to:

[0146] Couple the output GD1 corresponding to the time window TW1 to the ripple counter BIN2;

[0147] Couple the output GD2 corresponding to the time window TW2 to the ripple counter BIN3;

[0148] Couple the output GD3 corresponding to the time window TW3 to the ripple counter BIN4; and

[0149] Couple the output GD4 corresponding to the time window TW4 to the ripple counter BIN1.

[0150] Figure 15 For example, an additional rotation to a third phase rotation setting is shown, where the phase - shifted clock signals C1, C2, C3, and C4 correspond to the phase - shifted clock signals PHI3, PHI4, PHI1, and PHI2, respectively.

[0151] In Figure 15 's example, the phase rotation multiplexer is configured to:

[0152] Couple the output GD1 corresponding to the time window TW1 to the ripple counter BIN3;

[0153] Couple the output GD2 corresponding to the time window TW2 to the ripple counter BIN4;

[0154] Couple the output GD3 corresponding to the time window TW3 to the ripple counter BIN1; and

[0155] Couple the output GD4 corresponding to the time window TW4 to the ripple counter BIN2.

[0156] Figure 16 For example, an additional rotation to a fourth phase rotation setting is shown, where the phase - shifted clock signals C1, C2, C3, and C4 correspond to the phase - shifted clock signals PHI4, PHI1, PHI2, and PHI3, respectively.

[0157] In Figure 16 's example, the phase rotation multiplexer is configured to:

[0158] Couple the output GD1 corresponding to the time window TW1 to the ripple counter BIN4;

[0159] Couple the output GD2 corresponding to the time window TW2 to the ripple counter BIN1;

[0160] Couple the output GD3 corresponding to the time window TW3 to the ripple counter BIN2; and

[0161] Couple the output GD4 corresponding to the time window TW4 to the ripple counter BIN3.

[0162] As described above in connection with Figures 13 to 16The four rotation settings described respectively correspond to different configurations of the phase-shifted clock signals C1, C2, C3, and C4. For example, each of the four rotation settings corresponds to one of the four exposure sub-phases (ESPs) of the same exposure phase as described above in connection with Figure 9 as described.

[0163] Figure 17 Schematically illustrated in block form is the timing generator 500 and the multi-phase clock generator 1000 of the depth map sensor 100 according to an example embodiment. Figure 1 of the depth map sensor 100.

[0164] As Figure 17 shown, the multi-phase clock generator 1000 includes, for example, a phase-locked loop (PLL) 502. The phase-locked loop 502 acts as a clock generator, for example, by multiplying a low-frequency reference clock ( Figure 17 not shown in Figure 1 ) by the operating frequency of the depth map sensor 100 (

[0165] The output signal of the phase-locked loop 502, which is a single clock signal for example, is provided to the multi-phase clock divider 504 of the multi-phase clock generator 1000. The multi-phase clock divider 504 is configured to generate four phase-shifted clock signals, for example.

[0166] According to one embodiment, the multi-phase clock divider 504 generates Figure 12 the four phase-shifted clock signals PHI1, PHI2, PHI3, and PHI4. The four phase-shifted clock signals PHI1, PHI2, PHI3, and PHI4 are then provided to three blocks (synchronous clock gates) 506 of the timing generator 500.

[0167] More specifically, as Figure 17 shown, block 506-1 is configured to propagate the signals PHI1, PHI2, PHI3, and PHI4 to the multiplexing circuit 508-1 coupled to the return array (RTN array) 102, for example. Another block 506-2 is configured to propagate the signals PHI1, PHI2, PHI3, and PHI4 to another multiplexing circuit 508-2 coupled to the reference arrays (REF arrays) 108-1 and 108-2, for example. Yet another block 506-3 is configured to propagate one of the signals PHI1, PHI2, PHI3, and PHI4 to the illumination system (Illum Sys) 104, for example.

[0168] According to one embodiment, for example, the propagation of signals PHI1, PHI2, PHI3, and PHI4 to multiplexing circuit 508-1 is gated by block 506-1 using an enable signal (denoted herein as RTN_ENABLE_OUTPUT). Similarly, for example, the propagation of signals PHI1, PHI2, PHI3, and PHI4 to multiplexing circuit 508-2 is gated by block 506-2 using another enable signal (denoted herein as REF_ENABLE_OUTPUT). According to one embodiment, the enable signals RTN_ENABLE_OUTPUT and REF_ENABLE_OUTPUT are each binary signals and are generated, for example, by sequencer 510. Sequencer 510 is, for example, a state machine.

[0169] The enable signal RTN_ENABLE_OUTPUT provided by sequencer 510 to block 506-1 advantageously allows interruption of the propagation of the phase-shifted clock signals PHI1, PHI2, PHI3, and PHI4 to multiplexing circuit 508-1. This, for example, enables multiplexing circuit 508-1 to switch from one phase rotation setting to another during a period when the phase-shifted clock signals are not propagated to multiplexing circuit 508-1. This prevents glitches, for example, when switching from one phase rotation setting of return array 102 to the next. All of these advantages similarly apply to reference arrays 108-1 and 108-2.

[0170] Furthermore, the presence of the two enable signals RTN_ENABLE_OUTPUT and REF_ENABLE_OUTPUT advantageously allows independent execution of phase rotation for return array 102 and reference array 108-1. As shown in the reference Figure 9 This enables reference array 108-1 to perform phase rotation at a higher rate than return array 102, for example, resulting in shorter exposure sub-phases for reference array 108-1 than for return array 102.

[0171] Figure 18 Schematically illustrates a circuit configured to generate phase-shifted signals according to an example embodiment. In particular, Figure 18 depicts block 506-1 coupled to return array 102 according to an example embodiment. However, the following description may equally apply to block 506-2 coupled to reference arrays 108-1 and 108-2.

[0172] According to one embodiment, block 506-1 includes three flip-flops 602-1, 602-2, and 602-3 coupled in series. Flip-flops 602-1, 602-2, and 602-3 all receive signal PHI1 on their clock inputs (CP). Flip-flop 602-1 receives the enable signal RTN_ENABLE_OUTPUT on its data input (D), and provides a signal represented as EN_RTN1 on its output (Q).

[0173] The output of flip-flop 602-1 is coupled to the data input (D) of flip-flop 602-2. Thus, flip-flop 602-2 receives the EN_RTN1 signal on its data input. Flip-flop 602-2 provides another signal represented as EN_RTN2 on its output (Q).

[0174] The output of flip-flop 602-2 is coupled to the data input (D) of flip-flop 602-3. Thus, flip-flop 602-3 receives the EN_RTN2 signal on its data input. Flip-flop 602-3 provides yet another signal represented as EN_RTN_SAMPLED_MPIX0 on its output (Q).

[0175] Flip-flops 602-1, 602-2, and 602-3 are used, for example, to synchronize the enable signal RTN_ENABLE_OUTPUT with the clock signal PHI1 to prevent metastability.

[0176] The output of flip-flop 602-3 that provides signal EN_RTN_SAMPLED_MPIX0 is coupled to the data inputs (D) of three additional flip-flops 604-1, 604-2, and 604-3. The clock inputs (CP) of flip-flops 604-1, 604-2, and 604-3 receive phase-shifted clock signals PHI4, PHI1, and PHI3, respectively.

[0177] The output (Q) of flip-flop 604-1 is coupled to an input of AND gate 606-1, and signal UNGATE_RTN_MPIX0 is provided to AND gate 606-1. In a similar manner, the output (Q) of flip-flop 604-2 is coupled to an input of another AND gate 606-2, and another signal UNGATE_RTN_MPIX90 is provided to AND gate 606-2.

[0178] Signal PHI1 is further provided to AND gate 606-1, and AND gate 606-1 outputs a signal represented as MPIX0_RTN herein. Similarly, signal PHI2 is also provided to AND gate 606-2, and AND gate 606-2 outputs another signal represented as MPIX90_RTN herein.

[0179] Flip-flop 604-3 provides another signal at its output (Q) which is denoted herein as EN_RTN_SAMPLED_MPIX180.

[0180] The output of flip-flop 604-3 is coupled to the data inputs (D) of two additional flip-flops 608-1 and 608-2. Thus, the signal EN_RTN_SAMPLED_MPIX180 is provided to the data inputs of flip-flops 608-1 and 608-2. The signals PHI2 and PHI3 are provided to the clock inputs (CP) of flip-flops 608-1 and 608-2, respectively.

[0181] The output (Q) of flip-flop 608-1 is coupled to an input of AND gate 610-1, and the signal UNGATE_RTN_MPIX180 is provided to AND gate 610-1. In a similar manner, the output (Q) of flip-flop 608-2 is coupled to an input of another AND gate 610-2, and another signal UNGATE_RTN_MPIX270 is provided to AND gate 610-2.

[0182] In addition, the signal PHI3 is provided to AND gate 610-1, and AND gate 610-1 outputs a signal denoted herein as MPIX180_RTN. Similarly, the signal PHI4 is also provided to AND gate 610-2, and AND gate 610-2 outputs another signal denoted herein as MPIX270_RTN.

[0183] As Figure 18 depicted, flip-flops 602-1, 602-2, 602-3, 604-1, 604-2, 604-3, 608-1, and 608-2 receive a signal denoted herein as RSTN at their reset inputs (RN), respectively.

[0184] Figure 19 is a timing diagram showing the operation of circuit 506-1 according to an example embodiment. Figure 18 of.

[0185] The signals PHI1, PHI2, PHI3, and PHI4 are rectangular periodic signals, for example, and these rectangular periodic signals all have approximately the same period. In addition, the signals PHI1 to PHI4 are phase-shifted relative to each other such that compared to the signal PHI1, the signals PHI2, PHI3, and PHI4 exhibit phase shifts of 90°, 180°, and 270°, respectively.

[0186] At time t0, the signal PHI1 is at a low level. At time t0, the enable signal RTN_ENABLE_OUTPUT is set to a high level, for example, by sequencer 510.

[0187] At time t1, when the signal PHI1 first rises after time t0, the signal EN_RTN1 (not shown) is set high by the flip-flop 602-1( Figure 18 ).

[0188] At time t2, when the signal PHI1 secondarily rises after time t0, the signal EN_RTN2 (not shown) is set high by the flip-flop 602-2.

[0189] At time t3, when the signal PHI1 tertially rises after time t0, the signal EN_RTN_SAMPLED_MPIX0 is set high by the flip-flop 602-3.

[0190] At time t4, when the signal PHI3 first rises after time t3, the signal EN_RTN_SAMPLED_MPIX180 is set high by the flip-flop 604-3.

[0191] At time t5, when the signal PHI4 first rises after time t3, the signal UNGATE_RTN_MPIX0 is set high by the flip-flop 604-1.

[0192] Starting from time t5, the signal PHI1 is temporarily propagated through the output of the AND gate 606-1. As from time t5, the signal MPIX0_RTN, for example, exhibits the same shape as the signal PHI1.

[0193] At time t6, when the signal PHI1 first rises after time t3, the signal UNGATE_RTN_MPIX90 is set high by the flip-flop 604-2.

[0194] Starting from time t6, the signal PHI2 is temporarily propagated through the output of the AND gate 606-2. As from time t6, the signal MPIX90_RTN, for example, exhibits the same shape as the signal PHI2. In other words, the signal MPIX90_RTN is phase-shifted by approximately 90° relative to the signal MPIX0_RTN.

[0195] At time t7, when the signal PHI2 first rises after time t4, the signal UNGATE_RTN_MPIX180 is set high by the flip-flop 608-1.

[0196] Starting from time t7, the signal PHI3 is temporarily propagated through the output of the AND gate 610-1. As from time t7, the signal MPIX180_RTN, for example, exhibits the same shape as the signal PHI3. In other words, the signal MPIX180_RTN is phase-shifted by approximately 180° relative to the signal MPIX0_RTN.

[0197] At time t8, when signal PHI3 first rises after time t4, signal UNGATE_RTN_MPIX270 is set high by flip-flop 608-2.

[0198] Starting from time t8, signal PHI4 is temporarily propagated through the output of AND gate 610-2. As from time t8, signal MPIX270_RTN, for example, exhibits the same shape as signal PHI4. In other words, signal MPIX270_RTN is phase-shifted by approximately 270° relative to signal MPIX0_RTN.

[0199] At time t9, signal PHI1 is low. At time t9, enable signal RTN_ENABLE_OUTPUT is set low, for example, by sequencer 510.

[0200] At time t10, when signal PHI1 first rises after time t9, signal EN_RTN1 (not shown) is set low by flip-flop 602-1( Figure 18 ).

[0201] At time t11, when signal PHI1 secondarily rises after time t9, signal EN_RTN2 (not shown) is set low by flip-flop 602-2.

[0202] At time t12, when signal PHI1 tertially rises after time t9, signal EN_RTN_SAMPLED_MPIX0 is set low by flip-flop 602-3.

[0203] At time t13, when signal PHI3 first rises after time t12, signal EN_RTN_SAMPLED_MPIX180 is set low by flip-flop 604-3.

[0204] At time t14, when signal PHI4 first rises after time t12, signal UNGATE_RTN_MPIX0 is set low by flip-flop 604-1.

[0205] Starting from time t14, signal PHI1 is no longer propagated through the output of AND gate 606-1. As from time t14, signal MPIX0_RTN is set low.

[0206] At time t15, when signal PHI1 first rises after time t12, signal UNGATE_RTN_MPIX90 is set low by flip-flop 604-2.

[0207] Starting from time t15, the signal PHI2 is no longer propagated through the output of the AND gate 606-2. As of time t15, the signal MPIX90_RTN is set to low level.

[0208] At time t16, when the signal PHI2 rises for the first time after time t13, the signal UNGATE_RTN_MPIX180 is set to low level through the flip-flop 608-1.

[0209] Starting from time t16, the signal PHI3 is no longer propagated through the output of the AND gate 610-1. As of time t16, the signal MPIX180_RTN is set to low level.

[0210] At time t17, when the signal PHI3 rises for the first time after time t13, the signal UNGATE_RTN_MPIX270 is set to low level through the flip-flop 608-2.

[0211] Starting from time t17, the signal PHI4 is no longer propagated through the output of the AND gate 610-2. As of time t17, the signal MPIX270_RTN is set to low level.

[0212] As described above with reference to Figure 19 shown, Figure 18 the circuit 506-1 is configured to generate four additional phase-shifted clock signals MPIX0_RTN, MPIX90_RTN, MPIX180_RTN, and MPIX270_RTN using the enable signal RTN_ENABLE_OUTPUT and the four phase-shifted clock signals PHI1, PHI2, PHI3, and PHI4. In addition, the phase-shifted clock signals MPIX0_RTN, MPIX90_RTN, MPIX180_RTN, and MPIX270_RTN generated by the circuit 506-1 are interrupted using the enable signal RTN_ENABLE_OUTPUT.

[0213] Figure 20 illustrates the multiplexing circuit of the Figure 17 timing generator 500 according to an exemplary embodiment.

[0214] In particular, Figure 20 depicts the multiplexing circuit 508-1 coupled to the return array 102 according to an exemplary embodiment. However, the following description can equally apply to the multiplexing circuit 508-2 coupled to the reference arrays 108-1 and 108-2.

[0215] According to one embodiment, the multiplexing circuit 508-1 includes four multiplexers 702-1, 702-2, 702-3, and 702-4. Each multiplexer 702-1, 702-2, 702-3, and 702-4 is, for example, a 4:1 multiplexer. In Figure 20 the example of, each multiplexer 702-1, 702-2, 702-3, and 702-4 has four inputs (I1, I2, I3, and I4) and one output (O).

[0216] In Figure 20 the example of, the phase-shifted clock signals MPIX0_RTN, MPIX90_RTN, MPIX180_RTN, and MPIX270_RTN are provided to the inputs I1, I2, I3, and I4 of the multiplexers 702-1, 702-2, 702-3, and 702-4 according to a cyclic ring shift. For example, as depicted in Figure 20 the signal MPIX0_RTN is provided to:

[0217] input I1 of multiplexer 702-1;

[0218] input I2 of multiplexer 702-2;

[0219] input I3 of multiplexer 702-3; and

[0220] input I4 of multiplexer 702-4.

[0221] For example, the signal MPIX90_RTN is provided to:

[0222] input I4 of multiplexer 702-1;

[0223] input I1 of multiplexer 702-2;

[0224] input I2 of multiplexer 702-3; and

[0225] input I3 of multiplexer 702-4.

[0226] For example, the signal MPIX180_RTN is provided to:

[0227] input I3 of multiplexer 702-1;

[0228] input I4 of multiplexer 702-2;

[0229] input I1 of multiplexer 702-3; and

[0230] input I2 of multiplexer 702-4.

[0231] For example, the signal MPIX270_RTN is provided to:

[0232] Input I2 of multiplexer 702-1;

[0233] Input I3 of multiplexer 702-2;

[0234] Input I4 of multiplexer 702-3; and

[0235] Input I1 of multiplexer 702-4.

[0236] In addition, as Figure 20 shown, multiplexers 702-1, 702-2, 702-3, and 702-4 output phase-shifted clock signals C1, C2, C3, and C4, respectively.

[0237] According to one embodiment, multiplexers 702-1, 702-2, 702-3, and 702-4 are controlled by a two-bit control signal (CTRL). The two bits of the CTRL control signal, denoted herein as S0 and S1, are binary signals, for example, so the CTRL control signal has four different possible values. Each value of the CTRL control signal determines, for example, which of the inputs I1, I2, I3, and I4 of each of the multiplexers 702-1, 702-2, 702-3, and 702-4 is propagated to the output O of each of the multiplexers 702-1, 702-2, 702-3, and 702-4.

[0238] For example, for a value of the CTRL control signal, multiplexers 702-1, 702-2, 702-3, and 702-4 output phase-shifted clock signals C1, C2, C3, and C4 corresponding to the input signals, and these input signals (i.e., MPIX0_RTN, MPIX90_RTN, MPIX180_RTN, and MPIX270_RTN) are respectively provided to input I1 of the multiplexer. For another value of the CTRL control signal, multiplexers 702-1, 702-2, 702-3, and 702-4 output phase-shifted clock signals C1, C2, C3, and C4 corresponding to the input signals, and the input signals (i.e., MPIX270_RTN, MPIX0_RTN, MPIX90_RTN, and MPIX180_RTN) are respectively provided to input I2 of the multiplexer. For yet another value of the CTRL control signal, multiplexers 702-1, 702-2, 702-3, and 702-4 output phase-shifted clock signals C1, C2, C3, and C4 corresponding to the input signals, and these input signals (i.e., MPIX180_RTN, MPIX270_RTN, MPIX0_RTN, and MPIX90_RTN) are respectively provided to input I3 of the multiplexer. For yet another value of the CTRL control signal, multiplexers 702-1, 702-2, 702-3, and 702-4 output phase-shifted clock signals C1, C2, C3, and C4 corresponding to the input signals, and these input signals (i.e., MPIX90_RTN, MPIX180_RTN, MPIX270_RTN, and MPIX0_RTN) are respectively provided to input I4 of the multiplexer.

[0239] Thus, as described above with reference to Figures 13 to 16 the multiplexing circuit 508-1 can provide four phase rotation settings to the pixel circuit 300.

[0240] An advantage of the embodiment lies in the fact that, due to the enable signals RTN_ENABLE_OUTPUT and REF_ENABLE_OUTPUT, the timing generator allows switching from one phase rotation setting to another during periods when the phase-shifted clock signals are not propagated to the multiplexing circuits 508-1 and 508-2. This prevents glitches, for example, when switching from one phase rotation setting of the return array to the next. These advantages similarly apply to the reference arrays 108-1 and 108-2.

[0241] Another advantage of the embodiments lies in the fact that the two enable signals RTN_ENABLE_OUTPUT and REF_ENABLE_OUTPUT allow for independent phase rotation to be performed on the return array 102 and the reference array 108-1. This, for example, enables the reference array 108-1 to switch from one phase rotation setting to the next at a higher rate than the return array 102, thereby causing a shorter exposure sub-phase for the reference array 108-1 than for the return array 102. This, for example, further allows the reference array 108-1 to perform both an exposure phase and a readout phase during each exposure phase of the return array 102.

[0242] Various embodiments and variations have been described. Those skilled in the art should understand that certain features of these embodiments can be combined, and other variations will be readily envisioned by those skilled in the art. Specifically, the number of phase rotation settings can be adapted to the application.

[0243] In addition, although embodiments involving four bins BIN1, BIN2, BIN3, and BIN4 and four phase shift clock signals C1, C2, C3, and C4 have been described in the present disclosure, it will be apparent to those skilled in the art that the embodiments of the present disclosure can be adapted to any number of bins and corresponding numbers of phase shift clock signals. Specifically, the embodiments of the present disclosure can be adapted to two bins and two associated phase shift clock signals or to eight bins and eight associated phase shift clock signals. In addition, the number of bins of the return array 102 and the associated phase shift clock signals can be different from the number of bins of the reference arrays 108-1, 108-2 and the associated phase shift clock signals.

[0244] Finally, based on the functional descriptions provided above, the actual implementation of the embodiments and variations described herein is within the capabilities of those skilled in the art. Specifically, the actual methods for reading pixels and storing the corresponding information are within the capabilities of those skilled in the art.

Claims

1. A depth map sensor, comprising: a first array of first pixels, each first pixel including a first photodetector associated with a first pixel circuit, the first pixel circuit including a plurality of first bins for accumulating events; a second array of second pixels, each second pixel including a second photodetector associated with a second pixel circuit, the second pixel circuit including a plurality of second bins for accumulating events; a clock source configured to generate a plurality of phase-shifted clock signals; a first circuit having a plurality of first output lines coupled to the first array of the first pixels, the first circuit being configured to receive the plurality of phase-shifted clock signals, wherein the first circuit includes a first block and a second block, the first block being configured to propagate the plurality of phase-shifted clock signals to the second block during a first period determined by a first enable signal, wherein the propagation of the plurality of phase-shifted clock signals to the second block is interrupted at the end of the first period, and wherein the second block is configured to select each phase-shifted clock signal of the plurality of phase-shifted clock signals to be applied to one of the plurality of first output lines; and a second circuit having a plurality of second output lines coupled to the second array of the second pixels, the second circuit receiving the plurality of phase-shifted clock signals from the clock source, wherein the second circuit includes a third block and a fourth block, the third block being configured to propagate the plurality of phase-shifted clock signals to the fourth block during a second period determined by a second enable signal, and the fourth block being configured to select each phase-shifted clock signal of the plurality of phase-shifted clock signals to be applied to one of the plurality of second output lines, wherein the duration of the second period is different from the duration of the first period.

2. The depth map sensor according to claim 1, wherein the selection performed by the fourth block is different from the selection performed by the second block.

3. The depth map sensor according to claim 1, wherein: the first array of the first pixels is a return pixel array adapted to be illuminated by a light source of the depth map sensor, the light source being configured to transmit light into an image scene; and the second array of the second pixels is a reference array.

4. The depth map sensor according to claim 1, wherein the depth map sensor is configured to: illuminate a group of the first photodetectors of the first array of the first pixels of the depth map sensor during a first exposure phase; read the group of the first photodetectors of the first array of the first pixels of the depth map sensor during a first readout phase after the first exposure phase; and illuminate a group of the second photodetectors of the second array of the second pixels of the depth map sensor during a second exposure phase, and then read the second photodetectors during a second readout phase, the second exposure phase and the second readout phase being included in the first exposure phase of the group of the first photodetectors.

5. The depth map sensor according to claim 4, wherein the first exposure phase further comprises: a first exposure sub-phase, during which the plurality of phase-shifted clock signals are applied to the plurality of first output lines of the first array of the first pixels coupled to the depth map sensor in a first order; and a second exposure sub-phase, during which the plurality of phase-shifted clock signals are applied to the plurality of first output lines of the first array of the first pixels coupled to the depth map sensor according to a cyclic circular shift.

6. The depth map sensor according to claim 4, wherein the second exposure phase further comprises: a third exposure sub-phase, during which the plurality of phase-shifted clock signals are applied to the plurality of second output lines of the second array of the second pixels coupled to the depth map sensor in a second order; and a fourth exposure sub-phase, during which the plurality of phase-shifted clock signals are applied to the plurality of second output lines of the second array of the second pixels coupled to the depth map sensor according to a cyclic circular shift.

7. The depth map sensor according to claim 1, wherein the duration of the first period is longer than the duration of the second period.

8. The depth map sensor according to claim 7, wherein the duration of the second period is between 50% and 95% of the duration of the first period.

9. The depth map sensor according to claim 1, wherein the duration of the first period is between 10 μs and 20 μs.

10. The depth map sensor according to claim 9, wherein the duration of the second period is between 50% and 95% of the duration of the first period.

11. A method of operating a depth map sensor, comprising: generating a plurality of phase-shifted clock signals; propagating the phase-shifted clock signals via a first output line to a first array of first pixels and via a second output line to a second array of second pixels, each first pixel including a first photodetector associated with a first pixel circuit, the first pixel circuit including a plurality of first bins for accumulating events, each second pixel including a second photodetector associated with a second pixel circuit, the second pixel circuit including a plurality of second bins for accumulating events, the phase-shifted clock signals being propagated to the first array of the first pixels via the first output line during a first period determined by a first enable signal and being propagated to the second array of the second pixels via the second output line during a second period having a duration different from the duration of the first period; and selecting which one of the plurality of phase-shifted clock signals is applied to one of the first output lines and which one of the second output lines.

12. The method according to claim 11, wherein the selection performed for the first output line is different from the selection performed for the second output line.

13. The method according to claim 11, the method further comprises: illuminating a group of first photodetectors of a first array of the first pixels during a first exposure phase; reading the group of first photodetectors of the first array of the first pixels during a first readout phase after the first exposure phase; illuminating the second photodetectors of a second array of the second pixels during a second exposure phase; and reading the second photodetectors of the second array of the second pixels during a second readout phase after the second exposure phase, the second exposure phase and the second readout phase being included in the first exposure phase of the group of first photodetectors.

14. The method according to claim 13, wherein the first exposure phase comprises: a first exposure sub-phase, during which the plurality of phase-shifted clock signals are applied to the first output lines coupled to the first array of the first pixels in a first order; and a second exposure sub-phase, during which the plurality of phase-shifted clock signals are applied to the first output lines coupled to the first array of the first pixels according to a cyclic circular shift.

15. The method according to claim 14, wherein the second exposure phase further comprises: a third exposure sub-phase, during which the plurality of phase-shifted clock signals are applied to the second output lines coupled to the second array of the second pixels in a second order; and a fourth exposure sub-phase, during which the plurality of phase-shifted clock signals are applied to the second output lines coupled to the second array of the second pixels according to a cyclic circular shift.

16. The method according to claim 11, wherein the duration of the first period is between 10 μs and 20 μs, and the duration of the second period is between 50% and 95% of the duration of the first period.

17. A method of operating a depth map sensor, comprises: during a first period determined by a first enable signal, using a first block of a first circuit having a plurality of first output lines coupled to a first array of first pixels, propagating a plurality of phase-shifted clock signals that have been received by the first circuit and generated by a clock source to a second block of the first circuit, wherein each first pixel includes a first photodetector associated with a first pixel circuit, and the first pixel circuit includes a plurality of first bins for accumulating events; during a second period having a duration different from that of the first period and determined by a second enable signal, using a third block of a second circuit having a plurality of second output lines coupled to a second array of second pixels, propagating the plurality of phase-shifted clock signals that have been received by the second circuit from the clock source to a fourth block, wherein each second pixel includes a second photodetector associated with a second pixel circuit, and the second pixel circuit includes a plurality of second bins for accumulating events; Using the second block, each phase clock signal among the multiple phase-shifted clock signals is applied to one of the multiple first output lines; And Using the fourth block, each phase-shifted clock signal among the multiple phase-shifted clock signals is applied to one of the multiple second output lines.

18. The method according to claim 17, wherein the selection performed by the fourth block is different from the selection performed by the second block.

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