Memory-based neuromorphic devices

Abstract

A neuromorphic device includes: a memory cell array including a first memory cell and a second memory cell, the first memory cell corresponding to a first address and storing a first weight, the second memory cell corresponding to a second address and storing a second weight; and a neuron circuit including an integrator and an activation circuit, the integrator summing first read signals from the first memory cell, the activation circuit outputting a first activation signal based on a first sum signal of the first read signals output from the integrator.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0146341 filed on November 15, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present inventive concept relates to neuromorphic devices, and more particularly, to memory-based neuromorphic devices. Background Art

[0004] Artificial neural networks, similar to biological neural networks, are gaining attention. Artificial neural networks are being used in a variety of fields, such as machine learning, selection, reasoning, prediction, recognition, analysis, translation, and diagnosis. Artificial neural networks can include artificial neurons that are similar to biological neurons (e.g., nerve cells) and form multiple layers. Synaptic weights can indicate the strength of connections between artificial neurons and can be learned and changed through machine learning.

[0005] As the number of layers and artificial neurons in an artificial neural network increases, the synaptic weights and biases that indicate the strength of connections between artificial neurons also increase. When implementing artificial neural networks on semiconductor chips, high integration and low power consumption technologies are beneficial in storing the increasing synaptic weights and biases and in implementing multiple artificial neurons. Summary of the Invention

[0006] Embodiments of the inventive concept provide a memory-based neuromorphic device.

[0007] According to an example embodiment, a neuromorphic device may include: a memory cell array including a first memory cell corresponding to a first address and a second memory cell corresponding to a second address, the first memory cell configured to store a first weight, and the second memory cell configured to store a second weight; and a first neuron circuit including a first integrator and a first activation circuit, the first integrator configured to sum a first read signal from the first memory cell and output the first sum signal to the first activation circuit, and to sum a second read signal from the second memory cell and output the second sum signal to the first activation circuit, the first activation circuit configured to output a first activation signal based on a first sum signal of the first read signals output from the integrator, and to output a second activation signal based on the second sum signal of the second read signals output from the integrator. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other objects and features of the present inventive concept will become apparent by describing in detail example embodiments of the present inventive concept with reference to the attached drawings.

[0009] Figure 1 An artificial neural network according to an embodiment of the present invention is shown;

[0010] Figure 2 shows a block diagram of a neuromorphic device according to an embodiment of the inventive concept;

[0011] Figure 3 shows a block diagram of a neuromorphic device according to another embodiment of the inventive concept;

[0012] Figure 4 shows a block diagram of a neuromorphic device according to another embodiment of the inventive concept;

[0013] Figure 5 A block diagram of a neuromorphic device according to another embodiment of the present inventive concept is shown in detail;

[0014] Figure 6 A block diagram of a neuromorphic device according to another embodiment of the present inventive concept is shown in detail;

[0015] Figure 7 Shown in detail Figure 5 Block diagram of a neuromorphic device;

[0016] Figure 8 Shown in detail Figure 6 Block diagram of a neuromorphic device;

[0017] Figure 9 Shown in detail Figure 7 Block diagram of a neuromorphic device;

[0018] Figure 10 Shown Figure 9 a timing diagram of the operation of a neuromorphic device;

[0019] Figure 11 Shown in detail Figure 7 Block diagram of a neuromorphic device;

[0020] Figure 12 Shown Figure 11 a timing diagram of the operation of a neuromorphic device;

[0021] Figure 13 shows a circuit diagram of an integrator according to an embodiment of the inventive concept;

[0022] Figure 14 A circuit diagram of a summing circuit according to an embodiment of the inventive concept is shown;

[0023] Figure 15 shows a circuit diagram of an activation circuit according to an embodiment of the inventive concept;

[0024] Figure 16 shows a block diagram of a neuromorphic device according to an embodiment of the inventive concept;

[0025] Figure 17 Shown Figure 16 Neuromorphic devices can run artificial neural networks;

[0026] Figure 18 It shows Figure 16 A flowchart of a method of operating a neuromorphic device;

[0027] Figure 19 A block diagram illustrating a neuromorphic device according to an embodiment of the inventive concept; and

[0028] Figure 20 A block diagram of a system on chip according to an embodiment of the inventive concept is shown. DETAILED DESCRIPTION

[0029] When the terms "approximately" or "substantially" are used in conjunction with a numerical value in this specification, it is intended that the relevant numerical value include a manufacturing tolerance (e.g., ±10%) around the stated numerical value. In addition, when the words "generally" and "substantially" are used in conjunction with a geometric shape, it is intended that the accuracy of the geometric shape is not required, but the range of the shape is within the scope of the present disclosure. In addition, regardless of whether a numerical value or shape is modified as "approximately" or "substantially", it will be understood that these values ​​and shapes should be interpreted as including a manufacturing tolerance or operating tolerance (e.g., ±10%) around the stated numerical value or shape.

[0030] Figure 1 An artificial neural network according to an embodiment of the inventive concept is shown.

[0031] The artificial neural network ANN may include an input layer IL, at least one hidden layer HL, and an output layer OL. For example, the artificial neural network ANN may be a deep neural network (DNN), a recurrent neural network (RNN), a convolutional neural network (CNN), a spike neural network (SNN), etc. The input layer IL may include a plurality of input nodes IN1 to IN3, and may receive input data IN. The output layer OL may include a plurality of output nodes ON1 to ON3, and may output output data OUT based on data passing through the at least one hidden layer HL. The at least one hidden layer HL may include a plurality of hidden nodes HN1 to HN8, and the connection between the input layer IL and the output layer OL may be configured. Although the configuration shown in the present embodiment is Figure 1The example numbers of nodes IN1 to IN3, HN1 to HN8, and ON1 to ON3 of the respective layers IL, HL, and OL are shown, as well as the number of hidden layers HL and the connection relationships between the nodes IN1 to IN3, HN1 to HN8, and ON1 to ON3, but the number of nodes, layers, and connections can be greater or lesser. For example, the artificial neural network ANN can also include one or more pattern nodes IN1 to IN3, HN1 to HN8, and ON1 to ON3, one or more hidden layers HL, and one or more connection relationships between the nodes IN1 to IN3, HN1 to HN8, and ON1 to ON3. The nodes can be artificial neurons corresponding to the neurons of a biological neural network and can be referred to as "neuron circuits" or "perceptrons." The connection strength between neuron circuits can correspond to the connection strength of synapses in a biological neural network, and the connection strength between neuron circuits can be represented by weights (e.g., synaptic weights). As in neurons in a biological neural network, a neuron circuit can output an activation signal to another neuron circuit based on signals from the other neuron circuits, the weights of the other neuron circuits, the bias, and the threshold of the neuron circuit. The following will describe a hardware device in which the artificial neural network ANN is implemented and runs the artificial neural network ANN.

[0032] Figure 2 A block diagram of a neuromorphic device according to an embodiment of the inventive concept is shown.

[0033] The neuromorphic device 1000a may be a "neuromorphic computing device," a "neuromorphic chip," a "neuromorphic processor," a "neuromorphic system," a "neural network accelerator," a "neural network accelerator chip," an "artificial intelligence (AI) processor," an "AI memory device," a "processor," a "memory device," or a combination thereof. The neuromorphic device 1000a may be a memory-based neuromorphic device that uses a structure or architecture of a memory device for storing data. In some example embodiments, the neuromorphic device 1000a may include a plurality of processing elements that simultaneously and / or synchronously perform processing of a neural network, such as a group of processing elements that simultaneously and / or synchronously sum weights across several channels. In some example embodiments, the neuromorphic device 1000a may be configured to sequentially process a neural network, such as a series of operations for each of several channels as will be described below. The neuromorphic device 1000a may include a memory cell array 1100 and a neuron circuit 1200.

[0034] The memory cell array 1100 may include memory cells MC1 to MC4. For example, each of the memory cells MC1 to MC4 may be one of a static random access memory (SRAM) cell, a dynamic random access memory (DRAM) cell, a thyristor random access memory (TRAM) cell, a NAND flash memory cell, a NOR flash memory cell, a resistive random access memory (RRAM) cell, a ferroelectric random access memory (FRAM) cell, a phase change random access memory (PRAM) cell, and a magnetic random access memory (MRAM) cell. Each of the memory cells MC1 to MC4 may be a DRAM cell including a cell transistor "T" and a cell capacitor "C," and the neuromorphic device 1000a may be a DRAM-based neuromorphic device. However, the present inventive concept is not limited thereto. For example, each of the memory cells MC1 to MC4 may store a single bit. The cell voltage level Vcell (e.g., storage voltage) of each of the memory cells MC1 to MC4 may correspond to one of voltage levels VS0 and VS1 indicating logical values ​​represented by a single bit and different from each other (e.g., "0" and "1"). For example, each of the memory cells MC1 to MC4 may correspond to a single-layer cell (SLC). Weights W1 to W4 may be written to the memory cells MC1 to MC4, respectively, through an input / output line IO (e.g., an input and output line IO). The memory cells MC1 to MC4 may store weights W1 to W4, respectively. Each of the weights W1 to W4 may indicate the connection strength of the neuron circuit 1200. Although not described in Figure 2 , but at least one of the memory cells MC1 to MC4 may store a bias instead of a weight, or another memory cell other than the memory cells MC1 to MC4 may store a bias. For example, the number of bits of the weight and the number of bits of the bias may correspond to the number of bits that each of the memory cells MC1 to MC4 can store. For example, the memory cells MC1 to MC4 can be accessed separately via one input / output line IO. Although the number of memory cells MC1 to MC4 is shown in this embodiment, the number of memory cells may be more or less than shown, for example, one or more memory cells may be further included in the memory cell array 1100. The corresponding weights and / or biases may be written and / or stored separately in one or more further included memory cells.

[0035] The neuron circuit 1200 may include an integrator 1300 and an activation circuit 1400. The integrator 1300 may receive weights W1 to W4 transmitted from the memory cells MC1 to MC4 via the input / output line 10. The integrator 1300 may integrate, sum, and / or accumulate at least a portion of the weights W1 to W4. In the case where a portion of the memory cells MC1 to MC4 stores biases instead of weights, the integrator 1300 may receive and sum weight(s) and bias(es). The integrator 1300 may be referred to as an "accumulator" or "adder." For example, the integrator 1300 may sum at least one or more weights of the weights W1 to W4 at the input / output line 10. The integrator 1300 may sum a plurality of bits of the weights at one input / output line 10. The integrator 1300 may provide a sum signal indicating the summation result to the activation circuit 1400.

[0036] The activation circuit 1400 may output, generate, enable, and / or trigger the activation signal ACTa / ACTb based on the sum signal of the integrator 1300. For example, the activation circuit 1400 may output the activation signal ACTa / ACTb by comparing the threshold signal TH (or referred to as a "threshold," "reference signal," or "reference value") with the sum signal of the integrator 1300. When the sum signal of the integrator 1300 exceeds the threshold signal TH, the activation circuit 1400 may output and / or enable the activation signal ACTa / ACTb, or, for example, if the sum signal of the integrator 1300 does not exceed the threshold signal TH, the activation circuit 1400 may disable and / or not output the activation signal ACTa / ACTb. The activation signal ACTa / ACTb may be referred to as an "output signal." The activation circuit 1400 may output the activation signal ACTa / ACTb by using various activation functions such as a step function, a sigmoid function, a rectified linear unit (ReLU) function, a leaky ReLU function, and a Tanh function.

[0037] For example, because at least one or more weights are repeatedly transmitted through the input / output line IO, the neuron circuit 1200 can be reused. The integrator 1300 can sum the read signals from the memory cells MC1 and MC3 storing the weights W1 and W3 at one input / output line IO (①). The activation circuit 1400 can output the activation signal ACTa by comparing the sum signal output by the integrator 1300 as the sum of the weights W1 and W3 with the threshold signal TH. Next, the integrator 1300 can further sum the read signals from the memory cells MC2 and MC4 storing the weights W2 and W4 at the one input / output line IO (②). The activation circuit 1400 can further output the activation signal ACTb by comparing the sum signal output by the integrator 1300 as the sum of the weights W2 and W4 with the threshold signal TH. Because one neuron circuit 1200 repeatedly and differently receives at least a portion of different weights W1 to W4 through the input / output line IO and repeatedly and differently outputs activation signals ACTa and ACTb, the neuron circuit 1200 can be reused. At least one of the weights W2 and W4 can indicate the connection strength between the neuron circuit 1200 that receives read signals from the memory cells MC1 and MC3 and the neuron circuit 1200 that receives read signals from the memory cells MC2 and MC4. The two neuron circuits 1200 described above are examples of one neuron circuit 1200 that is physically implemented, but the neuron circuit 1200 can operate as two or more nodes of an artificial neural network ANN and can be reused.

[0038] In an example embodiment, memory cells MC1 to MC4 can be selected to output read signals from memory cells MC1 to MC4. In the case of "①", memory cells MC1 and MC3 can be selected, and in the case of "②", memory cells MC2 and MC4 can be selected. For example, the read signals from memory cells MC1 to MC4 can correspond to the product of the addresses used to select memory cells MC1 to MC4 and the weights W1 to W4 stored in memory cells MC1 to MC4. In another example, the read signals from memory cells MC1 to MC4 may include weights and / or biases stored in memory cells MC1 to MC4. The number of memory cells of the memory cell array 1100, the positions of the selected memory cells, the number of selected memory cells, etc. are merely examples and can be adjusted accordingly.

[0039] Figure 31000 a and 1000 b.

[0040] The neuromorphic device 1000b may include a memory cell array 1100b and a neuron circuit 1200. The memory cell array 1100b may include memory cells MC1b to MC4b. As in the neuromorphic device 1000a, each of the memory cells MC1b to MC4b may be a DRAM cell including a cell transistor "T" and a cell capacitor "C", but each of the memory cells MC1b to MC4b may store two bits. The cell voltage level Vcell of each of the memory cells MC1b to MC4b may correspond to one of the voltage levels VS00, VS01, VS10, and VS11 indicating a logical value represented by two bits and different from each other (e.g., 00, 01, 10, and 11). In this case, the weight and / or bias stored in each of the memory cells MC1b to MC4b may consist of two bits. In one embodiment, each of the memory cells MC1b to MC4b can store two or more bits, the cell voltage level Vcell can be further subdivided to indicate a logic value represented by the two or more bits, and the weight and / or bias can have two or more bits. Each of the memory cells MC1b to MC4b can correspond to a multi-level cell (MLC), a triple-level cell (TLC), a quad-level cell (QLC), etc.

[0041] The neuron circuit 1200 can be reused regardless of the number of bits that each of the memory cells MC1b to MC4b can store. The integrator 1300 can sum (①) the read signals from the memory cells MC1b and MC3b storing weights W1b and W3b at one input / output line IO, where the weights W1b and W3b are both multi-bit. The activation circuit 1400 can output an activation signal ACTa by comparing the sum signal output by the integrator 1300 as the sum of the weights W1b and W3b with the threshold signal TH. Next, the integrator 1300 can further sum (②) the read signals from the memory cells MC2 and MC4 storing weights W2b and W4b at the one input / output line IO, where the weights W2b and W4b are both multi-bit. The activation circuit 1400 can further output an activation signal ACTb by comparing the sum signal output by the integrator 1300 as the sum of the weights W2b and W4b with the threshold signal TH. In the above description, unless otherwise specified, a memory cell may store a single bit or may store two or more bits.

[0042] Figure 4 FIG2 is a block diagram of a neuromorphic device 1000 c according to another embodiment of the present inventive concept. To avoid redundancy, additional descriptions associated with components having the same reference numerals will be omitted, and the differences between the neuromorphic devices 1000 a, 1000 b, and 1000 c will be mainly described.

[0043] Memory cell array 1100c may include sub-memory blocks 1110_1 to 1110_2. All memory cells of memory cell array 1100 may be divided into sub-memory blocks 1110_1 to 1110_2. Sub-memory block 1110_1 may include memory cells MC1 and MC2. Memory cells MC1 and MC2 may be connected (e.g., coupled) to word lines WL1 and WL2, respectively, and may be commonly connected to bit line BL1. Sub-memory block 1110_2 may include memory cells MC3 and MC4. Memory cells MC3 and MC4 may be connected to word lines WL3 and WL4, respectively, and may be commonly connected to bit line BL2.

[0044] Memory cell array 1100c may include a bit line sense amplifier 1111_1 connected to bit line BL1. Bit line sense amplifier 1111_1 may sense and / or amplify the voltage level of bit line BL1, which may change depending on whether one of memory cells MC1 and MC2 is selected. For example, only one of memory cells MC1 and MC2 connected to bit line sense amplifier 1111_1 may be selected. Memory cell array 1100c may also include a bit line sense amplifier 1111_2 connected to bit line BL2. Bit line sense amplifier 1111_2 may sense and amplify the voltage level of bit line BL2, which may change depending on whether one of memory cells MC3 and MC4 is selected. For example, only one of memory cells MC3 and MC4 connected to bit line sense amplifier 1111_2 may be selected. Although memory cell array 1100c is shown as including memory cells MC1 to MC4, the memory cell array may include, for example, memory cells MC1b to MC4b.

[0045] Bit line sense amplifier 1111_1 can restore the weight and / or bias by storing the voltage level again. The stored voltage level can be obtained by sensing and / or amplifying the voltage level of bit line BL1 in a memory cell selected from memory cells MC1 and MC2. Similarly, bit line sense amplifier 1111_2 can restore the weight and / or bias by storing a voltage level in a memory cell selected from memory cells MC3 and MC4, which voltage level can be obtained by sensing and / or amplifying the voltage level of bit line BL2. Access (e.g., read) operations on the selected memory cell can be non-destructive.

[0046] The memory cell array 1100c may further include a column select switch 1112_1 that electrically connects the bit line BL1 to the input / output line IO. The column select switch 1112_1 may electrically connect the bit line BL1 to the input / output line IO based on a column select signal transmitted via the column select line CSL. The memory cell array 1100c may further include a column select switch 1112_2 that electrically connects the bit line BL2 to the input / output line IO. The column select switch 1112_2 may electrically connect the bit line BL2 to the input / output line IO based on a column select signal transmitted via the column select line CSL. For example, each of the column select switches 1112_1 and 1112_2 may be connected to the same column select line CSL and may receive the same column select signal via the same column select line CSL. The column select signal may allow each of the bit lines BL1 and BL2 to be electrically connected to the same input / output line IO.

[0047] However, the number of sub-memory blocks in memory cell array 1100, the number of memory cells in each sub-memory block, the number of word lines in each sub-memory block, and the number of bit lines in each sub-memory block are merely example embodiments, and the number may be greater or less than the number shown. Furthermore, for example, bit line sense amplifiers 1111_1 may be provided adjacent to sub-memory block 1110_1 as many as the number of bit lines BL1 belonging to sub-memory block 1110_1, and bit line sense amplifiers 1111_2 may be provided adjacent to sub-memory block 1110_2 as many as the number of bit lines BL2 belonging to sub-memory block 1110_2. Bit line sense amplifiers 1111_1 and 1111_2, as well as column select switches 1112_1 and 1112_2, may be interposed between sub-memory blocks 1110_1 and 1110_2. Sub-memory block 1110_1 may be interposed between bit line sense amplifier 1111_1 and another bit line sense amplifier adjacent to sub-memory block 1110_1. Memory cells MC1 to MC4 may be implemented identically, sub-memory blocks 1110_1 to 1110_2 may be implemented identically, bit line sense amplifiers 1111_1 to 1111_2 may be implemented identically, and column select switches 1112_1 to 1112_2 may be implemented identically.

[0048] The neuromorphic device 1000c may further include a row / column controller 1500, which includes an address generator 1510, a row decoder 1600, and a column decoder 1700. The row / column controller 1500 may control the row decoder 1600 and the column decoder 1700 based on activation signals ACTa and ACTb. The address generator 1510 may generate an address for selecting at least a portion of the memory cells MC1 to MC4 of the memory cell array 1100 based on the activation signals ACTa and ACTb. The address generator 1510 may generate an internal row address IRA and an internal column address ICA whenever each of the activation signals ACTa and ACTb is received. For example, the address generator 1510 may include a counter that performs a counting operation in response to the activation signals ACTa and ACTb and generates a count value (or address). Furthermore, based on the activation signals ACTa and ACTb, the row / column controller 1500 may provide a control signal for controlling the row decoder 1600 to select a word line corresponding to the internal row address IRA. Based on the activation signals ACTa and ACTb, the row / column controller 1500 may provide a control signal for controlling the column decoder 1700 to the column decoder 1700 , thereby selecting a column selection line corresponding to the internal column address ICA.

[0049] The row decoder 1600 may decode the internal row address IRA and may select at least one of the word lines WL1 to WL4 connected to the memory cells MC1 to MC4 of the memory cell array 1100c. Figure 2 and / or Figure 3 In the case of "①", the row decoder 1600 can decode the internal row address IRA and can select the word lines WL1 and WL3. Figure 2 and / or Figure 3 In the case of "②", the row decoder 1600 can decode the internal row address IRA and can select word lines WL2 and WL4. The internal row address IRA provided to the row decoder 1600 in the case of "①" and the internal row address IRA provided to the row decoder 1600 in the case of "②" may be different from each other.

[0050] Row decoder 1600 may include sub-row decoders 1610_1 through 1610_2 and a pre-row decoder 1620. For example, sub-row decoder 1610_1 may decode internal row address IRA and select one of word lines WL1 and WL2 belonging to sub-memory block 1110_1. Sub-row decoder 1610_2 may decode internal row address IRA and select one of word lines WL3 and WL4 belonging to sub-memory block 1110_2. Sub-row decoders 1610_1 through 1610_2 may be implemented identically. Row decoder 1600 may include as many sub-row decoders as the number of sub-memory blocks in memory cell array 1100.

[0051] The pre-row decoder 1620 may decode the internal row address IRA before the sub-row decoders 1610_1 to 1610_2 and / or may select the sub-row decoders 1610_1 to 1610_2. For example, the pre-row decoder 1620 may set the upper bits of the row address bits for selecting the word lines of each of the sub-memory blocks 1110_1 and 1110_2 to "don't care bits". In this case, the pre-decoder 1620 may select two or more sub-row decoders 1610_1 and 1610_2 at the same time. Figure 2 and / or Figure 3 In the case of "①", in order to select memory cells MC1 and MC3, the pre-row decoder 1620 can simultaneously select the sub-row decoders 1610_1 and 1610_2, and the sub-row decoders 1610_1 and 1610_2 can respectively select the word lines WL1 and WL3. Figure 2 and / or Figure 3 In the case of "②", to select memory cells MC2 and MC4, pre-row decoder 1620 can simultaneously select sub-row decoders 1610_1 and 1610_2, and sub-row decoders 1610_1 and 1610_2 can respectively select word lines WL2 and WL4. For another example, pre-row decoder 1620 can select one of sub-row decoders 1610_1 and 1610_2. In this case, a single word line can be selected from memory cell array 1100.

[0052] The column decoder 1700 can decode the internal column address ICA and can send (e.g., output) a column select signal via the column select line CSL. For example, the column decoder 1700 can start a selection operation after the selection operation of the row decoder 1600 is initiated. As described above, the column decoder 1700 can send a column select signal to each of the column select switches 1112_1 to 1112_2. The column decoder 1700 can select the bit lines BL1 to BL2 by sending a column select signal. Therefore, when the row decoder 1600 simultaneously selects two or more word lines WL1 and WL3 or WL2 and WL4, the bit line sense amplifiers 1111_1 and 1111_2 then sense and amplify the weights W1 and W3 or W2 and W4 of the memory cells MC1 and MC3 or MC2 and MC4, and then apply the column select signal to the column select switches 1112_1 and 1112_2. The weights W1 and W3 or W2 and W4 can then be sent (or provided) to the input / output line IO at the same time. Integrator 1300 may sum weights W1 and W3 at input / output line 10, or may sum weights W2 and W4 at input / output line 10. Here, because memory cells MC1 and MC2 can be connected to bit line BL1, bit line BL1 can be connected to column select switch 1112_1, memory cells MC3 and MC4 can be connected to bit line BL2, bit line BL2 can be connected to column select switch 1112_2, and column select switches 1112_1 and 1112_2 can be connected to the same column select line CSL, internal column addresses ICA corresponding to memory cells MC1 to MC4 may be the same.

[0053] In one embodiment, the address generator 1510 can sequentially increase or decrease the internal row address IRA, and can sequentially increase or decrease the internal column address ICA. For example, the row decoder 1600 can decode the internal row address IRA and can select word lines WL1 and WL3, and the column decoder 1700 can decode the internal column address ICA and can select the column select line CSL. Next, the row decoder 1600 can decode the internal row address IRA that increases or decreases depending on the activation signal ACTa and can select word lines WL2 and WL4, and the column decoder 1700 can decode the internal column address ICA and can select the column select line CSL. For example, the row decoder 1600 and the column decoder 1700 can sequentially select memory cells MC1 and MC3 and memory cells MC2 and MC4.

[0054] The integrator 1300, activation circuit 1400, row / column decoder 1500, row decoder 1600, column decoder 1700, address generator 1510, and pre-row decoder 1620 may constitute a processing circuit, such as hardware including logic circuits; a hardware / software combination, such as a processor running software; or a combination thereof. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA) and a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), and the like.

[0055] Figure 5 FIG. 1 is a block diagram of a neuromorphic device according to another embodiment of the present inventive concept. To avoid redundancy, additional descriptions associated with components having the same reference numerals will be omitted, and the differences between neuromorphic devices 1000 c and 1000 d will be mainly described.

[0056] The memory cell array 1100d may further include sub-memory blocks 1120_1 to 1130_1. The sub-memory blocks 1120_1 to 1130_1 may include memory cells MC connected to word lines WL1 and WL2 selected by the sub-row decoder 1610_1 and may be implemented identically. The memory cell array 1100d may further include sub-memory blocks 1120_2 to 1130_2. The sub-memory blocks 1120_2 to 1130_2 may include memory cells MC connected to word lines WL3 and WL4 selected by the sub-row decoder 1610_2 and may be implemented identically. The memory cell array 1100d may further include bit line sense amplifiers 1121_1 to 1121_2 and 1131_1 to 1131_2 that are substantially the same as the bit line sense amplifiers 1111_1 to 1111_2, and column select switches 1122_1 to 1122_2 and 1132_1 to 1132_2 that are substantially the same as the column select switches 1112_1 to 1112_2. The bit line sense amplifiers 1111_1 and 1131_1 and the column select switches 1112_1 and 1132_1 may be disposed adjacent to the sub-memory blocks 1110_1 to 1130_1. The bit line sense amplifiers 1111_2 and 1131_2 and the column select switches 1112_2 and 1132_2 may be disposed adjacent to the sub-memory blocks 1110_2 to 1130_2.

[0057] Sub-memory blocks and sub-word line driver arrays driving word lines WL1 and WL2 may be further disposed between sub-memory blocks 1110_1 to 1130_1. As described above, sub-word line driver arrays and sub-memory blocks may be further disposed between sub-memory blocks 1110_2 to 1130_2. Sub-memory blocks, bit line sense amplifiers, and column select switches may be further disposed between sub-memory blocks 1110_1 and 1110_2, between sub-memory blocks 1120_1 and 1120_2, and between sub-memory blocks 1130_1 and 1130_2.

[0058] The neuromorphic device 1000d may further include neuron circuits 1220 to 1230, wherein the neuron circuit 1210 corresponds to Figure 4 The number of additional neuron circuits 1220 to 1230 may correspond to the number of sub-memory blocks arranged along the direction in which word lines WL1 to WL4 extend. Neuron circuits 1210 to 1230 may include integrators 1310 to 1330, respectively, and activation circuits 1410 to 1430, respectively. Neuron circuits 1210 to 1230 may operate substantially the same as neuron circuit 1200 and may output activation signals ACT1 to ACT3, respectively. Neuron circuit 1210 may sum at least two or more of the weights stored in memory cells MC of sub-memory blocks 1110_1 to 1110_2 at input / output line 10. As in neuron circuit 1210, each of neuron circuits 1220 and 1230 may sum two or more weights at input / output line 10.

[0059] The column decoder 1700 may include additional sub-column decoders 1720 to 1730, wherein the sub-column decoder 1710 corresponds to Figure 4 Sub-column decoder 1700. Each of sub-column decoders 1710 to 1730 can decode an internal column address ICA and can send a column select signal via a column select line CSL. For example, sub-column decoder 1710 can select memory cells MC of sub-memory blocks 1110_1 to 1110_2, sub-column decoder 1720 can select memory cells MC of sub-memory blocks 1120_1 to 1120_2, and sub-column decoder 1730 can select memory cells MC of sub-memory blocks 1130_1 to 1130_2.

[0060] exist Figure 2 and / or Figure 3 In the case of "①", the row decoder 1600 can simultaneously select the word lines WL1 and WL3 and the memory cells MC of the sub-memory blocks 1110_1 to 1130_2 connected to the word lines WL1 and WL3. Figure 2 and / or Figure 3 In the case of "②", row decoder 1600 can simultaneously select word lines WL2 and WL4 and the memory cells MC of sub-memory blocks 1110_1 to 1130_2 connected to word lines WL2 and WL4. Sub-column decoders 1710 to 1730 can apply column select signals to column select switches 1112_1 to 1132_2 via column select line CSL. Neuron circuit 1210 can simultaneously sum read signals from memory cells selected by row decoder 1600 and column decoder 1700 at input / output line IO. Neuron circuit 1220 can simultaneously sum read signals from memory cells selected by row decoder 1600 and column decoder 1700 at input / output line IO. Neuron circuit 1230 can simultaneously sum read signals from memory cells selected by row decoder 1600 and column decoder 1700 at input / output line IO. Neuron circuits 1210 to 1230 can respectively output activation signals ACT1 to ACT3. The neuron circuit 1210 can compare the sum signal of the integrator 1310 with the threshold signal TH to output the activation signal ACT1, the neuron circuit 1220 can compare the sum signal of the integrator 1320 with the threshold signal TH to output the activation signal ACT2, and the neuron circuit 1230 can compare the sum signal of the integrator 1330 with the threshold signal TH to output the activation signal ACT3. Therefore, all, some, or none of the activation signals ACT1 to ACT3 can be enabled, or all, some, or none of the activation signals ACT1 to ACT3 can be disabled.

[0061] In one embodiment, the neuron circuit 1210 can reset the row decoder 1600, the sub-column decoder 1710, and / or the integrator 1310 by using an enabled activation signal ACT1. Because the sub-column decoder 1710 selects the accessed memory cell MC via the input / output line IO connected to the neuron circuit 1210, and the integrator 1300 is included in the neuron circuit 1210, the reset operation can be a self-reset operation. The neuron circuit 1210 can reset the sub-column decoder 1720 or the sub-column decoder 1730 adjacent to the neuron circuit 1210. Each of the sub-column decoders 1710 and 1720 can disable the column select signal in response to the enabled activation signal ACT1. The sub-column decoder 1720 can disable the column select signal in response to the enabled activation signal ACT2. The integrator 1300 can drive the voltage level of the input / output line IO to a precharge level or a reset level in response to the enabled activation signal ACT1. As in the neuron circuit 1210 , the neuron circuits 1220 and 1230 may each perform a reset operation, respectively. For example, the row decoder 1600 may disable a row selection signal transmitted through a selected word line in response to the enabled activation signal ACT1 / ACT2 / ACT3 .

[0062] Figure 6 FIG. 1 is a block diagram of a neuromorphic device according to another embodiment of the present inventive concept. To avoid redundancy, additional descriptions associated with components having the same reference numerals will be omitted, and the differences between neuromorphic devices 1000d and 1000e will be mainly described.

[0063] Compared to the neuromorphic device 1000d, the neuromorphic device 1000e may further include write drivers 1810 to 1830. The memory cells are decoded by the row decoder 1600 and the column decoder 1700 (see Figure 5 ) After selection, the write driver 1810 may write and / or update weights in memory cells selected from the memory cells of the sub-memory blocks 1110_1 to 1110_2 through the input / output lines 10, respectively. As in the write driver 1810, the write drivers 1820 and 1830 may perform a write operation.

[0064] The row decoder 1600 can decode the external row address ERA and select one of the word lines WL1 to WL4. The pre-row decoder 1620 can decode the external row address ERA and select one of the sub-row decoders 1610_1 to 1610_2. When decoding the internal row address IRA, the pre-row decoder 1620 can set the upper bits of the row address bits used to select the word line of each of the sub-memory blocks 1110_1 and 1110_2 to "don't cares." When decoding the external row address ERA, the pre-row decoder 1620 can effectively decode the upper bits. When the neuromorphic device 1000e performs a neural network operation (e.g., a "neuromorphic computing operation" or "neuromorphic processing") by using the weights and biases stored in the memory cell array 1100d, the row decoder 1600 can simultaneously select two or more word lines. When the neuromorphic device 1000e updates the weights and biases stored in the memory cell array 1100d, the row decoder 1600 can select one word line. Each of the sub-column decoders 1710 to 1730 may decode an external column address ECA to transmit a column selection signal through a column selection line CSL, or may decode an internal column address ICA to transmit a column selection signal through a column selection line CSL.

[0065] For example, the external row address ERA and the external column address ECA may be sent and / or provided to the neuromorphic device 1000 e to update the weights and biases stored in the memory cell array 1100. When the neuromorphic device 1000 e performs a neural network operation, the internal row address IRA and the internal column address ICA may be internally generated by the address generator 1510 based on the activation signals ACT1 to ACT3 output from the neuron circuits 1210 to 1230.

[0066] Figure 7 Shown in detail Figure 5 To avoid redundancy, additional descriptions associated with components having the same reference numerals will be omitted and reference will be made to Figure 5 and Figure 7 A neuromorphic device 1000d is described.

[0067] Figure 5 The example in FIG shows a sub-row decoder 1610_1 connected to word lines WL1 and WL2, but in FIG. Figure 7, wherein sub-row decoder 1610_1 is connected to word lines WL1[X:0] (X is an integer of 1 or greater), decodes an internal row address IRA to select one of word lines WL1[X:0] (i.e., WL1 and WL2 belong to WL1[X:0]), and outputs a row select signal through the selected word line. The remaining sub-row decoders 1610_2 and 1610_3 may be implemented substantially the same as sub-row decoder 1610_1. Figure 5 The example of FIG. 1 shows a sub-column decoder 1710 connected to one column select line CSL, but in FIG. Figure 7 , in which the sub-column decoder 1710 is connected to the column selection line CSL[Y:0] (Y is an integer of 1 or greater) (CSL belongs to CSL[Y:0]), decodes the internal column address ICA to select one of the column selection lines CSL[Y:0], and outputs a column selection signal through the selected column selection line. ( Figure 5 The remaining sub-column decoders 1720 to 1730 may be implemented substantially the same as the sub-column decoder 1710. The sub-memory block 1110_1 may include memory cells MC corresponding to the word line WL1[X:0] and the bit line BL[K:0] (K is an integer of 1 or greater) selected simultaneously by the column select signal transmitted through the column select line CSL[Y:0]. In addition, the bit line sense amplifiers 1111_1 respectively connected to the bit lines BL[K:0] may be provided adjacent to the sub-memory block 1110_1. The sub-memory blocks 1110_2 to 1110_3 may be implemented substantially the same as the sub-memory block 1110_1, and the bit line sense amplifiers 1111_2 to 1111_3 may be provided adjacent to the sub-memory blocks 1110_2 to 1110_3, respectively.

[0068] The memory cell array 1100 may include column selection switches 1112_1 to 1112_3. The column selection switch 1112_1 may electrically connect the bit line BL[K:0] of the sub-memory block 1110_1 to the local input / output line LIO1[K:0] in response to a column selection signal transmitted through a column selection line selected from the column selection line CSL[Y:0]. The column selection switch 1112_2 may electrically connect the bit line BL[K:0] of the sub-memory block 1110_2 to the local input / output line LIO2[K:0] in response to a column selection signal transmitted through a column selection line selected from the column selection line CSL[Y:0]. The column selection switch 1112_3 may electrically connect the bit line BL[K:0] of the sub-memory block 1110_3 to the local input / output line LIO3[K:0] in response to a column selection signal transmitted through a column selection line selected from the column selection line CSL[Y:0].

[0069] For example, the sub-row decoders 1610_1, 1610_2, and 1610_3 may select word lines WL1[0], WL2[0], and WL3[0], respectively, and the sub-column decoder 1710 may select the column select line CSL[0] (or, of course, only a portion of the sub-row decoders 1610_1, 1610_2, and 1610_3 may select word lines, and one of the remaining column select lines CSL[Y:1] may be selected). The bit line sense amplifiers 1111_1, 1111_2, and 1111_3 may sense the voltage level of the bit line BL[K:0], which is changed by the weights stored in the memory cells connected to the word lines WL1[0], WL2[0], and WL3[0]. Column selection switches 1112_1, 1112_2, and 1112_3 connected to column selection line CSL[0] can electrically connect bit line BL[K:0] to local input / output lines LIO1[K:0], LIO2[K:0], and LIO3[K:0], respectively. That is, the weight stored in the selected memory cell or the read signal including the weight from the selected memory cell can be transmitted to local input / output lines LIO1[K:0], LIO2[K:0], and LIO3[K:0]. In addition, bit line sense amplifiers 1111_1, 1111_2, and 1111_3 can amplify the sensed voltage level of bit line BL[K:0] and can restore the weight stored in the memory cells connected to word lines WL1[0], WL2[0], and WL3[0].

[0070] Integrator 1300 may include local sense amplifiers 1311_1, 1311_2, and 1311_3 connected to local input / output lines LIO1[K:0], LIO2[K:0], and LIO3[K:0]. Local sense amplifier 1311_1 may drive global input / output line GIO[K:0] based on a read signal transmitted to local input / output line LIO1[K:0] (i.e., the voltage level of local input / output line LIO1[K:0]). Local sense amplifier 1311_2 may drive global input / output line GIO[K:0] based on the voltage level of local input / output line LIO2[K:0]. Local sense amplifier 1311_3 may drive global input / output line GIO[K:0] based on the voltage level of local input / output line LIO3[K:0]. As described above, when a neural network operation is performed, at least two or more of the sub-row decoders 1610_1 to 1610_3 can simultaneously select a word line. Therefore, at least two or more of the local sense amplifiers 1311_1 to 1311_3 can simultaneously drive the global input / output line GIO[K:0]. For example, the local sense amplifiers 1311_1, 1311_2, and 1311_3 respectively connected to the local input / output lines LIO1[0], LIO2[0], and LIO3[0] can simultaneously and separately drive the global input / output line GIO[0]. As in the above description, the local sense amplifiers 1311_1, 1311_2, and 1311_3 respectively connected to the local input / output lines LIO1[0], LIO2[0], and LIO3[0] can simultaneously and separately drive the global input / output line GIO[1]. Local sense amplifiers and local input / output lines can be provided in each sub-memory block arranged along the word line direction. With reference to Figures 2 to 6 The described input / output lines IO may include local input / output lines LIO1 [K: 0 ] to LIO3 [K: 0 ] and a global input / output line GIO [K: 0 ].

[0071] The integrator 1300 may include a summing circuit 1313 and global sense amplifiers 1312 connected to the global input / output lines GIO[K:0]. The global sense amplifiers 1312 may sense and amplify the voltage levels of the global input / output lines GIO[K:0]. The global sense amplifiers 1312 may sense and amplify the weights or biases of the selected memory cells summed at the global input / output lines GIO[K:0]. The global sense amplifiers 1312 may provide the sensed voltage levels of the global input / output lines GIO[K:0] to the summing circuit 1313. The integrator 1300 may sum the read signals including the weights or biases of the memory cells MC at the global input / output lines GIO[K:0] using the local sense amplifiers 1311_1 to 1311_3 and the global sense amplifier 1312. The summing circuit 1313 may sum the voltage levels of the global input / output lines GIO[K:0] provided by the global sense amplifier 1312, may generate a sum signal SOUT, and / or may provide the sum signal SOUT to the activation circuit 1400. Only the sub-column decoder 1710 and the neuron circuit 1200 refer to Figure 7 Described, but Figure 5 The remaining sub-column decoders 1720 to 1730 and the remaining neuron circuits 1220 to 1230 may be implemented the same as the sub-column decoder 1710 and the neuron circuit 1200 .

[0072] Figure 8 Shown in detail Figure 6 To avoid any inconsistency, additional descriptions associated with components having the same reference numerals will be omitted and reference will be made to Figure 6 and Figure 8 A neuromorphic device 1000 e is described, and the differences between the neuromorphic device 1000 e and the neuromorphic device 1000 d will be primarily described.

[0073] The memory cell array 1100 may include an input / output switch 1910_1 that electrically connects the local input / output line LIO1[K:0] to the global input / output line GIO[K:0], an input / output switch 1910_2 that electrically connects the local input / output line LIO2[K:0] to the global input / output line GIO[K:0], and an input / output switch 1910_3 that electrically connects the local input / output line LIO3[K:0] to the global input / output line GIO[K:0]. For example, to update the weights and / or biases stored in the memory cell array 1100, the sub-row decoder 1610_1 may select the word line WL1[0], and the sub-column decoder 1710 may select the column select line CSL[0]. The input / output switch 1910_1 may electrically connect the local input / output line LIO1[K:0] to the global input / output line GIO[K:0]. Afterwards, the write driver 1810 can write the new weight and / or new bias to the memory cell selected by the sub-row decoder 1610_1 and the sub-column decoder 1710 through the global input / output line GIO[K:0], the input / output switch 1910_1, the local input / output line LIO1[K:0], the column select switch 1112_1, and the bit line BL[K:0]. The input / output switches 1910_1 to 1910_3 can transmit the new weight or new bias to the memory cell MC. As described above, the write (or update) operation can be performed on the remaining memory cells.

[0074] Figure 9 Shown in detail Figure 70], and a global input / output line GIOB[K:0] complementary to the bit line BL[K:0]; and the integrator 1300 of the neuromorphic device 1000d / 1000e. A line and a complementary line may be a pair, the line may be one of lines BL[K:0], LIO1[K:0], LIO2[K:0], LIO3[K:0], and GIO[K:0], and the complementary line may be one of lines BLB[K:0], LIOB1[K:0], LIOB2[K:0], LIOB3[K:0], and GIOB[K:0]. The complementary line may have the same voltage level as the voltage level of the line in the precharge mode, and may have a voltage level complementary to the voltage level of the line in the remaining modes (e.g., activation mode, read mode, and write mode) other than the precharge mode. For example, the complementary line may be changed or driven in a direction opposite to the direction in which the voltage level of the line is changed.

[0075] Reference Figure 9 , the memory cell MC may be connected to the word lines WL1[0] and WL2[0]. For example, each memory cell MC may store a single bit. For example, the cell voltage level Vcell of the memory cell MC connected to the word line WL1[0] and the bit line BL[0] may be a voltage level VC1 corresponding to the first logic value, the cell voltage level Vcell of the memory cell MC connected to the word line WL1[0] and the bit line BL[1] may be a voltage level VC0 corresponding to the second logic value, the cell voltage level Vcell of the memory cell MC connected to the word line WL2[0] and the bit line BL[0] may be a voltage level VC1 corresponding to the first logic value, and the cell voltage level Vcell of the memory cell MC connected to the word line WL2[0] and the bit line BL[1] may be a voltage level VC1 corresponding to the first logic value. However, the above voltage levels are merely example embodiments. When word lines WL1[0] and WL2[0] are selected by sub-row decoders 1610_1 and 1610_2, respectively, charge sharing may occur between memory cells MC and bit line BL[0] and between memory cells MC and bit line BL[1].

[0076] The bit line sense amplifiers 1111_1 and 1111_2 can respectively sense and amplify the voltage level difference between the bit line BL[0] and the complementary bit line BLB[0], and the voltage level difference between the bit line BL[1] and the complementary bit line BLB[1]. Based on the sensing result, the bit line sense amplifier 1111_1 can drive the bit line BL[0] and the complementary bit line BLB[0] at voltage levels VBL1 and VBL0, and can drive the bit line BL[1] and the complementary bit line BLB[1] at voltage levels VBL0 and VBL1. Based on the sensing result, the bit line sense amplifier 1111_2 can drive the bit line BL[0] and the complementary bit line BLB[0] at voltage levels VBL1 and VBL0, and can drive the bit line BL[1] and the complementary bit line BLB[1] at voltage levels VBL1 and VBL0. However, the above-mentioned voltage levels VBL1 and VBL0 are merely examples and may vary depending on the cell voltage level Vcell.

[0077] For example, bit lines BL[0] / BL[1] and complementary bit lines BLB[0] / BLB[1] can be arranged together in the same sub-memory block (folded bit line architecture). For another example, bit lines BL[0] / BL[1] and complementary bit lines BLB[0] / BLB[1] can be arranged in different sub-memory blocks (open bit line architecture).

[0078] Column selection switches 1112_1 and 1112_2 can electrically connect bit line BL[0] to local input / output line LIO[0], complementary bit line BLB[0] to complementary local input / output line LIOB[0], bit line BL[1] to local input / output line LIO[1], and complementary bit line BLB[1] to complementary local input / output line LIOB[1], respectively. When column selection switch 1112_1 is turned on by a column selection signal transmitted through column selection line CSL[0], bit line sense amplifier 1111_1 can drive local input / output line LIO0[0] and complementary local input / output line LIOB0[0] at voltage levels VBL1 and VBL0, and can drive local input / output line LIO0[1] and complementary local input / output line LIOB0[1] at voltage levels VBL0 and VBL1. When the column selection switch 1112_2 is turned on by the column selection signal transmitted through the column selection line CSL[0], the bit line sense amplifier 1111_2 can drive the local input / output line LIO1[0] and the complementary local input / output line LIOB1[0] at voltage levels VBL1 and VBL0, and can drive the local input / output line LIO1[1] and the complementary local input / output line LIOB1[1] at voltage levels VBL1 and VBL0.

[0079] The local sense amplifier 1311_1 connected to the local input / output line LIO0[0] and the complementary local input / output line LIOB0[0] can drive the global input / output line GIO[0] and the complementary global input / output line GIOB[0] based on the voltage levels VBL1 and VBL0. The local sense amplifier 1311_2 connected to the local input / output line LIO1[0] and the complementary local input / output line LIOB1[0] can drive the global input / output line GIO[0] and the complementary global input / output line GIOB[0] based on the voltage levels VBL1 and VBL0.

[0080] The local sense amplifier 1311_1 connected to the local input / output line LIO0[1] and the complementary local input / output line LIOB0[1] can drive the global input / output line GIO[1] and the complementary global input / output line GIOB[1] based on the voltage levels VBL0 and VBL1. The local sense amplifier 1311_2 connected to the local input / output line LIO1[1] and the complementary local input / output line LIOB1[1] can drive the global input / output line GIO[1] and the complementary global input / output line GIOB[1] based on the voltage levels VBL1 and VBL0.

[0081] For example, each voltage level of the global input / output lines GIO[0] and GIO[1] and the complementary global input / output lines GIOB[0] and GIOB[1] may be one of voltage levels VGIO0 to VGIOR (R is an integer of 1 or greater) corresponding to the logical value of the sum of the weights (or biases) stored in the two memory cells MC. The weight and / or bias of each memory cell MC having the cell voltage level Vcell (=VC1) may be summed at the global input / output line GIO[0] and the complementary global input / output line GIOB[0]. The weight or bias of the memory cell MC having the cell voltage level Vcell (=VC0) and the memory cell MC having the cell voltage level Vcell (=VC1) may be summed at the global input / output line GIO[1] and the complementary global input / output line GIOB[1]. Therefore, the voltage levels of the global input / output lines GIO[0] and GIO[1] may be different from each other, and the voltage levels of the complementary global input / output lines GIOB[0] and GIOB[1] may be different from each other.

[0082] Reference Figure 9In the following description, a 1-bit weight (or bias) of two memory cells MC is summed at the global input / output line GIO[0] / GIO[1] and the complementary global input / output line GIOB[0] / GIOB[1]. However, the number of logic values ​​and the number of voltage levels VGIO0 to VGIOR may further increase depending on the number of weights (or biases) summed at the global input / output line GIO[0] / GIO[1] and the complementary global output line GIOB[0] / GIOB[1] or the number of bits of the bias (or weight) summed at the global input / output line GIO[0] / GIO[1] and the complementary global input / output line GIOB[0] / GIOB[1].

[0083] The global sense amplifier 1312 can be connected to the global input / output line GIO[0] and the complementary global input / output line GIOB[0], and can sense and amplify the voltage levels of the global input / output line GIO[0] and the complementary global input / output line GIOB[0]. The global sense amplifier 1312 can be connected to the global input / output line GIO[1] and the complementary global input / output line GIOB[1], and can sense and amplify the voltage levels of the global input / output line GIO[1] and the complementary global input / output line GIOB[1]. The summing circuit 1313 can sum the voltage levels of the global input / output lines GIO[1:0] and the complementary global input / output lines GIOB[1:0] provided from the global sense amplifier 1312, can generate a sum signal SOUT and a complementary sum signal SOUTB, and can provide the sum signal SOUT and the complementary sum signal SOUTB to the activation circuit 1400.

[0084] Figure 10 Shown Figure 9 Timing diagram of the operation of the neuromorphic device. At the start of operation, Figure 9 The voltage levels of the illustrated lines WL1[0], WL2[0], BL[1:0], BLB[1:0], LIO0[1:0], LIOB0[1:0], LIO1[1:0], LIOB1[1:0], GIO[1:0], and GIOB[1:0] may be precharge levels of a precharge mode.

[0085] Under the control of the row / column controller 1500, the sub-row decoders 1610_1 and 1610_2 can select the word lines WL1[0] and WL2[0] corresponding to the internal row address IRA in the active mode. When the word lines WL1[0] and WL2[0] are selected, charge sharing can occur between the bit lines BL[1:0] and the memory cells MC. Figure 9, the bit line BL[1:0] is directly connected to the memory cell MC. However, since the complementary bit line BLB[1:0] can also be connected to any other memory cell, charge sharing can occur between the complementary bit line BLB[1:0] and the other memory cells.

[0086] When charge sharing between the bit lines BL[1:0] and the memory cells MC is completed, the neural network operation of the neuromorphic device 1000d can be initiated. After charge sharing, the bit line sense amplifiers 1111_1 and 1111_2 can sense and amplify the voltage level difference between the bit line BL[0] and the complementary bit line BLB[0], and the voltage level difference between the bit line BL[1] and the complementary bit line BLB[1]. The bit lines BL[1:0] and the complementary bit lines BLB[1:0] can be expanded or amplified to a voltage level corresponding to the logic value indicated by the cell voltage level Vcell of the memory cells MC. In addition, when the neural network operation of the neuromorphic device 1000d is initiated, the sub-column decoder 1710 can enable or select the column select line CSL[0] corresponding to the internal column address ICA under the control of the row / column controller 1500. When the sub-column decoder 1710 turns on the column selection switches 1112_1 and 1112_2 by using the column selection signal transmitted through the column selection line CSL[0], the local input / output lines LIO0[1:0] and LIO1[1:0] and the complementary local input / output lines LIOB0[1:0] and LIOB1[1:0] can have the voltage levels of the bit line BL[1:0] and the complementary bit line BLB[1:0], and the sense amplifiers 1311_1 and 1311_2 can drive the global input / output line GIO[1:0] and the complementary global input / output line GIOB[1:0] based on the voltage levels of the local input / output lines LIO0[1:0] and LIO1[1:0] and the complementary local input / output lines LIOB0[1:0] and LIOB1[1:0] (i.e., the first summation). After the first summation, the summing circuit 1313 may sum the voltage level of the global input / output line GIO[K:0] and the voltage level of the complementary global input / output line GIOB[K:0] (i.e., the second summation). After the second summation, under the control of the row / column controller 1500 and / or based on the activation signal of the activation circuit 1400, the sub-row decoders 1610_1 and 1610_2 and the sub-column decoder 1710_1 may drive the voltage levels of the lines WL1[0], WL2[0], BL[1:0], BLB[1:0], LIO0[1:0], LIOB0[1:0], LIO1[1:0], LIOB1[1:0], GIO[1:0], and GIOB[1:0] to the precharge level of the precharge mode. When repeated Figure 10When the timing diagram is shown, the neural network operation of the neuromorphic device 1000d can be performed.

[0087] Figure 11 Shown in detail Figure 7 The description will focus on the neuromorphic device. Figure 11 The neuromorphic device 1000d and Figure 9 The difference between the neuromorphic device 1000d and Figure 9 The memory cell MC is different, Figure 11 Each memory cell MC can store two bits. For example, the cell voltage level Vcell of the memory cell MC connected to the word line WL1[0] and the bit line BL[0] can be the voltage level VC11 corresponding to the first logic value, the cell voltage level Vcell of the memory cell MC connected to the word line WL1[0] and the bit line BL[1] can be the voltage level VC00 corresponding to the second logic value, the cell voltage level Vcell of the memory cell MC connected to the word line WL2[0] and the bit line BL[0] can be the voltage level VC01 corresponding to the third logic value, and the cell voltage level Vcell of the memory cell MC connected to the word line WL2[0] and the bit line BL[1] can be the voltage level VC10 corresponding to the fourth logic value. However, the above voltage levels are only examples. As described above, the memory cell MC can store two or more bits, and the number of logic values ​​and the number of cell voltage levels can further increase depending on the two or more bits. However, for the convenience of illustration and description, it is assumed that each memory cell MC stores two bits.

[0088] When word lines WL1[0] and WL2[0] are selected by sub-row decoders 1610_1 and 1610_2, respectively, charge sharing can occur between memory cells MC and bit lines BL[1:0]. Bit lines BL[1:0] intersecting word line WL1[0] can have voltage levels VBL00 and VBL11 due to charge sharing. Bit lines BL[1:0] intersecting word line WL2[0] can have voltage levels VBL10 and VBL01 due to charge sharing. When column select switches 1112_1 and 1112_2 are turned on by a column select signal transmitted through column select line CSL[0], local input / output lines LIO0[1:0] may have the same voltage levels VBL00 and VBL11 as bit lines BL[1:0] crossing word line WL1[0], and local input / output lines LIO1[1:0] may have the same voltage levels VBL10 and VBL01 as bit lines BL[1:0] crossing word line WL2[0]. Each of complementary bit lines BLB[1:0] and complementary local input / output lines LIOB0[1:0] and LIOB1[1:0] may have a precharge level VPBL. With respect to the memory cell MC having the cell voltage level Vcell (=VC11, VC00, VC01, and VC10), the corresponding voltage level differences between the bit lines BL[0], BL[1], BL[0], and BL[1] and the complementary bit lines BLB[0], BLB[1], BLB[0], and BLB[1], and the corresponding voltage level differences between the local input / output lines LIO0[0], LIO0[1], LIO1[0], and LIO1[1] and the complementary local input / output lines LIOB0[0], LIOB0[1], LIOB1[0], and LIOB1[1] can indicate logic values ​​corresponding to the cell voltage level Vcell (VC11, VC00, VC01, and / or VC10), respectively. The above voltage level differences can be formed by charge sharing between the memory cell MC and the bit lines BL[0], BL[1], BL[0], and BL[1] or by the bit line sense amplifiers 1111_1 and 1111_2. For example, when a neural network operation is performed, the bit line sense amplifiers 1111_1 and 1111_2 may maintain a corresponding voltage level difference between the bit line BL[1:0] and the complementary bit line BLB[1:0].

[0089] The local sense amplifiers 1311_1 and 1311_2 may drive the global input / output line GIO[0] and the complementary global input / output line GIOB[0] based on the voltage levels VBL11, VPBL, VBL01, and VPBL of the local input / output line LIO0[0], the complementary local input / output line LIOB0[0], the local input / output line LIO1[0], and the complementary local input / output line LIOB1[0]. The local sense amplifiers 1311_1 and 1311_2 may drive the global input / output line GIO[1] and the complementary global input / output line GIOB[1] based on the voltage levels VBL00, VPBL, VBL10, and VPBL of the local input / output line LIO0[1], the complementary local input / output line LIOB0[1], the local input / output line LIO1[1], and the complementary local input / output line LIOB1[1].

[0090] For example, each voltage level of the global input / output lines GIO[0] and GIO[1] and the complementary global input / output lines GIOB[0] and GIOB[1] may be one of voltage levels VGIO0 to VGIOS (S is an integer of 1 or greater) corresponding to a logical value of the sum of weights (or biases) stored in two memory cells MC. The weights and / or biases of the memory cells MC having the cell voltage level Vcell (=VC11) and the cell voltage level Vcell (=VC01) may be summed at the global input / output line GIO[0] and the complementary global input / output line GIOB[0]. The weights and / or biases of the memory cells MC having the cell voltage level Vcell (=VC00) and the cell voltage level Vcell (=VC10) may be summed at the global input / output line GIO[1] and the complementary global input / output line GIOB[1]. The voltage level difference between the global input / output line GIO[0] and the complementary global input / output line GIOB[0] may indicate the sum of weights or biases of memory cells MC having a cell voltage level Vcell (=VC11) and a cell voltage level Vcell (=VC01). The voltage level difference between the global input / output line GIO[1] and the complementary global input / output line GIOB[1] may indicate the sum of weights or biases of memory cells MC having a cell voltage level Vcell (=VC00) and a cell voltage level Vcell (=VC10).

[0091] Reference Figure 11As described below, 2-bit weights (and / or deviations) of two memory cells MC are summed at the global input / output line GIO[0] / GIO[1] and the complementary global input / output line GIOB[0] / GIOB[1]. However, the number of logic values ​​and the number of voltage levels VGIO0 to VGIOS may be further increased depending on the number of weights (and / or deviations) summed at the global input / output line GIO[0] / GIO[1] and the complementary global input / output line GIOB[0] / GIOB[1] or the number of deviations (and / or weights) summed at the global input / output line GIO[0] / GIO[1] and the complementary global input / output line GIOB[0] / GIOB[1]. For example, "S" may be greater than "R".

[0092] Figure 12 Shown Figure 11 The timing diagram of the operation of the neuromorphic device will be mainly described. Figure 12 Timing diagram of Figure 10 The difference between the timing diagrams.

[0093] After enabling charge sharing between the bit lines BL[1:0] and the memory cells MC, the neural network operation of the neuromorphic device 1000d can be enabled. The corresponding voltage level difference between the bit lines BL[1:0] and the complementary bit lines BLB[1:0] formed by the charge sharing can correspond to the logic value indicated by the cell voltage level Vcell of the memory cells MC. When the sub-column decoder 1710 turns on the column selection switches 1112_1 and 1112_2 by using the column selection signal transmitted through the column selection line CSL[0], the local input / output lines LIO0[1:0] and LIO1[1:0] and the complementary local input / output lines LIOB0[1:0] and LIOB1[1:0] can have the voltage levels of the bit line BL[1:0] and the complementary bit line BLB[1:0], and the local sense amplifiers 1311_1 and 1311_2 can drive the global input / output line GIO[1:0] and the complementary global input / output line GIOB[1:0] based on the voltage levels of the local input / output lines LIO0[1:0] and LIO1[1:0] and the complementary local input / output lines LIOB0[1:0] and LIOB1[1:0] (e.g., first summation). After the first summation, the summing circuit 1313 may sum the voltage level of the global input / output line GIO[K:0] and the voltage level of the complementary global input / output line GIOB[K:0] (eg, a second summation).

[0094] After the second summation and before the precharge mode, the bit line sense amplifiers 1111_1 and 1111_2 may amplify and / or expand the corresponding voltage level difference between the bit line BL[1:0] and the complementary bit line BLB[1:0]. The cell voltage level Vcell stored in the memory cell MC may be restored by the expansion operation of the bit line sense amplifiers 1111_1 and 1111_2. After the recovery operation, under the control of the row / column controller 1500, the sub-row decoders 1610_1 and 1610_2 and the sub-column decoder 1710_1 may drive the voltage levels of the lines WL1[0], WL2[0], BL[1:0], BLB[1:0], LIO0[1:0], LIOB0[1:0], LIO1[1:0], LIOB1[1:0], GIO[1:0], and GIOB[1:0] to the precharge levels of the precharge mode. When repeated Figure 12 When the timing diagram is shown, the neural network operation of the neuromorphic device 1000d can be performed.

[0095] Figure 13 FIG. 1 shows a circuit diagram of an integrator according to an embodiment of the present invention. Figure 8 describe Figure 13 . The integrator 1310 may include transistors M0 to M5. The transistors M0 to M2 may drive the global input / output line GIO[0] separately and simultaneously depending on the voltage levels of the local input / output lines LIO0[0] to LIO2[0]. For example, the transistors M0 to M2 may be placed at the local sense amplifiers 1311_1 to 1311_3, respectively. The transistor M3 may reset and / or precharge the global input / output line GIO[0] depending on the reset signal RST1. The reset signal RST1 may be the activation signal ACTa / ACTb of the activation circuit 1400, or may be a signal generated based on the activation signal ACTa / ACTb. Based on the selection signal SE1 and the complementary selection signal SEB1, the transistors M4 and M5 connected to the power supply voltage VDD and GND may or may not select the global input / output line GIO[0]. For example, the selection signal SE1 and the complementary selection signal SEB1 may be generated by the sub-column decoder 1710 that decodes the internal column address ICA or the external column address ECA. For example, transistors M3 to M5 may be placed at the global sense amplifier 1312. The integrator 1310 may further include transistors connected to the global input / output line GIO[K:1], the complementary global input / output line GIOB[K:0], the local input / output lines LIO1[K:1] to LIO3[K:1] and the complementary local input / output lines LIOB1[K:0] to LIOB3[K:0], a transistor connected to the reset signal RST1, and transistors connected to the selection signal SE1 and the complementary selection signal SEB1, which are connected similarly to the integrator 1310. Figure 13 The connections are shown. Figure 13 In FIG. 5 , the types of transistors, the connection relationship of the transistors, and the power supply voltage are merely examples and can be adjusted accordingly.

[0096] Figure 14 FIG. 1 shows a circuit diagram of a summing circuit according to an embodiment of the inventive concept. Figure 8 describe Figure 14 . The summing circuit 1313 may include transistors M6 to M11. Transistors M6 to M8 may drive the output lines separately and simultaneously depending on the voltage level of the global input / output line GIO[K:0] provided from the global sense amplifier 1312, thereby generating the sum signal SOUT. Transistor M9 may reset or precharge the output line depending on the reset signal RST2. For example, the reset signal RST2 may be substantially the same as the reset signal RST1. Based on the selection signal SE2 and the complementary selection signal SEB2, transistors M10 and M11 connected to the power supply voltage VDD and GND may or may not select the output line. For example, the selection signal SE2 and the complementary selection signal SEB2 may be substantially the same as the selection signal SE1 and the complementary selection signal SEB1. The summing circuit 1313 may also include transistors that drive the complementary output lines separately and simultaneously depending on the voltage level of the complementary global input / output line GIOB[K:0], transistors connected to the reset signal RST2, and transistors connected to the selection signal SE2 and the complementary selection signal SEB2, which are connected similarly to Figure 14 The connections are shown. Figure 14 In the figures, the types of transistors, the connection relationship of the transistors, and the power supply voltages are merely examples and can be adjusted accordingly.

[0097] Figure 15 A circuit diagram of an activation circuit according to an embodiment of the present inventive concept is shown. Activation circuit 1400 may include a comparator 1411 that compares signals SOUT and SOUTB with a threshold signal TH. For example, when the sum signal SOUT exceeds the threshold signal TH and the complementary sum signal SOUTB does not exceed the threshold signal TH, comparator 1411 may enable activation signal ACT and then disable activation signal ACT. The period during which activation signal ACT is enabled may be predetermined. Alternatively, when the sum signal SOUT does not exceed the threshold signal TH and the complementary sum signal SOUTB exceeds the threshold signal TH, comparator 1411 may disable activation signal ACT. For example, activation signal ACT may be a pulse signal that is selectively output depending on the comparison result.

[0098] Figure 16FIG. 2 is a block diagram of a neuromorphic device according to an embodiment of the inventive concept. A neuromorphic device 2000 may include a memory bank 2100 , a bus 2200 , a programmable router 2300 , and a peripheral circuit 2400 .

[0099] The memory bank 2100 may include a memory cell array 2110, a neuron circuit array 2120, a row / column controller 2150, a row decoder 2160, a column decoder 2170, and a write driver array 2180. The components 2110, 2150, 2160, and 2170 may be connected to a reference circuit. Figures 2 to 15 The components 1100, 1500, 1600 and 1700 described are substantially the same. The neuron circuit array 2120 may include reference Figures 2 to 15 The neuron circuits 1200 and 1210 to 1230 described above are shown in FIG. 2. The write driver array 2180 may include reference to FIG. Figures 2 to 15 Described are write drivers 1810 to 1830.

[0100] The bus 2200 can provide interconnection paths between the memory banks 2100, between the programmable routers 2300, between the peripheral circuits 2400 and the memory banks 2100, or between the peripheral circuits 2400 and the programmable routers 2300. For example, when the weights or biases stored in the memory cell array 2110 are updated, the addresses (including external memory bank addresses, external row addresses, and / or external column addresses) indicating the memory cells storing the previous weights or biases, the new weights, and the new biases can be transmitted to the memory banks via the bus 2200. For another example, when the neuromorphic device 2000 performs a neural network operation, an activation signal of the neuron circuit array 2120 of the first memory bank 2100 can be transmitted to the second memory bank 2100 (e.g., a target memory bank). In this case, the row / column controller 2150 of the second memory bank 2100 can generate internal addresses (e.g., internal row addresses and internal column addresses) for selecting memory cells of the memory cell array 2110 based on the transmitted activation signal.

[0101] The programmable router 2300 may receive an activation signal from the neuron circuit array 2120 of the first memory bank 2100 via the bus 2200, may generate an internal memory bank address corresponding to the second memory bank 2100 based on the received activation signal, and may transmit the received activation signal to the second memory bank 2100. Here, the internal memory bank address may indicate the memory cell array 2110 of the corresponding memory bank 2100. The programmable router 2300 may include: a memory bank address generator 2310 that generates a plurality of internal memory bank addresses corresponding to a plurality of different memory banks 2100 based on the received activation signal; and an arbiter 2320 that transmits the received activation signal to each of the plurality of different memory banks 2100 based on the plurality of internal memory bank addresses.

[0102] Specifically, the bank address generator 2310 may receive an activation signal ACT1 from the neuron circuit array 2120 of the first memory bank BK1 and, based on the activation signal ACT1, generate an internal memory bank address indicating the second memory bank BK2. The arbiter 2320 may transmit the activation signal ACT1 to the row / column controller 2150 of the second memory bank BK2 based on the internal memory bank address of the bank address generator 2310. The bank address generator 2310 may receive an activation signal ACT2 from the neuron circuit array 2120 of the second memory bank BK2 and, based on the activation signal ACT2, generate an internal memory bank address indicating the first memory bank BK1. The arbiter 2320 may transmit the activation signal ACT2 to the row / column controller 2150 of the first memory bank BK1 based on the internal memory bank address of the bank address generator 2310. As described above, the activation signal ACT1 of the neuron circuit array 2120 of the first memory bank BK1 can be provided to the row / column controller 2150 of the first memory bank BK1, and the activation signal ACT2 of the neuron circuit array 2120 of the second memory bank BK2 can be provided to the row / column controller 2150 of the first memory bank BK1. The row / column controller 2150 of the first memory bank BK1 can generate an internal row address IRA and an internal column address ICA based on the activation signal ACT1 or the activation signal ACT2. The row / column controller 2150 of the first memory bank BK1 can generate an internal row address IRA and an internal column address ICA based on the activation signal ACT1 or the activation signal ACT2. An example is shown in which the first memory bank BK1 and the second memory bank BK2 are adjacent to each other, but the first memory bank BK1 and the second memory bank BK2 may not be adjacent to each other.

[0103] The programmable router 2300 can dynamically adjust the number of memory banks 2100 of the neuromorphic device 2000 based on the received activation signal. In the case where the neuromorphic device 2000 performs a neural network operation, the neuron circuit array 2120 can be formed by reusing the neuron circuit array 2120 in one memory bank 2100. Figure 1 The layers IL, HL and OL of the memory bank 2100 are formed, and the neuron circuit array 2120 can be formed when the neuron circuit array 2120 between the multiple memory banks 2100 is reused. Figure 1 The arbiter 2320 of the programmable router 2300 can arbitrate communications between the memory banks 2100 connected to the bus 2200, any other programmable routers 2300, and the peripheral circuits 2400. For example, the weights stored in the memory cell array 2110 of the first memory bank 2100 can indicate the connection strength of the neuron circuit array 2120 reused in the first memory bank 2100. For another example, the weights stored in the memory cell array 2110 of the first memory bank 2100 can indicate the connection strength of the neuron circuit array 2120 of the first memory bank 2100 and the neuron circuit array 2120 of the second memory bank 2100.

[0104] The peripheral circuit 2400 may include a clock buffer 2410, a command and address buffer 2420, a command decoder 2430, an address demultiplexer 2440, a refresh controller 2450, a data input / output circuit 2460, a DQ buffer 2470, and a DQS buffer 2480. The clock buffer 2410 may receive a clock signal CK from the outside and may provide a clock signal ICK to any other component of the peripheral circuit 2400. The command and address buffer 2420 may receive command and address signals CA based on the clock signal CK received by the clock buffer 2410. The command and address signals CA may include an external bank address EBA, an external row address ERA, and an external column address ECA. Furthermore, the command and address signals CA may also include various commands for the memory cell array 2110, such as an activate command, a read command, a write command, and a precharge command. The neuromorphic device 2000 may operate synchronously with the clock signal CK. The command and address buffer 2420 may provide commands to the command decoder 2430 and addresses to the address demultiplexer 2440. The command decoder 2430 may decode the command and, based on the decoding result, may control the components 2100, 2200, 2300, 2410, 2420, and 2440 to 2480 of the neuromorphic device 2000. The address demultiplexer 2440 may receive the address and provide the received address to the memory bank 2100 as an external row address ERA or an external column address ECA via the bus 2200 or the programmable router 2300. The address demultiplexer 2440 may provide the external row address ERA or the external column address ECA to the memory bank 2100 indicated by the external bank address EBA.

[0105] The refresh controller 2450 may perform a refresh operation to restore the weight or bias stored in the memory cell array 2110. For example, the refresh controller 2450 may generate a refresh row address for a word line connected to a memory cell in which the weight or bias to be restored is stored, and a refresh bank address for the memory bank 2100 in which the memory cell is located. The refresh controller 2450 may select the memory bank 2100 based on the refresh bank address, and may transmit the refresh row address to the row decoder 2160 of the memory bank 2100 via the bus 2200 or the programmable router 2300. The row decoder 2160 may select the memory cell corresponding to the refresh row address, and the bit line sense amplifier connected to the selected memory cell may refresh or restore the weight or bias stored in the selected memory cell.

[0106] Under the control of the command decoder 2430, the data input / output circuit 2460 can process write data (e.g., weights or biases) to be written to the memory bank 2100 and can send (e.g., provide) the write data to the write driver array 2180 of the memory bank 2100 through the bus 2200 or the programmable router 2300. The data input / output circuit 2460 can control the DQ buffer 2470 and the DQS buffer 2480 to receive the write data from the external device. Under the control of the command decoder 2430, the data input / output circuit 2460 can receive read data including activation signals of the neuron circuit array 2120 of the memory bank 2100 through the bus 2200 or the programmable router 2300 and can process the read data. The data input / output circuit 2460 can control the DQ buffer 2470 and the DQS buffer 2480 to output the read data to the external device. The DQ buffer 2470 and the DQS buffer 2480 can respectively receive a write DQ signal including write data and a write DQS signal for capturing (and / or sampling) the write DQ signal, or can respectively transmit a read DQ signal including read data and a read DQS signal to the outside. Here, the DQ signal can be a bidirectional data input / output signal serving as a write DQ signal or a read DQ signal, and the DQS signal can be a bidirectional data strobe signal serving as a write DQS signal or a read DQS signal.

[0107] Furthermore, the clock buffer 2410, the command and address buffer 2420, the command decoder 2430, the address demultiplexer 2440, the refresh controller 2450, the data input / output circuit 2460, the DQ buffer 2470, and the DQS buffer 2480 may include processing circuitry, such as hardware including logic circuitry, a hardware / software combination, such as a processor running software, or a combination thereof. For example, the processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), and the like.

[0108] Figure 17 Shown Figure 16 The artificial neural network 2000 can be run with the neuromorphic device. Figure 1 The external bank address EBA, external row address ERA, and external column address ECA included in the command and address signals CA provided to the neuromorphic device 2000 may correspond to input data of the artificial neural network 2000 (e.g., Figure 1Various commands included in the command and address signals CA provided to the artificial neural network 2000 may correspond to input data of the artificial neural network 2000. Read data 2000 included in the read DQ output from the neuromorphic device 2000 may correspond to output data of the artificial neural network 2000 (e.g., Figure 1 The above-mentioned internal bank address IBA, internal row address IRA, and internal column address ICA may indicate connections (e.g., synapses) between the nodes IN1 to IN3 of the input layer IL and the nodes HN1 to HN4 of the hidden layer HL, connections between the nodes HN1 to HN8 of the hidden layer HL, and connections between the nodes HN5 to HN8 of the hidden layer HL and the nodes ON1 to ON3 of the output layer OL.

[0109] Figure 18 It shows Figure 16 Flowchart of an operating method of a neuromorphic device. In operation S110, the command and address buffer 2420 of the neuromorphic device 2000 may receive a command and address signal CA from an external device. In operation S120, the command decoder 2430 may decode the command and may determine whether the command received in operation S110 is a write command.

[0110] When the command is a write command (Y), in operation S130, the command decoder 2430 may select the memory bank 2100 corresponding to the memory bank address included in the address received in operation S110 through the bus 2200. The address demultiplexer 2440 may transmit the external row address ERA and the external column address ECA included in the address received in operation S110 to the memory bank 2100 corresponding to the memory bank address through the bus 2200. The DQ buffer 2470 and the DQS buffer 2480 may receive the write DQ signal and the write DQS signal including the write data, and the data input / output circuit 2460 may process the write data and transmit the write data to the memory bank 2100 corresponding to the memory bank address through the bus 2200 or the programmable router 2300. Here, the write data may be weighted or biased. The row decoder 2160 and the column decoder 2170 of the memory bank 2100 corresponding to the memory bank address may select a memory cell corresponding to the external row address ERA and the external column address ECA, and the write driver array 2180 may write write data into the selected memory cell.

[0111] When the command is a read command (N), in operation S140, the neuromorphic device 2000 may perform a neural network operation. The command received in operation S110 may be, for example, a read command. In this case, the command and address received in operation S110 may be considered to be input to the reference device. Figure 1 The command decoder 2430 can select the memory bank 2100 corresponding to the memory bank address included in the address received in operation S110 via the bus 2200. The address demultiplexer 2440 can transmit the external row address ERA and external column address ECA included in the address received in operation S110 to the memory bank 2100 corresponding to the memory bank address via the bus 2200. The neuron circuit array 2120 can sum the weights and / or biases stored in the memory cells corresponding to the external row address ERA and external column address ECA and output an activation signal. That is, the word lines and column select lines corresponding to the external row address ERA and external column address ECA can play the role of input data, which is input to the input layer IL of the neural network ANN and multiplied by the weights of the input layer IL. The row / column controller 2150 can generate the internal row address IRA and internal column address ICA based on the activation signal. The neuron circuit array 2120 may sum the weights and / or biases stored in the memory cells corresponding to the internal row address IRA and the internal column address ICA, and may further output an activation signal. When the above process is repeated, the neuron circuit array 2120 may be reused. The internal row address IRA and the internal column address ICA may be regarded as input data, which are input to the reference Figure 1 The hidden layer HL or output layer OL of the neural network ANN described above is multiplied by the weights of the hidden layer HL or output layer OL. The word lines and column select lines corresponding to the internal row address IRA and the internal column address ICA can play the role of input data, which is input to the hidden layer HL of the neural network ANN. In addition, the programmable router 2300 can generate a memory bank address corresponding to another memory bank 2100 based on the activation signal. The row / column controller 2150 of the other memory bank 2100 can generate the internal row address IRA and the internal column address ICA based on the activation signal provided by the programmable router 2300. The neuron circuit array 2120 of the other memory bank 2100 can sum the weights or biases stored in the memory cells corresponding to the internal row address IRA and the internal column address ICA, and can output the activation signal. The row / column controller 2150 can further generate the internal row address IRA and the internal column address ICA based on the activation signal. The neuron circuit array 2120 may sum the weights and / or biases stored in the memory cells corresponding to the internal row address IRA and the internal column address ICA, and may further output an activation signal. When the above process is repeated, the neuromorphic device 2000 may perform a neural network operation.

[0112] In operation S150, the data input / output circuit 2460 may receive an activation signal from the memory bank 2100 through the bus 2200 or the programmable router 2300 and may generate read data. Under the control of the data input / output circuit 2460, the DQ buffer 2470 and the DQS buffer 2480 may output a read DQ signal and a DQS signal including the read data to the outside.

[0113] In one embodiment, the reference Figures 2 to 16 In another embodiment, the threshold signal TH may be updated by a command received in operation S110. Information about the voltage level and / or current level of the threshold signal TH may be stored in a partial area of ​​the memory cell array 1100 / 2110 or in a register. The command received in operation S110 may be a write command for requesting a write operation of a partial area of ​​the memory cell array 1100 / 2110, a mode register setting command, a mode register write command, a multi-purpose command (MPC), or the like. Although in Figure 16 Although not shown, the peripheral circuit 2400 may further include a voltage generator and / or a current generator to generate a threshold signal TH. The command decoder 2430 may update information regarding the threshold signal TH stored in a partial region of the memory cell array 1100 / 2100 or in a register based on the command received in operation S110, and the voltage generator or current generator may variously change the threshold signal TH with reference to the updated information. For example, the voltage generator or current generator may generate one threshold signal TH, or may generate two or more threshold signals TH. Therefore, the one threshold signal TH may be commonly provided to the neuron circuit arrays 2120 of all memory banks 2100, or the two or more threshold signals TH may be provided to the neuron circuit arrays 2120 of each memory bank 2100. That is, the threshold signals TH of the neuron circuit arrays 2120 of each memory bank 2100 may be the same or different from each other, and the threshold signals TH of the neuron circuits 1210 to 1230 may be the same or different from each other.

[0114] Figure 19 FIG. 3 is a block diagram of a neuromorphic device according to an embodiment of the present invention. The neuromorphic device 3000 may include memory (processing) dies 3100 and 3200 and a buffer die 3300. The neuromorphic device 3000 may include a plurality of channels CH1 to CH3. Here, each of the channels CH1 to CH3 may include Figure 16 The through-silicon vias (TSVs) may provide physical and / or electrical paths between the memory dies 3100 and 3200 and the buffer die 3300 .

[0115] The memory die 3100 may include an active region 3110 and a transition region 3120. All components or references to the neuromorphic devices 1000a to 1000e Figure 16 Components 2100, 2200, and 2300 of the depicted neuromorphic device 2000 may be disposed in the active region 3110. Through-silicon vias (TSVs) may be disposed in the transition region 3120, or circuits for transmitting or receiving signals through the TSVs may be disposed therein. Memory die 3200 may be implemented substantially the same as memory die 3100.

[0116] The buffer die 3300 (e.g., a "core die" or a "logic die") may include an active region 3310 and a transition region 3320. A circuit for receiving or outputting signals transmitted from the outside through channels CH1 to CH3, all components of the neuromorphic devices 1000a to 1000e, and / or references Figure 16 All components of the described neuromorphic device 2000 may be provided in the active region 3310 . Through-silicon vias (TSVs) and / or circuits for transmitting or receiving signals through the through-silicon vias (TSVs) may be provided in the transition region 3320 .

[0117] Figure 20 FIG. 4 is a block diagram of a system on chip according to an embodiment of the present inventive concept. The system on chip (SoC) 4000 may be an application processor (AP). The system on chip 4000 may include a neural processing unit (NPU) 4100 .

[0118] NPU 4100 may include a core 4110, a bus 4120, a programmable router 4130, and glue logic circuits 4140. Core 4110 may include a memory cell array 4111, a neuron circuit array 4112, a row / column controller 4115, a row decoder 4116, a column decoder 4117, and a write driver array 4118. Core 4110 and components 4111 to 4118 may be substantially the same as memory bank 2100 and components 2110 to 2180. As in the core of CPU 4200 or GPU 4300, core 4110 may fetch, issue, and / or schedule instructions, and may perform arithmetic operations, logical operations, and / or shift operations of an arithmetic logic unit (ALU). Core 4110 may perform neural network operations using components 4111 to 4118. Bus 4120 and programmable router 4130 may be substantially the same as bus 2200 and programmable router 2300 described above.

[0119] The glue logic circuit 4140 may include circuits configured to interconnect and interface the cores 4110 and cache memories shared by the cores 4110. The glue logic circuit 4140 may include at least a portion or all of the components 2410 to 2480 of the peripheral circuit 2400 of the neuromorphic device 2000. The glue logic circuit 4140 may serve as an interface circuit for the NPU 4100 to communicate with other components 4200 to 4700 in the SoC 4100 via the bus 4800, and may connect the cores 4310 and the system bus 4800. The system on chip 4000 may include a central processing unit (CPU) 4200, a graphics processing unit (GPU) 4300, an interface circuit 4400 for performing communication with an external device or user device, an external memory controller 4500 for controlling an external memory device (not shown), a multimedia controller 4600 for controlling a multimedia device (not shown), a display controller 4700 for controlling a display device (not shown), and a system bus 4800 that provides an interface and communication (or transmission) path between components 4100 to 4700.

[0120] In some example embodiments, some or all of any system according to any example embodiment, including some or all of the peripheral circuit 2400 and the neuron circuit 1200 (including some or all of the integrator 1300, the activation circuit 1400, the row / column decoder 1500, the row decoder 1600, the column decoder 1700, the address generator 1510, the pre-row decoder 1620, the clock buffer 2410, the command and address buffer 2420, the command decoder 2430, the address demultiplexer 2440, the refresh controller 2450, the data input / output circuit 2460, the DQ buffer 2470, and the DQS buffer 2480), may include, may be included in, and / or may be implemented by: one or more instances (e.g., items, parts, units, etc.) of processing circuitry, such as hardware including logic circuitry; a hardware / software combination, such as a processor running software; or a combination thereof. For example, the processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), and the like. In some example embodiments, the processing circuitry may include: a non-transitory computer-readable storage device or memory storing an instruction program, such as a solid-state drive (SSD); and a processor configured to execute the instruction program to implement some or all of the functionality of any system according to any example embodiment. It will be understood that, as described herein, an element (e.g., a processing circuit, a digital circuit, etc.) described as "implementing" an element (e.g., integrator 1300, activation circuit 1400, row / column decoder 1500, row decoder 1600, column decoder 1700, address generator 1510, and pre-row decoder 1620, etc.) will be understood to implement the functionality of the implemented element (e.g., the functionality of neuron circuit 1200, peripheral circuit 2400, etc.).

[0121] A neuromorphic device according to an embodiment of the present invention can operate based on a highly integrated and low-power memory. The neuromorphic device can update weights and biases by using a write operation of the memory. The neuromorphic device can perform neural network operations by using a non-destructive read operation of the memory. The neuromorphic device can increase the number of neuron circuits by reusing neuron loops.

[0122] While the inventive concepts have been described with reference to example embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the inventive concepts as set forth in the appended claims.

Claims

1. A neuromorphic device comprising: a first memory cell array comprising a first memory cell corresponding to a first address and a second memory cell corresponding to a second address, the first memory cell being configured to store a first weight, and the second memory cell being configured to store a second weight; a first neuron circuit including a first integrator and a first activation circuit, the first integrator being configured to sum a first read signal from the first memory cell and output the first sum signal to the first activation circuit, and to sum a second read signal from the second memory cell and output the second sum signal to the first activation circuit, the first activation circuit being configured to output a first activation signal based on a first sum signal of the first read signal output from the integrator and a second activation signal based on a second sum signal of the second read signal output from the integrator; a row decoder configured to decode a first internal row address of the first address and a second internal row address of the second address, respectively; as well as a column decoder configured to decode a first internal column address of the first address and a second internal column address of the second address, respectively, The row decoder and the column decoder sequentially select the first memory unit and the second memory unit.

2. The neuromorphic device of claim 1 , wherein: At least one of the second weights indicates a connection strength between a first neuron circuit receiving the first read signal and a neuron circuit receiving the second read signal.

3. The neuromorphic device of claim 1 , further comprising: The address generator is configured to generate a second address based on the first activation signal and to generate a third address based on the second activation signal.

4. The neuromorphic device of claim 1 , wherein: The row decoder is configured to decode a first internal row address to simultaneously select first word lines respectively connected to the first memory cells, and to decode a second internal row address to simultaneously select second word lines respectively connected to the second memory cells.

5. The neuromorphic device of claim 4, wherein: The row decoder is configured to set upper bits of row address bits for selecting a word line of a sub-memory block to don't care bits, and The first word line and the second word line are respectively placed in the sub-memory blocks.

6. The neuromorphic device of claim 1 , wherein: The first activation circuit is configured to reset at least one of the row decoder, the column decoder, and the integrator by using at least one of the first activation signal or the second activation signal.

7. The neuromorphic device of claim 6, wherein: The first memory cell array further includes: a third memory cell corresponding to a third address, the third memory cell being configured to store a third weight; and a fourth memory cell corresponding to a fourth address, the fourth memory cell being configured to store a fourth weight, and Wherein, in response to at least one of the first activation signal or the second activation signal being enabled, the column decoder is configured to disable a first column selection signal that selects a first bit line connected to the first memory cell and the second memory cell, and is configured to disable a second column selection signal that selects a second bit line connected to the third memory cell and the fourth memory cell.

8. The neuromorphic device of claim 1 , further comprising: a programmable router configured to generate a memory bank address based on at least one of the first activation signal or the second activation signal; a second memory cell array including a third memory cell corresponding to the bank address and configured to store a third weight; as well as a second neuron circuit including a second integrator and a second activation circuit, the second integrator being configured to sum a third read signal from a third memory cell and output a third sum signal, the second activation circuit being configured to output a third activation signal based on the third sum signal of the third read signal, and At least one of the third weights indicates a connection strength between the first neuron circuit and the second neuron circuit.

9. The neuromorphic device of claim 1 , wherein: The first memory unit and the second memory unit are configured to each store one or more bits.

10. A neuromorphic device comprising: a memory cell array comprising memory cells; input / output lines configured to access the memory cells and write weights into the memory cells; a neuron circuit including an integrator and an activation circuit, the integrator configured to sum read signals from the memory cells at an input / output line and output a sum signal to the activation circuit, the activation circuit configured to receive the sum signal and output an activation signal based on the sum signal of the read signals output from the integrator; a write driver configured to write the weights to the memory cells via the input / output lines; a row decoder configured to select a word line connected to one of the memory cells before writing one of the weights into the one of the memory cells by a write driver, and to select all word lines respectively connected to the memory cells before outputting a read signal from the memory cell; as well as The column decoder is configured to select a column select line through which a column select signal that selects a bit line connected to a memory cell is transmitted.

11. The neuromorphic device of claim 10 , further comprising: an address generator configured to generate an internal row address and an internal column address based on the activation signal, in, a row decoder configured to decode an internal row address to select all word lines and to decode an external row address of the neuromorphic device to select a word line connected to the one of the memory cells, wherein the column decoder is configured to decode an internal column address to select a column select line and decode an external column address to select a column select line, and The external row address and the external column address correspond to input data of a neural network executed by the memory cell array, the row decoder, the column decoder, and the neuron circuit, and the input data is multiplied by at least a portion of the weights.

12. The neuromorphic device of claim 10, wherein The memory cell array further includes an input / output switch configured to transfer the weight to the memory cell through the input / output line, and in, The integrator includes a local sense amplifier configured to simultaneously drive the input / output lines based on read signals respectively sensed by bit line sense amplifiers connected to the bit lines, and a global sense amplifier connected to the input / output lines and simultaneously driven by the local sense amplifier.

13. The neuromorphic device of claim 10 , further comprising: a command decoder configured to decode a first command to control the row decoder, the column decoder, and the write driver, and to decode a second command to control the row decoder, the column decoder, and the neuron circuit; and A data input / output circuit is configured to receive a weight under the control of a command decoder that decodes a first command, provide the weight to a write driver, and output read data to an external device based on an activation signal under the control of a command decoder that decodes a second command.

14. The neuromorphic device of claim 10, wherein: Bit line sense amplifiers respectively connected to the bit lines are configured to restore weights stored in memory cells.

15. A neuromorphic device comprising: A neuron circuit includes an integrator and an activation circuit that compares a sum signal of the integrator with a threshold signal to output a pulse signal, wherein the integrator includes: a first local sense amplifier configured to output a first weight stored in the first memory cell and sensed by the first bit line sense amplifier to a first global input / output line; a second local sense amplifier configured to output a second weight stored in the second memory cell and sensed by the second bit line sense amplifier to the first global input / output line; a third local sense amplifier configured to output a third weight stored in the third memory cell and sensed by the third bit line sense amplifier to the second global input / output line; a fourth local sense amplifier configured to output a fourth weight stored in a fourth memory cell and sensed by a fourth bit line sense amplifier to a second global input / output line; a first global sense amplifier configured to sense a first weight and a second weight summed at a first global input / output line; a second global sense amplifier configured to sense the third weight and the fourth weight summed at the second global input / output line; as well as a summing circuit configured to sum the first to fourth weights sensed by the first global sense amplifier and the second global sense amplifier to output a sum signal, and A memory cell array, the memory cell array comprising: first to fourth memory units; first to fourth bit line sense amplifiers configured to output first to fourth weights to first to fourth local input / output lines, respectively; a first input / output switch electrically connecting the first local input / output line to the first global input / output line; a second input / output switch electrically connecting the second local input / output line to the first global input / output line; a third input / output switch electrically connecting the third local input / output line to the second global input / output line; and The fourth input / output switch electrically connects the fourth local input / output line to the second global input / output line.

16. The neuromorphic device of claim 15 , further comprising: a row decoder configured to control a first word line connected to the first memory cell and the third memory cell and a second word line connected to the second memory cell and the fourth memory cell; and a column decoder configured to control a column selection line, wherein a column selection signal is transmitted through the column selection line, the column selection line electrically connecting at least one of the first bit lines connected to the first memory cell to the first local input / output line, and electrically connecting the second bit line connected to the second memory cell to the second local input / output line or electrically connecting the third bit line connected to the third memory cell to the third local input / output line, and electrically connecting the fourth bit line connected to the fourth memory cell to the fourth local input / output line.

17. The neuromorphic device of claim 16 , further comprising: The address generator is configured to generate an internal row address and an internal column address based on the pulse signal.

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