Display panel and manufacturing method thereof, and display device

Abstract

The present invention provides a display panel and a manufacturing method thereof, and a display device, which relate to the field of display technology, and solve the problem in the related technology that when a fingerprint recognition module is integrated inside an electronic device, the fingerprint recognition module is likely to have an adverse effect on the working performance of a driving circuit in the electronic device. The display panel includes a driving circuit layer, a plurality of pixel units, and a first shading pattern arranged on a substrate; the driving circuit layer includes a plurality of sub-pixel driving circuits and a first signal line, the sub-pixel driving circuit corresponds to the sub-pixels included in the pixel unit one by one, the sub-pixel driving circuit is coupled to the first electrode in the corresponding sub-pixel, and the first signal line is used to provide a first signal with a fixed potential to the sub-pixel driving circuit; the first shading pattern is electrically connected to the first signal line, and the first shading pattern has a plurality of imaging pinholes. The display panel is used to display images.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof, and a display device. Background Art

[0002] In the field of electronic devices, especially mobile phones, it has become standard to use biometrics, especially fingerprint recognition technology, for identity authentication and other operations. Currently, fingerprint recognition modules are usually external and are usually set on the back of the phone or integrated on the HOME button of the phone. The method of setting it on the back of the phone is not conducive to the convenience of operation, and the method of setting it on the HOME button does not achieve full-screen display.

[0003] In view of the existence of the above problems, the related art considers integrating the fingerprint recognition module inside the electronic device, but this method makes it easy for the fingerprint recognition module to have an adverse effect on the working performance of the driving circuit in the electronic device. Summary of the invention

[0004] The object of the present invention is to provide a display panel and a manufacturing method thereof, and a display device, which are used to solve the problem in the related art that when a fingerprint recognition module is integrated inside an electronic device, the fingerprint recognition module is likely to have an adverse effect on the working performance of a driving circuit in the electronic device.

[0005] A first aspect of the present invention provides a display panel, comprising: a substrate, a driving circuit layer arranged on the substrate, and a plurality of pixel units arranged on a side of the driving circuit layer facing away from the substrate; each of the pixel units comprises at least two sub-pixels, each of the sub-pixels comprises an organic electroluminescent element, the organic electroluminescent element comprises: a first electrode, an organic light-emitting layer, and a second electrode stacked in sequence in a direction away from the substrate; the driving circuit layer comprises: a plurality of sub-pixel driving circuits and a first signal line, the sub-pixel driving circuits correspond to the sub-pixels one-to-one, the sub-pixel driving circuits are coupled to the first electrodes in the corresponding sub-pixels, and the first signal line is used to provide a first signal with a fixed potential to the sub-pixel driving circuit; the display panel also comprises: a first shading pattern arranged on the substrate, the first shading pattern is electrically connected to the first signal line, and the first shading pattern has a plurality of imaging pinholes.

[0006] Optionally, each of the sub-pixel driving circuits includes a driving transistor, a storage capacitor and a first capacitor; wherein the gate of the driving transistor is multiplexed as the first plate of the storage capacitor and is multiplexed as the first plate of the first capacitor;

[0007] The second plate of the storage capacitor is located at a side of the gate of the driving transistor away from the substrate, and the second plate of the storage capacitor is connected to the first signal line;

[0008] The orthographic projection of the first light-shielding pattern on the substrate at least partially overlaps with the orthographic projection of the gate of the driving transistor on the substrate, and the first light-shielding pattern is multiplexed as the second plate of the first capacitor.

[0009] Optionally, the first signal line is located on a side of the second plate of the storage capacitor away from the substrate, an orthographic projection of the first signal line on the substrate and an orthographic projection of the first shading pattern on the substrate have an overlapping area, and the first signal line is connected to the first shading pattern through at least one via hole arranged in the overlapping area.

[0010] Optionally, the via holes correspond to the sub-pixels one-to-one, and the orthographic projection of each via hole on the substrate is located within a preset range around the orthographic projection of the corresponding sub-pixel on the substrate.

[0011] Optionally, the driving circuit layer further includes a power signal line, and the power signal line is multiplexed as the first signal line.

[0012] Optionally, the display panel includes a display area and a non-display area located around the display area;

[0013] The driving circuit layer further includes: a second signal line located in the non-display area;

[0014] The display panel further includes: a second shading pattern provided with the same layer and the same material as the first shading pattern, the second shading pattern being located in the non-display area and insulated from the first shading pattern, the second shading pattern being multiplexed as at least part of the second signal line.

[0015] Optionally, the non-display area includes a fan-out area;

[0016] The driving circuit layer further includes: a third signal line located in the display area;

[0017] The second signal line includes a signal lead-out line located in the fan-out area and corresponding to the third signal line one by one, and the signal lead-out line is connected to the corresponding third signal line;

[0018] The second light shielding pattern is multiplexed as at least a portion of the signal lead-out line.

[0019] Optionally, the driving circuit layer further includes a first gate metal layer and a second gate metal layer arranged in different layers, and the first gate metal layer and the second gate metal layer are both located in the fan-out area; wherein the first gate metal layer and the gate of the driving transistor are arranged in the same layer and the same material, and the second gate metal layer and the second plate of the storage capacitor are arranged in the same layer and the same material;

[0020] The third signal line includes a plurality of data signal lines, and the plurality of data signal lines include a plurality of first data signal lines, a plurality of second data signal lines, and a plurality of third data signal lines; wherein at least one second data signal line and / or at least one third data signal line is arranged between two adjacent first data signal lines, at least one first data signal line and / or at least one third data signal line is arranged between two adjacent second data signal lines, and at least one first data signal line and / or at least one second data signal line is arranged between two adjacent third data signal lines;

[0021] The signal lead-out lines include a plurality of data signal lead-out lines, and the data signal lines are connected to the data signal lead-out lines in a one-to-one correspondence;

[0022] The second shading pattern is multiplexed as data signal lead lines corresponding to all the first data signal lines, the first gate metal layer is multiplexed as data signal lead lines corresponding to all the second data signal lines, and the second gate metal layer is multiplexed as data signal lead lines corresponding to all the third data signal lines.

[0023] Optionally, the display panel includes a display area and a non-display area located around the display area;

[0024] The driving circuit layer further includes: a second signal line located in the non-display area;

[0025] The display panel further includes: a second light shielding pattern provided in the same layer and material as the first light shielding pattern, the second light shielding pattern is located in the non-display area and is insulated from the first light shielding pattern, and the second light shielding pattern is connected in parallel with the second signal line.

[0026] Optionally, the non-display area includes a fan-out area;

[0027] The driving circuit layer further includes: a third signal line located in the display area;

[0028] The second signal line includes a signal lead-out line located in the fan-out area and corresponding to the third signal line one by one, and the signal lead-out line is connected to the corresponding third signal line;

[0029] The second light shielding pattern is connected in parallel with the signal lead line.

[0030] Optionally, the third signal line includes at least one of an initialization signal line, a data signal line and a negative power signal line;

[0031] The second signal line includes at least one of an initialization signal lead line, a data signal lead line, and a negative power signal lead line.

[0032] Optionally, the display panel includes a display area and a non-display area located around the display area;

[0033] The display panel also includes: a third shading pattern set in the same layer and material as the first shading pattern, the third shading pattern is located in the non-display area and is insulated from the first shading pattern, and the orthographic projection of the third shading pattern on the substrate surrounds the orthographic projection of the display area on the substrate.

[0034] Optionally, the orthographic projection of the imaging pinhole on the substrate does not overlap with the orthographic projection of all conductive patterns included in the display panel on the substrate.

[0035] Optionally, the driving circuit layer includes: a power signal line, a light emitting control signal line, a data signal line, an initialization signal line and a reset signal line; the plurality of sub-pixel driving circuits are arranged in an array, and each of the sub-pixel driving circuits includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a sixth transistor; wherein the source of the fourth transistor is connected to the power signal line, the drain of the fourth transistor is connected to the source of the first transistor, the gate of the fourth transistor is connected to the light emitting control signal line, the gate of the second transistor is connected to the gate control signal line, the source of the second transistor is connected to the data signal line, the drain of the second transistor is connected to the source of the first transistor, the gate of the third transistor is connected to the gate control signal line, the source of the third transistor is connected to the drain of the first transistor, the drain of the third transistor is connected to the gate of the first transistor, the gate of the fifth transistor is connected to the light emitting control signal line, the source of the fifth transistor is connected to the drain of the first transistor, the drain of the fifth transistor is connected to the first electrode of the corresponding sub-pixel, the gate of the sixth transistor is connected to the reset signal line, the source of the sixth transistor is connected to the initialization signal line, and the drain of the sixth transistor is connected to the gate of the first transistor;

[0036] The orthographic projection of the imaging pinhole on the substrate is located between two adjacent rows of the sub-pixel driving circuits, and the distance between the orthographic projection of the imaging pinhole on the substrate and the orthographic projection of the channel of the nearest fifth transistor in the sub-pixel driving circuits in the previous row on the substrate is smaller than the distance between the orthographic projection of the imaging pinhole on the substrate and the orthographic projection of the channel of the nearest sixth transistor in the sub-pixel driving circuits in the next row on the substrate; and smaller than the distance between the orthographic projection of the imaging pinhole on the substrate and the orthographic projection of the channel of the nearest third transistor in the sub-pixel driving circuits in the next row on the substrate.

[0037] Optionally, the aperture of the imaging pinhole is between 2 μm and 20 μm.

[0038] Optionally, the imaging pinholes are located in a designated area within the display area of ​​the display panel; or, the imaging pinholes are distributed throughout the display area.

[0039] Optionally, the plurality of imaging holes are distributed in an array.

[0040] Based on the technical solution of the above-mentioned display panel, a second aspect of the present invention provides a display device including the above-mentioned display panel.

[0041] Based on the technical solution of the above display panel, a third party of the present invention provides a method for manufacturing a display panel, the manufacturing method comprising:

[0042] A driving circuit layer and a first light-shielding pattern having a plurality of imaging pinholes are formed on a substrate; the driving circuit layer comprises a plurality of sub-pixel driving circuits and a first signal line, the first signal line is used to provide a first signal having a fixed potential to the sub-pixel driving circuit, and the first light-shielding pattern is electrically connected to the first signal line;

[0043] A plurality of pixel units are made on the side of the driving circuit layer facing away from the substrate, each of the pixel units includes at least two sub-pixels, each of the sub-pixels includes an organic electroluminescent element, and the organic electroluminescent element includes: a first electrode, an organic light-emitting layer, and a second electrode stacked in sequence in a direction away from the substrate; the sub-pixels correspond one-to-one to the sub-pixel driving circuits, and the first electrode in the sub-pixels is coupled to the corresponding sub-pixel driving circuit.

[0044] Optionally, the display panel includes a display area and a non-display area located around the display area; the driving circuit layer further includes: a second signal line located in the non-display area;

[0045] The steps of making the first light-shielding pattern specifically include:

[0046] The first light-shielding pattern and the second light-shielding pattern are formed simultaneously through one patterning process. The second light-shielding pattern is located in the non-display area and is insulated from the first light-shielding pattern. The second light-shielding pattern is multiplexed as at least part of the second signal line.

[0047] Optionally, the display panel includes a display area and a non-display area located around the display area;

[0048] The steps of making the driving circuit layer specifically include:

[0049] Manufacturing a second signal line located in the non-display area;

[0050] The steps of making the first light-shielding pattern specifically include:

[0051] The first light-shielding pattern and the second light-shielding pattern are formed simultaneously through one patterning process. The second light-shielding pattern is located in the non-display area and is insulated from the first light-shielding pattern. The second light-shielding pattern is connected in parallel with the second signal line.

[0052] Optionally, the display panel includes a display area and a non-display area located around the display area;

[0053] The steps of making the first light-shielding pattern specifically include:

[0054] The first shading pattern and the third shading pattern are formed simultaneously through a single patterning process. The third shading pattern is located in the non-display area and is insulated from the first shading pattern. The orthographic projection of the third shading pattern on the substrate surrounds the orthographic projection of the display area on the substrate.

[0055] In the technical solution provided by the present invention, the first light-shielding pattern is electrically connected to the first signal line in the driving circuit layer for transmitting a first signal with a fixed potential, so that when the sub-pixel driving circuit in the driving circuit layer is working, the first signal is loaded on the first light-shielding pattern, that is, the first light-shielding pattern has a fixed potential, thereby avoiding the problem of the first light-shielding pattern being in a floating state and affecting the performance of the transistors included in the driving circuit layer, thereby ensuring the stable operating performance of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0057] Figure 1 A first structural schematic diagram of a sub-pixel driving circuit provided by an embodiment of the present invention;

[0058] Figure 2 is a working timing diagram of a sub-pixel driving circuit;

[0059] Figure 3 is a schematic diagram of the layout of a sub-pixel driving circuit;

[0060] Figures 4 to 7 for Figure 3 Schematic diagram of each membrane layer corresponding to the layout method in;

[0061] Figure 8 A partial cross-sectional schematic diagram of a sub-pixel driving circuit;

[0062] Fig. 9 A second structural schematic diagram of a sub-pixel driving circuit provided by an embodiment of the present invention;

[0063] Fig.10 A schematic top view of a display panel provided by an embodiment of the present invention;

[0064] Fig.11 A schematic diagram of an imaging pinhole provided in an embodiment of the present invention being arranged in a designated area;

[0065] Fig.12 A schematic diagram of an array distribution of imaging holes provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0066] In order to further illustrate the display panel and its manufacturing method, and the display device provided by the embodiments of the present invention, a detailed description is given below in conjunction with the accompanying drawings.

[0067] The present invention provides a display panel, in which a fingerprint recognition module is integrated inside the display panel, and an imaging hole corresponding to the fingerprint recognition module is arranged inside the back plate of the display panel. When fingerprint recognition is performed in the display area, the light emitted by the display panel is used as the light source for fingerprint recognition. The light is irradiated to the finger used for fingerprint recognition and then reflected by the finger. The reflected light can pass through the imaging hole arranged in the back plate of the display panel and be received by the fingerprint recognition module (the fingerprint recognition module usually adopts a charge coupled device image sensor CCD). The fingerprint recognition module synthesizes and analyzes the image formed by each imaging hole to obtain fingerprint pattern information. The display panel provided by the present invention can use the display area for fingerprint recognition, and there is no need to separately arrange a fingerprint recognition area on the display surface, which is conducive to achieving full-screen display.

[0068] The above-mentioned display panel also includes a driving circuit layer for driving the pixel unit display, the driving circuit layer includes a plurality of sub-pixel driving circuits, each sub-pixel driving circuit includes a plurality of transistors, and when the driving circuit layer is made on the substrate, generally, a stacked active film layer, a gate insulating layer, a first gate metal layer, a first interlayer insulating layer, a second gate metal layer, a second interlayer insulating layer and a source-drain metal layer are sequentially made in a direction from close to the substrate to far from the substrate; wherein, the active film layer is used to form the active pattern in each transistor included in the sub-pixel driving circuit, the first gate metal layer is used to form the gate of each transistor included in the sub-pixel driving circuit, and the source-drain metal layer is used to form the source electrode and the drain electrode of each transistor included in the sub-pixel driving circuit. It is worth noting that the specific formation position of the source electrode and the drain electrode of each transistor is not limited, and the formation position of the source electrode and the drain electrode of the same transistor can be interchanged according to actual needs.

[0069] The present invention sets a light shielding layer in the display panel, and forms a plurality of imaging holes for fingerprint identification on the light shielding layer. The light shielding layer is set between the substrate and the driving circuit layer of the display panel. However, the inventors have found that the display panel with the light shielding layer directly set between the substrate and the driving circuit layer will have grayscale jitter and display quality degradation. The inventors have adjusted the light shielding layer structure, materials and hole positions, but have not been able to solve the above problems well. After research, the inventors found that the occurrence of grayscale jitter and display quality degradation are directly related to the switching state of the switching transistor in the pixel circuit and the output current stability of the driving transistor. Specifically, since the active film layer in the driving circuit layer (generally including P-Si (low temperature polycrystalline silicon) material) is close to the light shielding layer, and the light shielding layer is directly set between the substrate and the driving circuit layer and is in a floating state, its potential is prone to fluctuate and thus generates an unstable bias voltage to the channel region formed by the active layer in each transistor, thereby affecting the switching state of the switching transistor, resulting in increased leakage of the switching transistor and fluctuation of the driving transistor current. In the pixel circuit provided by the present invention, if Figure 1 As shown, the switching states of the switching transistors T3 and T6 directly affect the stability of the gate potential of the driving transistor T1. For example, when the potential fluctuation of the light shielding layer causes the leakage of T3 and T6 to increase, the gate potential of the driving transistor will deviate greatly from the predetermined value, and the current of the driving transistor is directly related to its gate potential, thus causing the current of the driving transistor to change, ultimately affecting the accuracy of the grayscale display.

[0070] Based on the existence of the above-mentioned problems, the inventors of the present invention have discovered through research that when making a light-shielding layer in a display panel, the light-shielding layer can be electrically connected to a signal line included in the display panel for transmitting a signal with a fixed potential so that the light-shielding layer has a fixed potential, thereby reducing the impact of the light-shielding layer on the performance of the transistor.

[0071] It should be noted that one or more embodiments described herein correspond to a display panel having a 7T1C (i.e., 7 thin film transistors and 1 capacitor) sub-pixel driving circuit. In another embodiment, the display panel may include a different sub-pixel driving circuit, for example, more than or less than 7 thin film transistors, and one or more capacitors.

[0072] like Figure 1 As shown, each sub-pixel driving circuit included in the display panel may include: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a storage capacitor Cst.

[0073] Taking the sub-pixel driving circuit located in the nth row and the nth column as an example, each transistor included in the sub-pixel driving circuit adopts a P-type transistor, wherein the source S4 of the fourth transistor T4 is connected to the power signal line VDD(n), the drain D4 of the fourth transistor T4 is connected to the source S1 of the first transistor T1, the gate G4 of the fourth transistor T4 is connected to the light emitting control signal line EM(n), the gate G2 of the second transistor T2 is connected to the gate control signal line G(n), the source S2 of the second transistor T2 is connected to the data signal line D(n), the drain D2 of the second transistor T2 is connected to the source S1 of the first transistor T1, the gate G3 of the third transistor T3 is connected to the gate control signal line G(n), the source S3 of the third transistor T3 is connected to the drain D1 of the first transistor T1, the drain D3 of the third transistor T3 is connected to the gate G1 of the first transistor T1, the gate G5 of the fifth transistor T5 is connected to the light emitting control signal line EM(n), and the gate G2 of the fifth transistor T5 is connected to the gate control signal line EM(n). The source S5 is connected to the drain D1 of the first transistor T1, the drain D5 of the fifth transistor T5 is connected to the anode layer of the corresponding sub-pixel, the gate G6 of the sixth transistor T6 is connected to the nth reset signal line RST(n), the source S6 of the sixth transistor T6 (located in the source area 90S6) is connected to the nth initialization signal line VINT(n), the drain D6 of the sixth transistor T6 is connected to the gate G1 of the first transistor T1, the gate G7 of the seventh transistor T7 is connected to the n+1th reset signal line RST(n+1), the source S7 of the seventh transistor T7 is connected to the n+1th initialization signal line VINT(n+1), or the source S7 of the seventh transistor T7 is connected to the negative power supply VSS, the drain D7 of the seventh transistor T7 is connected to the anode layer of the corresponding sub-pixel, the first plate Cstb of the storage capacitor Cst is connected to the gate G1 of the first transistor T1, and the second plate Csta of the storage capacitor Cst is connected to the power signal line VDD(n).

[0074] like Figure 2As shown, when the sub-pixel driving circuit of the above structure is working, each working cycle includes a reset period P1, a write compensation period P2 and a light-emitting period P3. In the reset period P1, the nth reset signal input by the nth reset signal line RST(n) is at a valid level, the sixth transistor T6 is turned on, and the gate G1 of the first transistor T1 is reset.

[0075] During the write compensation period P2, the nth reset signal is at a non-valid level, the sixth transistor T6 is turned off, the n+1th reset signal input by the n+1th reset signal line RST(n+1) is at a valid level, the seventh transistor T7 is turned on, and the anode of the light-emitting element OLED is reset; the gate control signal input by the gate control signal line G(n) is at a valid level, controlling the second transistor T2 and the third transistor T3 to be turned on, the data signal line D(n) writes the data signal, and the first transistor T1, the second transistor T2 and the third transistor T3 work together to achieve threshold voltage compensation for the first transistor T1.

[0076] In the light-emitting period P3, the n+1th reset signal is at a non-valid level, the seventh transistor T7 is turned off, the gate control signal is at a non-valid level, the second transistor T2 and the third transistor T3 are both turned off, the light-emitting control signal written into the light-emitting control signal line EM(n) is at a valid level, the fourth transistor T4 and the fifth transistor T5 are turned on, and the first transistor T1 is turned on at the same time, and the leakage current generated flows to the corresponding anode layer, driving the corresponding organic light-emitting layer to emit light.

[0077] When manufacturing the above sub-pixel driving circuit, the layout of each film layer corresponding to the sub-pixel driving circuit is as follows:

[0078] The active film layers (such as Figure 4 As shown, generally a low temperature polysilicon layer), a gate insulating layer, a first gate metal layer (such as Figure 5 As shown), a first interlayer insulating layer, a second gate metal layer (as shown Figure 6 As shown), a second interlayer insulating layer, a first source-drain metal layer (as shown Figure 7As shown), a third interlayer insulating layer and a second source-drain metal layer; wherein the first gate metal layer is used to form the gate of each transistor in the sub-pixel driving circuit, and the gate control signal line, the light emitting control signal line and the reset signal line included in the driving circuit layer, wherein the gate G1 of the first transistor T1 in each sub-pixel driving circuit is reused as the first electrode Cstb of the storage capacitor Cst in the sub-pixel driving circuit; the second gate metal layer is used to form the second electrode Csta of the storage capacitor Cst, and the initialization signal line VINT(n) included in the driving circuit layer; the first source-drain metal layer is used to form the source and drain of each transistor in the sub-pixel driving circuit, and the connecting portion for conducting the two transistors, and the data signal line D(n) and the power signal line VDD(n) included in the driving circuit layer.

[0079] For more details, please refer to Figure 3 to Figure 7 , the source S4 of the fourth transistor T4 is located in the source region 90S4, the drain D4 of the fourth transistor T4 is located in the drain region 90D4, the gate G4 of the fourth transistor T4 is connected to the light emitting control signal line EM(n), the gate G2 of the second transistor T2 is connected to the gate control signal line G(n), the source S2 of the second transistor T2 is located in the source region 90S2, the drain D2 of the second transistor T2 is located in the drain region 90D2, the gate G3 of the third transistor T3 is connected to the gate control signal line G(n), the source S3 of the third transistor T3 is located in the source region 90S3, the drain D3 of the third transistor T3 is located in the drain region 90D3, the gate G5 of the fifth transistor T5 is connected to the light emitting control signal line EM(n), the source S5 of the fifth transistor T5 is located in the source region 90S5, the fifth transistor T 5 is located in the drain area 90D5, the gate G6 of the sixth transistor T6 is connected to the nth reset signal line RST(n), the source S6 of the sixth transistor T6 is located in the source area 90S6, the drain D6 of the sixth transistor T6 is located in the drain area 90D6, the gate G7 of the seventh transistor T7 is connected to the n+1th reset signal line RST(n+1), the source S7 of the seventh transistor T7 is located in the source area 90S7, the drain D7 of the seventh transistor T7 is located in the drain area 90D7, the source of the first transistor T1 is located in the source area 90S1, the drain of the first transistor T1 is located in the drain area 90D1, the first plate Cstb of the storage capacitor Cst is connected to the gate G1 of the first transistor T1, and the second plate Csta of the storage capacitor Cst is connected to the power signal line VDD(n).

[0080] It is worth noting that among the transistors included in the sub-pixel driving circuit, there are some transistors whose source and drain are not made of source-drain metal layers, that is, the source and drain of these transistors can be directly made of active film layers, and it is only necessary to make the active film layers used as the source and drain have conductive properties after being doped. In this case, when it is necessary to connect the source or drain of two transistors to the source or drain of another transistor, the corresponding active film layers can be directly connected.

[0081] It should be noted that the multiple sub-pixel driving circuits may be distributed in an array, and the nth (n is an integer greater than or equal to 1) row of sub-pixel driving circuits share the same initialization signal line VINT(n), nth reset signal line RST(n), gate control signal line G(n), and light emission control signal line EM(n); the nth column of sub-pixel driving circuits share the same power signal line VDD(n) and data signal line D(n). In addition, Figure 3 RST(n+1) is the n+1th reset signal line RST(n+1) applied by the n+1th row sub-pixel driving circuit, G(n+1) is the gate control signal line applied by the n+1th row sub-pixel driving circuit, and EM(n+1) is the light emission control signal line applied by the n+1th row sub-pixel driving circuit. In addition, Figure 3 The small rectangular boxes with cross lines in them represent vias.

[0082] In addition, the above-mentioned reset signal line, gate control signal line and light-emitting control signal line can all be coupled to the output end of the corresponding shift register, and the corresponding signal is generated by the corresponding shift register and output to the corresponding signal line. For example, the reset shift register RST GOA generates a reset signal and transmits it to the corresponding reset signal line; the gate control shift register Gate GOA generates a gate control signal and transmits it to the corresponding gate control signal line; the light-emitting control shift register EM GOA generates a light-emitting control signal and transmits it to the corresponding light-emitting control signal line.

[0083] At the same time, in order to further improve the screen-to-body ratio, the present invention integrates RST GOA and Gate GOA, omits RSTGOA, and cascades at the output end of Gate GOA, connects the gate control signal line G(n) of this row with the downstream reset signal line RST(n+1), and uses the gate control signal output by the gate control signal line G(n) of this row as the downstream reset signal.

[0084] See also Figure 8 and Fig. 9As shown, an embodiment of the present invention provides a display panel, comprising: a substrate 10, a driving circuit layer arranged on the substrate 10, and a plurality of pixel units arranged on a side of the driving circuit layer facing away from the substrate 10; each of the pixel units comprises at least two sub-pixels, each of the sub-pixels comprises an organic electroluminescent element, the organic electroluminescent element comprises: a first electrode (optionally an anode with a reflective function), an organic light-emitting layer, and a second electrode (optionally a cathode) sequentially stacked in a direction away from the substrate 10; the driving circuit layer comprises: a plurality of sub-pixel driving circuits and a first signal line, the sub-pixel driving circuits correspond to the sub-pixels one-to-one, the sub-pixel driving circuits are coupled to the first electrodes in the corresponding sub-pixels, and the first signal line is used to provide a first signal with a fixed potential to the sub-pixel driving circuit; the display panel also comprises: a first shading pattern LS1 arranged on the substrate 10, the first shading pattern is electrically connected to the first signal line, and the first shading pattern has a plurality of imaging pinholes Via.

[0085] Specifically, the driving circuit layer includes a plurality of sub-pixel driving circuits and signal lines for providing various signals to the plurality of sub-pixel driving circuits. In actual application, the signal lines provide corresponding signals to each sub-pixel driving circuit. Each sub-pixel driving circuit generates a driving signal under the control of the signal provided by each signal line to drive the corresponding organic electroluminescent element to emit light. The driving circuit layer includes a plurality of signal lines, the plurality of signal lines include a first signal line, the first signal line is used to transmit a first signal with a fixed potential, and the plurality of signal lines also include other signal lines for transmitting signals with non-fixed potentials. After the first light shielding pattern LS1 is connected to the first signal line, when the plurality of sub-pixel driving circuits are in working state, when the first signal line transmits a first signal with a fixed potential, the first light shielding pattern LS1 is also loaded with the first signal, so that when the sub-pixel driving circuit is in working state, the first light shielding pattern LS1 has a stable potential and will not be affected by the characteristics of the transistor included in the sub-pixel driving circuit.

[0086] The above-mentioned first shading pattern LS1 is generally made of metal material, and the specific production process is as follows: a whole layer of shading film is formed by metal material, a photoresist is formed on the whole layer of shading film, and the photoresist is exposed using a mask plate including a light-transmitting area and a non-light-transmitting area to form a photoresist retaining area and a photoresist removal area, wherein the photoresist retaining area corresponds to the area where the portion of the first shading pattern LS1 where the imaging pinhole Via is not formed is located, and the photoresist removal area corresponds to other areas except the area where the portion of the first shading pattern LS1 where the imaging pinhole Via is not formed is located, and then the exposed photoresist is developed to remove the photoresist located in the photoresist removal area, and then the shading film layer located in the photoresist removal area is etched to remove the shading film layer located in the photoresist removal area, and finally the photoresist located in the photoresist retaining area is stripped off to form a first shading pattern LS1 with multiple imaging pinholes Via.

[0087] According to the specific structure and practical application of the above-mentioned display panel, it can be known that in the display panel provided by the embodiment of the present invention, the first shading pattern LS1 is electrically connected to the first signal line in the driving circuit layer for transmitting the first signal with a fixed potential, so that when the sub-pixel driving circuit in the driving circuit layer is working, the first shading pattern LS1 is loaded with the first signal, that is, the first shading pattern LS1 has a fixed potential, thereby avoiding the problem of the first shading pattern LS1 being in a floating state and affecting the performance of the transistors included in the driving circuit layer, thereby ensuring the stable operating performance of the display panel.

[0088] like Figure 8 and Fig. 9 As shown, in some embodiments, the driving circuit layer includes a plurality of sub-pixel driving circuits, each of which includes a driving transistor (i.e., the first transistor T1 in the above embodiment), a storage capacitor Cst and a first capacitor C1; wherein the gate of the driving transistor is multiplexed as the first plate Cstb of the storage capacitor Cst, and is multiplexed as the first plate C1b of the first capacitor;

[0089] The second plate Csta of the storage capacitor Cst is located at a side of the gate of the driving transistor away from the substrate 10, and the second plate Csta of the storage capacitor Cst is connected to the first signal line;

[0090] The orthographic projection of the first light-shielding pattern LS1 on the substrate 10 at least partially overlaps with the orthographic projection of the gate of the driving transistor on the substrate 10 , and the first light-shielding pattern LS1 is multiplexed as the second electrode plate C1a of the first capacitor C1 .

[0091] Specifically, the driving circuit layer may include a plurality of sub-pixel driving circuits distributed in an array, the sub-pixel driving circuits corresponding to the sub-pixels one by one, and each sub-pixel driving circuit is used to drive the organic light-emitting layer in the corresponding sub-pixel to emit light. Each sub-pixel driving circuit includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor Cst and a first capacitor C1. Taking the example of each transistor using a P-type transistor, the connection method of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 included in the sub-pixel driving circuit has been described in the above embodiment and will not be repeated here.

[0092] like Fig. 9 As shown, the first plate Cstb of the storage capacitor Cst is connected to the gate G1 of the first transistor T1, the second plate Csta of the storage capacitor Cst is connected to the first signal line, the first plate C1b of the first capacitor C1 is connected to the gate G1 of the first transistor T1, and the second plate C1a of the first capacitor C1 is connected to the first signal line.

[0093] like Figure 3 and Figure 8 As shown, the gate G1 of the first transistor T1 can be reused as the first plate Cstb of the storage capacitor Cst and the first plate C1b of the first capacitor C1; the second plate Csta of the storage capacitor Cst can be formed by using the second gate metal layer, and the second plate Csta of the storage capacitor Cst is located on the side of the gate G1 of the first transistor T1 away from the substrate 10, and it can be ensured that the orthographic projection of the second plate Csta of the storage capacitor Cst formed by the second gate metal layer on the substrate 10 and the orthographic projection of the first plate Cstb of the storage capacitor Cst reused by the gate G1 of the first transistor T1 on the substrate 10 have an overlapping area; since the first shading pattern LS1 is connected to the first signal line, the orthographic projection of the first shading pattern LS1 on the substrate 10 can be set to at least partially overlap with the orthographic projection of the gate G1 of the first transistor T1 on the substrate 10, so that the first shading pattern LS1 can be reused as the second plate C1a of the first capacitor C1.

[0094] In the display panel provided by the above-mentioned embodiment, by setting each sub-pixel driving circuit to include the storage capacitor Cst and the first capacitor C1, the storage capacitor Cst and the first capacitor C1 form a parallel capacitor structure. The parallel capacitor structure enhances the storage capacity of the capacitor in the sub-pixel driving circuit, increases the potential holding capacity of the N1 node formed by the gate of the driving transistor in the sub-pixel driving circuit, thereby improving the stability of the N1 node, better improving the driving performance of the sub-pixel driving circuit, and ensuring the display accuracy of the display panel when used for display.

[0095] In addition, in the display panel provided by the above embodiment, the gate G1 of the first transistor T1 is reused as the first plate Cstb of the storage capacitor Cst and the first plate C1b of the first capacitor C1, thereby avoiding the production of additional conductive patterns used as the first plate Cstb of the storage capacitor Cst and the first plate C1b of the first capacitor C1, so that there is a larger layout space when manufacturing the sub-pixel driving circuit, which is more convenient for manufacturing the sub-pixel driving circuit.

[0096] In addition, in the display panel provided by the above embodiment, the first shading pattern LS1 is reused as the second plate C1a of the first capacitor C1, avoiding the need to add an additional composition process to produce the second plate C1a of the first capacitor C1, thereby greatly simplifying the manufacturing process of the display panel and saving manufacturing costs.

[0097] like Figure 8 As shown, in some embodiments, the first signal line (such as Figure 8 The power signal line VDD(n)) is located on the side of the second plate Csta of the storage capacitor Cst away from the substrate 10, and the orthographic projection of the first signal line on the substrate 10 and the orthographic projection of the first shading pattern LS1 on the substrate 10 have an overlapping area, and the first signal line is connected to the first shading pattern LS1 through at least one via arranged in the overlapping area.

[0098] Specifically, the specific position of the first signal line can be set according to actual needs. For example, the first signal line can be set on the side of the second plate Csta of the storage capacitor Cst away from the substrate 10. Since the sub-pixel driving circuit also includes a conductive pattern on the side of the second plate Csta of the storage capacitor Cst away from the substrate 10, the first signal line and the conductive pattern can be set in the same layer and material. In this way, the first signal line and the conductive pattern can be formed simultaneously through a single composition process, thereby avoiding the need to add an additional composition process to produce the first signal line.

[0099] Moreover, when the first signal line is set on the side of the second plate Csta of the storage capacitor Cst away from the substrate 10, the orthographic projection of the first signal line on the substrate 10 and the orthographic projection of the first shading pattern LS1 on the substrate 10 can be set to have an overlapping area, so that at least one via can be made in the overlapping area to achieve electrical connection between the first signal line and the first shading pattern LS1 through the via.

[0100] In some embodiments, the via holes correspond to the sub-pixels one by one, and the orthographic projection of each via hole on the substrate 10 is located within a preset range around the orthographic projection of the corresponding sub-pixel on the substrate 10 .

[0101] Specifically, when forming vias for connecting the first shading pattern LS1 and the first signal line, the number and specific setting positions of the vias can be set according to actual needs. For example, the vias can be set to correspond one-to-one to the sub-pixels, and the orthographic projection of each of the vias on the substrate 10 is located within a preset range around the orthographic projection of the corresponding sub-pixel on the substrate 10; this setting method enables the first shading pattern LS1 to be connected to the first signal line through a plurality of vias evenly distributed on the entire display panel, thereby ensuring good connection performance between the first shading pattern LS1 and the first signal line, so that the first shading pattern LS1 has a stable fixed potential, thereby better avoiding the first shading pattern LS1 from affecting the performance of the driving transistor in the sub-pixel driving circuit.

[0102] It should be noted that the number of the via holes may also be different from the number of sub-pixels, as long as the number and positions of the via holes are sufficient to ensure that the first light-shielding pattern LS1 has a stable fixed potential.

[0103] Please continue reading Figure 8 In some embodiments, the driving circuit layer further includes a power signal line VDD(n), and the power signal line VDD(n) is multiplexed as the first signal line.

[0104] Specifically, the driving circuit layer includes a plurality of signal lines for transmitting signals with a fixed potential. For example, the signal lines include: a power signal line VDD(n) and an initialization signal line VINT(n), etc. For example, the power signal line can be multiplexed as the first signal line; in more detail, Figure 8 and Fig.10As shown, the orthographic projection of the power signal line VDD(n) on the substrate 10 has a first overlapping area with the orthographic projection of the first light-shielding pattern LS1 on the substrate 10, and a first via X1 can be provided in the first overlapping area, and the first light-shielding pattern LS1 can be electrically connected to the power signal line VDD(n) through the first via X1. The orthographic projection of the power signal line VDD(n) on the substrate 10 also has a second overlapping area with the orthographic projection of the second plate Csta of the storage capacitor Cst on the substrate 10, and a second via X2 can be provided in the second overlapping area, and the second plate Csta of the storage capacitor Cst can be electrically connected to the power signal line VDD(n) through the second via X2.

[0105] It is worth noting that since the power signal line is used to transmit a power signal with a fixed potential, multiplexing the power signal line as the first signal line can make the second plate Csta of the storage capacitor Cst and the first shading pattern LS1 have the same fixed potential as the power signal.

[0106] In the display panel provided in the above embodiment, the power signal line is reused as the first signal line, avoiding the need to add an additional manufacturing process for manufacturing the first signal line, thereby greatly simplifying the manufacturing process of the display panel and saving manufacturing costs.

[0107] like Fig.10 As shown, in some embodiments, the display panel includes a display area AA and a non-display area located around the display area AA; the driving circuit layer further includes: a second signal line located in the non-display area;

[0108] The display panel also includes: a second shading pattern LS2 set in the same layer and material as the first shading pattern LS1, the second shading pattern LS2 is located in the non-display area and is insulated from the first shading pattern LS1, and the second shading pattern LS2 is multiplexed as at least part of the second signal line.

[0109] Specifically, the display area AA of the display panel generally includes a plurality of pixel units and a sub-pixel driving circuit corresponding to the sub-pixels included in the pixel unit. A gate driving circuit and a second signal line for providing corresponding signals to the gate driving circuit and the sub-pixel driving circuit are generally provided in the non-display area of ​​the display panel. When the first light-shielding pattern LS1 is produced, a second light-shielding pattern LS2 can be produced in the non-display area of ​​the display panel at the same time, and the second light-shielding pattern LS2 can be multiplexed as the second signal line.

[0110] It is worth noting that, since the first light-shielding pattern LS1 is mainly used to form an imaging aperture Via for fingerprint recognition, the first light-shielding pattern LS1 is generally located in the display area AA of the display panel.

[0111] In the display panel provided by the above embodiment, a second shading pattern LS2 with the same layer and material as the first shading pattern LS1 is arranged in the non-display area, and the second shading pattern LS2 is multiplexed as the second signal line, so that the second signal line can be formed in the same composition process as the first shading pattern LS1, thereby avoiding adding an additional composition process for producing the second signal line, and greatly simplifying the production process of the display panel.

[0112] It should be noted that the specific layout positions of the first light-shielding pattern LS1 and the second light-shielding pattern LS2 can be set according to actual needs. For example, the first light-shielding pattern LS1 and the second light-shielding pattern LS2 are both located on the surface of the substrate 10; or, the first light-shielding pattern LS1 and the second light-shielding pattern LS2 are located between any two film layers included in the driving circuit layer. In addition, in the above embodiment, the second light-shielding pattern LS2 is multiplexed as at least part of the second signal line, that is, the second light-shielding pattern LS2 is used as at least part of the second signal line.

[0113] In some embodiments, the non-display area includes a fan-out area;

[0114] The driving circuit layer further includes: a third signal line located in the display area AA;

[0115] The second signal line includes a signal lead-out line located in the fan-out area and corresponding to the third signal line one by one, and the signal lead-out line is connected to the corresponding third signal line; the second light-shielding pattern LS2 is multiplexed as at least part of the signal lead-out line.

[0116] Specifically, the non-display area of ​​the display panel generally includes a fan-out area and a binding area, the fan-out area is located between the display area AA and the binding area, the third signal line in the display area AA corresponds to the signal lead-out line of the fan-out area one by one, and the third signal line is connected to the corresponding binding terminal (such as Fig.10 Pad1~Pad3) are electrically connected.

[0117] Since the second shading pattern LS2 is set at the same layer and material as the first shading pattern LS1, the second shading pattern LS2 is reused as at least part of the signal lead line, so that the signal lead line and the first shading pattern LS1 can be formed in the same composition process, avoiding the addition of an additional composition process for making the signal lead line, thereby greatly simplifying the manufacturing process of the display panel.

[0118] In some embodiments, the driving circuit layer further includes a first gate metal layer and a second gate metal layer arranged in different layers, and the first gate metal layer and the second gate metal layer are both located in the fan-out region; wherein the first gate metal layer and the gate of the driving transistor are arranged in the same layer and the same material, and the second gate metal layer and the second electrode plate Csta of the storage capacitor Cst are arranged in the same layer and the same material;

[0119] The third signal line includes a plurality of data signal lines, and the plurality of data signal lines include a plurality of first data signal lines, a plurality of second data signal lines, and a plurality of third data signal lines; wherein at least one second data signal line and / or at least one third data signal line is arranged between two adjacent first data signal lines, at least one first data signal line and / or at least one third data signal line is arranged between two adjacent second data signal lines, and at least one first data signal line and / or at least one second data signal line is arranged between two adjacent third data signal lines;

[0120] The signal lead-out lines include a plurality of data signal lead-out lines, and the data signal lines are connected to the data signal lead-out lines in a one-to-one correspondence;

[0121] The second shading pattern LS2 is multiplexed as data signal lead lines corresponding to all the first data signal lines, the first gate metal layer is multiplexed as data signal lead lines corresponding to all the second data signal lines, and the second gate metal layer is multiplexed as data signal lead lines corresponding to all the third data signal lines.

[0122] Specifically, the display area AA of the display panel includes multiple data signal lines, each data signal line is used to provide a data signal for a corresponding column of sub-pixels, and the fan-out area of ​​the display panel includes multiple data signal lead-out lines, each data signal line is electrically connected to a corresponding binding terminal located in the binding area through the corresponding data signal lead-out line.

[0123] By setting at least one second data signal line and / or at least one third data signal line between two adjacent first data signal lines, setting at least one first data signal line and / or at least one third data signal line between two adjacent second data signal lines, and setting at least one first data signal line and / or at least one second data signal line between two adjacent third data signal lines, a wider distance is provided between adjacent first data signal lines, between adjacent second data signal lines, and between adjacent third data signal lines; at the same time, by setting the second shading pattern LS2 to be multiplexed as the data signal lead-out lines corresponding to all the first data signal lines, the first gate metal layer is multiplexed as The data signal lead-out lines corresponding to all the second data signal lines and the second gate metal layer are reused as the data signal lead-out lines corresponding to all the third data signal lines, so that the data signal lead-out lines corresponding to the first data signal lines, the data signal lead-out lines corresponding to the second data signal lines, and the data signal lead-out lines corresponding to the third data signal lines are respectively corresponding to different film layers, so that the data signal lead-out lines corresponding to the first data signal lines, the data signal lead-out lines corresponding to the second data signal lines, and the data signal lead-out lines corresponding to the third data signal lines have wider wiring spaces in their respective film layers, thereby reducing the difficulty of the manufacturing process of the data signal leads and improving the manufacturing yield of the display panel.

[0124] In addition, by setting the second shading pattern LS2 to be multiplexed as the data signal lead-out lines corresponding to all the first data signal lines, the first gate metal layer to be multiplexed as the data signal lead-out lines corresponding to all the second data signal lines, and the second gate metal layer to be multiplexed as the data signal lead-out lines corresponding to all the third data signal lines, the data signal lead lines corresponding to the first data signal lines can be formed in the same patterning process as the first shading pattern LS1, the data signal lead lines corresponding to the second data signal lines can be formed in the same patterning process as the gate of the driving transistor, and the data signal lead lines corresponding to the third data signal lines can be formed in the same patterning process as the second electrode of the storage capacitor, thereby avoiding the need to add additional patterning processes for producing the data signal leads corresponding to the first data signal lines, the data signal leads corresponding to the second data signal lines, and the data signal leads corresponding to the third data signal lines, thereby greatly simplifying the manufacturing process of the display panel.

[0125] In addition, it is worth noting that the data signal lead lines multiplexed by the second shading pattern LS2 can be connected to the corresponding first data signal lines through vias; the data signal lead lines multiplexed by the first gate metal layer can be connected to the corresponding second data signal lines through vias; and the data signal lead lines multiplexed by the second gate metal layer can be connected to the corresponding third data signal lines through vias.

[0126] At the same time, the signal line and the signal line lead are connected through vias, which avoids the problem of static electricity release caused by charge accumulation due to a single line being too long, and well ensures the operability of the sub-pixel driving circuit.

[0127] In some embodiments, the display panel includes a display area AA and a non-display area located around the display area AA; the driving circuit layer further includes: a second signal line located in the non-display area;

[0128] The display panel further includes: a second shading pattern LS2 provided in the same layer and material as the first shading pattern LS1, the second shading pattern LS2 is located in the non-display area and is insulated from the first shading pattern LS1, and the second shading pattern LS2 is connected in parallel with the second signal line.

[0129] Specifically, the display area AA of the display panel generally includes a plurality of pixel units and a sub-pixel driving circuit corresponding to the sub-pixels included in the pixel unit. A gate driving circuit and a second signal line for providing corresponding signals to the gate driving circuit and the sub-pixel driving circuit are generally provided in the non-display area of ​​the display panel. When the first light-shielding pattern LS1 is produced, a second light-shielding pattern LS2 can be produced in the non-display area of ​​the display panel at the same time, and the second light-shielding pattern LS2 is connected in parallel with the second signal line.

[0130] In the display panel provided by the above embodiment, a second light-shielding pattern LS2 of the same layer and material as the first light-shielding pattern LS1 is provided in the non-display area, and the second light-shielding pattern LS2 is connected in parallel with the second signal line, so that the resistance of the second signal line is effectively reduced, thereby better improving the working performance of the display panel. In addition, since the second light-shielding pattern LS2 is provided in the same layer and material as the first light-shielding pattern LS1, the second light-shielding pattern LS2 can be formed in the same patterning process as the first light-shielding pattern LS1, thereby avoiding the need to add an additional patterning process to produce the second light-shielding pattern LS2, and greatly simplifying the production process of the display panel.

[0131] In some embodiments, the non-display area includes a fan-out area; the driving circuit layer further includes: a third signal line located in the display area AA;

[0132] The second signal line includes a signal lead-out line located in the fan-out area and corresponding to the third signal line one by one, and the signal lead-out line is connected to the corresponding third signal line; the second light-shielding pattern LS2 is connected in parallel with the signal lead-out line.

[0133] Specifically, the non-display area of ​​the display panel generally includes a fan-out area and a binding area, the fan-out area is located between the display area AA and the binding area, the third signal line in the display area AA corresponds to the signal lead-out line of the fan-out area one by one, and the third signal line is connected to the corresponding binding terminal (such as Fig.10 Pad1~Pad3) are electrically connected.

[0134] The second light-shielding pattern LS2 can be set in the same layer or in a different layer as the signal lead-out line. When the second light-shielding pattern LS2 and the signal lead-out line are set in a different layer, the orthographic projection of the second light-shielding pattern LS2 on the substrate 10 and the orthographic projection of the signal lead-out line on the substrate 10 can be set to have an overlapping area. In this way, the second light-shielding pattern LS2 can be connected in parallel with the signal lead-out line by setting a via in the overlapping area.

[0135] The above-mentioned connecting the second light-shielding pattern LS2 and the signal lead-out line in parallel effectively reduces the resistance of the signal lead-out line and improves the signal transmission performance of the signal lead-out line, which is more conducive to improving the working performance of the display panel.

[0136] In some embodiments, Figure 3 As shown, the third signal line includes at least one of an initialization signal line VINT(n), a data signal line D(n) and a negative power signal line VSS (not shown in the figure); the second signal line includes at least one of an initialization signal lead line, a data signal lead line and a negative power signal lead line.

[0137] Specifically, when the second signal line includes an initialization signal lead line, a data signal lead line, and a negative power signal lead line, the initialization signal lead line, the data signal lead line, and the negative power signal lead line are generally arranged in a different layer from the second light shielding pattern LS2. Therefore, the second light shielding pattern LS2 can be arranged to be connected in parallel with the initialization signal lead line, the data signal lead line, or the negative power signal lead line through a via hole to form a double-layer lead line structure, thereby reducing the resistance of the initialization signal lead line, the data signal lead line, or the negative power signal lead line. Since the double-layer lead line structure can reduce the resistance of the lead line, the width of the lead line can be appropriately reduced to be more conducive to the display panel to realize a narrow frame structure.

[0138] Exemplarily, the second signal line includes a data signal lead line, and the data signal lead line includes a first data signal lead line made of a first gate metal layer, and a second data signal lead line made of a second gate metal layer. The second shading pattern LS2 can be connected in parallel with the first data signal lead line and the second data signal lead line through a via.

[0139] like Fig.10 As shown, in some embodiments, the display panel includes a display area AA and a non-display area located around the display area AA; the display panel also includes: a third shading pattern LS3 that is arranged on the same layer and material as the first shading pattern LS1, the third shading pattern LS3 is located in the non-display area and is insulated from the first shading pattern LS1, and the orthographic projection of the third shading pattern LS3 on the substrate 10 surrounds the orthographic projection of the display area AA on the substrate 10.

[0140] Specifically, the above-mentioned setting of the orthographic projection of the third shading pattern LS3 on the substrate 10 surrounds the orthographic projection of the display area AA on the substrate 10, so that the third shading pattern LS3 can be formed as a crack blocking structure surrounding the display area AA, so that when a crack occurs at the edge of the display panel, the crack can be blocked by the third shading pattern LS3 when it extends to the area where the third shading pattern LS3 is located, thereby preventing the crack from further extending to the display area AA of the display panel, effectively improving the reliability of the display panel.

[0141] It is worth noting that the third shading pattern LS3 can also be specifically set as a plurality of nested annular metal sub-patterns, and the annular metal sub-pattern located in the innermost ring surrounds the display area AA, so that the crack blocking structure formed by the third shading pattern LS3 can achieve multi-layer protection for the display area AA, which is more conducive to improving the reliability of the display panel.

[0142] In addition, the third shading pattern LS3 is set on the same layer and with the same material as the first shading pattern LS1, so that the third shading pattern LS3 can be formed in one composition process with the first shading pattern LS1, thereby avoiding adding an additional composition process to produce the third shading pattern LS3, effectively simplifying the production process of the display panel and saving production costs.

[0143] In some embodiments, the orthographic projection of the imaging pinhole Via on the substrate 10 may be arranged to partially overlap with the orthographic projections of all conductive patterns included in the display panel on the substrate 10 .

[0144] Furthermore, the orthographic projection of the imaging pinhole Via on the substrate 10 may be set to not overlap with the orthographic projections of all the conductive patterns included in the display panel on the substrate 10 .

[0145] Specifically, most of the conductive patterns included in the display panel are made of metal materials, which have poor light transmittance. Therefore, when setting the position of the imaging pinhole Via, the orthographic projection of the imaging pinhole Via on the substrate 10 can be set so that it does not overlap with the orthographic projections of all the conductive patterns included in the display panel on the substrate 10, so that all the conductive patterns included in the display panel will not block the imaging pinhole Via, thereby ensuring the luminous flux of the imaging pinhole Via to the light reflected by the fingerprint, so that the display panel has a higher fingerprint recognition accuracy.

[0146] Furthermore, it can be set that the minimum distance between the orthographic projection of each of the conductive patterns on the substrate 10 and the orthographic projection of the imaging pinhole Via on the substrate 10 is greater than a preset reference value.

[0147] Specifically, the minimum distance between the orthographic projection of each of the conductive patterns on the substrate 10 and the orthographic projection of the imaging pinhole Via on the substrate 10 is greater than a preset reference value. Exemplarily, the preset reference value is 0.5 μm, which better ensures the luminous flux of the imaging pinhole Via to the light reflected by the fingerprint, which is beneficial to further improve the fingerprint recognition accuracy of the display panel.

[0148] It is worth noting that the above-mentioned preset reference value can be set according to actual needs, and it is only necessary to ensure that the luminous flux of the light reflected by the fingerprint through the imaging hole Via can meet the fingerprint recognition needs.

[0149] In some embodiments, the driving circuit layer includes: a power signal line, a light-emitting control signal line, a data signal line, an initialization signal line and a reset signal line; the multiple sub-pixel driving circuits are arranged in an array, and each of the sub-pixel driving circuits includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a sixth transistor; wherein the source of the fourth transistor is connected to the power signal line, the drain of the fourth transistor is connected to the source of the first transistor, the gate of the fourth transistor is connected to the light-emitting control signal line, the gate of the second transistor is connected to the gate control signal line, the source of the second transistor is connected to the data signal line, the drain of the second transistor is connected to the source of the first transistor, the gate of the third transistor is connected to the gate control signal line, the source of the third transistor is connected to the drain of the first transistor, the drain of the third transistor is connected to the gate of the first transistor, the gate of the fifth transistor is connected to the light-emitting control signal line, the source of the fifth transistor is connected to the drain of the first transistor, the drain of the fifth transistor is connected to the first electrode of the corresponding sub-pixel, the gate of the sixth transistor is connected to the reset signal line, the source of the sixth transistor is connected to the initialization signal line, and the drain of the sixth transistor is connected to the gate of the first transistor.

[0150] The orthographic projection of the imaging pinhole on the substrate is located between two adjacent rows of the sub-pixel driving circuits, and the distance between the orthographic projection of the imaging pinhole on the substrate and the orthographic projection of the channel of the nearest fifth transistor in the sub-pixel driving circuits in the previous row on the substrate is smaller than the distance between the orthographic projection of the imaging pinhole on the substrate and the orthographic projection of the channel of the nearest sixth transistor in the sub-pixel driving circuits in the next row on the substrate; and smaller than the distance between the orthographic projection of the imaging pinhole on the substrate and the orthographic projection of the channel of the nearest third transistor in the sub-pixel driving circuits in the next row on the substrate.

[0151] Specifically, Figure 3 and Fig. 9 As shown, the distance between the imaging aperture Via and the channel region of the nearest sixth transistor T6 in the next row of sub-pixel driving circuits, and the distance between the imaging aperture Via and the channel region of the nearest third transistor T3 in the next row of sub-pixel driving circuits can be set to be relatively far, as shown in FIG. Figure 3 As shown in the figure, the distance d1 between the imaging pinhole Via and the channel region of the sixth transistor T6 is greater than the distance d2 between the imaging pinhole Via and the channel region of the fifth transistor T5. This arrangement can reduce the influence of the light passing through the imaging pinhole Via on the working performance of the sixth transistor T6 and the third transistor T3, further avoiding the influence on the node N1, thereby effectively improving the working stability of the sub-pixel driving circuit.

[0152] In some embodiments, the aperture of the imaging pinhole Via is between 2 μm and 20 μm.

[0153] Specifically, the aperture of the imaging pinhole Via is set within the above range, so that the imaging pinhole Via occupies a smaller space while meeting the fingerprint recognition requirements, thereby being more conducive to the arrangement of the conductive patterns in the display panel.

[0154] like Fig.11 As shown, in some embodiments, the imaging pinholes Via are located in a designated area 30 within the display area of ​​the display panel 1; or, the imaging pinholes Via are distributed throughout the display area.

[0155] Specifically, according to actual application needs, the fingerprint recognition area in the display panel can be set in a designated area in the display area AA, or the entire display area AA can be set as the fingerprint recognition area. When the fingerprint recognition area is set in the designated area of ​​the display area AA, the imaging holes Via can be set in the designated area. When the entire display area AA is set as the fingerprint recognition area, the imaging holes Via can be evenly distributed in the entire display area AA.

[0156] It is worth noting that when setting the imaging pinhole Via, it is not necessary to set an imaging pinhole Via corresponding to each pixel unit, and an imaging pinhole Via can be set every few pixel units.

[0157] like Fig.12 As shown, in some embodiments, the plurality of imaging pinholes Via are distributed in an array.

[0158] Specifically, the plurality of imaging pinholes Via included in the display panel may be distributed according to actual needs. For example, the plurality of imaging pinholes Via may be arranged to be distributed in an array, and the lateral spacing and the longitudinal spacing of the plurality of imaging pinholes Via may be the same or different.

[0159] Distributing the plurality of imaging pinholes Via included in the display panel in an array is more conducive to all-round collection of fingerprints, thereby further improving the fingerprint recognition accuracy of the display panel.

[0160] Need to explain, such as Figure 8 As shown, in the display panel provided in the above embodiment, the substrate 10 used can be a polyimide (PI) substrate, which can be a single-layer PI substrate or a double-layer PI substrate (such as Figure 8A first buffer layer 102 is added between the first PI substrate 101 and the second PI substrate 103 in the embodiment; in addition, a second buffer layer 20 can be introduced between the substrate 10 and the first shading pattern LS1. After the driving circuit layer is made, a flat layer can be formed on the side of the driving circuit layer facing away from the substrate 10, and then a stacked anode layer 50, a pixel defining layer, a light-emitting layer and a cathode layer are formed in sequence on the side of the flat layer facing away from the substrate 10, wherein the light-emitting layer is formed in the opening area defined by the pixel defining layer. The display panel provided in the above embodiment also includes a first interlayer insulating layer 301, a second interlayer insulating layer 302, a third interlayer insulating layer 303, a fourth interlayer insulating layer 304, a gate insulating layer 305 and a fingerprint recognition module 40.

[0161] It is also worth noting that a second source-drain metal layer can be formed on the side of the first source-drain metal layer facing away from the substrate 10 in the display panel, and the second source-drain metal layer can be used to form a metal pattern corresponding to the anode layer 50, and in the direction perpendicular to the substrate 10, the metal pattern is located between the corresponding sub-pixel driving circuit and the corresponding anode layer 50, and the anode layer 50 can be electrically connected to the corresponding sub-pixel driving circuit through the corresponding metal pattern. When the anode layer 50 is electrically connected to the corresponding sub-pixel driving circuit through the corresponding metal pattern, the metal pattern can be electrically connected to the drain D5 of the fifth transistor T5 in the corresponding sub-pixel driving circuit, which can not only reduce the resistance of the drain D5 of the fifth transistor T5, but also realize the electrical connection between the drain D5 of the fifth transistor T5 and the corresponding anode layer 50.

[0162] An embodiment of the present invention further provides a display device, comprising the display panel provided by the above embodiment.

[0163] In the display panel provided by the above embodiment, the first shading pattern LS1 is electrically connected to the first signal line in the driving circuit layer for transmitting the first signal with a fixed potential, so that when the sub-pixel driving circuit in the driving circuit layer is working, the first signal is loaded on the first shading pattern LS1, that is, the first shading pattern LS1 has a fixed potential, thereby avoiding the problem that the first shading pattern LS1 is in a floating state and affects the performance of the transistor included in the driving circuit layer, thereby ensuring the stable working performance of the display panel; therefore, the display device provided by the embodiment of the present invention also has the above-mentioned beneficial effects when including the above-mentioned display panel, which will not be repeated here.

[0164] It should be noted that the display device may be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, and a tablet computer.

[0165] An embodiment of the present invention further provides a method for manufacturing a display panel, which is used to manufacture the display panel provided in the above embodiment. The manufacturing method includes:

[0166] A driving circuit layer and a first light shielding pattern LS1 having a plurality of imaging pinholes Via are formed on a substrate 10; the driving circuit layer includes a plurality of sub-pixel driving circuits and a first signal line, the first signal line is used to provide a first signal with a fixed potential to the sub-pixel driving circuit, and the first light shielding pattern LS1 is electrically connected to the first signal line;

[0167] A plurality of pixel units are made on the side of the driving circuit layer facing away from the substrate, each of the pixel units includes at least two sub-pixels, each of the sub-pixels includes an organic electroluminescent element, and the organic electroluminescent element includes: a first electrode, an organic light-emitting layer, and a second electrode stacked in sequence in a direction away from the substrate; the sub-pixels correspond one-to-one to the sub-pixel driving circuits, and the first electrode in the sub-pixels is coupled to the corresponding sub-pixel driving circuit.

[0168] Specifically, the driving circuit layer includes a plurality of sub-pixel driving circuits and signal lines for providing various signals to the plurality of sub-pixel driving circuits. In actual application, the signal lines provide corresponding signals to each sub-pixel driving circuit. Each sub-pixel driving circuit generates a driving signal under the control of the signal provided by each signal line to drive the corresponding light-emitting unit to emit light. The driving circuit layer includes a plurality of signal lines, the plurality of signal lines include a first signal line, the first signal line is used to transmit a first signal with a fixed potential, and the plurality of signal lines also include other signal lines for transmitting signals with non-fixed potentials. After the first light shielding pattern LS1 is connected to the first signal line, when the plurality of sub-pixel driving circuits are in a working state, when the first signal line transmits a first signal with a fixed potential, the first light shielding pattern LS1 is also loaded with the first signal, so that when the sub-pixel driving circuit is in a working state, the first light shielding pattern LS1 has a stable potential, and will not affect the characteristics of the transistor included in the sub-pixel driving circuit.

[0169] The above-mentioned first shading pattern LS1 is generally made of metal material, and the specific production process is as follows: a whole layer of shading film is formed by metal material, a photoresist is formed on the whole layer of shading film, and the photoresist is exposed using a mask plate including a light-transmitting area and a non-light-transmitting area to form a photoresist retaining area and a photoresist removal area, wherein the photoresist retaining area corresponds to the area where the portion of the first shading pattern LS1 where the imaging pinhole Via is not formed is located, and the photoresist removal area corresponds to other areas except the area where the portion of the first shading pattern LS1 where the imaging pinhole Via is not formed is located, and then the exposed photoresist is developed to remove the photoresist located in the photoresist removal area, and then the shading film layer located in the photoresist removal area is etched to remove the shading film layer located in the photoresist removal area, and finally the photoresist located in the photoresist retaining area is stripped off to form a first shading pattern LS1 with multiple imaging pinholes Via.

[0170] In the display panel manufactured by the manufacturing method provided by the embodiment of the present invention, the first shading pattern LS1 is electrically connected to the first signal line in the driving circuit layer for transmitting a first signal with a fixed potential, so that when the sub-pixel driving circuit in the driving circuit layer is working, the first signal is loaded on the first shading pattern LS1, that is, the first shading pattern LS1 has a fixed potential, thereby avoiding the problem of the first shading pattern LS1 being in a floating state and affecting the performance of the transistors included in the driving circuit layer, thereby ensuring the stable operating performance of the display panel.

[0171] In some embodiments, the display panel includes a display area AA and a non-display area located around the display area AA; the driving circuit layer further includes: a second signal line located in the non-display area;

[0172] The steps of making the first light-shielding pattern LS1 specifically include:

[0173] The first light-shielding pattern LS1 and the second light-shielding pattern LS2 are formed simultaneously through one patterning process. The second light-shielding pattern LS2 is located in the non-display area and is insulated from the first light-shielding pattern LS1. The second light-shielding pattern LS2 is multiplexed as at least part of the second signal line.

[0174] Specifically, the display area AA of the display panel generally includes a plurality of pixel units and a sub-pixel driving circuit corresponding to the sub-pixels included in the pixel unit. A gate driving circuit and a second signal line for providing corresponding signals to the gate driving circuit and the sub-pixel driving circuit are generally provided in the non-display area of ​​the display panel. When the first light-shielding pattern LS1 is produced, a second light-shielding pattern LS2 can be produced in the non-display area of ​​the display panel at the same time, and the second light-shielding pattern LS2 can be multiplexed as the second signal line.

[0175] It is worth noting that, since the first light-shielding pattern LS1 is mainly used to form an imaging aperture Via for fingerprint recognition, the first light-shielding pattern LS1 is generally located in the display area AA of the display panel.

[0176] In the display panel manufactured by the manufacturing method provided by the above embodiment, the first shading pattern LS1 and the second shading pattern LS2 are formed simultaneously through one composition process, and the second shading pattern LS2 is multiplexed as at least a part of the second signal line, thereby avoiding adding an additional composition process for manufacturing the second signal line, and greatly simplifying the manufacturing process of the display panel.

[0177] In some embodiments, the display panel includes a display area AA and a non-display area located around the display area AA;

[0178] The steps of making the driving circuit layer specifically include:

[0179] Manufacturing a second signal line located in the non-display area;

[0180] The steps of making the first light-shielding pattern LS1 specifically include:

[0181] The first light-shielding pattern LS1 and the second light-shielding pattern LS2 are formed simultaneously through one patterning process. The second light-shielding pattern LS2 is located in the non-display area and is insulated from the first light-shielding pattern LS1. The second light-shielding pattern LS2 is connected in parallel with the second signal line.

[0182] Specifically, the display area AA of the display panel generally includes a plurality of pixel units and a sub-pixel driving circuit corresponding to the sub-pixels included in the pixel unit. A gate driving circuit and a second signal line for providing corresponding signals to the gate driving circuit and the sub-pixel driving circuit are generally provided in the non-display area of ​​the display panel. When the first light-shielding pattern LS1 is produced, a second light-shielding pattern LS2 can be produced in the non-display area of ​​the display panel at the same time, and the second light-shielding pattern LS2 is connected in parallel with the second signal line.

[0183] In the display panel manufactured by the manufacturing method provided by the above embodiment, the first shading pattern LS1 and the second shading pattern LS2 are formed at the same time through one composition process, and the second shading pattern LS2 is connected in parallel with the second signal line. This not only avoids adding an additional composition process to manufacture the second shading pattern LS2, greatly simplifies the manufacturing process of the display panel, but also effectively reduces the resistance of the second signal line, thereby better improving the working performance of the display panel.

[0184] In some embodiments, the display panel includes a display area AA and a non-display area located around the display area AA;

[0185] The steps of making the first light-shielding pattern LS1 specifically include:

[0186] The first shading pattern LS1 and the third shading pattern LS3 are formed simultaneously through a single patterning process. The third shading pattern LS3 is located in the non-display area and is insulated from the first shading pattern LS1. The orthographic projection of the third shading pattern LS3 on the substrate 10 surrounds the orthographic projection of the display area AA on the substrate 10.

[0187] The above-mentioned first shading pattern LS1 and the third shading pattern LS3 are formed simultaneously through a single patterning process, and the orthographic projection of the third shading pattern LS3 on the substrate 10 is set to surround the orthographic projection of the display area AA on the substrate 10, so that the third shading pattern LS3 can be formed into a crack blocking structure surrounding the display area AA, so that when a crack is generated at the edge of the display panel, the crack can be blocked by the third shading pattern LS3 when it extends to the area where the third shading pattern LS3 is located, thereby preventing the crack from further extending to the display area AA of the display panel, effectively improving the reliability of the display panel. Moreover, the third shading pattern LS3 can be formed in a single patterning process with the first shading pattern LS1, avoiding the need to add an additional patterning process to produce the third shading pattern LS3, effectively simplifying the production process of the display panel and saving production costs.

[0188] It should be noted that each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiment, since it is basically similar to the product embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the product embodiment.

[0189] Unless otherwise defined, the technical terms or scientific terms used in the present invention should be understood by people with ordinary skills in the field to which the present invention belongs. "First", "second" and similar words used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "couple" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0190] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0191] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0192] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A display panel, characterized in that: include: A substrate, a driving circuit layer disposed on the substrate, and a plurality of pixel units disposed on a side of the driving circuit layer facing away from the substrate; Each of the pixel units includes at least two sub-pixels, each of the sub-pixels includes an organic electroluminescent element, and the organic electroluminescent element includes: a first electrode, an organic light-emitting layer, and a second electrode stacked in sequence in a direction away from the substrate; The driving circuit layer comprises: a plurality of sub-pixel driving circuits and a first signal line, wherein the sub-pixel driving circuits correspond to the sub-pixels one by one, the sub-pixel driving circuits are coupled to the first electrodes in the corresponding sub-pixels, and the first signal line is used to provide a first signal with a fixed potential to the sub-pixel driving circuit; The display panel further comprises: a first light shielding pattern disposed on the substrate, the first light shielding pattern being electrically connected to the first signal line, and the first light shielding pattern having a plurality of imaging pinholes; The display panel includes a display area and a non-display area located around the display area; The driving circuit layer further includes: a second signal line located in the non-display area; The display panel further includes: a second light shielding pattern provided in the same layer and material as the first light shielding pattern, the second light shielding pattern being located in the non-display area and insulated from the first light shielding pattern, the second light shielding pattern being multiplexed as at least part of the second signal line, or the second light shielding pattern being connected in parallel with the second signal line; The display panel also includes: a third shading pattern set in the same layer and material as the first shading pattern, the third shading pattern is located in the non-display area and is insulated from the first shading pattern, and the orthographic projection of the third shading pattern on the substrate surrounds the orthographic projection of the display area on the substrate.

2. The display panel according to claim 1, characterized in that: Each of the sub-pixel driving circuits comprises a driving transistor, a storage capacitor and a first capacitor; wherein the gate of the driving transistor is multiplexed as the first plate of the storage capacitor and is multiplexed as the first plate of the first capacitor; The second plate of the storage capacitor is located at a side of the gate of the driving transistor away from the substrate, and the second plate of the storage capacitor is connected to the first signal line; The orthographic projection of the first light-shielding pattern on the substrate at least partially overlaps with the orthographic projection of the gate of the driving transistor on the substrate, and the first light-shielding pattern is multiplexed as the second plate of the first capacitor.

3. The display panel according to claim 2, characterized in that: The first signal line is located on a side of the second plate of the storage capacitor away from the substrate, an orthographic projection of the first signal line on the substrate and an orthographic projection of the first shading pattern on the substrate have an overlapping area, and the first signal line is connected to the first shading pattern through at least one via hole arranged in the overlapping area.

4. The display panel according to claim 3, characterized in that: The via holes correspond to the sub-pixels one by one, and the orthographic projection of each via hole on the substrate is located within a preset range around the orthographic projection of the corresponding sub-pixel on the substrate.

5. The display panel according to claim 3, characterized in that: The driving circuit layer further includes a power signal line, and the power signal line is multiplexed as the first signal line.

6. The display panel according to claim 1, characterized in that: The non-display area includes a fan-out area; The driving circuit layer further includes: a third signal line located in the display area; The second signal line includes a signal lead-out line located in the fan-out area and corresponding to the third signal line one by one, and the signal lead-out line is connected to the corresponding third signal line; The second light shielding pattern is multiplexed as at least a portion of the signal lead-out line.

7. The display panel according to claim 6, characterized in that: The driving circuit layer further comprises a first gate metal layer and a second gate metal layer arranged in different layers, wherein the first gate metal layer and the second gate metal layer are both located in the fan-out region; wherein the first gate metal layer and the gate electrode of the driving transistor are arranged in the same layer and the same material, and the second gate metal layer and the second electrode plate of the storage capacitor are arranged in the same layer and the same material; The third signal line includes a plurality of data signal lines, and the plurality of data signal lines include a plurality of first data signal lines, a plurality of second data signal lines, and a plurality of third data signal lines; wherein at least one second data signal line and / or at least one third data signal line is arranged between two adjacent first data signal lines, at least one first data signal line and / or at least one third data signal line is arranged between two adjacent second data signal lines, and at least one first data signal line and / or at least one second data signal line is arranged between two adjacent third data signal lines; The signal lead-out lines include a plurality of data signal lead-out lines, and the data signal lines are connected to the data signal lead-out lines in a one-to-one correspondence; The second shading pattern is multiplexed as data signal lead lines corresponding to all the first data signal lines, the first gate metal layer is multiplexed as data signal lead lines corresponding to all the second data signal lines, and the second gate metal layer is multiplexed as data signal lead lines corresponding to all the third data signal lines.

8. The display panel according to claim 1, characterized in that: The non-display area includes a fan-out area; The driving circuit layer further includes: a third signal line located in the display area; The second signal line includes a signal lead-out line located in the fan-out area and corresponding to the third signal line one by one, and the signal lead-out line is connected to the corresponding third signal line; The second light shielding pattern is connected in parallel with the signal lead line.

9. The display panel according to claim 8, characterized in that: The third signal line includes at least one of an initialization signal line, a data signal line, and a negative power signal line; The second signal line includes at least one of an initialization signal lead line, a data signal lead line, and a negative power signal lead line.

10. The display panel according to any one of claims 1 to 5, characterized in that: The orthographic projection of the imaging pinhole on the substrate does not overlap with the orthographic projection of all conductive patterns included in the display panel on the substrate.

11. The display panel according to any one of claims 1 to 4, characterized in that: The driving circuit layer includes: a power signal line, a light emitting control signal line, a data signal line, an initialization signal line and a reset signal line; the plurality of sub-pixel driving circuits are arranged in an array, and each of the sub-pixel driving circuits includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a sixth transistor; wherein the source of the fourth transistor is connected to the power signal line, the drain of the fourth transistor is connected to the source of the first transistor, the gate of the fourth transistor is connected to the light emitting control signal line, the gate of the second transistor is connected to the gate control signal line, the source of the second transistor is connected to the data signal line, the drain of the second transistor is connected to the source of the first transistor, the gate of the third transistor is connected to the gate control signal line, the source of the third transistor is connected to the drain of the first transistor, the drain of the third transistor is connected to the gate of the first transistor, the gate of the fifth transistor is connected to the light emitting control signal line, the source of the fifth transistor is connected to the drain of the first transistor, the drain of the fifth transistor is connected to the first electrode of the corresponding sub-pixel, the gate of the sixth transistor is connected to the reset signal line, the source of the sixth transistor is connected to the initialization signal line, and the drain of the sixth transistor is connected to the gate of the first transistor; The orthographic projection of the imaging pinhole on the substrate is located between two adjacent rows of the sub-pixel driving circuits, and the distance between the orthographic projection of the imaging pinhole on the substrate and the orthographic projection of the channel of the nearest fifth transistor in the sub-pixel driving circuits in the previous row on the substrate is smaller than the distance between the orthographic projection of the imaging pinhole on the substrate and the orthographic projection of the channel of the nearest sixth transistor in the sub-pixel driving circuits in the next row on the substrate; and smaller than the distance between the orthographic projection of the imaging pinhole on the substrate and the orthographic projection of the channel of the nearest third transistor in the sub-pixel driving circuits in the next row on the substrate.

12. The display panel according to any one of claims 1 to 5, characterized in that: The aperture of the imaging pinhole is between 2 μm and 20 μm.

13. The display panel according to any one of claims 1 to 5, characterized in that: The imaging pinholes are located in a designated area within the display area of ​​the display panel; or, the imaging pinholes are distributed throughout the display area.

14. The display panel according to any one of claims 1 to 5, characterized in that: The plurality of imaging pinholes are distributed in an array.

15. A display device, characterized in that: The invention comprises the display panel according to any one of claims 1 to 14.

16. A method for manufacturing a display panel, characterized in that: The production method comprises: A driving circuit layer and a first light-shielding pattern having a plurality of imaging pinholes are formed on a substrate; the driving circuit layer comprises a plurality of sub-pixel driving circuits and a first signal line, the first signal line is used to provide a first signal having a fixed potential to the sub-pixel driving circuit, and the first light-shielding pattern is electrically connected to the first signal line; A plurality of pixel units are fabricated on a side of the driving circuit layer facing away from the substrate, each of the pixel units comprises at least two sub-pixels, each of the sub-pixels comprises an organic electroluminescent element, and the organic electroluminescent element comprises: a first electrode, an organic light-emitting layer, and a second electrode which are sequentially stacked in a direction away from the substrate; the sub-pixels correspond to the sub-pixel driving circuits one by one, and the first electrode in the sub-pixels is coupled to the corresponding sub-pixel driving circuit; The display panel includes a display area and a non-display area located around the display area; The step of manufacturing the driving circuit layer specifically includes: manufacturing a second signal line located in the non-display area; The step of making the first light shielding pattern specifically includes: forming the first light shielding pattern and the second light shielding pattern simultaneously through a single patterning process, wherein the second light shielding pattern is located in the non-display area and is insulated from the first light shielding pattern, and the second light shielding pattern is multiplexed as at least part of the second signal line, or the second light shielding pattern is connected in parallel with the second signal line; The steps of making the first light-shielding pattern specifically include: The first shading pattern and the third shading pattern are formed simultaneously through a single patterning process. The third shading pattern is located in the non-display area and is insulated from the first shading pattern. The orthographic projection of the third shading pattern on the substrate surrounds the orthographic projection of the display area on the substrate.

Images