Display device

Abstract

A display device is disclosed. The display device includes: a pixel portion including a plurality of pixels; a scan driver portion composed of a plurality of driver stages and supplying a scan signal to the pixel portion; and a light-emission control driver portion composed of a plurality of driver stages and supplying a light-emission control signal to the pixel portion. A first transistor among a plurality of transistors included in at least one of the driver stages of the scan driver portion and the light-emission control driver portion may include: an active layer pattern including a channel region configured on one side of a base layer to form a channel, and a first region and a second region configured on both sides of the channel region; and a gate electrode spaced apart from the active layer pattern with a first insulating film interposed therebetween and overlapping with the channel region, wherein a channel width of the channel region is narrower than a channel width of at least one of the remaining transistors among the plurality of transistors.

Description

Technical Field

[0001] The present invention relates to a display device, and more particularly, to a display device including a drive stage including a scanning drive unit or a light emission control drive unit. Background Art

[0002] With the advancement of information technology, the importance of display devices as a medium connecting users and information is gradually becoming apparent. In response, the use of display devices such as liquid crystal display devices (LCDs), organic light emitting display devices (OLEDs), and plasma display devices (PDPs) is increasing.

[0003] Each pixel of the display device can emit light at a brightness corresponding to a data voltage supplied through the data line, and the display device can display an image frame by combining the light emission of each pixel.

[0004] Each data line can be connected to multiple pixels. Therefore, a scan driver is required to provide scan signals for selecting the pixels to which the data voltage should be supplied. The scan driver consists of a driver stage comprising multiple transistors, which sequentially provide scan signals with an on-level for each scan line. Furthermore, a light control driver provides light control signals to the pixel unit via the light control line. Summary of the Invention

[0005] An object of the present invention is to provide a display device including a transistor having a characteristic strong against HCI (Hot Carrier Instability) phenomenon.

[0006] Another object of the present invention is to provide a display device including a transistor that prevents a drop in driving current.

[0007] However, the purpose of the present invention is not limited to the above-mentioned purpose, and various extensions can be made without departing from the scope of the idea and field of the present invention.

[0008] One aspect of the present invention to achieve the above-mentioned objective provides a display device.

[0009] The display device may include: a pixel portion including a plurality of pixels; a scan drive portion consisting of a plurality of drive stages and supplying a scan signal to the pixel portion; and a light emission control drive portion consisting of a plurality of drive stages and supplying a light emission control signal to the pixel portion.

[0010] A first transistor among the multiple transistors included in each of the driving stages of the scanning driving unit and at least one of the driving stages of the light-emitting control driving unit includes: an active layer pattern, including a channel region arranged on a base layer to form a channel and a first region and a second region arranged on both sides of the channel region; and a gate electrode, which is separated from the active layer pattern with a first insulating film sandwiched therebetween and overlaps with the channel region, and a channel width of the channel region is narrower than a channel width of at least one of the remaining transistors among the multiple transistors.

[0011] The first transistor may include a first sub-transistor and a second sub-transistor connected in parallel to each other.

[0012] A channel width of the first sub-transistor may be narrower than a channel width of the second sub-transistor, and a channel length of the first sub-transistor may be shorter than a channel length of the second sub-transistor.

[0013] The first sub-transistor and the second sub-transistor share the gate electrode, and the gate electrode may include: a first gate region having a first width corresponding to the channel length of the first sub-transistor; and a second gate region having a second width corresponding to the channel length of the second sub-transistor and longer than the first width.

[0014] At least one of the first region and the second region may be separated into a region of the first sub-transistor and a region of the second sub-transistor that is away from the region of the first sub-transistor.

[0015] The first sub-transistor and the second sub-transistor may share a single first region and may share a single second region.

[0016] The first transistor may include a first sub-transistor, and second and third sub-transistors having a common gate electrode and connected to each other in series.

[0017] A channel width of the first sub-transistor may be narrower than a channel width of the second sub-transistor or a channel width of the third sub-transistor.

[0018] A channel width of the second sub-transistor may be the same as a channel width of the third sub-transistor.

[0019] Channel lengths of the first sub-transistor, the second sub-transistor, and the third sub-transistor may be smaller than a channel length of at least one of the remaining transistors.

[0020] The first sub-transistor, the second sub-transistor and the third sub-transistor share the gate electrode with each other, and the gate electrode may include: a first gate region having a first width corresponding to the channel length of the first sub-transistor; a second gate region having a second width corresponding to the channel length of the second sub-transistor; and a third gate region having a third width corresponding to the channel length of the third sub-transistor.

[0021] The gate electrode may further include a fourth gate region connecting the first gate region, the second gate region, and the third gate region to one another.

[0022] The first sub-transistor and the second sub-transistor may share a single first region, and the first sub-transistor and the third sub-transistor may share a single second region.

[0023] The gate electrode may include a portion shaped like a capital letter "T".

[0024] The first transistor may include: a first sub-transistor and a second sub-transistor connected in parallel to each other; and a third sub-transistor connected in series with the first sub-transistor and the second sub-transistor.

[0025] Channel widths of the first and second sub-transistors may be narrower than a channel width of the third sub-transistor.

[0026] Channel lengths of the first sub-transistor, the second sub-transistor, and the third sub-transistor may be smaller than a channel length of at least one of the remaining transistors.

[0027] The first sub-transistor, the second sub-transistor and the third sub-transistor can share the gate electrode with each other, and the gate electrode may include: a first gate region overlapping with the channel region of the first sub-transistor and the channel region of the second sub-transistor; and a second gate region overlapping with the channel region of the third sub-transistor.

[0028] The second gate region may be connected to the first gate region.

[0029] The first transistor may include a first sub-transistor and a second sub-transistor connected in parallel to each other, and the second sub-transistor may further include a bottom gate electrode away from the gate electrode, the first insulating film and the active layer pattern, and the channel width of the first sub-transistor may be narrower than the channel width of the second sub-transistor.

[0030] Another aspect of the present invention to achieve the above-mentioned objective provides a display device.

[0031] The display device may include: a pixel portion including a plurality of pixels; a scan drive portion consisting of a plurality of drive stages and supplying a scan signal to the pixel portion; and a light emission control drive portion consisting of a plurality of drive stages and supplying a light emission control signal to the pixel portion.

[0032] The first transistor among the multiple transistors included in each of the driving stages of the scanning driving unit and at least one of the driving stages of the light-emitting control driving unit includes: an active layer pattern, including a channel region arranged on a buffer layer to form a channel and a first region and a second region arranged on both sides of the channel region; and a gate electrode, which is separated from the active layer pattern with a first insulating film sandwiched therebetween and overlaps with the channel region.

[0033] The channel region may include: a first edge region and a second edge region located on two side surfaces based on the channel width; and a body region located between the first edge region and the second edge region.

[0034] A thickness of a region of the first insulating film overlapping with the body region may be thicker than a thickness of a region of the first insulating film overlapping with the first edge region or the second edge region.

[0035] (Effects of the Invention)

[0036] The display device according to the present invention forms a driver stage circuit in which the channel width of a transistor is reduced, thereby having characteristics that are strong against the HCI phenomenon.

[0037] Furthermore, since the driver stage circuit is configured based on transistors having a reduced channel length or channel width, there is an advantage in that the circuit area can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 A diagram for explaining a display device according to an embodiment of the present invention.

[0039] Figure 2 This is a diagram for explaining a light emission control drive unit according to an embodiment of the present invention.

[0040] Figure 3 Yes Figure 2 An example circuit diagram of the driver stage involved.

[0041] Figure 4 It is aimed at Figure 3 A cross-sectional view of the first transistor involved.

[0042] Figure 5 yes Figure 3 A plan view of the first transistor involved.

[0043] Figure 6Yes Figure 5 Graphs of the lateral electric fields measured for each area involved.

[0044] Figure 7 It is applicable Figure 3 A circuit diagram of a first embodiment of a first transistor is provided.

[0045] Figure 8 It is aimed at Figure 7 A plan view of a first embodiment of a first transistor is shown.

[0046] Figure 9 It is applicable Figure 3 A circuit diagram of a second embodiment of the first transistor is shown.

[0047] Figure 10 It is aimed at Figure 9 A plan view of a second embodiment of the first transistor is shown.

[0048] Figure 11 It is applicable Figure 3 A circuit diagram of a third embodiment of the first transistor is shown.

[0049] Figure 12 It is aimed at Figure 11 A plan view of a third embodiment of the first transistor is shown.

[0050] Figure 13 It is applicable Figure 3 A circuit diagram of a fourth embodiment of the first transistor is shown.

[0051] Figure 14 It is aimed at Figure 13 A cross-sectional view of a fourth embodiment of the second sub-transistor.

[0052] Figure 15 yes Figure 4 R-R' involves a cross-sectional view. DETAILED DESCRIPTION

[0053] Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. The present invention can be implemented in various ways and is not limited to the embodiments described herein.

[0054] In order to clearly illustrate the present invention, parts not related to the description are omitted, and the same or similar components are given the same reference numerals throughout the specification. Therefore, the reference numerals previously described may be used in other figures.

[0055] In addition, the size and thickness of each component shown in the figure are arbitrarily shown for the convenience of explanation, and the present invention is not necessarily limited to the case shown in the figure. In order to clearly show each layer and region in the figure, the thickness is exaggerated.

[0056] Figure 1 A diagram for explaining a display device according to an embodiment of the present invention.

[0057] Reference Figure 1 A display device according to an embodiment of the present invention may include a pixel unit 10 , a scan driving unit 20 , a data driving unit 30 , a light emitting control driving unit 40 , and a timing control unit 50 .

[0058] The pixel unit 10 includes a plurality of pixels PXij, which are connected to scan lines SC1 to SCn, data lines D1 to Dm, and emission control lines E1 to En and arranged in a matrix. Pixels PXij receive scan signals via scan lines SC1 to SCn, data signals via data lines D1 to Dm, and emission control signals via emission control lines E1 to En. When supplied with scan signals from scan lines SC1 to SCn, pixels PXij emit light at a brightness corresponding to the data signals supplied from data lines D1 to Dm.

[0059] The scan driver 20 is connected to a plurality of scan lines SC1 to SCn, generates scan signals in response to a scan drive control signal SCS from the timing control unit 50, and outputs the generated scan signals to the scan lines SC1 to SCn. The scan driver 20 may be composed of a plurality of driver stage circuits. The scan driver 20 may sequentially provide scan signals having pulses with an on-level to the pixels PXij via the scan lines SC1 to SCn. The scan driver 20 may be configured in the form of a shift register. In this case, the driver stage circuits of the scan driver 20 may include a plurality of transistors and / or a plurality of capacitors.

[0060] The data driver 30 is connected to a plurality of data lines D1 to Dm. It generates data signals based on the data drive control signal DCS from the timing control unit 50 and the image data DATA', and outputs the generated data signals to the data lines D1 to Dm. The data signals supplied to the data lines D1 to Dm are supplied to the pixels PXij selected by the scan signal each time a scan signal is supplied. This allows the pixels PXij to be charged with a voltage corresponding to the data signal.

[0061] The light-emission control driver 40 is connected to a plurality of light-emission control lines E1 to En. It generates light-emission control signals in response to light-emission drive control signals ECS from the timing control unit 50 and outputs the generated light-emission control signals to the light-emission control lines E1 to En. The light-emission control driver 40 may be comprised of a plurality of driver-stage circuits and supplies light-emission control signals to the light-emission control lines E1 to En to control the light-emission period of the pixels PXij.

[0062] The timing control unit 50 receives inputs such as image data DATA, synchronization signals Hsync and Vsync for controlling the display of the image data DATA, and a clock signal CLK. The timing control unit 50 performs image processing on the input image data DATA to generate image data DATA′ that has been corrected to be suitable for image display by the pixel unit 10 and outputs the corrected image data to the data driver unit 30. Furthermore, the timing control unit 50 can generate drive control signals (SCS, DCS, and ECS) for controlling the drive of the scan driver unit 20, the data driver unit 30, and the light control driver unit 40 based on the synchronization signals Hsync and Vsync and the clock signal CLK. Specifically, the timing control unit 50 generates a scan drive control signal SCS and supplies it to the scan driver unit 20, generates a data drive control signal DCS and supplies it to the data driver unit 30, and generates a light drive control signal ECS and supplies it to the light control driver unit 40.

[0063] Figure 2 This is a diagram for explaining a light emission control drive unit according to an embodiment of the present invention.

[0064] Refer to Figure 1 as well as Figure 2 The light emission control driving unit 40 may include a plurality of driving stages (401, 402, 403, ...) for supplying light emission control signals (EM1, EM2, EM3, ...) to the light emission control lines E1 to En. However, for ease of explanation, only three driving stages (401, 402, 403) are shown in the figure.

[0065] The driver stages (401, 402, 403, ...) are driven by a light emission start signal FLM, a first clock signal CLK1, and a second clock signal CLK2, and output light emission control signals (EM1, EM2, EM3, ...). The light emission start signal FLM, the first clock signal CLK1, and the second clock signal CLK2 can be received via a light emission drive control signal ECS from the timing control unit 50. The driver stages (401, 402, 403, ...) can be formed of the same or different circuits.

[0066] The driver stages ( 401 , 402 , 403 , . . . ) may respectively include a first input terminal 101 , a second input terminal 102 , a third input terminal 103 and an output terminal 104 .

[0067] The first input terminal 101 can receive the carrier signal (CR1, CR2, ...) of the previous driver stage or the light emission start signal FLM. For example, the first driver stage 401 can receive the light emission start signal FLM through the first input terminal 101, and the remaining driver stages can receive the carrier signal (CR1, CR2, ...) of the previous driver stage through the first input terminal 101. The carrier signal (CR1, CR2, ...) can also include the light emission control signal (EM1, EM2, EM3, ...) of the previous driver stage.

[0068] The second input terminal 102 and the third input terminal 103 can receive inputs of the first clock signal CLK1 and the second clock signal CLK2 respectively.

[0069] The output terminal 104 can be connected to one of the light emitting control lines E1, E2, ..., En, and output a light emitting control signal (EM1, EM2, EM3, ...).

[0070] The first clock signal CLK1 or the second clock signal CLK2 can be a rectangular wave signal that repeatedly switches between a logic high level and a logic low level. The periods of the first clock signal CLK1 and the second clock signal CLK2 can be the same, for example, two horizontal periods (2H). The first clock signal CLK1 and the second clock signal CLK2 can be signals with identical waveforms. The first clock signal CLK1 and the second clock signal CLK2 can have a phase difference of more than half a period, and the gate-on voltage periods of the first clock signal CLK1 and the second clock signal CLK2 can be set to not overlap. For example, during a period when the first clock signal CLK1 is at a logic high level, the second clock signal CLK2 can be at a logic low level, and during a period when the first clock signal CLK1 is at a logic low level, the second clock signal CLK2 can be at a logic high level. However, this is merely an example, and the waveform relationship between the first clock signal CLK1 and the second clock signal CLK2 is not necessarily limited to this.

[0071] Reference Figure 2 The first driving stage 401 can output the first light-emitting control signal EM1 to the pixel connected to one of the light-emitting control lines E1~En in response to the light-emitting start signal FLM, the first clock signal CLK1 and the second clock signal CLK2, and output the first carrier signal CR1 to the second driving stage 402.

[0072] The second driving stage 402 may output a second emission control signal EM2 to a pixel PXij connected to one of the emission control lines E1 ˜En in response to the first and second clock signals CLK1 , CLK2 , and the first carrier signal CR1 , and output a second carrier signal CR2 to the third driving stage 403 .

[0073] The third driving stage 403 can output a third emission control signal EM3 to a pixel connected to one of the emission control lines E1 to En in response to the first clock signal CLK1, the second clock signal CLK2 and the second carrier signal CR2, and output the third carrier signal CR3 to the fourth driving stage (not shown).

[0074] On the other hand, Figure 2 , each driver stage directly receives inputs of the first clock signal CLK1 and the second clock signal CLK2 via the second input terminal 102 and the third input terminal 103, but the present invention is not necessarily limited to this. As another embodiment, the first driver stage 401 can directly receive inputs of the first clock signal CLK1 and the second clock signal CLK2, but the remaining driver stages (402, 403, ...) can receive one of the first clock signal CLK1 and the second clock signal CLK2 from the previous driver stage. As a specific example, the odd-numbered driver stages (403, ...) other than the first driver stage 401 can receive inputs of the first clock signal CLK1 from the previous driver stage and directly receive inputs of the second clock signal CLK2. The even-numbered driver stages (402, ...) can directly receive inputs of the first clock signal CLK1 and receive inputs of the second clock signal CLK2 from the previous driver stage. Thus, according to another embodiment, the carrier signal can include at least one of the first clock signal CLK1 and the second clock signal CLK2.

[0075] In addition, the first clock signal CLK1 and the second clock signal CLK2 may be input alternately to each driving stage.

[0076] For example, Figure 2 As shown, the odd-numbered driver stages (401, 403, ...) can receive the input of the first clock signal CLK1 at the second input terminal 102 and the input of the second clock signal CLK2 at the third input terminal 103; the even-numbered driver stages (402, ...) can receive the input of the second clock signal CLK2 at the second input terminal 102 and the input of the first clock signal CLK1 at the third input terminal 103.

[0077] Figure 3 Yes Figure 2 An example circuit diagram of the driver stage involved.

[0078] Reference Figure 3 , indicating that Figure 2 The circuit diagram of any i-th driver stage 400 among the driver stages (401, 402, 403, ...) shown in FIG. Figure 2As shown in the odd-numbered driving stages, the first input terminal 101 can be applied with the light-emitting start signal FLM and the carrier signal CR[i-1] of the previous driving stage, and the second input terminal 102 and the third input terminal 103 can receive the input of the first clock signal CLK1 and the second clock signal CLK2 respectively.

[0079] However, if Figure 2 As described in , it should be understood that the second input terminal 102 may receive the second clock signal CLK2 as input, and the third input terminal 103 may receive the first clock signal CLK1 as input.

[0080] Reference Figure 3 , the i-th driving stage 400 may include a plurality of transistors ( T1 ˜ T10 ) and a plurality of capacitors ( C1 , C2 , C3 ).

[0081] The first transistor T1 may be connected between the first power supply VGH and the fourth node N4 and may include a gate electrode connected to the second node N2. When the first transistor T1 is turned on by a voltage (e.g., a low-level voltage) applied to the second node N2, the first transistor T1 may transmit a voltage (e.g., a high-level voltage) based on the first power supply VGH to the fourth node N4.

[0082] The second transistor T2 may include a gate electrode connected to the second input terminal 102 and may be connected between the first input terminal 101 to which one of the light emission start signal FLM and the carrier signal CR[i-1] of the previous driving stage is applied and the first node N1. When the second transistor T2 is turned on by the first clock signal CLK1, the first input terminal 101 and the first node N1 may be electrically connected.

[0083] The third transistor T3 may include a gate electrode connected to the third input terminal 103 and may be connected between the fourth node N4 and the first node N1.

[0084] The fourth transistor T4 may include a gate electrode connected to the first node N1 and may be connected between the second node N2 and the second input terminal 102 .

[0085] The fifth transistor T5 may include a gate electrode connected to the second input terminal 102 and may be connected between the second node N2 and the second power source VGL.

[0086] The sixth transistor T6 may include a gate electrode connected to the third node N3 and may be connected between the first power supply VGH and the output terminal 104 .

[0087] The seventh transistor T7 may include a gate electrode connected to the first node N1 and may be connected between the output terminal 104 and the second power supply VGL.

[0088] The eighth transistor T8 may include a gate electrode connected to the first node N1 and may be connected between the first power source VGH and the third node N3 .

[0089] The ninth transistor T9 may include a gate electrode connected to the third input terminal 103 and may be connected between the fifth node N5 and the third node N3 .

[0090] The tenth transistor T10 may include a gate electrode connected to the second node N2 and may be connected between the fifth node N5 and the third input terminal 103 .

[0091] The first capacitor C1 may be connected between the first node N1 and the third input terminal 103 .

[0092] The second capacitor C2 may be connected between the second node N2 and the fifth node N5.

[0093] The third capacitor C3 may be connected between the first power source VGH and the third node N3 .

[0094] Figure 3 The plurality of transistors (T1 to T10) shown may be P-type transistors. Figure 3 The gate-on voltage of the plurality of transistors (T1 to T10) shown in FIG. 1 may be a low level, and the gate-off voltage may be a high level. However, this is not necessarily limited to this, and it should be interpreted that an embodiment of the present invention also includes Figure 3 All or part of the plurality of transistors ( T1 to T10 ) shown may be transformed into N-type transistors.

[0095] also, Figure 3 In the i-th driving stage 400 involved, the first power supply VGH can provide a high-level voltage (or gate-off voltage) that turns off the P-type transistor (or multiple transistors (T1~T10)), and the second power supply VGL can provide a low-level voltage (or gate-on voltage) that turns on the P-type transistor (or multiple transistors (T1~T10)).

[0096] on the other hand, Figure 3 The first transistor T1 shown in the figure transmits the current of the first power supply VGH to the fourth node N4. The current transmitted to the fourth node N4 is then transmitted to the first node N1 via the third transistor T3. In other words, the first transistor T1 can transmit the current of the first power supply VGH to the first node N1. At this time, the first node N1 can be connected to the second transistor T2 connected to the light emission start signal FLM or the carrier signal CR[i-1] of the previous driver stage.

[0097] Figure 4 It is aimed at Figure 3 A cross-sectional view of the first transistor involved.

[0098] Figure 4 Illustrated Figure 3 Cross-sectional view CC of the first transistor T1 is concerned.

[0099] Reference Figure 4 The first transistor T1 is arranged on one surface of the base layer 200 on which the buffer layer 201 is formed, and may include: an active layer pattern 202, including a channel region 202a forming a channel of the first transistor T1, a first region 202b1 and a second region 202b2 arranged on both sides of the channel region 202a; a gate electrode 204, which is separated from the active layer pattern 202 by a first insulating film 203 and overlaps with the channel region 202a of the active layer pattern 202; and a first electrode 206 and a second electrode 207, which are separated from the active layer pattern 202 by a first insulating film 203 and a second insulating film 205 and are connected to the first region 202b1 and the second region 202b2 of the active layer pattern 202, respectively.

[0100] One of the first region 202b1 and the second region 202b2 can be the source region of the first transistor T1, and the other can be the drain region of the first transistor T1. As an example, if the first region 202b1 is the source region of the first transistor T1, the second region 202b2 can be the drain region of the first transistor T1. Conversely, if the first region 202b1 is the drain region of the first transistor T1, the second region 202b2 can be the source region of the first transistor T1. This can vary depending on the carrier type of the first transistor T1 (for example, N-type or P-type) and the direction of current flow.

[0101] On the other hand, in the present invention, the positions of the first electrode 206 and the second electrode 207 are not particularly limited and may be variously modified according to the embodiment. In addition, at least one of the first electrode 206 and the second electrode 207 may be omitted according to the embodiment.

[0102] For example, when the first transistor T1 is directly connected to other circuit elements (for example, at least one other transistor and / or capacitor) via the first region 202b1, the first electrode 206 can be omitted. Similarly, when the first transistor T1 is directly connected to other circuit elements via the second region 202b2, the second electrode 207 can be omitted.

[0103] In addition, depending on the viewpoint, the first region 202b1 and / or the second region 202b2 can be considered as the source electrode and / or drain electrode of the first transistor T1, and the first electrode 206 and / or the second electrode 207 can be considered as the wiring connected to an electrode of the first transistor T1 or the electrode of other circuit elements.

[0104] The channel region 202 a , the first region 202 b 1 , and the second region 202 b 2 may each include polysilicon (Poly-Si).

[0105] At this time, the length of the channel region 202a in the first direction DR1 can be defined as a channel length (channel length) L, and the length of the channel region 202a in the second direction DR2 perpendicular to the first direction DR1 can be defined as a channel width (channel width), wherein the first direction DR1 passes through the first region 202b1 and the second region 202b2 of the active layer pattern 202 (or is perpendicular to the first region 202b1 and the second region 202b2).

[0106] In addition, the gate electrode 204 may include Figure 4 As shown in the figure, the region has a width (the width of the gate electrode 204 in the first direction DR1 ) equal to the channel length L, but the present invention is not necessarily limited to this.

[0107] On the other hand, when the voltage of the source electrode or drain electrode of a thin film transistor (TFT) increases, the driving current of the transistor (the current flowing through the transistor when the transistor is on, the source-drain current) decreases due to the HCI (hot carrier instability) phenomenon. Figure 4 Taking the first transistor T1 shown as an example, when the voltage of the second electrode 207 increases, the electric field in the pinch-off region near the second region 202b2 (or the drain region) increases, causing electrons to be accelerated by the electric field, resulting in high speed and kinetic energy. As a result, these more mobile electrons may penetrate the first insulating film 203, or, although they may be stored in the first insulating film 203, they may disrupt the electrical characteristics of the first transistor T1, potentially reducing the drive current.

[0108] As mentioned above, Figure 3 In that case, if at least one transistor (for example, the first transistor T1) among the multiple transistors (T1 to T10) constituting the i-th driving stage 400 of the light-emitting drive control unit 40 generates an HCI phenomenon, problems such as flickering may occur due to a decrease in the output waveform of the light-emitting control signal.

[0109] Below, in Figure 3The structure for preventing degradation and improving the driving current drop is described based on the first transistor T1 which has a high tendency to deteriorate due to the HCI phenomenon, but it is not necessarily limited to the first transistor T1. For example, it can be applied to Figure 3 One or more transistors among the multiple transistors shown. In addition, it can also be applied to form Figure 1 At least one transistor among the transistors in the driving stage of the scan driving unit 20 shown.

[0110] Figure 5 yes Figure 3 A plan view of the first transistor involved. Figure 6 It is aimed at Figure 5 A graph of the lateral electric field measured across the area involved.

[0111] Figure 5 Yes Figure 3 A plan view of the active layer pattern 202 and the gate electrode 204 of the first transistor T1.

[0112] Figure 5 The channel region 202 a of the active layer pattern 202 shown may include regions ( 202 a 1 , 202 a 2 , 202 a 3 ) overlapping with the gate electrode 204 .

[0113] Reference Figure 5 The channel region 202a of the active layer pattern 202 includes a first edge region 202a2 and a second edge region 202a3 located on opposite sides thereof, with a channel width W as a reference, and a bulk region 202a1 located between the first edge region 202a2 and the second edge region 202a3. In this case, the channel width W may be equal to the sum of the width Wedge1 of the first edge region 202a2, the width Wedge2 of the second edge region 202a3, and the width Wbulk of the bulk region 202a1.

[0114] exist Figure 5 The first edge region 202a2 or the second edge region 202a3 shown in FIG. 2 concentrates the vertical electric field. Therefore, under the same voltage condition, the lateral electric field is reduced.

[0115] Reference Figure 6 It can be confirmed that the side electric field of the first edge region 202a2 or the second edge region 202a3 is lower than that of the body region 202a1. Therefore, the HCI phenomenon is relatively reduced in the first edge region 202a2 and the second edge region 202a3 located on both sides of the channel region 202a compared to the body region 202a1.

[0116] At this time, if the channel width W is narrowed, the area occupied by the edge regions (202a2, 202a3) in the channel region 202a increases, and the area occupied by the body region 202a1 decreases. Therefore, the narrower the channel width W, the more effective it is in preventing the drop in drive current caused by the HCI phenomenon.

[0117] Based on the above points, a structure in which the channel width W of the channel region 202 a can be made narrow to prevent the HCI phenomenon will be described below.

[0118] Figure 7 It is applicable Figure 3 A circuit diagram of a first embodiment of a first transistor is provided. Figure 8 It is aimed at Figure 7 A plan view of a first embodiment of a first transistor is shown.

[0119] Reference Figure 7 The first transistor T1 may include a first sub-transistor T1_1 and a second sub-transistor T1_2 connected in parallel. The first sub-transistor T1_1 and the second sub-transistor T1_2 may each include a channel region and a first region and a second region located on both sides of the channel region.

[0120] Here, the first sub-transistor T1_1 and the second sub-transistor T1_2 may be connected between the first power source VGH and the fourth node N4. The first sub-transistor T1_1 and the second sub-transistor T1_2 may each include a gate electrode commonly connected to the second node N2.

[0121] Figure 8 1 shows a plan view of a first transistor T1 including a first sub-transistor T1_1 and a second sub-transistor T1_2 connected in parallel to each other.

[0122] Reference Figure 8 The channel width EBD1_W1 of the first sub-transistor T1_1 may be narrower than the channel width EBD1_W2 of the second sub-transistor T1_2. The first sub-transistor T1_1 having such a narrow channel width is less affected by the HCI phenomenon and thus may have strong characteristics.

[0123] Furthermore, a channel length EBD1_L1 of the first sub-transistor T1_1 may be shorter than a channel length EBD1_L2 of the second sub-transistor T1_2 .

[0124] On the other hand, the first sub-transistor T1_1 and the second sub-transistor T1_2 can be as follows Figure 8As shown by the symbols EBD1-1 or EBD1-2, they share a single gate electrode 204. In this case, the width of the gate electrode 204 overlapping with the channel region of the first sub-transistor T1_1 can be narrower than the width of the gate electrode 204 overlapping with the channel region of the second sub-transistor T1_2. For example, the width of the gate electrode 204 overlapping with the channel region of the first sub-transistor T1_1 can be less than 4 μm, and can be 1 μm.

[0125] As indicated by symbol EBD1-1, the gate electrode 204 may include a first gate region 204a having a first width corresponding to the channel length EBD1_L1 of the first sub-transistor T1_1 (not shown because it is the same as EBD1_L1) and a second gate region 204b having a second width corresponding to the channel length EBD1_L2 of the second sub-transistor T1_2 and longer than the first width (not shown because it is the same as EBD1_L2). The second gate region 204b may be connected to the first gate region 204a along a second direction DR2.

[0126] Furthermore, at least one of the first region 202b1 and the second region 202b2 of the first transistor T1 can be separated into a region of a first sub-transistor T1_1 and a region of a second sub-transistor T1_2 that is spaced apart from the region of the first sub-transistor T1_1. For example, as shown by symbol EBD1-1, the first region 202b1-1 of the first sub-transistor T1_1 and the first region 202b1-2 of the second sub-transistor T1_2 can be spaced apart and separated, and the second region 202b2-1 of the first sub-transistor T1_1 and the second region 202b2-2 of the second sub-transistor T1_2 can be spaced apart and separated. In this case, the first region 202b1-1 of the first sub-transistor T1_1 and the first region 202b1-2 of the second sub-transistor T1_2 can be included in the first region 202b1 of the first transistor T1. Furthermore, the second region 202b2-1 of the first sub-transistor T1_1 and the second region 202b2-2 of the second sub-transistor T1_2 can be included in the second region 202b2 of the first transistor T1.

[0127] On the other hand, as indicated by symbol EBD1-2, the first sub-transistor T1_1 and the second sub-transistor T1_2 share a single first region 202b1 of the first transistor T1, and share a single second region 202b2 of the first transistor T1. For example, the first region 202b1-1 of the first sub-transistor T1_1 can be combined with the first region 202b1-2 of the second sub-transistor T1_2 to form the first region 202b1 of the first transistor T1 (e.g., the source region or the drain region), and the second region 202b2-1 of the first sub-transistor T1_1 can be combined with the second region 202b2-2 of the second sub-transistor T1_2 to form the second region 202b2 of the first transistor T1 (e.g., the drain region or the source region).

[0128] Figure 9 It is applicable Figure 3 A circuit diagram of a second embodiment of the first transistor is shown. Figure 10 It is aimed at Figure 9 A plan view of a second embodiment of the first transistor is shown.

[0129] Reference Figure 9 The first transistor T1 may include a first sub-transistor T1_1 and a second sub-transistor T1_2 and a third sub-transistor T1_3 having a common gate electrode and connected in series. The first sub-transistor T1_1, the second sub-transistor T1_2, and the third sub-transistor T1_3 may each include a channel region and a first region and a second region located on either side of the channel region.

[0130] The first sub-transistor T1_1 may be connected between the first power source VGH and the fourth node N4 and may include a gate electrode connected to the second node N2 .

[0131] The second sub-transistor T1_2 may be connected between the first power source VGH and one end of the third sub-transistor T1_3 and include a gate electrode connected to the second node N2 .

[0132] The third sub-transistor T1_3 may be connected between one end of the second sub-transistor T1_2 and the fourth node N4 and include a gate electrode connected to the second node N2.

[0133] Figure 10 A plan view of a first transistor T1 including a first sub-transistor T1_1, a second sub-transistor T1_2, and a third sub-transistor T1_3 is shown.

[0134] Reference Figure 10The channel width EBD2_W1 of the first sub-transistor T1_1 may be narrower than the channel width EBD2_W2 of the second sub-transistor T1_2 or the channel width EBD2_W3 of the third sub-transistor T1_3. The first sub-transistor T1_1 with such a narrow channel width EBD2_W1 is less affected by the HCI phenomenon and thus can have strong characteristics.

[0135] Furthermore, the channel width EBD2_W2 of the second sub-transistor T1_2 may be equal to the channel width EBD2_W3 of the third sub-transistor T1_3 .

[0136] Furthermore, the channel length EBD2_L1 of the first sub-transistor T1_1, the channel length EBD2_L2 of the second sub-transistor T1_2, and the channel length EBD2_L3 of the third sub-transistor T1_3 may be smaller than the channel length of at least one of the remaining transistors included in the driver stage. For example, the channel length EBD2_L1 of the first sub-transistor T1_1, the channel length EBD2_L2 of the second sub-transistor T1_2, and the channel length EBD2_L3 of the third sub-transistor T1_3 may be less than 4 μm, and may be 1 μm.

[0137] Furthermore, the first, second, and third sub-transistors T1_1, T1_2, and T1_3 may share a gate electrode 204. For example, as indicated by symbol EBD2-1, gate electrode 204 may include: a first gate region 204a having a first width corresponding to the channel length EBD2_L1 of the first sub-transistor T1_1 (the same as EBD2_L1 and therefore not shown); a second gate region 204b having a second width corresponding to the channel length EBD2_L2 of the second sub-transistor T1_2 (the same as EBD2_L2 and therefore not shown); and a third gate region 204c having a third width corresponding to the channel length EBD2_L3 of the third sub-transistor T1_3 (the same as EBD2_L3 and therefore not shown). In this case, the first width may be equal to the second width.

[0138] In addition, the gate electrode 204 may further include a fourth gate region 204 d connecting the first gate region 204 a , the second gate region 204 b , and the third gate region 204 c .

[0139] The first gate region 204 a may overlap with the channel region of the first sub-transistor T1_1 , the second gate region 204 b may overlap with the channel region of the second sub-transistor T1_2 , and the third gate region 204 c may overlap with the channel region of the third sub-transistor T1_3 .

[0140] Furthermore, the second region 202b2-2 of the second sub-transistor T1_2 and the first region 202b1-3 of the third sub-transistor T1_3 may be adjacent to each other.

[0141] Reference Figure 10 In the example of FIG. 1 , the first region 202b1-1 of the first sub-transistor T1_1 can be combined with the first region 202b1-2 of the second sub-transistor T1_2 to form the first region 202b1 of the first transistor T1. The second region 202b2-1 of the first sub-transistor T1_1 can be combined with the second region 202b2-3 of the third sub-transistor T1_3 to form the second region 202b2 of the first transistor T1. Furthermore, a region 202b12 in which the second region of the first sub-transistor T1_1 (not shown) and the first region of the third sub-transistor T1_3 are adjacent to each other and in which the second region of the first sub-transistor T1_1 and the first region of the third sub-transistor T1_3 are adjacent to each other may be included in the channel region 202a of the first transistor T1.

[0142] Furthermore, as shown by symbol EBD2-2, the gate electrode 204 may be in the shape of a capital letter "T." For example, the first gate region 204a, the second gate region 204b, and the fourth gate region 204d may be connected to have a single width (the first width or the second width), and the third gate region 204c may be connected to the fourth gate region 204d in a direction perpendicular to the first gate region 204a or the second gate region 204b. Specifically, the first gate region 204a may be connected to the fourth gate region 204d in a first direction DR1, the second gate region 204b may be connected to the fourth gate region 204d in a direction DR1' opposite to the first direction DR1, and the third gate region 204c may be connected to the fourth gate region 204d in a direction DR2' opposite to the second direction DR2.

[0143] Figure 11 It is applicable Figure 3 A circuit diagram of a third embodiment of the first transistor is shown. Figure 12 It is aimed at Figure 11 A plan view of a third embodiment of the first transistor is shown.

[0144] Reference Figure 11 The first transistor T1 may include a first sub-transistor T1_1 and a second sub-transistor T1_2 connected in parallel, and a third sub-transistor T1_3 connected in series with the first sub-transistor T1_1 and the second sub-transistor T1_2. The first sub-transistor T1_1, the second sub-transistor T1_2, and the third sub-transistor T1_3 may each include a channel region and a first region and a second region located on opposite sides of the channel region.

[0145] The first sub-transistor T1_1 may be connected between the fourth node N4 and one end of the third sub-transistor T1_3 and include a gate electrode connected to the second node N2 .

[0146] The second sub-transistor T1_2 may be connected between the fourth node N4 and one end of the third sub-transistor T1_3 and include a gate electrode connected to the second node N2 .

[0147] The third sub-transistor T1_3 may be connected between the first power source VGH and one end of the first sub-transistor T1_1 and the second sub-transistor T1_2 , and include a gate electrode connected to the second node N2 .

[0148] Figure 12 1 shows a plan view of a first transistor T1 including a first sub-transistor T1_1 , a second sub-transistor T1_2 , and a third sub-transistor T1_3 .

[0149] Reference Figure 12 denoted by EBD3-1, the channel width EBD3_W1 of the first sub-transistor T1_1 can be narrower than the channel width EBD3_W3 of the third sub-transistor T1_3. The channel width EBD3_W2 of the second sub-transistor T1_2 can be narrower than the channel width EBD3_W3 of the third sub-transistor T1_3. Therefore, the first sub-transistor T1_1 and the second sub-transistor T1_2, each having narrow channel widths (EBD3_W1, EBD3_W2), are less affected by the HCI phenomenon and thus have strong characteristics. Furthermore, the channel width EBD3_W2 of the second sub-transistor T1_2 can be equal to the channel width EBD3_W1 of the first sub-transistor T1_1.

[0150] Furthermore, the channel lengths EBD3_L1 of the first sub-transistor T1_1, EBD3_L2 of the second sub-transistor T1_2, and EBD3_L3 of the third sub-transistor T1_3 may be smaller than the channel lengths of the remaining transistors. For example, the channel lengths EBD3_L1 of the first sub-transistor T1_1, EBD3_L2 of the second sub-transistor T1_2, and EBD3_L3 of the third sub-transistor T1_3 may be less than 4 μm, and may be 1 μm.

[0151] Furthermore, the first, second, and third sub-transistors T1_1, T1_2, and T1_3 may share a gate electrode 204. For example, as indicated by symbol EBD3-1, the gate electrode 204 may include a first gate region 204a having a first width corresponding to the channel length EBD3_L1 of the first sub-transistor T1_1 and the channel length EBD3_L2 of the second sub-transistor T1_2 (which may be the same as EBD3_L1 or EBD3_L2 and is therefore not shown); and a second gate region 204b having a second width corresponding to the channel length EBD3_L3 of the third sub-transistor T1_3 (which may be the same as EBD3_L3 and is therefore not shown).

[0152] In addition, the first gate region 204a may overlap with the channel region of the first sub-transistor T1_1 and the channel region of the second sub-transistor T1_2 , and the second gate region 204b may overlap with the channel region of the third sub-transistor T1_3 .

[0153] Reference Figure 12 Referring to symbol EBD3-1, gate electrode 204 may further include a third gate region 204c connecting first gate region 204a and second gate region 204b. Third gate region 204c may include: region 204c1 connecting one end of first gate region 204a and second gate region 204b; and region 204c2 connecting the other ends of first gate region 204a and second gate region 204b.

[0154] On the other hand, refer to Figure 12 In the example of the embodiment of the present invention, the third gate region 204c may not be provided, and the first gate region 204a and the second gate region 204b may be directly connected to each other. For example, the first gate region 204a and the second gate region 204b may be connected to each other at an angle between 75 degrees and 105 degrees (or 90 degrees). More specifically, the side corresponding to the first width of the first gate region 204a (the same as EBD3_L1 or EBD3_L2 in the figure) and the side corresponding to the second width of the second gate region 204b (the same as EBD3_L3 in the figure) may be connected to each other at an angle between 75 degrees and 105 degrees (or 90 degrees). In this case, the first gate region 204a may have a first width along the first direction DR1, and the second gate region 204b may have a second width along the second direction DR2 perpendicular to the first direction DR1.

[0155] Figure 13 It is applicable Figure 3 A circuit diagram of a fourth embodiment of the first transistor is shown. Figure 14 It is aimed at Figure 13A cross-sectional view of a fourth embodiment of the second sub-transistor.

[0156] Reference Figure 13 The first transistor T1 may include a first sub-transistor T1_1 and a second sub-transistor T1_2 having a dual gate electrode. The first sub-transistor T1_1 and the second sub-transistor T1_2 may each include a channel region and a first region and a second region located on both sides of the channel region.

[0157] The first sub-transistor T1_1 may be connected between the first power source VGH and the fourth node N4 and include a gate electrode connected to the second node N2 .

[0158] The second sub-transistor T1_2 may be connected between the first power source VGH and the fourth node N4 and include a first gate electrode connected to the first power source VGH and a second gate electrode connected to the second node N2 .

[0159] The channel length of the first sub-transistor T1_1 can be relatively shorter than the channel length of the remaining transistors included in at least one of the driver stages of the scan driver 20 and the light-emission control driver 40. Furthermore, the channel width of the first sub-transistor T1_1 can be relatively narrower than the channel width of the remaining transistors included in at least one of the driver stages of the scan driver 20 and the light-emission control driver 40. For example, the channel length and channel width of the first sub-transistor T1_1 can be less than 4 μm. More specifically, the channel length and channel width of the first sub-transistor T1_1 can be 1 μm. Therefore, the first sub-transistor T1_1 is less affected by the HCI phenomenon and can have strong characteristics.

[0160] Reference Figure 14 , Figure 13 The second sub-transistor T1_2 with a dual gate electrode may include: a bottom gate electrode (first gate electrode) 304b, which is disposed on one surface of the base layer 300; an active layer pattern 302, which includes a channel region 302a, which is separated from the first gate electrode 304b and separated from the first gate electrode 304b via a first insulating film 301 and forms a channel of the second sub-transistor T1_2, and a first region 302b1 and a second region 302b2 disposed on both sides of the channel region 302a; a top gate electrode ( a second gate electrode) 304a, which is sandwiched between the active layer pattern 302 and the second insulating film 303, is away from the active layer pattern 302 and overlaps with the channel region 302a of the active layer pattern 302; and a first electrode 306 and a second electrode 307, which are sandwiched between the second insulating film 303, the third insulating film 304 and the fourth insulating film 305, are away from the active layer pattern 302 and are connected to the first region 302b1 and the second region 302b2 of the active layer pattern 302.

[0161] At this time, the top gate electrode 304a may include Figure 4 Regarding the gate electrode 204, the second insulating film 303 may include Figure 4 The first insulating film 203 is involved. In addition, the base layer 300 may be Figure 4 Regarding the base layer 200, the active layer pattern 302 may include Figure 4 The active layer pattern 202 is involved.

[0162] One of the first region 302b1 and the second region 302b2 can be the source region of the second sub-transistor T1_2, and the other can be the drain region of the second sub-transistor T1_2. For example, if the first region 302b1 is the source region of the second sub-transistor T1_2, then the second region 302b2 can be the drain region of the second sub-transistor T1_2. Conversely, if the first region 302b1 is the drain region of the second sub-transistor T1_2, then the second region 302b2 can be the source region of the second sub-transistor T1_2. This can vary depending on the carrier type of the second sub-transistor T1_2 (for example, N-type or P-type) and the direction of current flow.

[0163] The first gate electrode 304 b may be electrically connected to an electrode 309 of a wiring connected to a first power supply VGH, and in this case, one or more other electrodes 308 may be used.

[0164] On the other hand, the channel length L of the second sub-transistor T1_2 can be smaller than the channel length of at least one of the remaining transistors included in at least one of the driver stages of the scan driver 20 and the light emission control driver 40. For example, the channel length L of the second sub-transistor T1_2 can be less than 4 μm. More specifically, the channel length of the second sub-transistor T1_2 can be 1 μm.

[0165] Furthermore, the channel width (not shown) of the second sub-transistor T1_2 can be relatively larger than the channel width of at least one of the remaining transistors included in at least one of the driver stages of the scan driver 20 and the light emission control driver 40. For example, the channel width of the second sub-transistor T1_2 can be greater than 4 μm.

[0166] exist Figure 14 In the embodiment, the channel length L may be the length of the channel region 302 a along the first direction DR1 , and the channel width may be the length of the channel region 302 a along the second direction DR2 perpendicular to the first direction DR1 on the same plane.

[0167] like Figure 14As shown, in the case where the second sub-transistor T1_2 includes dual gate electrodes (a top gate electrode 304 a and a bottom gate electrode 304 b ), as the number of gate electrodes increases, the mobility of the driving current may increase.

[0168] Figure 15 It is along Figure 4 R-R' cross-sectional view.

[0169] and Figure 4 compared to, Figure 15 The cross-sectional view of the first transistor shown along RR' shows that the second direction DR2 corresponds to the lateral direction in the figure. Therefore, it can be assumed that there is a current flow along the first direction DR1.

[0170] Reference Figure 15 The channel region 202a of the active layer pattern 202 includes: a first edge region 202a2 and a second edge region 202a3 located on both sides with the channel width W as a reference; and a body region 202a1 located between the first edge region 202a2 and the second edge region 202a3 (see Figure 5 floor plan).

[0171] At this time, the thickness d1 of the region of the first insulating film 203 overlapping with the body region 202 a 1 may be formed to be thicker than the thickness d2 of the region overlapping with the first edge region 202 a 2 or the second edge region 202 a 3 .

[0172] As described above, if the thickness of the region overlapping with the body region 202 a 1 in the first insulating film 203 is formed relatively thick, it is possible to have strong resistance to the HCl phenomenon and prevent a decrease in the driving current.

[0173] Figure 15The process method for the first transistor T1 involved may be, for example, first forming a buffer layer 201 on a base layer 200, depositing amorphous silicon (a-Si) on the buffer layer 201, and then converting the amorphous silicon into polycrystalline silicon (Poly-Si) through a laser crystallization process. Then, an active layer pattern 202 may be formed on the polycrystalline silicon through a photolithography process, and a first insulating film 203 may be formed on the formed active layer pattern 202 through chemical vapor deposition (CVD). At this time, a hard mask may be used to shave off a portion of the first edge region 202a2 and / or the second edge region 202a3 of the first insulating film 203, thereby forming a first insulating film 203 with a relatively thick thickness in the region overlapping with the body region 202a1. Then, a gate layer may be deposited on the first insulating film 203, and a photolithography process may be performed to leave only a portion of the gate layer, thereby forming a gate electrode 204. Then, a second insulating film 205 may be formed after the source region and the drain region are formed in the active layer pattern 202 by ion doping.

[0174] The drawings and detailed description of the invention referred to so far are merely illustrative of the present invention and are used solely for the purpose of illustrating the present invention. They are not intended to limit or restrict the scope of the invention as described in the claims. Therefore, those skilled in the art will appreciate that various modifications and equivalent embodiments are possible. Therefore, the true technical scope of the present invention should be defined by the technical principles of the claims.

Claims

1. A display device comprising: a pixel portion including a plurality of pixels; a scanning driving portion, comprising a plurality of driving stages and supplying a scanning signal to the pixel portion; as well as The light emission control driving unit is composed of a plurality of driving stages and supplies a light emission control signal to the pixel unit. The first transistor among the plurality of transistors included in at least one of the driving stages of the scanning driving unit and the driving stages of the light emitting control driving unit includes: An active layer pattern, comprising a channel region disposed on the base layer to form a channel, and a first region and a second region disposed on both sides of the channel region; as well as a gate electrode spaced apart from the active layer pattern with a first insulating film interposed therebetween and overlapping the channel region; a channel width of the channel region being narrower than a channel width of at least one of the remaining transistors among the plurality of transistors, The first transistor includes a first sub-transistor and a second sub-transistor connected in parallel to each other, A channel width of the first sub-transistor is narrower than a channel width of the second sub-transistor, and a channel length of the first sub-transistor is shorter than a channel length of the second sub-transistor.

2. The display device according to claim 1, wherein The first sub-transistor and the second sub-transistor share the gate electrode. The gate electrode includes a first gate region having a first width corresponding to a channel length of the first sub-transistor, and a second gate region having a second width corresponding to a channel length of the second sub-transistor and longer than the first width.

3. The display device according to claim 2, wherein: At least one of the first region and the second region is separated into a region of the first sub-transistor and a region of the second sub-transistor that is away from the region of the first sub-transistor.

4. The display device according to claim 2, wherein The first sub-transistor and the second sub-transistor share a single first region and may share a single second region.

5. The display device according to claim 1, wherein The first transistor further includes a third sub-transistor, and the second sub-transistor and the third sub-transistor have a common gate electrode and are connected to each other in series. The display device according to claim 5 , wherein: A channel width of the first sub-transistor is narrower than a channel width of the third sub-transistor.

7. The display device according to claim 5, wherein: A channel width of the second sub-transistor is the same as a channel width of the third sub-transistor.

8. The display device according to claim 5, wherein Channel lengths of the first sub-transistor, the second sub-transistor, and the third sub-transistor are smaller than a channel length of at least one of the remaining transistors.

9. The display device according to claim 5, wherein: The first sub-transistor, the second sub-transistor, and the third sub-transistor share the gate electrode. The gate electrode includes: a first gate region having a first width corresponding to a channel length of the first sub-transistor; a second gate region having a second width corresponding to a channel length of the second sub-transistor; and The third gate region has a third width corresponding to the channel length of the third sub-transistor.

10. The display device according to claim 9, wherein The gate electrode further includes a fourth gate region connecting the first gate region, the second gate region, and the third gate region.

11. The display device according to claim 10, wherein: The first sub-transistor and the second sub-transistor share a single first region, The first sub-transistor and the third sub-transistor share a single second region.

12. The display device according to claim 10, wherein: The gate electrode includes a portion shaped like a capital letter "T".

13. The display device according to claim 1, wherein The first transistor further includes: The third sub-transistor is connected in series with the first sub-transistor and the second sub-transistor.

14. The display device according to claim 13, wherein: Channel widths of the first sub-transistor and the second sub-transistor are narrower than a channel width of the third sub-transistor.

15. The display device according to claim 14, wherein Channel lengths of the first sub-transistor, the second sub-transistor, and the third sub-transistor are smaller than a channel length of at least one of the remaining transistors.

16. The display device according to claim 14, wherein: The first sub-transistor, the second sub-transistor, and the third sub-transistor share the gate electrode. The gate electrode includes: a first gate region overlapping with a channel region of the first sub-transistor and a channel region of the second sub-transistor; and The second gate region overlaps with the channel region of the third sub-transistor.

17. The display device according to claim 16, wherein: The second gate region is connected to the first gate region.

18. The display device according to claim 1, wherein The first transistor includes a first sub-transistor and a second sub-transistor connected in parallel to each other, The second sub-transistor further includes a bottom gate electrode away from the gate electrode, the first insulating film, and the active layer pattern. A channel width of the first sub-transistor is narrower than a channel width of the second sub-transistor.

19. A display device comprising: a pixel portion including a plurality of pixels; a scanning driving portion, comprising a plurality of driving stages and supplying a scanning signal to the pixel portion; as well as The light emission control driving unit is composed of a plurality of driving stages and supplies a light emission control signal to the pixel unit. The first transistor among the plurality of transistors included in at least one of the driving stages of the scanning driving unit and the driving stages of the light emitting control driving unit includes: an active layer pattern, comprising a channel region disposed on the buffer layer to form a channel, and a first region and a second region disposed on both sides of the channel region; and a gate electrode spaced apart from the active layer pattern with a first insulating film interposed therebetween and overlapping the channel region; The first transistor includes a first sub-transistor and a second sub-transistor connected in parallel to each other, The channel width of the first sub-transistor is narrower than the channel width of the second sub-transistor, and the channel length of the first sub-transistor is shorter than the channel length of the second sub-transistor, The channel region includes: a first edge region and a second edge region, which are located on two side surfaces based on the channel width; and a body region, which is located between the first edge region and the second edge region. The thickness of the first insulating film in a region overlapping with the body region is thicker than the thickness of the first insulating film in a region overlapping with the first edge region or the second edge region.

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