Apparatus and method for buffering data for transmission

Abstract

The invention relates to an apparatus for buffered transmission of data and a corresponding method. The apparatus comprises a central processing unit 200, a plurality of first buffer areas 510, 520, 530, one or more second buffer areas 820, 840, and a controller 600, wherein the controller 600 is arranged to determine a first buffer area 510, 520, 530 based on a descriptor list entry 1200 in response to a first signal 1000, to lock the determined first buffer area 510, 520, 530 for external access, to store an address 1400 of the determined first buffer area 510, 520, 530 in a parameter memory 610 of the controller 600, to copy first data 1500 from the determined first buffer area 510, 520, 530 into the second buffer area 820, and to mark the first data 1500 as valid or invalid after copying the first data 1500, the first signal 1000 initiating the transmission of the first data 1500 from the first buffer area 510, 520, 530 to the one or certain second buffer area 820, 840.

Description

TECHNICAL FIELD

[0001] The invention relates to an apparatus and a method for buffered transmission of data. The invention especially relates to the buffered transmission of data from a field bus to a local bus and vice versa by a modular field bus node. BACKGROUND

[0002] The transmission of data from a field bus to a local bus and vice versa by a modular field bus node can be carried out by a front-end station of the modular field bus node. The front-end station can have, for example, a field bus interface and a local bus interface and a central processing unit which coordinates or at least monitors the data transmission between the buses. SUMMARY

[0003] Within the framework of the invention, by having the validity check and the addressing of the data no longer carried out by the central processing unit but by a controller specifically set up for this task, the burden of the central processing unit, which arises through the data transmission between the buses, can be avoided or at least reduced.

[0004] The apparatus according to the invention comprises a central processing unit, a plurality of first buffer areas, one or more second buffer areas and a controller, wherein the controller is set up to, in response to a first signal, determine a first buffer area on the basis of a descriptor list entry, lock the determined first buffer area for external access, store the address of the determined first buffer area in a parameter memory of the controller, copy the first data from the determined first buffer area into a second buffer area and mark the first data as valid or invalid after copying, the first signal initiating the transmission of the first data from the first buffer area to the one or the second buffer area.

[0005] Herein, the concept of "central processing unit" used in the description and claims especially refers to an electronic circuit which is set up to process data on the basis of a command sequence. Furthermore, the concept of "controller" used in the description and claims especially refers to a direct memory access controller ("DMA", "EDMA" and the like). Furthermore, the concept of "buffer area" used in the description and claims especially refers to a data area for temporary storage of data (in an electronic memory). Furthermore, the concept of "descriptor list" used in the description and claims especially refers to data from which it can be derived which data is located in which buffer area. Furthermore, the concept of "address" is to be understood broadly and is to include every kind of unambiguous identification, for example a buffer area number.

[0006] The determined first buffer area can contain the most recent valid data.

[0007] The controller can be arranged to, prior to locking the determined first buffer, temporarily store one or more descriptor list entries in a memory and to determine the first buffer on the basis of the temporarily stored descriptor list entries.

[0008] The controller can be arranged to prepend a message header to the copied first data or to append the message header to the copied first data.

[0009] The controller can be arranged to, in response to a second signal, copy the second data from the second buffer into a first buffer, to check, after copying the second data, whether the second data is marked as valid or invalid on the side of the sender, and to update one or more descriptor list entries from which it can be derived which first buffer contains the most recent valid data, the second signal initiating the transfer of the second data from the or a second buffer to the first buffer.

[0010] The controller can be arranged to overwrite invalid and / or outdated data in the first buffer when copying the second data.

[0011] The controller can be configured as a "Direct Memory Access, DMA, controller" or as an "Enhanced Direct Memory Access, EDMA, controller".

[0012] The method according to the invention comprises receiving, by a controller, a first signal, the first signal initiating the transfer of first data from a first buffer to a second buffer, the method further comprising determining, by the controller, a first buffer on the basis of a descriptor list entry, including locking, by the controller, the determined first buffer for external access, including storing, by the controller, the address of the determined first buffer in a parameter memory of the controller, including copying, by the controller, the first data from the determined first buffer into the second buffer, and including marking the first data copied into the second buffer as valid or invalid.

[0013] The method can further comprise receiving, by the controller, a second signal, the second signal initiating the transfer of second data from the second buffer to the first buffer, including copying, by the controller, the second data from the second buffer into a first buffer, including checking, by the controller, whether the second data is marked as valid or invalid on the side of the sender, and including generating one or more descriptor list entries from which it can be derived which first buffer contains the most recent valid data.

[0014] The copy of the data can serve the transfer of the data between the field bus and the local bus.

[0015] In this context, the concept of "local bus" used in the present description refers, in particular, to a bus via which the E / A modules arranged next to the head station are connected to one another or to the head station (directly). Furthermore, the concept of "head station" used in the present description refers to a component of a modular field bus node, the task of which is to make the data and / or services of the E / A modules arranged next to the head station available to other field bus user devices, such as a superordinate control unit, via a bus interface and via a field bus connected to the bus interface.

[0016] Furthermore, the concept of "E / A module" used in the present description refers, in particular, to a device which can be arranged next to another E / A module or head station or which is arranged in operation, the device connecting one or more field devices to the head station and, in certain cases, to a superordinate control unit (via the head station). Here, the concept of "field device" used in the present description refers, in particular, to a sensor and / or an actuator which is (for example, is connected to) the E / A module (in signal technology).

[0017] It is clear here that the steps carried out by the device can be regarded as possible steps of a corresponding method which can be implemented under the application of the device, and vice versa. BRIEF DESCRIPTION OF DRAWINGS

[0018] The application will be explained in detail below by means of examples, with reference to the drawings, in which:

[0019] Figure 1 a field bus system is shown;

[0020] Figure 2 a field bus system is shown Figure 1 a modular field bus node of the field bus system shown, and a field bus device connected to the field bus node;

[0021] Figure 3 a block diagram of a device according to the application is shown, the device being constructed exemplarily as Figure 2 a head station of the modular field bus node shown;

[0022] Figure 4a a flow chart illustrating the application of a device according to the application is shown;

[0023] Figure 4b further steps illustrating the application of a device according to the application are shown;

[0024] Figure 5a illustrate Figure 3 a possible modification of the example illustrated; and

[0025] Figure 5b illustrate Figure 5a a further possible modification of the example illustrated.

[0026] Herein, identical or functionally similar elements are denoted by the same reference signs throughout the figures.

[0027] 1. An apparatus (110) for buffered transmission of data, comprising:

[0028] a central processing unit (200);

[0029] a plurality of first buffers (510, 520, 530);

[0030] one or more second buffers (820, 840); and

[0031] a controller (600), wherein the controller (600) is arranged to, in response to a first signal (1000) initiating a transmission of first data (1500) from the first buffers (510, 520, 530) to the one or a certain second buffer (820, 840):

[0032] determine a first buffer (510, 520, 530) based on a descriptor list entry (1200);

[0033] lock the determined first buffer (510, 520, 530) for external access;

[0034] store an address (1400) of the determined first buffer (510, 520, 530) in a parameter memory (610) of the controller (600);

[0035] copy the first data (1500) from the determined first buffer (510, 520, 530) into the second buffer (820); and

[0036] mark the first data (1500) as valid or invalid after copying the first data (1500).

[0037] 2. The apparatus (110) according to embodiment 1,

[0038] wherein the determined first buffer (510, 520, 530) contains the most recent valid data.

[0039] 3. The apparatus (110) according to embodiment 1,

[0040] wherein the controller (600) is arranged to, prior to locking the determined first buffer (510, 520, 530), temporarily store one or more descriptor list entries (1200) in the memory (300) and to determine the first buffer (510, 520, 530) based on the temporarily stored descriptor list entries (1200).

[0041] 4. The apparatus (110) according to embodiment 2,

[0042] wherein the controller (600) is arranged to, prior to locking the determined first buffer (510, 520, 530), temporarily store one or more descriptor list entries in the memory (300) and to determine the first buffer (510, 520, 530) based on the temporarily stored descriptor list entries.

[0043] 5. The apparatus (110) according to embodiment 1,

[0044] wherein the controller (600) is arranged to prepend a message header (1100) to the copied first data (1500) or to append the message header (1100) to the copied first data (1500).

[0045] 6. The apparatus (110) according to embodiment 4,

[0046] wherein the controller (600) is arranged to prepend a message header (1100) to the copied first data (1500) or to append the message header (1100) to the copied first data (1500).

[0047] 7. The apparatus (110) according to embodiment 1,

[0048] wherein the controller (600) is arranged to, in response to a second signal (2000) initiating the transfer of second data (2100) from the one or the second buffer (840) to the first buffer (510, 520, 530):

[0049] copy the second data (2100) from the second buffer (840) into the first buffer (510, 520, 530);

[0050] after copying the second data (2100), check whether the second data (2100) is marked as valid or invalid on the sending side; and

[0051] updating one or more descriptor list entries from which it can be derived which first buffer (510, 520, 530) contains the latest valid data.

[0052] 8. The apparatus (110) according to embodiment 6,

[0053] wherein the controller (600) is arranged to, in response to a second signal (2000) initiating the transfer of second data (2100) from the one or certain second buffer to the first buffer (510, 520, 530):

[0054] copying the second data (2100) from the second buffer into the first buffer (510, 520, 530);

[0055] after copying the second data (2100), checking whether the second data (2100) is marked as valid or invalid at the side of the sender; and

[0056] updating one or more descriptor list entries from which it can be derived which first buffer (510, 520, 530) contains the latest valid data.

[0057] 9. The apparatus (110) according to embodiment 7,

[0058] wherein the controller (600) is arranged to, when copying the second data (2100), overwrite invalid and / or outdated data in the first buffer (510, 520, 530).

[0059] 10. The apparatus (110) according to any one of embodiments 1 to 9, wherein the controller (600) is configured as a "Direct Memory Access (DMA) controller" or as an "Enhanced Direct Memory Access (EDMA) controller".

[0060] 11. A method for buffered transmission of data (1500, 2100), comprising:

[0061] receiving (4000), by a controller (600), a first signal (1000) initiating the transfer of first data (1500) from a first buffer (510, 520, 530) to a second buffer (820, 840);

[0062] determining (4100), by the controller (600), a first buffer (510, 520, 530) based on a descriptor list entry (1200);

[0063] determining (4300), by the controller (600), an address (1400) of the first buffer (510, 520, 530) which has been determined by the controller (600) for the external access lock (4200);

[0064] storing (4300), by the controller (600), the address (1400) of the first buffer (510, 520, 530) which has been determined in a parameter memory (610) of the controller (600);

[0065] copying (4400), by the controller (600), the first data (1500) from the first buffer (510, 520, 530) which has been determined into the second buffer (820); and

[0066] marking (4500) the first data (1500) copied into the second buffer (820) as valid or invalid.

[0067] 12. The method according to embodiment 11, further comprising:

[0068] receiving (4600), by the controller (600), a second signal (2000) which initiates a transfer of second data (2100) from the second buffer (820, 840) to the first buffer (510, 520, 530);

[0069] copying (4700), by the controller (600), the second data (2100) from the second buffer (840) into the first buffer (510, 520, 530);

[0070] checking (4800), by the controller (600), whether the second data (2100) is marked as valid or invalid on the side of the sender; and

[0071] generating (4900) one or more descriptor list entries (3000) from which it can be derived which first buffer (510, 520, 530) contains the latest valid data.

[0072] 13. The method according to embodiment 11 or 12, wherein the copying (4700) of the data (1500, 2100) serves a transfer between a field bus (30) and a local bus (180). DETAILED DESCRIPTION

[0073] Figure 1A block diagram of a field bus system 10 is shown. The field bus system 10 comprises a superordinate control unit 20 by means of which a plurality of modular field bus nodes 100 can be connected via a field bus 30. The superordinate control unit 20 can be used both for monitoring and for regulating devices (not shown) controlled via the field bus system 10.

[0074] When the superordinate control unit 20 monitors the devices, the superordinate control unit 20 can receive input process data from the field bus nodes 100 periodically or aperiodically, which describe the state of the devices and generate fault signals or alarm signals when the state of the devices deviates (in principle) from the desired / allowed state or state range. When the superordinate control unit 20 (not only monitors, but also) regulates the devices, the superordinate control unit 20 can receive input process data from the field bus nodes 100 periodically or aperiodically and determine output process data transmitted to the field bus nodes 100 taking into account the input process data.

[0075] Figure 2 An exemplary modular field bus node 100 is shown, which consists of a front-end station 110 and two input / output modules 120, 130 (E / A modules) arranged next to the front-end station 110, to which input / output modules 120, 130 field devices 140, 150, 160, 170, such as sensors and actuators, are connected. During operation, the E / A modules 120, 130 read in sensor signals via the inputs and generate input process data from the sensor signals, which are transmitted to the front-end station 110 via the local bus 180. The front-end station 110 can process the input process data locally and / or forward them (in altered form in certain cases) to the superordinate control unit 20. The superordinate control unit 20 can then generate output process data taking into account the input process data (or when processed locally by the front-end station 110).

[0076] The output process data generated by the superior control unit 20 can then be transmitted to the (same or) one (other) front-end station 110 via the field bus 30. The output process data transmitted to the front-end station 110 (or generated by the front-end station 110) is then forwarded / transmitted (in altered form in certain cases) to the E / A modules 120, 130. The E / A modules 120, 130 receive the output process data and issue control signals corresponding to the output process data to the outputs connected to the actuators. The communication of data between the components of the field bus system 10, the mapping of the sensor signals to input process data and the mapping of the control data to output process data can be adapted to different use scenarios here by the configuration of the field bus node 100.

[0077] Figure 3 A block diagram illustrating a possible configuration of the front-end station 110 is shown. The front-end station 110 comprises a central processing unit 200, three first buffers 510, 520, 530, a second send buffer 820, which can be designed as a "double buffer FIFO", for example, and a controller 600. In order to initiate the transmission of data via the local bus 180, the bus interface 800 transmits a trigger signal to the controller 600. In response to the trigger signal, the controller 600 determines the first buffer 520 on the basis of an entry in the descriptor list 420 and locks the first buffer 520 for external access, for example by writing the buffer number into a buffer lock register 410.

[0078] In addition, the controller 600 stores the address of the determined first buffer 520 in a parameter memory 610 of the controller 600, copies the first data from the determined first buffer 520 into the second send buffer 820 and marks the first data as valid or invalid after copying it, for example by writing a "valid" bit into a register 830 of the bus interface 800. When the device 110 is intended to be used in a situation in which bidirectional communication is to be implemented, the bus interface 800 in the vicinity of the send buffer 820 (which can be designed as a separate buffer, a "double FIFO", a "triple buffer" or the like) can also have a receive buffer 840 (which can likewise be designed as a separate buffer, a "double FIFO", a "triple buffer" or the like).

[0079] Figure 4a A flow chart illustrating the operation of the front-end station 110 is shown. Figure 3The steps of the data transfer in the illustrated example. The data transfer starts in step 4000, in which a first signal is received by the controller 600, which initiates the transfer of first data from the first buffer 510, 520, 530 to the send buffer 820. In step 4100, the first buffer 520 is determined by the controller 600 based on the entries in the descriptor list 420. In step 4200, the determined first buffer 520 is locked for external access by the controller 600, e.g. by writing the buffer number into the "buffer lock register". In step 4300, the address of the determined first buffer 520 is stored in the parameter memory 610 of the controller 600. Subsequently, in step 4400, the first data is copied from the determined first buffer 520 into the send buffer 820, and in step 4500 the first data copied into the second buffer 820 is marked as valid or invalid.

[0080] Figure 4b The reverse data transfer is illustrated. The reverse data transfer starts in step 4600, in which a second signal is received by the controller 600, which initiates the transfer of second data from the receive buffer 840 to the first buffer 510, 520, 530. In response to the second signal, in step 4700 the second data is copied from the receive buffer 840 to the first buffer 520. Subsequently, in step 4800 it is checked whether the second data is marked as valid or invalid on the sending side. Furthermore, in step 4900 one or more entries in the descriptor list 420 are generated from which it can be derived which of the first buffers 510, 520, 530 contains the latest valid data.

[0081] Figure 5a Data transfer from the front-end station 110 to the local bus 180 is illustrated, which is performed by means of the improved front-end station 110 compared to Figure 3 which, in addition to Figure 3The components shown in the middle additionally comprise a memory 300 (for storing and in particular for staging data 310) and a bus interface 800. The bus interface 800 (which can be implemented for example as a "field programmable gate array" FPGA) sends a trigger signal 1000 (which can be implemented entirely in hardware) to the controller 600 (which can be implemented for example as a DMA controller or an EDMA controller) at a fixed point in time and thereby initiates the transfer of the process data. If necessary, any data 1100 (for example a message header) can be copied from the memory 300 before the process data 1500 or appended to the process data 1500.

[0082] The controller 600 can copy the entry 1200 in the descriptor list 420 which is assigned to the first buffer 520 into the memory 300 (which can be constructed for example as a "random access memory" RAM) (in order to avoid data inconsistencies) and can protect the first buffer 520 to be read from external access by copying the buffer number 1300 of the memory 300 into the buffer lock register 410. The controller 600 can subsequently copy the buffer address 1400 of the memory 300 into the source address area of the memory 610 (parameter random access memory) and transfer the process data 1500 from the buffer 520 to the send buffer 820. For the case of a multi-host system or a runtime system with multiple tasks, the described method can be applied to multiple instances of the first buffers 510, 520, 530.

[0083] When the process data 1500 written into the send buffer 820 is valid, the controller 600 can write a "valid" bit 1600 into the register 300 of the bus interface 800. This can be achieved for example by transferring a constant mask from the memory 300 to the register 830.

[0084] Figure 5b Data transfer from the local bus 180 to the front-end station 110 is illustrated. Here, the bus interface 800 sends the trigger signal 2000 to the controller 600 at a fixed point in time and initiates data transfer, in which the process data 2100 is transferred from the receive buffer 840 to one of the first buffers 510, 520, 530. For the case of a multi-host system or a runtime system with multiple tasks, the described method can be applied to multiple instances of the first buffers 510, 520, 530.

[0085] To inform the reading process that it has ended, the controller 600 can write a "finished" bit 2200. This can again be achieved by transferring a constant mask from the memory 300 to the register 830. Furthermore, a "valid" bit belonging to the process data 2100 can be copied into the memory 610 of the controller 600 and evaluated. In the case of invalid process data 2100, for example, a zero transfer can be carried out, in which the process data 2100 is not copied and the transfer ends.

[0086] When the process data 2100 is valid, a mask triggering the data transfer can be copied from the memory 300 into a register of the controller 600. Subsequently, the addresses and numbers 3000 of the first buffer 510, 520, 530 in which the process data 2100 is located can be copied from the memory 300 into the descriptor list 420. From this point in time, the process data 2100 can be transferred to other field bus user devices via the local bus 30. For the next data transfer, a new buffer address 3100 can subsequently be written into the memory 610.

[0087] The data transfer can thus completely bypass the central processing unit 200 and be carried out by the controller 600, which, in addition to copy operations, carries out a validity check and is able to configure itself. Here, the controller 600 can lock the buffer 510, 520, 530 used, control the send and receive buffers 820, 840, check the validity of the data 1500, 2100 and select (configure itself) the next buffer 510, 520, 530 for the subsequent data transfer. By this, the calculation time of the central processing unit 200 is no longer required in the scope of the data transfer, the controller 600 can start the processing chain of the data directly upon receipt of the trigger signal 1000, 2000 and the data transfer can be implemented in hardware independently of software (by which transmission jitter is reduced).

[0088] List of reference signs

[0089] 10 field bus system

[0090] 20 control unit

[0091] 30 field bus

[0092] 40 computer

[0093] 100 field bus node

[0094] 110 front-end station

[0095] 120 E / A module

[0096] 130 E / A module

[0097] 140 field device

[0098] 150 field device

[0099] 160 field device

[0100] 170 field device

[0101] 180 local bus

[0102] 200 central processing unit

[0103] 300 memory

[0104] 310 data

[0105] 410 buffer "lock" register

[0106] 420 descriptor list

[0107] 510 buffer

[0108] 520 buffer

[0109] 530 buffer

[0110] 600 controller

[0111] 610 memory

[0112] 700 interface

[0113] 800 bus interface

[0114] 810 RDC

[0115] 820 send buffer

[0116] 830 register

[0117] 840 receive buffer

[0118] 1000 (trigger) signal

[0119] 1100 data / message header

[0120] 1200 descriptor list entry

[0121] 1300 buffer number

[0122] 1400 buffer address

[0123] 1500 (process) data

[0124] 1600 "valid" bit

[0125] 2000 (trigger) signal

[0126] 2100 (process) data

[0127] 2200 "done" bit

[0128] 2300 "valid" bit

[0129] 2400 trigger

[0130] 3000 descriptor list entry

[0131] 3100 buffer address

[0132] 4000 process step

[0133] 4200 process step

[0134] 4300 process step

[0135] 4400 process step

[0136] 4500 process step

[0137] 4600 process step

[0138] 4700 process step

[0139] 4800 process step

[0140] 4900 process step.

Claims

1. A device (110) for buffered data transmission, comprising: Central processing unit (200); Multiple first buffers (510, 520, 530); One or more second buffers; and A controller (600), wherein the controller (600) is configured to respond to a first signal (1000) in response to initiating the transmission of first data (1500) from the first buffer (510, 520, 530) to one or more of the second buffers: The first buffer (510, 520, 530) is determined based on the descriptor list entries; Lock the first buffer (510, 520, 530) for external access; The addresses (1400) of the first buffers (510, 520, 530) that have been determined are stored in the parameter memory (610) of the controller (600); Copy the first data (1500) from the determined first buffer (510, 520, 530) to the second buffer; and After copying the first data (1500), mark the first data as valid or invalid.

2. The apparatus (110) according to claim 1, The first buffer (510, 520, 530) that has been identified contains the latest valid data.

3. The apparatus (110) according to claim 1, The controller (600) is configured to temporarily store one or more descriptor list entries in memory (300) before locking the determined first buffer (510, 520, 530), and to determine the first buffer (510, 520, 530) based on the temporarily stored descriptor list entries.

4. The apparatus (110) according to claim 2, The controller (600) is configured to temporarily store one or more descriptor list entries in memory (300) before locking the determined first buffer (510, 520, 530), and to determine the first buffer (510, 520, 530) based on the temporarily stored descriptor list entries.

5. The apparatus (110) according to claim 1, The controller (600) is configured to either prepend a message header (1100) to the copied first data (1500) or append the message header (1100) to the copied first data (1500).

6. The apparatus (110) according to claim 4, The controller (600) is configured to either prepend a message header (1100) to the copied first data (1500) or append the message header (1100) to the copied first data (1500).

7. The apparatus (110) according to claim 1, The controller (600) is configured to respond to a second signal (2000) in response to initiating the transmission of second data (2100) from one of the second buffers or from one of the second buffers to the first buffer (510, 520, 530): Copy the second data (2100) from the second buffer to the first buffer (510, 520, 530); After copying the second data (2100), check whether the second data (2100) is marked as valid or invalid on the sending side; and Update one or more descriptor list entries, from which it can be determined which first buffer (510, 520, 530) contains the latest valid data.

8. The apparatus (110) according to claim 6, The controller (600) is configured to respond to a second signal (2000) in response to initiating the transmission of second data (2100) from one of the second buffers or from one of the second buffers to the first buffer (510, 520, 530): Copy the second data (2100) from the second buffer to the first buffer (510, 520, 530); After copying the second data (2100), check whether the second data (2100) is marked as valid or invalid on the sending side; and Update one or more descriptor list entries, from which it can be determined which first buffer (510, 520, 530) contains the latest valid data.

9. The apparatus (110) according to claim 7, The controller (600) is configured to overwrite invalid and / or outdated data in the first buffer (510, 520, 530) when copying the second data (2100).

10. The apparatus (110) according to any one of claims 1 to 9, wherein the controller (600) is configured as a "direct memory access (DMA) controller" or an "enhanced direct memory access (EDMA) controller".

11. A method for buffered data transmission (1500, 2100), comprising: The controller (600) receives a first signal (1000), which initiates the transmission of first data (1500) from the first buffer (510, 520, 530) to the second buffer; The controller (600) determines (4100) the first buffer (510, 520, 530) based on the descriptor list entries; The first buffer (510, 520, 530) has been determined by the controller (600) for external access locking (4200); The controller (600) stores (4300) the determined addresses (1400) of the first buffer (510, 520, 530) in the parameter memory (610) of the controller (600); The controller (600) copies the first data (1500) from the determined first buffer (510, 520, 530) to the second buffer; and The first data (1500) copied into the second buffer is marked (4500) as valid or invalid.

12. The method of claim 11, further comprising: The controller (600) receives a second signal (2000), which initiates the transmission of second data (2100) from the second buffer to the first buffer (510, 520, 530). The controller (600) copies the second data (2100) from the second buffer to the first buffer (510, 520, 530); The controller (600) verifies (4800) whether the second data (2100) is marked as valid or invalid on the sending side; and Generate (4900) one or more descriptor list entries, from which it can be determined which first buffer (510, 520, 530) contains the latest valid data.

13. The method according to claim 11 or 12, wherein the copying of the data (1500, 2100) serves a transfer between the fieldbus (30) and the local bus (180).

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