Control circuit and sensor device

Abstract

The present invention suppresses the current from winding back from the signal line to the power line when the power is disconnected, thereby preventing the output of the intermediate potential. The present invention is a control circuit (11), which receives the power supply voltage from the power line (L11) and outputs the output signal to the signal line (L12), and comprises: a load (R11) arranged between the power line and the signal line; a first transistor (P11) arranged between the load and the signal line; a second transistor (P12) arranged between the well of the first transistor and the power line; and a gate control circuit (15), which connects the gate terminal of the first transistor and the gate terminal of the second transistor to the signal line when the power is disconnected, thereby cutting off the first transistor and the second transistor.

Description

Technical Field

[0001] The invention relates to a control circuit and a sensor device. Background Art

[0002] In the past, as a control circuit that receives power supply voltage to operate, there is a known control circuit that uses the reverse connection of the power supply to protect the circuit (for example, refer to Patent Document 1). The control circuit described in Patent Document 1 is provided with a first transistor (PMOS transistor) between the power supply line and the signal line, and a second transistor (PMOS transistor) for well control is provided between the power supply line and the well (body) of the first transistor. The gate terminals of the first transistor and the second transistor are connected to the ground. When the power supply is reversely connected, the first transistor and the second transistor are cut off, thereby preventing the current from the ground to the power supply line.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2016-192838 Summary of the invention

[0006] Problem that the invention aims to solve

[0007] However, in the control circuit described in Patent Document 1, when the power supply is disconnected, the gates of the first transistor and the second transistor become the ground potential, thereby turning on the first transistor and the second transistor. In addition, since the power supply line becomes the ground potential, the first transistor and the second transistor are turned on when the signal potential is High, and there is a problem that the current flows back from the signal line to the power supply line and outputs an intermediate potential.

[0008] The present invention solves the above-mentioned problems and has an object to provide a control circuit and a sensor device that can suppress the current from looping back from a signal line to a power line when the power supply is disconnected and prevent the output of an intermediate potential.

[0009] Technical means of solving problems

[0010] A control circuit in one form of the present invention receives a power supply voltage from a power supply line and outputs an output signal to a signal line, and is characterized in that it comprises: a load, which is arranged between the power supply line and the signal line; a first transistor, which is arranged between the load and the signal line or between the power supply line and the load; a second transistor, which is arranged between a well of the first transistor and the power supply line; and a gate control circuit, which connects the gate terminal of the first transistor and the gate terminal of the second transistor to the signal line when the power supply is disconnected, thereby cutting off the first transistor and the second transistor.

[0011] Effects of the Invention

[0012] According to the present invention, by cutting off the first transistor and the second transistor when the power supply is disconnected, it is possible to suppress the current from the signal line to the power supply line and prevent the output of the intermediate potential. More features related to the present invention will be clarified based on the description and drawings of this specification. In addition, the following description of the embodiments will clarify the problems, structures and effects other than the above. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is a circuit diagram of the sensor device according to the first embodiment.

[0014] Figure 2 This is an explanatory diagram of the normal operation of the first embodiment.

[0015] Figure 3 This is an explanatory diagram of the first embodiment when the power supply is disconnected.

[0016] Figure 4 This is a circuit diagram of a sensor device according to a second embodiment.

[0017] Figure 5 This is a circuit diagram of a sensor device according to a third embodiment.

[0018] Figure 6 This is a circuit diagram of a sensor device according to a fourth embodiment.

[0019] Figure 7 This is a circuit diagram of a sensor device according to a fifth embodiment.

[0020] Figure 8 This is a circuit diagram of a sensor device according to a sixth embodiment.

[0021] Fig. 9 This is a circuit diagram of a sensor device according to a seventh embodiment.

[0022] Fig.10 This is a circuit diagram of a sensor device according to an eighth embodiment. DETAILED DESCRIPTION

[0023] [First embodiment]

[0024] Below, reference Figures 1 to 3 , a sensor device according to a first embodiment is described.

[0025] Figure 1 2 is a circuit diagram of the sensor device according to the first embodiment. Note that, as the sensor device, an air flow sensor can be cited, for example, but the sensor device is not particularly limited as long as the electrical characteristics thereof change according to a physical quantity.

[0026] like Figure 1As shown, the sensor device 10 is connected to a host device such as an ECU (not shown) via a power terminal 12 and a signal terminal 13, and includes an LSI internal circuit (detection circuit) 14 on which a sensor element is mounted and a control circuit 11 that processes a detection signal from the sensor element. The LSI internal circuit 14 is connected to a power line L11 connected to the power terminal 12, and receives a power supply voltage from the host device through the power line L11 to operate the sensor element, etc. In addition, the LSI internal circuit 14 performs various processes on the physical quantity detected by the sensor element, and outputs a control signal corresponding to the physical quantity to the control circuit 11.

[0027] The control circuit 11 receives a power supply voltage from a host device via a power supply line L11 connected to a power supply terminal 12, and outputs an output signal corresponding to a control signal of an LSI internal circuit 14 to the host device via a signal line L12 connected to a signal terminal 13. In the control circuit 11, a first NMOS transistor N11 for circuit driving is provided between the signal line L12 and a ground G11. In addition, the control circuit 11 is provided with a load R11 for current adjustment connected to the power supply line L11, a first PMOS transistor (first transistor) P11 for current interruption provided between the load R11 and the signal line L12, and a second PMOS transistor (second transistor) P12 for well control provided between a well of the first PMOS transistor P11 and the power supply line L11.

[0028] Furthermore, the control circuit 11 is provided with a gate control circuit 15 for cutting off the first PMOS transistor P11 and the second PMOS transistor P12 when the power supply is disconnected. The gate control circuit 15 is provided with a second NMOS transistor N12 and a third PMOS transistor P13. The second NMOS transistor N12 is provided between a connection point 17 of the gate terminal of the first PMOS transistor P11 and the gate terminal of the second PMOS transistor P12 and the ground G12. The third PMOS transistor P13 is provided between a connection point 17 of the gate terminal of the first PMOS transistor P11 and the gate terminal of the second PMOS transistor P12 and the signal line L12.

[0029] In more detail, the drain terminal of the first NMOS transistor N11 for circuit driving is connected to the signal line L12, and the source terminal of the first NMOS transistor N11 is connected to the ground G11. The LSI internal circuit 14 is connected to the gate terminal of the first NMOS transistor N11, and the first NMOS transistor N11 is driven by receiving a control signal from the LSI internal circuit 14. The first NMOS transistor N11 is driven on / off according to the control signal from the LSI internal circuit 14, and generates an output signal corresponding to the physical quantity detected by the sensor element in the LSI internal circuit 14.

[0030] One input / output terminal of the first PMOS transistor P11 for current interruption is connected to the load R11, and the other input / output terminal is connected to the signal line L12. The first PMOS transistor P11 is used to cut off the current path from the signal line L12 to the power line L11. One input / output terminal of the second PMOS transistor P12 for well control is connected to the power line L11, and the other input / output terminal is connected to the well of the first PMOS transistor P11 to the third PMOS transistor P13. The second PMOS transistor P12 fixes the well potential of the first PMOS transistor P11 to the third PMOS transistor P13 to a constant value.

[0031] The drain terminal of the second NMOS transistor N12 of the gate control circuit 15 is connected to the gate terminals of the first PMOS transistor P11 and the second PMOS transistor P12, and the source terminal is connected to its own well and the ground G12. The gate terminal of the second NMOS transistor N12 is connected to the power supply line L11. In normal operation when the gate potential of the second NMOS transistor N12 is the power supply potential, the second NMOS transistor N12 is turned on. As a result, the gate terminals of the first PMOS transistor P11 and the second PMOS transistor P12 are connected to the ground G12, and the first PMOS transistor P11 and the second PMOS transistor P12 are turned on.

[0032] One input / output terminal of the third PMOS transistor P13 of the gate control circuit 15 is connected to the gate terminals of the first PMOS transistor P11 and the second PMOS transistor P12, and the other input / output terminal is connected to the signal line L12. The gate terminal of the third PMOS transistor P13 is connected to the power line L11. When the power supply is disconnected and the gate potential of the third PMOS transistor P13 is the ground potential, the third PMOS transistor P13 is turned on. As a result, the gate terminals of the first PMOS transistor P11 and the second PMOS transistor P12 are connected to the signal line L12, and the first PMOS transistor P11 and the second PMOS transistor P12 are cut off.

[0033] Thus, in the sensor device 10 of the present embodiment, the gate control circuit 15 is used to cut off the first PMOS transistor P11 and the second PMOS transistor P12 when the power is cut off, so as to prevent the current from flowing back from the signal line L12 to the power line L11 when the power is cut off. The first PMOS transistor P11 is used to cut off the direct current path from the signal line L12 to the power line L11. The second PMOS transistor P12 is used to cut off the direct current from the signal line L12 through the parasitic diode D1 of the first PMOS transistor P11 and the parasitic diode D2 of the third PMOS transistor P13 (see FIG. Figure 3 ) to the power supply line L11. This prevents the output of the intermediate potential that may affect the LSI internal circuit 14.

[0034] Below, reference Figure 2 and Figure 3 , explaining the control circuit during normal operation and when the power is off. Figure 2 This is an explanatory diagram of the normal operation of the first embodiment. Figure 3 This is an explanatory diagram of the first embodiment when the power supply is disconnected.

[0035] like Figure 2 As shown, during normal operation, a power supply voltage is applied to the gate terminal of the second NMOS transistor N12 and the gate terminal of the third PMOS transistor P13 of the gate control circuit 15. The gate potential of the second NMOS transistor N12 becomes the power supply potential, so that the second NMOS transistor N12 is turned on, and the gate potential of the third PMOS transistor P13 becomes the power supply potential, so that the third PMOS transistor P13 is turned off. By turning on the second NMOS transistor N12 and turning off the third PMOS transistor P13, the gate terminals of the first PMOS transistor P11 and the second PMOS transistor P12 are connected to the ground G12.

[0036] The gate potential of the first PMOS transistor P11 and the second PMOS transistor P12 becomes the ground potential, and the well potential of the first PMOS transistor P11 and the second PMOS transistor P12 is fixed at the power supply potential, thereby maintaining the on state of the first PMOS transistor P11 and the second PMOS transistor P12. At this time, in the first PMOS transistor P11, one input-output terminal connected to the load R11 works as a source, and the other input-output terminal connected to the signal line L12 works as a drain. In addition, in the second PMOS transistor P12, one input-output terminal connected to the power supply line L11 works as a source, and the other input-output terminal connected to the well of each PMOS transistor P11-P13 works as a drain.

[0037] In addition, by turning on the second PMOS transistor P12, the well potential of the third PMOS transistor P13 is fixed to the power supply potential, thereby maintaining the cut-off state of the third PMOS transistor P13. As a result, the signal line L12 is not connected to the ground G12 via the third PMOS transistor P13 and the second NMOS transistor N12. In this way, during normal operation, the gate terminal of the first PMOS transistor P11 is connected to the ground G12, and the well potential of the first PMOS transistor P11 is set to the power supply potential, thereby maintaining the on state of the first PMOS transistor P11.

[0038] like Figure 3As shown, when the power supply is disconnected, the gate terminal of the second NMOS transistor N12 and the gate terminal of the third PMOS transistor P13 of the gate control circuit 15 are connected to the ground G13 via the load of the LSI internal circuit 14. The gate potential of the second NMOS transistor N12 becomes the ground potential to cut off the second NMOS transistor N12, and the gate potential of the third PMOS transistor P13 becomes the ground potential to turn on the third PMOS transistor P13. By cutting off the second NMOS transistor N12 and turning on the third PMOS transistor P13, the gate terminals of the first PMOS transistor P11 and the second PMOS transistor P12 are connected to the signal line L12.

[0039] The signal potential is usually pulled up, so the gate potentials of the first PMOS transistor P11 and the second PMOS transistor P12 become the signal potential through the third PMOS transistor P13.

[0040] In addition, the well potential of the first PMOS transistor P11 to the third PMOS transistor P13 is fixed at a potential lowered from the signal potential in accordance with the parasitic diode D1 of the first PMOS transistor P11. In this case, the threshold voltage of the first PMOS transistor P11 and the second PMOS transistor P12 is lowered, but the gate-source voltage of the first PMOS transistor P11 and the second PMOS transistor P12 is lower than the threshold voltage, so the first PMOS transistor P11 and the second PMOS transistor P12 are maintained in the cut-off state.

[0041] When the power supply is disconnected, the source-drain of a pair of input-output terminals of the first PMOS transistor P11 is switched from the normal operation, and the source-drain of a pair of input-output terminals of the second PMOS transistor P12 is switched from the normal operation. In the first PMOS transistor P11, one input-output terminal connected to the load R11 works as a drain, and the other input-output terminal connected to the signal line L12 works as a source. In addition, in the second PMOS transistor P12, one input-output terminal connected to the power supply line L11 works as a drain, and the other input-output terminal connected to the well of each PMOS transistor P11-P13 works as a source.

[0042] Thus, the first PMOS transistor P11 is maintained in the cutoff state, and the DC path of the current from the signal line L12 to the power line L11 is cut off. Although the first PMOS transistor P11 forms a current path due to the parasitic diode D1 shown by the dotted line, the second PMOS transistor P12 is maintained in the cutoff state, and the current path from the signal line L12 to the power line L11 through the parasitic diode D1 is cut off. Similarly, although the third PMOS transistor P13 also forms a current path due to the parasitic diode D2 shown by the dotted line, the current path from the signal line L12 to the power line L11 through the parasitic diode D2 is cut off by the second PMOS transistor P12.

[0043] The second PMOS transistor P12 controls the wells of the PMOS transistors P11-P13 and cuts off the current paths of the parasitic diode D1 of the first PMOS transistor P11 and the parasitic diode D2 of the third PMOS transistor P13. Therefore, it is not necessary to prepare separate transistors for the well control of the first PMOS transistor P11 and the third PMOS transistor P13 and for cutting off the current paths of the parasitic diodes D1 and D2. The wells of the PMOS transistors P11-P13 can be shared to reduce the chip area. Furthermore, in this embodiment, separate transistors can also be prepared for the well control of the first PMOS transistor P11 and the third PMOS transistor P13.

[0044] As described above, in the first embodiment, when the power supply is disconnected, the gate potential of the first PMOS transistor P11 and the second PMOS transistor P12 becomes the signal potential, and the well potential of the first PMOS transistor P11 and the second PMOS transistor P12 is fixed at a predetermined potential. The first PMOS transistor P11 is cut off, thereby cutting off the DC path from the signal line L12 to the power line L11. In addition, the second PMOS transistor P12 is cut off, thereby cutting off the current path from the signal line L12 to the power line L11 through the parasitic diode D1 of the first PMOS transistor P11 and the parasitic diode D2 of the third PMOS transistor P13. Therefore, the current from the signal line L12 to the power line L11 is suppressed from winding around, thereby preventing the output of the intermediate potential. By preventing the output of the intermediate potential, the damage of the LSI and the erroneous diagnosis of the output signal by the upper device can be suppressed.

[0045] [Second embodiment]

[0046] refer to Figure 4, the sensor device of the second embodiment is described. In the first embodiment, when the power is cut off, the well potential of each PMOS transistor is fixed at a potential that is lowered from the signal potential in accordance with the parasitic diode. Therefore, there is a situation where the threshold voltage drops and a leakage current is generated when the current is cut off. Therefore, the sensor device of the second embodiment is equipped with a fourth PMOS transistor for well control when the power is cut off. Here, the description of the same structure as the first embodiment will be omitted as much as possible. Figure 4 This is a circuit diagram of a sensor device according to a second embodiment.

[0047] like Figure 4 As shown, the sensor device 20 of the second embodiment is different from the first embodiment in that a fourth PMOS transistor P24 is provided for well control when the power is off. That is, in the control circuit 21, a load R21, a first NMOS transistor N21, a second NMOS transistor N22, and a first PMOS transistor P21 to a third PMOS transistor P23 are provided, as in the control circuit 11 of the first embodiment. In addition, in the control circuit 21, a fourth PMOS transistor P24 for well control when the power is off is provided between the connection point 28 of the well of the first PMOS transistor P21 and the well of the second PMOS transistor P22 and the signal line L22.

[0048] One input / output terminal of the fourth PMOS transistor P24 is connected to the wells of the PMOS transistors P21 to P24 , and the other input / output terminal is connected to the signal line L22 .

[0049] The gate terminal of the fourth PMOS transistor P24 is connected to the power supply line L21. In the fourth PMOS transistor P24, in normal operation, one input / output terminal connected to the well of each PMOS transistor P21-P24 works as a source, and the other input / output terminal connected to the signal line L22 works as a drain. When the power supply is disconnected, one input / output terminal connected to the well of each PMOS transistor P21-P24 works as a drain, and the other input / output terminal connected to the signal line L22 works as a source.

[0050] During normal operation, a power supply voltage is applied to the gate terminal of the fourth PMOS transistor P24, and the gate potential of the fourth PMOS transistor P24 becomes the power supply potential. In addition, by turning on the second PMOS transistor P22, the well potential of the fourth PMOS transistor P24 is fixed at the power supply potential, thereby maintaining the cutoff state of the fourth PMOS transistor P24. Therefore, in the control circuit 21 of the second embodiment, the operation is performed in the same manner as the control circuit 11 of the first embodiment, so the operation of the control circuit 21 is not adversely affected by the addition of the fourth PMOS transistor P24.

[0051] When the power supply is disconnected, the gate terminal of the fourth PMOS transistor P24 is connected to the ground G23 via the load of the LSI internal circuit 24. The gate potential of the fourth PMOS transistor P24 becomes the ground potential, and the well potential of the first PMOS transistor P21 to the third PMOS transistor P23 is fixed at the signal potential through the fourth PMOS transistor P24. As a result, the voltage drop of the parasitic diode of the first PMOS transistor P21 as in the first embodiment no longer exists, and the threshold voltages of the first PMOS transistor P21 and the second PMOS transistor P22 are increased, thereby reducing the leakage current when the current is cut off.

[0052] As described above, in the second embodiment, as in the first embodiment, the current looping from the signal line L22 to the power line L21 when the power is disconnected can be suppressed. In addition, when the power is disconnected, the current interruption effect of the first PMOS transistor P21 and the second PMOS transistor P22 can be improved by the fourth PMOS transistor P24.

[0053] [Third Embodiment]

[0054] refer to Figure 5 , the sensor device of the third embodiment is described. In the first embodiment, the first PMOS transistor is provided between the load and the signal line, so the gate-source voltage of the first PMOS transistor becomes small due to the load, and the chip area cannot be fully reduced. Therefore, the sensor device of the third embodiment is provided with the first PMOS transistor between the power line and the load. Here, the description of the same structure as the first embodiment will be omitted as much as possible. Figure 5 This is a circuit diagram of a sensor device according to a third embodiment.

[0055] like Figure 5 As shown, the difference between the sensor device 30 of the third embodiment and the first embodiment is that the positions of the first PMOS transistor P31 and the load R31 are swapped. That is, in the control circuit 31, as in the control circuit 11 of the first embodiment, a load R31, a first NMOS transistor N31, a second NMOS transistor N32, and a first PMOS transistor P31 to a third PMOS transistor P33 are provided. The first PMOS transistor P31 is provided between the power line L31 and the load R31, so during normal operation, the gate-source voltage of the first PMOS transistor P31 increases. Therefore, the ON resistance of the first PMOS transistor P31 can be reduced, thereby achieving a smaller chip area.

[0056] As described above, in the third embodiment, the current looping from the signal line L32 to the power line L31 when the power supply is disconnected can be suppressed as in the first embodiment. In addition, the chip area of ​​the first PMOS transistor P31 can be reduced.

[0057] [Fourth embodiment]

[0058] In the above embodiments, the second NMOS transistor is used as the first element of the gate control circuit and the third PMOS transistor is used as the second element, but the present invention is not limited to this configuration. The gate control circuit only needs to include a first element that connects the gate terminals of the first PMOS transistor and the second PMOS transistor to the ground during normal operation and a second element that connects the gate terminals of the first PMOS transistor and the second PMOS transistor to the signal line when the power is disconnected. For example, Figure 6 As shown, the first element of the gate control circuit is formed by a resistor.

[0059] refer to Figure 6 , a sensor device according to a fourth embodiment will be described. The sensor device according to the fourth embodiment uses a resistor as a first element of a gate control circuit and a PMOS transistor as a second element. Here, descriptions of the same configurations as those of the first embodiment will be omitted as much as possible. Figure 6 This is a circuit diagram of a sensor device according to a fourth embodiment.

[0060] like Figure 6 As shown, the sensor device 40 of the fourth embodiment is different from the first embodiment in that the second NMOS transistor N12 (refer to Figure 1 ) is replaced by a resistor R42. That is, in the control circuit 41, a load R41, a first NMOS transistor N41, and first to third PMOS transistors P41 to P43 are provided, as in the control circuit 11 of the first embodiment. The resistor R42 of the gate control circuit 45 is provided between the connection point 47 of the gate terminals of the first PMOS transistor P41 and the second PMOS transistor P42 and the ground G42.

[0061] In addition, the resistance value of the resistor R42 is set larger than the resistance value of the ON resistor of the third PMOS transistor P43.

[0062] During normal operation, a power supply voltage is applied to the gate terminal of the third PMOS transistor P43 of the gate control circuit 45. The gate potential of the third PMOS transistor P43 becomes the power supply potential and the third PMOS transistor P43 is cut off. Therefore, the gate terminals of the first PMOS transistor P41 and the second PMOS transistor P42 are connected to the ground G42 via the resistor R42. The gate potential of the first PMOS transistor P41 and the second PMOS transistor P42 becomes the ground potential, and the well potential of the first PMOS transistor P41 and the second PMOS transistor P42 is fixed at the power supply potential, thereby maintaining the on state of the first PMOS transistor P41 and the second PMOS transistor P42.

[0063] When the power supply is disconnected, the gate terminal of the third PMOS transistor P43 of the gate control circuit 45 is connected to the ground G43 via the load of the LSI internal circuit 44. The gate potential of the third PMOS transistor P43 becomes the ground potential, so that the third PMOS transistor P43 is turned on. Since the third PMOS transistor P43 is turned on and the resistance value of the resistor R42 is set high, the gate terminals of the first PMOS transistor P41 and the second PMOS transistor P42 are connected to the signal line L42. The gate potential of the first PMOS transistor P41 and the second PMOS transistor P42 becomes the signal potential, thereby maintaining the cut-off state of the first PMOS transistor P41 and the second PMOS transistor P42.

[0064] As described above, in the fourth embodiment, the current looping from the signal line L42 to the power line L41 when the power is off can be suppressed as in the first embodiment. In addition, the gate control circuit 45 can be formed by the resistor R42 and the third PMOS transistor P43.

[0065] [Fifth embodiment]

[0066] In addition, if Figure 7 As shown, the second element of the gate control circuit can also be formed by a resistor. Figure 7 , a sensor device according to a fifth embodiment will be described. The sensor device according to the fifth embodiment uses an NMOS transistor as a first element of a gate control circuit and a resistor as a second element. Here, descriptions of the same configurations as those of the first embodiment will be omitted as much as possible. Figure 7 This is a circuit diagram of a sensor device according to a fifth embodiment.

[0067] like Figure 7 As shown, the sensor device 50 of the fifth embodiment is different from the first embodiment in that the third PMOS transistor P13 (refer to Figure 1) is replaced by a resistor R52. That is, in the control circuit 51, a load R51, a first NMOS transistor N51, a second NMOS transistor N52, a first PMOS transistor P51, and a second PMOS transistor P52 are provided, as in the control circuit 11 of the first embodiment. The resistor R52 of the gate control circuit 55 is provided between the connection point 57 of the gate terminals of the first PMOS transistor P51 and the second PMOS transistor P52 and the signal line L52. In addition, the resistance value of the resistor R52 is set to be larger than the resistance value of the combined resistance of the load R51 and the ON resistance of the first PMOS transistor P51.

[0068] During normal operation, a power supply voltage is applied to the gate terminal of the second NMOS transistor N52 of the gate control circuit 55. The gate potential of the second NMOS transistor N52 becomes the power supply potential, so that the second NMOS transistor N52 is turned on. Since the resistance value of the resistor R52 is set to be relatively high, the gate terminals of the first PMOS transistor P51 and the second PMOS transistor P52 are connected to the ground G52 via the second NMOS transistor N52. The gate potential of the first PMOS transistor P51 and the second PMOS transistor P52 becomes the ground potential, and the well potential of the first PMOS transistor P51 and the second PMOS transistor P52 is fixed at the power supply potential, thereby maintaining the on state of the first PMOS transistor P51 and the second PMOS transistor P52.

[0069] When the power supply is disconnected, the gate terminal of the second NMOS transistor N52 of the gate control circuit 55 is connected to the ground G53 via the load of the LSI internal circuit 54. The gate potential of the second NMOS transistor N52 becomes the ground potential and the second NMOS transistor N52 is cut off. By cutting off the second NMOS transistor N52, the gate terminals of the first PMOS transistor P51 and the second PMOS transistor P52 are connected to the signal line L52 via the resistor R52. The gate potentials of the first PMOS transistor P51 and the second PMOS transistor P52 increase, thereby maintaining the cut-off state of the first PMOS transistor P51 and the second PMOS transistor P52.

[0070] As described above, in the fifth embodiment, the current looping from the signal line L52 to the power line L51 when the power is off can be suppressed as in the first embodiment. In addition, the gate control circuit 55 can be formed by the second NMOS transistor N52 and the resistor R52.

[0071] [Sixth embodiment]

[0072] In the second embodiment described above, the configuration in which the well is controlled by the second PMOS transistor and the fourth PMOS transistor is exemplified, but the present invention is not limited to this configuration. Figure 8 As shown in the figure, the second PMOS transistor that is turned on during normal operation is replaced with a resistor. Figure 8 Here, description of the sensor device according to the sixth embodiment will be omitted as much as possible for the same configuration as that of the second embodiment. Figure 8 This is a circuit diagram of a sensor device according to a sixth embodiment.

[0073] like Figure 8 As shown, the sensor device 60 of the sixth embodiment is different from the second embodiment in that the second PMOS transistor P22 for well control (refer to Figure 4 ) is replaced by a resistor R62. That is, in the control circuit 61, as in the control circuit 21 of the second embodiment, a load R61, a first NMOS transistor N61, a second NMOS transistor N62, a first PMOS transistor P61, a third PMOS transistor P63, and a fourth PMOS transistor P64 are provided. The resistor R62 for well control is provided between the power line L61 and the fourth PMOS transistor P64. The resistance value of the resistor R62 is set to be larger than the resistance value of the pull-up resistor of the upper device such as the ECU (not shown).

[0074] During normal operation, a power supply voltage is applied to the gate terminal of the fourth PMOS transistor P64, and the gate potential of the fourth PMOS transistor P64 becomes the power supply potential. Since the fourth PMOS transistor P64 is cut off, the well potentials of the first PMOS transistor P61, the third PMOS transistor P63, and the fourth PMOS transistor P64 are fixed at a high potential via the resistor R62 for well control. The first PMOS transistor P61 is maintained in the on state, and the third PMOS transistor P63 and the fourth PMOS transistor P64 are maintained in the cut-off state. Thus, with the help of the resistor R62 and the fourth PMOS transistor P64, the well potentials of the PMOS transistors P61, P63, and P64 can be controlled in the same manner as the control circuit 11 of the first embodiment.

[0075] When the power supply is disconnected, the gate terminal of the fourth PMOS transistor P64 is connected to the ground G63 via the load of the LSI internal circuit 64. The gate potential of the fourth PMOS transistor P64 becomes the ground potential, and the fourth PMOS transistor P64 is turned on. Since the resistance value of the resistor R62 is set high, the well potentials of the first PMOS transistor P61, the third PMOS transistor P63, and the fourth PMOS transistor P64 are fixed at the signal potential through the fourth PMOS transistor P64. As a result, the voltage drop of the parasitic diode of the first PMOS transistor P61 as in the first embodiment no longer exists, and the threshold voltage of the first PMOS transistor P61 increases as in the second embodiment, which can reduce the leakage current when the current is cut off.

[0076] As described above, in the sixth embodiment, the current looping from the signal line L62 to the power line L61 when the power supply is disconnected can be suppressed as in the second embodiment. In addition, the well potentials of the first PMOS transistor P61, the third PMOS transistor P63, and the fourth PMOS transistor P64 can be controlled by the resistor R62 and the fourth PMOS transistor P64.

[0077] [Seventh embodiment]

[0078] In addition, if Fig. 9 As shown, the fourth PMOS transistor that is turned on when the power is disconnected can also be replaced by a resistor. Fig. 9 Here, description of the sensor device according to the seventh embodiment will be omitted as much as possible for the same configuration as that of the second embodiment. Fig. 9 This is a circuit diagram of a sensor device according to a seventh embodiment.

[0079] like Fig. 9 As shown, the sensor device 70 of the seventh embodiment is different from the second embodiment in that the fourth PMOS transistor P24 (refer to Figure 4 ) is replaced by a resistor R72. That is, in the control circuit 71, as in the control circuit 21 of the second embodiment, a load R71, a first NMOS transistor N71, a second NMOS transistor N72, and a first PMOS transistor P71 to a third PMOS transistor P73 are provided. The resistor R72 for well control is provided between the second PMOS transistor P72 and the signal line L72.

[0080] During normal operation, the gate terminal of the second PMOS transistor P72 is connected to the ground G72 through the second NMOS transistor N72 of the gate control circuit 75, and the gate potential of the second PMOS transistor P72 becomes the ground potential. Therefore, the well potential of the first PMOS transistor P71 to the third PMOS transistor P73 is fixed at the power supply potential via the second PMOS transistor P72. The first PMOS transistor P71 and the second PMOS transistor P72 are maintained in the on state, and the third PMOS transistor P73 is maintained in the off state.

[0081] Furthermore, during normal operation, the first PMOS transistor P71 and the second PMOS transistor P72 are turned on, and a series circuit of a load R71 and the first PMOS transistor P71 and a series circuit of the second PMOS transistor P72 and a resistor R72 are formed in parallel between the power line L71 and the signal line L72. Therefore, the resistance value of each element of the parallel circuit is set in such a way that the reference of the Low voltage of the upper device is satisfied by the voltage division of the resistance value of the combined resistance of the parallel circuit composed of the two series circuits and the resistance value of the ON resistance of the first NMOS transistor N71 for circuit driving.

[0082] When the power supply is turned off, the second PMOS transistor P72 is cut off, and thus the well potential of the first PMOS transistor P71 to the third PMOS transistor P73 is controlled by the resistor R72.

[0083] Thus, the well potentials of the PMOS transistors P71 to P73 can be controlled by the second PMOS transistor P72 and the resistor R72 in the same manner as the control circuit 21 of the second embodiment.

[0084] As described above, in the seventh embodiment, the current looping from the signal line L72 to the power line L71 when the power is disconnected can be suppressed as in the second embodiment. In addition, the well potential of the first PMOS transistor P71 to the third PMOS transistor P73 can be controlled by the second PMOS transistor P72 and the resistor R72.

[0085] [Eighth embodiment]

[0086] In the above-mentioned embodiments, a load is set in the control circuit, and the load can be composed of a resistor or a transistor. Fig.10 As shown in the figure, a PMOS transistor is used to form a load. Fig.10 Here, description will be given of a sensor device according to an eighth embodiment. Here, description of the same configuration as that of the first embodiment will be omitted as much as possible. Fig.10 This is a circuit diagram of a sensor device according to an eighth embodiment.

[0087] like Fig.10As shown, the difference between the sensor device 80 of the eighth embodiment and the first embodiment is that a fifth PMOS transistor P85 is provided as a load for current adjustment. That is, in the control circuit 81, as in the control circuit 11 of the first embodiment, a first NMOS transistor N81, a second NMOS transistor N82, and a first PMOS transistor P81 to a third PMOS transistor P83 are provided. In addition, in the control circuit 81, a fifth PMOS transistor P85 for current adjustment is provided between the power line L81 and the first PMOS transistor P81. By forming the load with a transistor, the current adjustment effect is improved.

[0088] One input / output terminal (source terminal) of the fifth PMOS transistor P85 is connected to the power supply line L81, and the other input / output terminal (drain terminal) is connected to one input / output terminal of the first PMOS transistor P81. The LSI internal circuit 84 is connected to the gate terminal of the fifth PMOS transistor P85, and the fifth PMOS transistor P85 is driven by receiving a control signal from the LSI internal circuit 84. The well potential of the fifth PMOS transistor P85 is controlled by the second PMOS transistor P82. Therefore, the wells of the PMOS transistors P81-P83 and P85 can be shared to achieve a smaller chip area.

[0089] As described above, in the eighth embodiment, the current looping from the signal line L82 to the power line L81 when the power is off can be suppressed as in the first embodiment. In addition, the current adjustment effect can be improved by using the fifth PMOS transistor P85 as a load.

[0090] In addition, in order to support the SENT (Signal Edge Nibble Transmission) specification, each sensor of this embodiment can also control the signal potential by means of a pull-up circuit. Even if the pull-up circuit is not used and the power supply is disconnected while the signal potential is always pulled up, the current can be suppressed from looping back from the signal line to the power line to prevent the output of the intermediate potential.

[0091] The embodiments of the present invention are described in detail above, but the present invention is not limited to the embodiments, and various design changes can be made within the scope of the spirit of the present invention recorded in the claims. For example, the embodiments are detailed descriptions of the present invention in an easy-to-understand manner, and are not necessarily limited to all the structures described. In addition, a part of the structure of a certain embodiment can be replaced with the structure of other embodiments, and in addition, the structure of other embodiments can be added to the structure of a certain embodiment. Furthermore, other structures can be added, deleted, or replaced to a part of the structure of each embodiment.

[0092] Explanation of symbols

[0093] 10, 20, 30, 40, 50, 60, 70, 80...Sensor device

[0094] 11, 21, 31, 41, 51, 61, 71, 81…control circuit

[0095] 14, 24, 34, 44, 54, 64, 74, 84…LSI internal circuit (detection circuit)

[0096] 15, 45, 55, 75...Gate control circuit

[0097] L11, L21, L31, L41, L51, L61, L71, L81…power cord

[0098] L12, L22, L32, L42, L52, L62, L72, L82…Signal lines

[0099] N12, N22, N32, N52, N62, N72, N82…second NMOS transistor

[0100] P11, P21, P31, P41, P51, P61, P71, P81 ... first PMOS transistor (first transistor)

[0101] P12, P22, P32, P42, P52, P72, P82…second PMOS transistor (second transistor)

[0102] P13, P23, P33, P43, P63, P73, P83…third PMOS transistor

[0103] P24, P64…the fourth PMOS transistor

[0104] P85…Fifth PMOS transistor

[0105] R11, R21, R31, R41, R51, R61, R71…load

[0106] R42, R52, R62, R72…resistors.

Claims

1. A control circuit that receives a power supply voltage from a power supply line and outputs an output signal to a signal line, characterized in that: have: A load, which is arranged between the power line and the signal line; A first transistor is provided between the load and the signal line or between the power line and the load; a second transistor disposed between the well of the first transistor and the power line; as well as a gate control circuit that connects the gate terminal of the first transistor and the gate terminal of the second transistor to the signal line to cut off the first transistor and the second transistor when the power supply is disconnected, The first transistor is a first PMOS transistor, The second transistor is a second PMOS transistor, The gate control circuit has: a first element provided between a connection point of a gate terminal of the first PMOS transistor and a gate terminal of the second PMOS transistor and ground; as well as a second element provided between a connection point between a gate terminal of the first PMOS transistor and a gate terminal of the second PMOS transistor and the signal line, In normal operation, the gate terminal of the first PMOS transistor and the gate terminal of the second PMOS transistor are connected to the ground via the first element, and when the power is cut off, the gate terminal of the first PMOS transistor and the gate terminal of the second PMOS transistor are connected to the signal line via the second element. One input / output terminal of the first PMOS transistor is connected to the load, and the other input / output terminal of the first PMOS transistor is connected to the signal line. One input / output terminal of the second PMOS transistor is connected to the power line, and the other input / output terminal of the second PMOS transistor is connected to the well of the first PMOS transistor, the well of the second PMOS transistor, and the second element.

2. The control circuit according to claim 1, characterized in that: During normal operation, the gate control circuit connects the gate terminal of the first transistor and the gate terminal of the second transistor to the ground, and sets the well potential of the first transistor to the power supply potential via the second transistor, thereby turning on the first transistor.

3. The control circuit according to claim 1, characterized in that: The first element is an NMOS transistor, the second element is a third PMOS transistor, A gate terminal of the NMOS transistor is connected to the power line, and a gate terminal of the third PMOS transistor is connected to the power line.

4. The control circuit according to claim 3, characterized in that: The other input / output terminal of the second PMOS transistor is connected to the well of the first PMOS transistor, the well of the second PMOS transistor, and the well of the third PMOS transistor.

5. The control circuit according to claim 4, characterized in that: A fourth PMOS transistor is provided, wherein the fourth PMOS transistor is provided between a connection point between the well of the first PMOS transistor and the well of the second PMOS transistor and the signal line, A gate terminal of the fourth PMOS transistor is connected to the power supply line.

6. The control circuit according to claim 5, characterized in that: One input / output terminal of the fourth PMOS transistor is connected to the well of the first PMOS transistor, the well of the second PMOS transistor, the well of the third PMOS transistor, and the well of the fourth PMOS transistor, and the other input / output terminal of the fourth PMOS transistor is connected to the signal line.

7. The control circuit according to claim 6, characterized in that: Either the second PMOS transistor or the fourth PMOS transistor is replaced with a resistor.

8. The control circuit according to claim 1, characterized in that: The first element is a resistor, the second element is a third PMOS transistor, A gate terminal of the third PMOS transistor is connected to the power supply line.

9. The control circuit according to claim 1, characterized in that: The first element is an NMOS transistor, the second element is a resistor, A gate terminal of the NMOS transistor is connected to the power supply line.

10. The control circuit according to claim 1, characterized in that: The load is composed of a resistor or a transistor.

11. A sensor device, characterized in that: have: A control circuit according to any one of claims 1 to 10; and The detection circuit outputs a control signal corresponding to the physical quantity to the control circuit.

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