Semiconductor device and method

Abstract

The present disclosure relates to semiconductor devices and methods. In an embodiment, a method includes: forming fins extending from a substrate; forming a first gate mask over the fins, the first gate mask having a first width; forming a second gate mask over the fins, the second gate mask having a second width that is greater than the first width; depositing a first fill layer over the first gate mask and the second gate mask; depositing a second fill layer over the first fill layer; planarizing the second fill layer using a chemical mechanical polishing (CMP) process, performing the CMP process until the first fill layer is exposed; and planarizing the remaining portion of the second fill layer and the first fill layer using an etch-back process that etches the materials of the first fill layer, the second fill layer, the first gate mask, and the second gate mask at the same rate.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices and methods. Background Art

[0002] Semiconductor devices are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate and patterning the various material layers using lithography to form circuit components and elements thereon.

[0003] The semiconductor industry has continuously improved the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size is reduced, other problems arise that should be addressed. Summary of the Invention

[0004] According to one embodiment of the present disclosure, a method of manufacturing a semiconductor device is provided, including: forming fins extending from a substrate; forming a first gate mask over the fins, the first gate mask having a first width; forming a second gate mask over the fins, the second gate mask having a second width greater than the first width; depositing a first fill layer over the first gate mask and the second gate mask; depositing a second fill layer over the first fill layer; planarizing the second fill layer using a chemical mechanical polishing (CMP) process, performing the CMP process until the first fill layer is exposed; and planarizing the remaining portion of the second fill layer and the first fill layer using an etch-back process, the etch-back process etching the materials of the first fill layer, the second fill layer, the first gate mask, and the second gate mask at the same rate.

[0005] According to another embodiment of the present disclosure, a method of manufacturing a semiconductor device is provided, including: forming fins extending from a substrate; forming a first gate mask over the fins, the first gate mask having a first width; forming a second gate mask over the fins, the second gate mask having a second width greater than the first width; depositing a fill layer over the first gate mask and the second gate mask; planarizing the fill layer using a chemical mechanical polishing (CMP) process; and after the CMP process, planarizing the fill layer using an etch-back process, the etch-back process etching the materials of the fill layer, the first gate mask, and the second gate mask at the same rate.

[0006] According to another embodiment of the present disclosure, a method of manufacturing a semiconductor device is provided, including: forming fins extending from a substrate; forming a first gate stack over a first channel region of the fins; forming a second gate stack over a second channel region of the fins, the second channel region of the fins having a different length from the first channel region of the fins; depositing a first fill layer over the first gate stack and the second gate stack; patterning the first fill layer; using the patterned first fill layer as an etch mask to etch an opening in the first gate stack; depositing a second fill layer in the opening and over the first fill layer; polishing the second fill layer until a portion of the first fill layer is exposed; and etching a remaining portion of the second fill layer and the first fill layer using a non-selective etch process, after which a top surface of the remaining portion of the second fill layer and the first fill layer is flush. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of various features may be arbitrarily increased or reduced.

[0008] Figure 1 An example of a FinFET in a three-dimensional view according to some embodiments is shown.

[0009] Figures 2 to 20B are various views of an intermediate stage in FinFET manufacturing according to some embodiments.

[0010] Figures 21A to 23B are various views of an intermediate stage in FinFET manufacturing according to some other embodiments.

[0011] Figures 24A to 26B are various views of an intermediate stage in FinFET manufacturing according to some other embodiments. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or over a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] In addition, spatially relative terms (e.g., "below", "beneath", "lower", "above", "upper", etc.) may be used herein to facilitate describing the relationship of one element or feature shown in the figures to another (one or more) element or (one or more) feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0014] According to some embodiments, FinFETs are formed having channel regions of different lengths. The channel regions of different lengths may be formed from the same semiconductor fin. During a replacement gate process for a FinFET, pattern loading may occur, resulting in the material layer of the replacement gate having different heights. The gate mask formed to protect the replacement gate may thus also have different heights. A multi-step planarization process is performed to planarize the gate mask and the surrounding interlayer dielectric (ILD) mask. The multi-step planarization process includes a chemical mechanical polishing (CMP) process that is used to reset the flatness of the structure, followed by an etch-back process that is non-selective and etches the gate mask and the ILD mask at the same rate. Thus, even when the gate mask pattern is heavily loaded, the top surfaces of the gate mask and the ILD mask may be flush.

[0015] Figure 1Shows an example of a FinFET in a three-dimensional view according to some embodiments. The FinFET includes fins 52 located on a substrate 50 (e.g., a semiconductor substrate). Isolation regions 56 are disposed in the substrate 50, and the fins 52 protrude above and between adjacent isolation regions 56. Although the isolation regions 56 are depicted / illustrated as being separate from the substrate 50, as used herein, the term "substrate" can be used to refer to only the semiconductor substrate or a semiconductor substrate including the isolation regions. Additionally, although the fins 52 are shown as a single continuous material as the substrate 50, the fins 52 and / or the substrate 50 can include a single material or multiple materials. In this case, the fins 52 refer to the portions extending between adjacent isolation regions 56.

[0016] A gate dielectric 100 is along the sidewalls of the fins 52 and above the top surface of the fins 52, and a gate electrode 102 is located above the gate dielectric 100. Source / drain regions 82 are disposed on opposite sides of the fins 52 relative to the gate dielectric 100 and the gate electrode 102. Figure 1 Also shown are reference cross-sections used in the subsequent figures. Cross-section A-A is along the longitudinal axis of the gate electrode 102 and in a direction, for example, perpendicular to the direction of current flow between the source / drain regions 82 of the FinFET. Cross-section B-B is perpendicular to cross-section A-A and along the longitudinal axis of the fins 52 and in the direction of the current, for example, between the source / drain regions 82 of the FinFET. Cross-section C-C is parallel to cross-section A-A and extends through the source / drain regions of the FinFET. For clarity, the subsequent figures refer to these reference cross-sections.

[0017] Some embodiments discussed herein are discussed in the context of FinFETs formed using a gate-last process. In other embodiments, a gate-first process can be used. Similarly, some embodiments contemplate aspects for use in planar devices (e.g., planar FETs).

[0018] Figures 2 to 20B Are various views of an intermediate stage in the manufacture of a FinFET according to some embodiments. Figure 2 and Figure 3 Are three-dimensional views. Figure 4A 、 Figure 5A 、 Figure 6A 、 Figure 7A 、 Figure 8A 、 Figure 9A 、 Figure 10A 、 Figure 11A 、 Figure 12A 、 Figure 13A 、 Figure 14A 、 Figure 15A 、Figure 16A , Figure 17A , Figure 18A , Figure 19A and Figure 20A are cross-sectional views shown along reference cross-section A-A as shown in Figure 1 , except for the plurality of fins / FinFETs. Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B and Figure 20B are cross-sectional views in which the figures ending with "A" are illustrated along reference cross-section A-A as shown in Figure 1 and in the corresponding figures ending with "B" along reference cross-section A-A, except for the plurality of fins / FinFETs. Figure 5C and Figure 5D are illustrated along reference cross-section C-C as shown in Figure 1 , except for the plurality of fins / FinFETs.

[0019] In Figure 2 , a substrate 50 is provided. The substrate 50 can be a semiconductor substrate, e.g., a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 50 can be a wafer, e.g., a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer can be, e.g., a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate, which is typically a silicon or glass substrate. Other substrates can also be used, e.g., multi-layer or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 can include: silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide; or combinations thereof.

[0020] The substrate 50 has a region 50N and a region 50P. The region 50N can be used to form n-type devices, such as NMOS transistors, such as n-type FinFETs. The region 50P can be used to form p-type devices, such as PMOS transistors, such as p-type FinFETs. The region 50N can be physically separated from the region 50P, and any number of device features (such as other active devices, doped regions, isolation structures, etc.) can be provided between the region 50N and the region 50P. The figures (discussed below) marked with the letter "B" illustrate the features in either the region 50N or the region 50P. For example, the structures shown in the figures marked with the letter "B" can be applicable to both the region 50N and the region 50P. The structural differences (if any) between the region 50N and the region 50P are described in the text associated with each figure.

[0021] A fin 52 is formed on the substrate 50 and extends from the substrate 50. The fin 52 is a semiconductor strip. In some embodiments, the fin 52 can be formed in the substrate 50 by etching trenches in the substrate 50. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching can be anisotropic.

[0022] The fins can be patterned by any suitable method. For example, one or more lithography processes can be used to pattern the fins, including double patterning or multi-patterning processes. Generally, double patterning or multi-patterning processes combine lithography and self-alignment processes, allowing the creation of patterns with pitches, for example, smaller than those achievable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a lithography process. A spacer is formed adjacent to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacer can then be used to pattern the fins. In some embodiments, a mask (or other layer) can be retained on the fin 52.

[0023] The STI region 56 is formed above the substrate 50 and between adjacent fins 52. As an example of forming the STI region 56, an insulating material is formed above the substrate 50 and between adjacent fins 52. The insulating material can be an oxide, such as silicon oxide, nitride, etc., or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition and post-curing in a remote plasma system to convert it into another material, such as an oxide), etc., or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by the FCVD process. Once the insulating material is formed, an annealing process can be performed. In an embodiment, the insulating material is formed such that excess insulating material covers the fins 52. Although the insulating material is shown as a single layer, some embodiments can use multiple layers. For example, in some embodiments, a liner (not shown) can be formed first along the surfaces of the substrate 50 and the fins 52. Thereafter, a filling material, such as the one discussed above, can be formed above the liner. Then a removal process is applied to the insulating material to remove the excess insulating material above the fins 52. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), etch-back process, a combination thereof, etc., can be used. The planarization process exposes the fins 52 such that after the planarization process is completed, the top surfaces of the fins 52 and the insulating material are flush. In embodiments where a mask remains on the fins 52, the planarization process can expose the mask or remove the mask such that after the planarization process is completed, the top surface of the mask or the fins 52 and the insulating material are flush respectively. The insulating material is then recessed to form the STI region 56. The insulating material is recessed such that the upper portions of the fins 52 in the regions 50N and 50P protrude between adjacent STI regions 56. Additionally, the top surface of the STI region 56 can have a flat surface, a convex surface, a concave surface (e.g., a groove), or a combination thereof as shown. Through appropriate etching, the top surface of the STI region 56 can be formed to be flat, convex, and / or concave. The STI region 56 can be recessed using an acceptable etching process, such as an etching process selective to the material of the insulating material (e.g., etching the material of the insulating material at a faster rate than the material of the fins 52). For example, oxide removal using, for example, diluted hydrofluoric acid (dHF) can be used.

[0024] The above process is only one example of how the fin 52 can be formed. In some embodiments, the fin can be formed by an epitaxial growth process. For example, a dielectric layer can be formed above the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. A homoepitaxial structure can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the homoepitaxial structure protrudes from the dielectric layer to form the fin. Additionally, in some embodiments, a heteroepitaxial structure can be used for the fin 52. For example, the fin 52 in FIG. 5 can be recessed, and a material different from that of the fin 52 can be epitaxially grown above the recessed fin 52. In such an embodiment, the fin 52 includes the recessed material and the epitaxially grown material disposed above the recessed material. In a further embodiment, a dielectric layer can be formed above the top surface of the substrate 50, and trenches can be etched through the dielectric layer. Then a heteroepitaxial structure can be epitaxially grown in the trenches using a material different from that of the substrate 50, and the dielectric layer can be recessed such that the heteroepitaxial structure protrudes from the dielectric layer to form the fin 52. In some embodiments, when epitaxially growing a homoepitaxial structure or a heteroepitaxial structure, the epitaxially grown material can be in-situ doped during growth, which can avoid prior and subsequent implantations, although in-situ doping and implant doping can be used together.

[0025] Further, it may be advantageous to epitaxially grow a material different from that in the region 50P (e.g., PMOS region) in the region 50N (e.g., NMOS region). In various embodiments, the upper portion of the fin 52 can be formed of silicon germanium (Si x Ge 1-x , where x can range from 0 to 1), silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, available materials for forming III-V compound semiconductors include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, aluminum indium arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, etc.

[0026] In addition, appropriate wells (not shown) can be formed in the fin 52 and / or the substrate 50. In some embodiments, a P well can be formed in the region 50N, and an N well can be formed in the region 50P. In some embodiments, a P well or an N well is formed in both the region 50N and the region 50P.

[0027] In embodiments having different well types, a photoresist or other mask (not shown) may be used to implement different implantation steps for regions 50N and 50P. For example, a photoresist may be formed over fins 52 and STI regions 56 in region 50N. The photoresist is patterned to expose region 50P of substrate 50, e.g., the PMOS region. The photoresist may be formed by using a spin coating technique, and the photoresist may be patterned using acceptable photolithography techniques. Once the photoresist is patterned, an n-type impurity implantation is performed in region 50P, and the photoresist may be used as a mask to substantially prevent the n-type impurity from being implanted into region 50N, e.g., the NMOS region. The n-type impurity may be phosphorus, arsenic, antimony, etc. implanted into the region at a concentration equal to or less than 10 18 cm -3 (e.g., between about 10 16 cm -3 and about 10 18 cm -3 ). After the implantation, the photoresist is removed, e.g., by an acceptable ashing process.

[0028] After implanting region 50P, a photoresist is formed over fins 52 and STI regions 56 in region 50P. The photoresist is patterned to expose region 50N of substrate 50, e.g., the NMOS region. The photoresist may be formed by using a spin coating technique, and the photoresist may be patterned using acceptable photolithography techniques. Once the photoresist is patterned, a p-type impurity implantation is performed in region 50N, and the photoresist may be used as a mask to substantially prevent the p-type impurity from being implanted into region 50P, e.g., the PMOS region. The p-type impurity may be boron, boron fluoride, indium, etc. implanted into the region at a concentration equal to or less than 10 18 cm -3 (e.g., between about 10 16 cm -3 and about 10 18 cm -3 ). After the implantation, the photoresist is removed, e.g., by an acceptable ashing process.

[0029] After implanting regions 50N and 50P, annealing may be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins may be in-situ doped during growth, which may avoid implantation, but in-situ doping and implant doping may be used together.

[0030] In Figure 3In [the structure], a dummy dielectric layer 60 is formed on the fin 52. The dummy dielectric layer 60 can be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 62 is formed above the dummy dielectric layer 60, and a mask layer 64 is formed above the dummy gate layer 62. The dummy gate layer 62 can be deposited on the dummy dielectric layer 60 and then planarized, for example, by CMP. The mask layer 64 can be deposited above the dummy gate layer 62. The dummy gate layer 62 can be a conductive or non-conductive material and can be selected from the group including amorphous silicon, polysilicon, polycrystalline silicon germanium (polycrystalline SiGe), metal nitride, metal silicide, metal oxide, and metal. The dummy gate layer 62 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques known in the art and used for depositing the selected material. The dummy gate layer 62 can be made of other materials having a high etch selectivity with respect to the etching of the isolation region. The mask layer 64 can include, for example, silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed across the region 50N and the region 50P. Note that, for illustrative purposes only, the dummy dielectric layer 60 is shown covering only the fin 52. In some embodiments, the dummy dielectric layer 60 can be deposited such that the dummy dielectric layer 60 covers the STI region 56 and extends between the dummy gate layer 62 and the STI region 56.

[0031] In Figure 4A and Figure 4B [the structure], acceptable lithography and etching techniques can be used to pattern the mask layer 64 to form a mask 74. Then, the pattern of the mask 74 can be transferred to the dummy gate layer 62 to form a dummy gate 72. In some embodiments (not shown), the pattern of the mask 74 can also be transferred to the dummy dielectric layer 60 by acceptable etching techniques to form a dummy gate dielectric 70. The dummy gate dielectric 70 and the dummy gate 72 can be collectively referred to as a "dummy gate stack", and each dummy gate stack includes the dummy gate dielectric 70 and the dummy gate 72. The dummy gate stack covers the corresponding channel region 58 of the fin 52. The pattern of the mask 74 can be used to physically separate each dummy gate 72 from adjacent dummy gates. The dummy gate 72 can also have a length direction that is substantially perpendicular to the length direction of the corresponding fin 52.

[0032] The dummy gate 72 includes dummy gates of different widths. In the example shown, the dummy gate 72 includes a dummy gate 72A having a first width W 1 and a dummy gate 72B having a larger second width W 2 and a dummy gate 72C having an even larger third width W 3 and a dummy gate having an even further larger fourth width W4 dummy gate 72D. For example, the first width W 1 may be in the range of about 3 nm to about 15 nm, the second width W 2 may be in the range of about 22 nm to about 90 nm, the third width W 3 may be in the range of about 100 nm to about 172 nm, and the fourth width W 4 may be in the range of about 210 nm to about 250 nm. In addition, the mask 74 (and the dummy gate dielectric 70 during patterning) has the same width W as its corresponding dummy gate 72 1 / W 2 / W 3 / W 4 . The varying width W of the dummy gate 72 1 / W 2 / W 3 / W 4 allows the formation of FinFETs with channel regions 58 of different lengths. Varying the length of the channel region 58 allows the formation of FinFETs with different threshold voltages. The width W of the dummy gate 72 is selected based on the desired threshold voltage of the resulting FinFET 1 / W 2 / W 3 / W 4 .

[0033] In addition, implantation of a lightly doped source / drain (LDD) region (not explicitly shown) may be performed. In embodiments with different device types, similar to the implantations discussed above, a mask (e.g., photoresist) may be formed over the region 50N while exposing the region 50P, and an impurity of an appropriate type (e.g., p-type) may be implanted into the exposed fins 52 in the region 50P. The mask may then be removed. Subsequently, a mask (e.g., photoresist) may be formed over the region 50P while exposing the region 50N, and an impurity of an appropriate type (e.g., n-type) may be implanted into the exposed fins 52 in the region 50N. The mask may then be removed. The n-type impurity may be any of the n-type impurities discussed above, and the p-type impurity may be any of the p-type impurities discussed above. The lightly doped source / drain region may have an impurity concentration between about 10 15 cm -3 and about 10 19 cm -3 . Annealing may be used to repair implantation damage and activate the implanted impurities.

[0034] In addition, gate spacers 84 are formed along the sidewalls of the mask 74 and dummy gates 72 (and dummy gate dielectrics 70 during patterning). The gate spacers 84 are located on the exposed surfaces of the fins 52. The gate spacers 84 can be formed of an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, combinations thereof, etc. The (one or more) material layers of the gate spacers 84 can be conformally formed, for example, by thermal oxidation, deposition, etc., and then can be etched to form the gate spacers 84. The gate spacers 84 can be a single layer or can include multiple layers. For example, the gate spacers 84 can include a gate seal spacer layer and a main gate spacer layer. In some embodiments, the gate spacers 84 are an oxide-nitride-oxide structure that includes a nitride layer (e.g., formed of silicon nitride) between oxide layers (e.g., formed of silicon oxide).

[0035] Note that the above disclosure generally describes processes for forming gate spacers and LDD regions. Other processes and sequences can be used. For example, fewer or additional spacers can be utilized, different orders of steps can be employed, spacers can be formed and removed, etc. In addition, different structures and steps can be used to form n-type and p-type devices.

[0036] In Figure 5A and Figure 5B , epitaxial source / drain regions 82 are formed in the fins 52. The epitaxial source / drain regions 82 can apply stress in the respective channel regions 58, thereby improving performance. The epitaxial source / drain regions 82 are formed in the fins 52 such that each dummy gate 72 is disposed between corresponding adjacent pairs of epitaxial source / drain regions 82. In some embodiments, the epitaxial source / drain regions 82 can extend into the fins 52. In some embodiments, the gate spacers 84 are used to separate the epitaxial source / drain regions 82 from the dummy gates 72 by an appropriate lateral distance such that the epitaxial source / drain regions 82 do not short-circuit the gates of the subsequently formed FinFETs.

[0037] The epitaxial source / drain regions 82 in the region 50N (e.g., NMOS region) can be formed by masking the region 50P (e.g., PMOS region) and etching the source / drain regions of the fins 52 in the region 50N to form grooves in the fins 52. Then, the epitaxial source / drain regions 82 in the region 50N grow epitaxially in the grooves. The epitaxial source / drain regions 82 can include, for example, any acceptable material suitable for n-type FinFETs. For example, if the fins 52 are silicon, the epitaxial source / drain regions 82 in the region 50N can include a material that applies tensile strain in the channel regions 58, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain regions 82 in the region 50N can have a surface that protrudes from the corresponding surfaces of the fins 52 and can have facets.

[0038] The epitaxial source / drain regions 82 in region 50P (e.g., PMOS region) can be formed by masking region 50N (e.g., NMOS region) and etching the source / drain regions of fins 52 in region 50P to form grooves in fins 52. Then, the epitaxial source / drain regions 82 in region 50P grow epitaxially in the grooves. The epitaxial source / drain regions 82 can include, for example, any acceptable material suitable for p-type FinFETs. For example, if fin 52 is silicon, the epitaxial source / drain regions 82 in region 50P can include materials that apply compressive strain in channel region 58, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, etc. The epitaxial source / drain regions 82 in region 50P can also have a surface that protrudes from the corresponding surface of fin 52 and can have facets.

[0039] The epitaxial source / drain regions 82 and / or fins 52 can be implanted with dopants to form source / drain regions, similar to the process discussed previously for forming lightly doped source / drain regions, and then annealed. The impurity concentration of the source / drain regions can be between about 10 19 cm -3 and about 10 21 cm -3 . The n-type and / or p-type impurities of the source / drain regions can be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 82 can be in-situ doped during growth.

[0040] As a result of the epitaxial process for forming the epitaxial source / drain regions 82 in region 50N and region 50P, the upper surface of the epitaxial source / drain regions has facets that laterally extend outward beyond the sidewalls of fins 52. In some embodiments, these facets cause adjacent epitaxial source / drain regions 82 of the same FinFET to merge (as Figure 5C shown). In other embodiments, after the epitaxial process is completed, adjacent epitaxial source / drain regions 82 remain separated (as Figure 5D shown).

[0041] After forming the epitaxial source / drain regions 82, an ILD 86 is deposited over the intermediate structure. The first ILD 86 can be formed of a dielectric material and can be deposited by any suitable method, e.g., CVD, plasma enhanced CVD (PECVD), or FCVD. The dielectric material can include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process can be used. In some embodiments, a contact etch stop layer (CESL) (not shown) is disposed between the first ILD 86 and the epitaxial source / drain regions 82, the mask 74, and the gate spacers 84. The CESL can include a dielectric material, e.g., silicon nitride, silicon oxide, silicon oxynitride, etc., which has an etch rate different from that of the overlying first ILD 86 material.

[0042] After Figure 6A and Figure 6B a planarization process such as CMP is performed to make the top surface of the first ILD 86 flush with the top surface of the dummy gate 72 or the mask 74. The planarization process can also remove the mask 74 on the dummy gate 72 and portions of the gate seal spacers 80 and the gate spacers 84 along the sidewalls of the mask 74. After the planarization process, the top surfaces of the dummy gate 72, the gate seal spacers 80, the gate spacers 84, and the first ILD 86 are flush. Thus, the top surface of the dummy gate 72 is exposed through the first ILD 86. In some embodiments, the mask 74 can be retained, in which case the planarization process makes the top surface of the first ILD 86 flush with the top surface of the mask 74.

[0043] After Figure 7A and Figure 7B an ILD mask 88 is formed over the remaining portion of the first ILD 86. According to some embodiments, the first ILD 86 is recessed to form a groove between the opposing gate spacers 84. The recessing can be any acceptable etching process, e.g., wet etching or dry etching. The ILD mask 88 is formed of one or more layers of dielectric material, e.g., silicon nitride, silicon oxynitride, etc. In some embodiments, the ILD mask 88 is a silicon nitride layer. The ILD mask 88 is formed by filling the groove in the first ILD86. Then a planarization process can be performed to remove the excess dielectric material extending above the dummy gate 72 and the gate spacers 84.

[0044] After Figure 8A and Figure 8BIn [the figure], dummy gate 72 (and mask 74, if present) is removed in one or more etching steps to form recess 90. The dummy gate dielectric 70 in recess 90 may also be removed. In some embodiments, only dummy gate 72 is removed, and dummy gate dielectric 70 remains and is exposed by recess 90. In some embodiments, dummy gate dielectric 70 is removed from recess 90 in a first region of the die (e.g., the core logic region), and dummy gate dielectric 70 remains in recess 90 of a second region of the die (e.g., the input / output region). In some embodiments, dummy gate 72 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using one or more reactive gases that selectively etch dummy gate 72 without etching gate spacer 84. ILD mask 88 protects first ILD 86 during etching. Each recess 90 exposes and / or covers channel region 58 of a corresponding fin 52. Each channel region 58 is disposed between adjacent pairs of epitaxial source / drain regions 82. During removal, dummy gate dielectric 70 may be used as an etch stop layer when dummy gate 72 is etched. Dummy gate dielectric 70 may then be optionally removed after removing dummy gate 72.

[0045] Recess 90 includes recesses of different widths. In the illustrated example, recess 90 includes recesses 90A, 90B, 90C, and 90D, which correspond to dummy gates 72A, 72B, 72C, and 72D that are removed, respectively. Similar to dummy gate 72, recess 90 has different widths W 1 / W 2 / W 3 / W 4 。

[0046] In Figure 9A and Figure 9B [the figure], a gate dielectric layer 92 is formed in recess 90 and on the top surface of ILD mask 88. According to some embodiments, gate dielectric layer 92 includes silicon oxide, silicon nitride, or a multi-layer thereof. In some embodiments, gate dielectric layer 92 includes a high-k dielectric material, and in these embodiments, gate dielectric layer 92 may have a k value greater than about 7.0, and gate dielectric layer 92 may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The method of forming gate dielectric layer 92 may include molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, etc. In embodiments where a portion of dummy gate dielectric 70 remains in recess 90, gate dielectric layer 92 may be formed only in recess 90 not occupied by the remaining dummy gate dielectric 70.

[0047] In addition, a gate electrode layer 94 is formed on the gate dielectric layer 92 to fill the remaining portion of the trench 90. The gate electrode layer 94 can be formed of a conductive material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, etc., and can be formed by MBD, ALD, PECVD, etc. The gate electrode layer 94 can include any number of liner layers (not shown), any number of work function adjustment layers 94A, and a fill layer 94B. The portions of the gate dielectric layer 92 and the gate electrode layer 94 located in each trench 90 will be used to form the replacement gate of the resulting FinFET. The portions of the gate dielectric layer 92 and the gate electrode layer 94 located in each trench 90 can be collectively referred to as a "metal gate stack". The metal gate stack can extend along the sidewalls of the channel region 58 of the fin 52. As described above, the trench 90 includes trenches having different widths W 1 / W 2 / W 3 / W 4 such that FinFETs having channel regions 58 of different lengths can be formed. Thus, the metal gate stack also has different widths.

[0048] In addition, a gate mask layer 96 is formed on the gate electrode layer 94. The gate mask layer 96 can be formed of an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or combinations thereof. The gate mask layer 96 can be formed by MBD, ALD, PECVD, etc.

[0049] During the formation of the gate electrode layer 94, some of the trenches 90 (e.g., smaller trenches) can be filled before the formation of the gate mask layer 96 and all of the gate electrode layer 94. In the example shown, the trench 90A is filled with the work function adjustment layer 94A; the trench 90B is filled with the work function adjustment layer 94A and the fill layer 94B; and the trenches 90C and 90D are filled with the work function adjustment layer 94A, the fill layer 94B, and the gate mask layer 96. Thus, the resulting metal gate stacks in the trenches 90 of different sizes can include different materials. Filling the trenches 90 of different sizes with different materials allows for the formation of metal gate stacks having different work functions. Since the channel region 58 has a length (and thus the trenches 90 have different widths), pattern loading occurs during the deposition of the gate electrode layer 94. In this way, the portions of the gate electrode layer 94 located above the trenches 90C and 90D are thicker than the portions of the gate electrode layer 94 located above the trenches 90A and 90B.

[0050] In Figure 10A and Figure 10BDuring this process, a planarization process is performed to expose the bottommost layer of the gate electrode layer 94, for example, the work function adjustment layer 94A. The planarization process may include performing one or more CMP processes. For example, a first CMP process may be performed to remove the overlying portion of the gate mask layer 96, where the fill layer 94B serves as a CMP stop layer during the first CMP process. Then, a second CMP process may be performed to remove the fill layer 94B, where the work function adjustment layer 94A serves as a CMP stop layer during the second CMP process. The remaining portion of the gate mask layer 96 located above each channel region 58 is referred to as the gate mask 98. The gate mask 98 can assist in controlling the second CMP process, for example, by acting as an etch control layer and / or a pattern loading control layer, slowing down the planarization rate of the second CMP process, and thereby controlling the amount of the remaining work function adjustment layer 94A. The gate mask 98 will also protect the longer channel regions 58 during subsequent processing and can assist in reducing the pattern loading effect on the longer channel regions 58 during the middle end of line (MEOL) processing. As described above, pattern loading occurs during the deposition of the gate electrode layer 94. Pattern loading results in a non-uniform profile of the planarization process. As a result, the remaining portion of the planarized layer above the ILD mask 88 may have a large height variation H 1 . For example, the height variation H 1 can be in the range of about to about . In this embodiment, the top surface of the gate mask 98 extends above the top surface of the ILD mask 88. In another embodiment (discussed below), the top surface of the ILD mask 88 extends above the top surface of the gate mask 98.

[0051] At Figure 11A and Figure 11BTherein, a recess process is performed to etch-back the gate dielectric layer 92 and the gate electrode layer 94, thereby reforming the grooves 90A / 90B / 90C / 90D. The remaining portion of the gate dielectric layer 92 located above each channel region 58 is referred to as the gate dielectric 100, and the remaining portion of the gate electrode layer 94 located above each channel region 58 is referred to as the gate electrode 102. The recess process may include performing one or more etch-back processes. Each etch-back process may be accomplished by any acceptable etching process, e.g., reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching may be anisotropic. The (one or more) etch-back processes are selective to the materials of the gate dielectric 100 and the gate electrode 102 such that the gate mask 98 is not significantly recessed by the (one or more) etch-back processes. However, even if there is substantially no recess, the (one or more) etch-back processes may still increase the surface roughness of the gate mask 98 and may also leave some by-products 103. As further discussed below, the increased surface roughness may reduce the CMP removal rate of the gate mask 98, increasing the selectivity during CMP. Thus, in further processing, the gate mask 98 is planarized by performing additional (one or more) etch-back processes (instead of only by performing the CMP process), thereby allowing a more uniform removal rate.

[0052] The formation of the gate dielectric 100 in the region 50N and the region 50P (see Figure 2 and Figure 3 ) may occur simultaneously such that the gate dielectric 100 in each region is formed of the same material, and the formation of the gate electrode 102 may occur simultaneously such that the gate electrode 102 in each region is formed of the same material. In some embodiments, the gate dielectric 100 in each region may be formed by different processes such that the gate dielectric 100 may be different materials, and / or the gate electrode 102 in each region may be formed by different processes such that the gate electrode 102 may be different materials. For example, the process described with respect to Figures 9A to 11B may be performed once in the region 50N while the region 50P is masked, and then may be performed again in the region 50P while the region 50N is masked. Channel regions 58 of different lengths may be formed in both the regions 50N and 50P. When different processes are used, various masking steps may be used to mask and expose the appropriate regions.

[0053] In Figure 12A and Figure 12BIn [description], a first fill layer 104 is deposited over the intermediate structure shown. The first fill layer 104 is selective to the etch-back process that will be performed to planarize the gate mask 98, and the first fill layer 104 will be used as an etch stop layer in subsequent processing steps. The first fill layer 104 can be formed of a non-conductive material such as silicon nitride, undoped polysilicon, undoped amorphous silicon, silicon carbonitride, zirconium oxide, hafnium oxide, etc., and can be formed by a deposition process such as CVD, ALD, etc. In some embodiments, the first fill layer 104 is a silicon layer. The deposition of the first fill layer 104 is conformal such that the topography of the first fill layer 104 conforms to the topography of the underlying features.

[0054] In Figure 13A and Figure 13B In [description], the first fill layer 104 is patterned with openings 106, including openings 106A and 106B. The openings 106 can be patterned using acceptable lithography and etching techniques. The openings 106A and 106B can be formed by different lithography processes, for example, using different lithography masks. The etch process used to form the openings 106 is continued to remove the features located below the openings 106. For example, the etch process for opening 106A can be continued to remove the underlying portion of the gate electrode 102 (and optionally, the gate dielectric 100), thereby forming a notch for the replacement gate of the resulting FinFET. Similarly, the etch process for opening 106B can be continued to remove the underlying portions of the gate dielectric 100 and the gate electrode 102 and portions of the fin 52 and the epitaxial source / drain region 82, thereby forming a notch for isolating the fins of adjacent FinFETs. During the formation of the openings 106, some etching of the ILD mask 88 may also occur, but the first ILD 86 remains substantially unetched.

[0055] In Figure 14A and Figure 14B In [description], a second fill layer 108 is deposited over the first fill layer 104 and in the openings 106. The second fill layer 108 is selective to the etch-back process that will be performed to planarize the first fill layer 104, the gate mask 98, and the ILD mask 88. After forming the notch for the replacement gate and the notch between adjacent fins, the second fill layer 108 will be used as an isolation material. The second fill layer 108 can be formed of a dielectric material such as silicon oxide, silicon nitride, a combination thereof, etc., and can be formed by a deposition process such as CVD, ALD, etc. In some embodiments, the second fill layer 108 is a silicon nitride layer. The deposition of the second fill layer 108 is conformal such that the topography of the second fill layer 108 conforms to the topography of the underlying features. Thus, the top surface of the second fill layer 108 can have a groove 108R over features with deep grooves (e.g., over opening 106B).

[0056] In Figure 15A and Figure 15B a first planarization process 112A is performed to remove the excess portion of the second fill layer 108 that is located above the top surface of the first fill layer 104. The remaining portion of the second fill layer 108 that is located within the opening 106 is referred to as the isolation feature 110. In some embodiments, the first planarization process 112A is a CMP process. A portion of the first fill layer 104 serves as a CMP stop layer for the first planarization process 112A such that most of the first fill layer 104 remains after the first planarization process 112A. Due to the conformal morphology of the first fill layer 104 and the second fill layer 108, some residual portions of the second fill layer 108 may remain in the grooves in the top surface of the first fill layer 104. In other words, most of the uppermost surface of the structure includes the first fill layer 104, but certain portions of the uppermost surface include the remaining portion of the second fill layer 108 and the isolation feature 110. Accordingly, the first planarization process 112A serves as a planarization reset step in which the non-uniformity in the morphology of the intermediate structure shown is substantially reduced.

[0057] In Figure 16A and Figure 16B a second planarization process 112B is performed to remove the excess portion of the first fill layer 104 and the isolation feature 110 that is located above the top surface of the ILD mask 88. The second planarization process 112B may also remove portions of the ILD mask 88 and the gate mask 98 as well as the by-products 103. The second planarization process 112B is different from the first planarization process 112A and the selectivity of the second planarization process 112B is less than the selectivity of the first planarization process 112A. In some embodiments, the second planarization process 112B is an etch-back process. The etch-back process is a non-selective etch that etches the materials of the isolation feature 110, the first fill layer 104, the gate mask 98, and the ILD mask 88 at the same rate. As described above, in some embodiments, the first fill layer 104 is a silicon layer and the isolation feature 110, the gate mask 98, and the ILD mask 88 are silicon nitride layers. In such embodiments, the etch-back process etches silicon and silicon nitride at substantially the same rate, e.g., the silicon nitride to silicon etch rate ratio of the etch-back process is in the range of about 0.9:1 to about 1.5:1, e.g., about 1.0:1.

[0058] As an example, the etch-back process may be a dry etch. During the dry etch, a gas source including one or more precursor gases as well as an inert gas is provided to the etch chamber. For example, the gas source may include a first precursor gas (e.g., NF 3 )), a second precursor gas (e.g., H 2) and an inert gas (e.g., Ar), where the first precursor gas and the second precursor gas are provided at a ratio in the range of about 0.5:1 to about 1.125:1. The etching chamber can be an oxygen-free environment. Then, the plasma generator then generates RF power, which generates a plasma sheath from the gas source in the etching chamber. The plasma generator can be, for example, a transformer-coupled plasma generator, an inductively coupled plasma system, a magnetically enhanced reactive ion etching system, an electron cyclotron resonance system, a remote plasma generator, etc. For example, the plasma generator can generate RF power in the range of about 200 W to about 1000 W (e.g., about 450 W). The dry etching can be carried out at low pressure and low temperature, for example, at a pressure in the range of about 200 mT to about 2500 mT (e.g., about 400 mT), and for example, at a temperature in the range of about 15 °C to about 85 °C (e.g., about 50 °C). The dry etching can be performed in multiple cycles, for example, up to about 5 cycles. For example, each cycle of the dry etching can be performed for a duration in the range of about 10 seconds to about 60 seconds (e.g., about 30 seconds).

[0059] After the second planarization process 112B, the top surfaces of the isolation features 110, the first fill layer 104, the gate mask 98, and the ILD mask 88 are planar. A non-selective etch process (instead of CMP) is used to planarize the isolation features 110, the first fill layer 104, the gate mask 98, and the ILD mask 88, allowing for a reduction in the loading effect during planarization. Further, an etch process (instead of CMP) is used to planarize the gate mask 98, allowing the materials of the isolation features 110, the first fill layer 104, the gate mask 98, and the ILD mask 88 to be removed at substantially the same rate, despite the surface roughness of the gate mask 98. Since the second planarization process 112B (e.g., etch-back) is performed after the first planarization process 112A (e.g., planarization reset), the planar topography generated by the first planarization process 112A can be transferred to the underlying features by the second planarization process 112B. Thus, the planar topography generated by the first planarization process 112A can be maintained, especially when the etch-back process itself would otherwise preserve any non-uniformities in the topography.

[0060] In Figure 17A and Figure 17B the remaining portion of the first fill layer 104 is removed. The remaining portion of the first fill layer 104 can be removed by, for example, an acceptable etch process that is selective to the material of the first fill layer 104 and does not remove the materials of the isolation features 110, the gate mask 98, or the ILD mask 88.

[0061] In Figure 18A and Figure 18BIn [description], a gate mask layer 114 is deposited over the illustrated intermediate structure. The gate mask layer 114 may include one or more dielectric materials, such as silicon nitride, silicon oxynitride, etc. The gate mask layer 114 is formed of a material having a high etch selectivity with respect to the same etching process compared to the first ILD 86, which can reduce the chance of shorting the epitaxial source / drain regions 82 and the gate electrode 102 during subsequent gate contact or source / drain contact formation processes. In some embodiments, the gate mask layer 114 is a silicon nitride layer. The gate mask layer 114 can be formed by a deposition process such as CVD, ALD, etc.

[0062] In Figure 19A and Figure 19B [description], a planarization process is performed to remove the excess portion of the gate mask layer 114 that extends above the first ILD 86. The ILD mask 88 can also be removed by the planarization process, thereby exposing the first ILD 86. The remaining portion of the gate mask layer 114 thus forms a gate mask 116 that contacts the top surface of the gate electrode 102. The subsequently formed gate contact passes through the gate mask 98 and / or 116 to contact the top surface of the gate electrode 102.

[0063] In Figure 20A and Figure 20B [description], a second ILD 118 is deposited over the first ILD 86. In some embodiments, the second ILD 118 is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD 118 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD and PECVD.

[0064] Then, gate contacts 120 and source / drain contacts 122 are formed through the second ILD 118 and the first ILD 86. Openings for the source / drain contacts 122 are formed through the first ILD 86 and the second ILD 118, and openings for the gate contacts 120 are formed through the second ILD 118 and the gate masks 98 and / or 116. The openings can be formed using acceptable lithography and etching techniques. A liner (e.g., a diffusion barrier layer, an adhesion layer, etc.) and a conductive material are formed in the openings. The liner can include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material can be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP can be performed to remove excess material from the surface of the second ILD 118. The remaining liner and conductive material form the source / drain contacts 122 and the gate contacts 120 in the openings. An annealing process can be performed to form a silicide at the interface between the epitaxial source / drain region 82 and the source / drain contacts 122. The source / drain contacts 122 are physically and electrically coupled to the epitaxial source / drain region 82, and the gate contacts 120 are physically and electrically coupled to the gate electrode 102. The source / drain contacts 122 and the gate contacts 120 can be formed using different processes or can be formed using the same process. Although shown as being formed in the same cross-section, it should be understood that each of the source / drain contacts 122 and the gate contacts 120 can be formed in different cross-sections, which can avoid short-circuiting of the contacts.

[0065] Figures 21A to 23B are various views of an intermediate stage in FinFET fabrication according to some other embodiments. Figure 21A 、 Figure 22A and Figure 23A are cross-sectional views taken along the Figure 1 reference cross-section A-A shown in Figure 21B 、 Figure 22B and Figure 23B are cross-sectional views taken along the Figure 1 reference cross-section B-B shown in

[0066] Figure 21A and Figure 21B show structures in a similar intermediate processing stage as shown in Figure 14A and Figure 14B In this embodiment, the top surface of the ILD mask 88 extends higher than the top surface of the gate mask 98. Thus, in this embodiment, the second fill layer 108 also has a groove 108R located above the gate mask 98.

[0067] In Figure 22A and Figure 22BIn , a first planarization process 112A is performed to remove the excess portion of the second fill layer 108 that is above the top surface of the first fill layer 104. Details regarding the first planarization process 112A have been described above and will not be repeated.

[0068] In Figure 23A and Figure 23B a second planarization process 112B is performed to remove the excess portions of the first fill layer 104 and the isolation features 110 that are above the top surface of the ILD mask 88. Details regarding the second planarization process 112B have been described above and will not be repeated. After the second planarization process 112B, the gate mask 98 remains covered by the remaining portion of the first fill layer 104. Then, further processing can be performed as described above with respect to Figures 17A to 20B to form a FinFET device.

[0069] Figures 24A to 26B are various views of an intermediate stage in the FinFET fabrication according to some other embodiments. Figure 24A 、 Figure 25A and Figure 26A are cross-sectional views taken along the reference cross-section A-A shown in Figure 1 except for the multiple fins / FinFETs. Figure 24B 、 Figure 25B and Figure 26B are cross-sectional views taken along the reference cross-section B-B shown in Figure 1 except for the multiple fins / FinFETs.

[0070] Figure 24A and Figure 24B show structures in a similar intermediate processing stage as shown in Figure 12A and Figure 12B In this embodiment, no opening 106 is formed in the first fill layer 104. Thus, no second fill layer 108 and isolation features 110 are formed. The first fill layer 104 can be formed to have a large average thickness T that is above the ILD mask 88 1 . For example, the average thickness T 1 can be in the range of about to about .

[0071] In Figure 25A and Figure 25BIn this process, a first planarization process 112A is performed to planarize the top surface of the first fill layer 104. The first planarization process 112A is stopped while the first fill layer 104 remains above the underlying features. The first planarization process 112A can be performed until the first fill layer 104 has a small average thickness T remaining above the ILD mask 88. 2 For example, the average thickness T 2 can be in the range of about to about . The first planarization process 112A can be timed to ensure that it stops after removing a desired amount of material, especially when a CMP stop layer is not used. For example, the first planarization process 112A can be performed for a duration in the range of about 50 seconds to about 120 seconds.

[0072] In Figure 26A and Figure 26B , a second planarization process 112B is performed to remove the excess portion of the first fill layer 104 that is above the top surface of the ILD mask 88. The second planarization process 112B can also remove portions of the ILD mask 88 and the gate mask 98. Details regarding the second planarization process 112B have been described above and will not be repeated. Then, further processing can be performed as described above with respect to Figures 17A to 20B to form a FinFET device.

[0073] Embodiments can achieve advantages. Due to the pattern loading caused by the channel regions 58 of different lengths, the first fill layer 104 and the second fill layer 108 may have non-uniform CMP removal rates. The increase in the surface roughness of the gate mask 98 caused by etching back the gate electrode 102 may exacerbate the non-uniformity of the CMP removal rate. Performing the first planarization process 112A (e.g., CMP) helps to initially reset the flatness of the structure. Performing the second planarization process 112B (e.g., etching back) helps to transfer the reset planar topography to the underlying features, such as the ILD 86 and the gate mask 98. Therefore, the planarization efficiency in subsequent processes can be improved. In addition, forming the gate mask 98 for the longer channel regions 58 can help reduce the pattern loading effect during the MEOL process, thereby reducing the chance of over-etching / under-etching when forming the gate contacts 120.

[0074] In an embodiment, a method includes: forming fins extending from a substrate; forming a first gate mask over the fins, the first gate mask having a first width; forming a second gate mask over the fins, the second gate mask having a second width, the second width being greater than the first width; depositing a first fill layer over the first gate mask and the second gate mask; depositing a second fill layer over the first fill layer; planarizing the second fill layer using a chemical mechanical polishing (CMP) process, performing the CMP process until the first fill layer is exposed. Planarizing the remaining portion of the second fill layer and the first fill layer using an etch-back process, the etch-back process etching the materials of the first fill layer, the second fill layer, the first gate mask, and the second gate mask at the same rate.

[0075] In some embodiments, the method further includes: patterning a first interlayer dielectric (ILD) with a first opening and a second opening, the first opening and the second opening exposing the fins; forming an ILD mask over the first ILD; depositing a gate dielectric layer in the first opening and the second opening; forming a gate electrode layer over the gate dielectric layer; depositing a gate mask layer over the gate electrode layer; planarizing the gate mask layer to form a first gate mask in the first opening and a second gate mask in the second opening. In some embodiments of the method, before the etch-back process, the uppermost surfaces of the first gate mask and the second gate mask extend above the uppermost surface of the ILD mask. In some embodiments of the method, after the etch-back process, the uppermost surfaces of the first gate mask, the second gate mask, the ILD mask, and the first fill layer are flush. In some embodiments of the method, before the etch-back process, the uppermost surface of the ILD mask extends above the uppermost surfaces of the first gate mask and the second gate mask. In some embodiments of the method, after the etch-back process, the uppermost surfaces of the ILD mask and the first fill layer are flush, and after the etch-back process, the first fill layer covers the first gate mask and the second gate mask. In some embodiments, the method further includes: etching back the gate electrode layer and the gate dielectric layer to form a first gate dielectric and a first gate electrode in the first opening, and a second gate dielectric and a second gate electrode in the second opening. In some embodiments, the method further includes: after the etch-back process, removing the first fill layer to expose portions of the first gate electrode and the second gate electrode, the first gate mask and the second gate mask remaining over the unexposed portions of the first gate electrode and the second gate electrode, respectively. In some embodiments, the method further includes: forming a third gate mask over the exposed portion of the first gate electrode; and forming a fourth gate mask over the exposed portion of the second gate electrode.

[0076] In an embodiment, a method includes: forming fins extending from a substrate; forming a first gate mask over the fins, the first gate mask having a first width; forming a second gate mask over the fins, the second gate mask having a second width greater than the first width; depositing a fill layer over the first gate mask and the second gate mask; planarizing the fill layer using a chemical mechanical polishing (CMP) process; and after the CMP process, planarizing the fill layer using an etch-back process that etches the materials of the fill layer, the first gate mask, and the second gate mask at the same rate.

[0077] In some embodiments, the method further includes: forming a first interlayer dielectric (ILD) over the fins; patterning the first ILD with a first opening and a second opening; forming a first gate mask in the first opening and a second gate mask in the second opening; and forming an ILD mask over the first ILD. In some embodiments of the method, after the etch-back process, the top surfaces of the ILD mask and the fill layer are flush. In some embodiments of the method, after the etch-back process, the top surfaces of the first gate mask and the second gate mask are flush with the top surfaces of the ILD mask and the fill layer. In some embodiments of the method, after the etch-back process, the fill layer covers the first gate mask and the second gate mask.

[0078] In an embodiment, a method includes: forming fins extending from a substrate; forming a first gate stack over a first channel region of the fins; forming a second gate stack over a second channel region of the fins, the second channel region of the fins having a different length than the first channel region of the fins; depositing a first fill layer over the first gate stack and the second gate stack; patterning the first fill layer; etching an opening in the first gate stack using the patterned first fill layer as an etch mask; depositing a second fill layer in the opening and over the first fill layer; polishing the second fill layer until portions of the first fill layer are exposed; and etching the remaining portion of the second fill layer and the first fill layer using a non-selective etch-back process, after which the top surfaces of the remaining portion of the second fill layer and the first fill layer are flush.

[0079] In some embodiments of the method, the non-selective etch-back process is a dry etch performed in an oxygen-free environment. In some embodiments of the method, the dry etch is performed using a gas source including NF 3 、H 2 and Ar. In some embodiments of the method, NF 3 in the gas source and H 2The ratio is in the range of 0.5:1 to 1.125:1. In some embodiments of the method, the dry etching is performed by generating a plasma using a gas source, and the plasma is generated at a pressure in the range of 200 mT to 2500 mT and at a temperature in the range of 15 °C to 85 °C using an RF power in the range of 200 W to 1000 W. In some embodiments of the method, the first fill layer is formed of silicon, the second fill layer is formed of silicon nitride, and the etching rate ratio of silicon nitride to silicon in the non-selective etch-back process is in the range of 0.9 to 1.5.

[0080] The features of several embodiments are outlined above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructs do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

[0081] Example 1. A method of manufacturing a semiconductor device, comprising: forming fins extending from a substrate; forming a first gate mask over the fins, the first gate mask having a first width; forming a second gate mask over the fins, the second gate mask having a second width greater than the first width; depositing a first fill layer over the first gate mask and the second gate mask; depositing a second fill layer over the first fill layer; planarizing the second fill layer using a chemical mechanical polishing (CMP) process, performing the CMP process until the first fill layer is exposed; and planarizing the remaining portion of the second fill layer and the first fill layer using an etch-back process that etches the materials of the first fill layer, the second fill layer, the first gate mask, and the second gate mask at the same rate.

[0082] Example 2. The method according to Example 1, further comprising: patterning a first interlayer dielectric (ILD) with a first opening and a second opening that expose the fins; forming an ILD mask over the first ILD; depositing a gate dielectric layer in the first opening and the second opening; forming a gate electrode layer over the gate dielectric layer; depositing a gate mask layer over the gate electrode layer; and planarizing the gate mask layer to form the first gate mask in the first opening and the second gate mask in the second opening.

[0083] Example 3. The method according to Example 2, wherein, before the etch-back process, the uppermost surfaces of the first gate mask and the second gate mask extend above the uppermost surface of the ILD mask.

[0084] Example 4. The method according to Example 3, wherein, after the etch-back process, the uppermost surfaces of the first gate mask, the second gate mask, the ILD mask, and the first fill layer are flush.

[0085] Example 5. The method according to Example 2, wherein, before the etch-back process, the uppermost surface of the ILD mask extends above the uppermost surfaces of the first gate mask and the second gate mask.

[0086] Example 6. The method according to Example 5, wherein, after the etch-back process, the uppermost surfaces of the ILD mask and the first fill layer are flush, and after the etch-back process, the first fill layer covers the first gate mask and the second gate mask.

[0087] Example 7. The method according to Example 2, further comprising: etching the gate electrode layer and the gate dielectric layer to form a first gate dielectric and a first gate electrode in the first opening and a second gate dielectric and a second gate electrode in the second opening.

[0088] Example 8. The method according to Example 7, further comprising: after the etch-back process, removing the first fill layer to expose portions of the first gate electrode and the second gate electrode, and the first gate mask and the second gate mask are respectively retained above the unexposed portions of the first gate electrode and the second gate electrode.

[0089] Example 9. The method according to Example 8, further comprising: forming a third gate mask above the exposed portion of the first gate electrode; and forming a fourth gate mask above the exposed portion of the second gate electrode.

[0090] Example 10. A method of manufacturing a semiconductor device, comprising: forming fins extending from a substrate; forming a first gate mask above the fins, the first gate mask having a first width; forming a second gate mask above the fins, the second gate mask having a second width greater than the first width; depositing a fill layer above the first gate mask and the second gate mask; planarizing the fill layer using a chemical mechanical polishing (CMP) process; and after the CMP process, planarizing the fill layer using an etch-back process that etches the materials of the fill layer, the first gate mask, and the second gate mask at the same rate.

[0091] Example 11. The method according to Example 10 further includes: forming a first interlayer dielectric (ILD) over the fin; patterning the first ILD with a first opening and a second opening; forming the first gate mask in the first opening and forming the second gate mask in the second opening; and forming an ILD mask over the first ILD.

[0092] Example 12. The method according to Example 11, wherein after the etch-back process, the uppermost surfaces of the ILD mask and the fill layer are flush.

[0093] Example 13. The method according to Example 12, wherein after the etch-back process, the uppermost surfaces of the first gate mask and the second gate mask are flush with the uppermost surfaces of the ILD mask and the fill layer.

[0094] Example 14. The method according to Example 12, wherein after the etch-back process, the fill layer covers the first gate mask and the second gate mask.

[0095] Example 15. A method of manufacturing a semiconductor device includes: forming fins extending from a substrate; forming a first gate stack over a first channel region of the fin; forming a second gate stack over a second channel region of the fin, the second channel region of the fin having a different length from the first channel region of the fin; depositing a first fill layer over the first gate stack and the second gate stack; patterning the first fill layer; using the patterned first fill layer as an etch mask to etch an opening in the first gate stack; depositing a second fill layer in the opening and over the first fill layer; polishing the second fill layer until a portion of the first fill layer is exposed; and etching a remaining portion of the second fill layer and the first fill layer using a non-selective etch-back process, after the non-selective etch-back process, the uppermost surfaces of the remaining portion of the second fill layer and the first fill layer are flush.

[0096] Example 16. The method according to Example 15, wherein the non-selective etch-back process is a dry etch performed in an oxygen-free environment.

[0097] Example 17. The method according to Example 16, wherein the dry etch is performed using a gas source including NF 3 、H 2 and Ar.

[0098] Example 18. The method according to Example 17, wherein in the gas source, NF 3 and H 2The ratio is in the range of 0.5:1 to 1.125:1.

[0099] Example 19. The method according to Example 17, wherein the dry etching is performed by generating a plasma using the gas source, and the plasma is generated at a pressure in the range of 200 mT to 2500 mT and at a temperature in the range of 15 °C to 85 °C using an RF power in the range of 200 W to 1000 W.

[0100] Example 20. The method according to Example 15, wherein the first filling layer is formed of silicon, the second filling layer is formed of silicon nitride, and the etching rate ratio of silicon nitride to silicon in the non-selective etch-back process is in the range of 0.9:1 to 1.5:1.

Claims

1. A method of manufacturing a semiconductor device, comprising: forming a dielectric material over a first source / drain region and a second source / drain region; forming a first gate mask adjacent to the first source / drain region, the first gate mask having a first width; forming a second gate mask adjacent to the second source / drain region, the second gate mask having a second width greater than the first width; depositing a first fill layer over the first gate mask and the second gate mask; depositing a second fill layer over the first fill layer; planarizing the second fill layer using a chemical mechanical polishing (CMP) process, performing the CMP process until the first fill layer is exposed; and planarizing the remaining portion of the second fill layer and the first fill layer using an etch-back process, the etch-back process etching the materials of the first fill layer, the second fill layer, the first gate mask, and the second gate mask at the same rate, wherein, after the etch-back process, the uppermost surfaces of the dielectric material and the first fill layer are flush.

2. The method according to claim 1, further comprising: patterning a first interlayer dielectric (ILD) with a first opening and a second opening, wherein the dielectric material includes an ILD mask over the first interlayer dielectric (ILD); depositing a gate dielectric layer in the first opening and the second opening; forming a gate electrode layer over the gate dielectric layer; depositing a gate mask layer over the gate electrode layer; and planarizing the gate mask layer to form the first gate mask in the first opening and the second gate mask in the second opening.

3. The method according to claim 2, wherein, before the etch-back process, the uppermost surfaces of the first gate mask and the second gate mask extend above the uppermost surface of the ILD mask.

4. The method according to claim 3, wherein, after the etch-back process, the uppermost surfaces of the first gate mask, the second gate mask, the ILD mask, and the first fill layer are flush.

5. The method according to claim 2, wherein, before the etch-back process, the uppermost surface of the ILD mask extends above the uppermost surfaces of the first gate mask and the second gate mask.

6. The method according to claim 5, wherein, after the etch-back process, the uppermost surfaces of the ILD mask and the first fill layer are flush, and after the etch-back process, the first fill layer covers the first gate mask and the second gate mask.

7. The method according to claim 2, further comprising: etching the gate electrode layer and the gate dielectric layer to form a first gate dielectric and a first gate electrode in the first opening and a second gate dielectric and a second gate electrode in the second opening.

8. The method according to claim 7, further comprising: After the etch-back process, the first fill layer is removed to expose portions of the first gate electrode and the second gate electrode, and the first gate mask and the second gate mask are respectively retained over unexposed portions of the first gate electrode and the second gate electrode.

9. The method of claim 8, further comprising: forming a third gate mask over the exposed portion of the first gate electrode; and forming a fourth gate mask over the exposed portion of the second gate electrode.

10. A method of manufacturing a semiconductor device, comprising: forming fins extending from a substrate; forming a first interlayer dielectric (ILD) over the fins; forming an ILD mask over the first ILD; patterning the first ILD to have a first opening and a second opening; forming a first gate mask in the first opening, the first gate mask having a first width; forming a second gate mask in the second opening, the second gate mask having a second width greater than the first width; depositing a fill layer over the first gate mask and the second gate mask; planarizing the fill layer using a chemical mechanical polishing (CMP) process; and after the CMP process, planarizing the fill layer using an etch-back process that etches the fill layer, the first gate mask, and the second gate mask materials at the same rate, wherein after the etch-back process, the top surfaces of the ILD mask and the fill layer are flush.

11. The method of claim 10, wherein after the etch-back process, the top surfaces of the first gate mask and the second gate mask are flush with the top surfaces of the ILD mask and the fill layer.

12. The method of claim 10, wherein after the etch-back process, the fill layer covers the first gate mask and the second gate mask.

13. A method of manufacturing a semiconductor device, comprising: forming fins extending from a substrate; forming a first gate stack over a first channel region of the fins; forming a second gate stack over a second channel region of the fins, the second channel region of the fins having a different length than the first channel region of the fins; depositing a first fill layer over the first gate stack and the second gate stack; patterning the first fill layer; using the patterned first fill layer as an etch mask to etch an opening in the first gate stack; depositing a second fill layer in the opening and over the first fill layer; polishing the second fill layer until a portion of the first fill layer is exposed; and etching the remaining portion of the second fill layer and the first fill layer using a non-selective etch-back process, wherein after the non-selective etch-back process, the top surfaces of the remaining portion of the second fill layer and the first fill layer are flush.

14. The method of claim 13, wherein the non-selective etch-back process is a dry etch performed in an oxygen-free environment.

15. The method according to claim 14, wherein, The dry etching is performed using a gas source including NF 3 , H 2 and Ar.

16. The method according to claim 15, wherein, The ratio of NF 3 in the gas source to H 2 is in the range of 0.5:1 to 1.125:

1.

17. The method according to claim 15, wherein, the dry etching is performed by generating a plasma using the gas source, and the plasma is generated at a pressure in the range of 200 mT to 2500 mT and at a temperature in the range of 15 °C to 85 °C using an RF power in the range of 200 W to 1000 W.

18. The method according to claim 13, wherein, the first filling layer is formed of silicon, the second filling layer is formed of silicon nitride, and the etching rate ratio of silicon nitride to silicon in the non-selective etch-back process is in the range of 0.9:1 to 1.5:1.

Images