A multi-chip parallel power module

Abstract

The present invention discloses a multi-chip parallel power module. The upper power module in the multi-chip parallel power module includes a copper-clad ceramic substrate unit, a signal collection area unit, and a chip parallel unit; the lower power module has the same structure as the upper power module; the copper-clad ceramic substrate unit includes a gate copper-clad ceramic substrate, an auxiliary source copper-clad ceramic substrate, a drain copper-clad ceramic substrate, and a source copper-clad ceramic substrate; the signal collection area unit includes a gate signal collection area, an auxiliary source signal collection area, and a source signal collection area; the drain signal collection area is provided on the copper clad surface of the drain copper-clad ceramic substrate of the upper power module; the MOSFET chip parallel group in the chip parallel unit includes n MOSFET chips connected in parallel and arranged circumferentially; the gate, source, auxiliary source, and drain of the MOSFET chip are respectively connected to corresponding signal collection areas. The present invention solves the problem of unbalanced current distribution between parallel chips.

Description

Technical Field

[0001] The present invention relates to the field of module packaging, and in particular to a multi-chip parallel power module. Background Art

[0002] Silicon carbide (SiC) material offers the advantages of a wide bandgap, a large critical electric field, and high thermal conductivity, enabling SiC devices to meet the demands of high frequency, high temperature, and high power density. Among various SiC devices, SiC MOSFETs, due to their fast switching speed and low on-state resistance, are expected to replace silicon MOSFETs and IGBTs in applications such as electric vehicle chargers, photovoltaic inverters, and high-voltage circuit breakers. However, the production process for SiC MOSFETs is currently less mature than that for silicon-based devices. Larger chip sizes result in lower production yields and higher prices. To balance current rating with chip cost, the current rating of a single SiC MOSFET chip is relatively low. For high-current applications, equipment developers have resorted to paralleling multiple devices or multi-chip modules as an alternative solution. Current welded power modules utilize multiple chips in parallel to achieve higher current ratings. However, as the number of paralleled chips increases, the stray inductance becomes unevenly distributed, leading to uneven current distribution among the paralleled chips within the power module. Summary of the Invention

[0003] Based on this, it is necessary to provide a multi-chip parallel power module to solve the problem of uneven current distribution between parallel chips caused by uneven distribution of stray inductance in the power module.

[0004] To achieve the above object, the present invention provides the following solutions:

[0005] A multi-chip parallel power module, comprising: an upper power module, a lower power module and a drain signal collection area;

[0006] The upper power module includes a copper-clad ceramic substrate unit, a signal collection area unit and a chip parallel unit; the lower power module has the same structure as the upper power module;

[0007] The copper-clad ceramic substrate unit includes a gate copper-clad ceramic substrate, an auxiliary source copper-clad ceramic substrate, a drain copper-clad ceramic substrate and a source copper-clad ceramic substrate; the gate copper-clad ceramic substrate, the auxiliary source copper-clad ceramic substrate and the drain copper-clad ceramic substrate are all semi-annular structures, and the source copper-clad ceramic substrate is a circular structure; the gate copper-clad ceramic substrate, the auxiliary source copper-clad ceramic substrate and the drain copper-clad ceramic substrate are concentric and radially arranged in sequence from the outside to the inside; the source copper-clad ceramic substrate is located in an area semi-enclosed by the drain copper-clad ceramic substrate and is spaced from the drain copper-clad ceramic substrate;

[0008] The signal collection area unit includes a gate signal collection area, an auxiliary source signal collection area, and a source signal collection area; the gate signal collection area is provided on the copper clad of the gate copper-clad ceramic substrate; the auxiliary source signal collection area is provided on the copper clad of the auxiliary source copper-clad ceramic substrate; the source signal collection area is provided on the copper clad of the source copper-clad ceramic substrate; the signal collection area unit is used to connect the gate drive signal terminal, the auxiliary source drive signal terminal, and the source power signal terminal;

[0009] The drain signal collection area is provided on the copper clad portion of the drain copper-clad ceramic substrate of the upper power module; the drain signal collection area is used to connect the drain power signal terminal;

[0010] The chip parallel unit includes a MOSFET chip parallel group located on the drain copper-clad ceramic substrate; the MOSFET chip parallel group includes n MOSFET chips connected in parallel and arranged circumferentially; the gate of the MOSFET chip parallel group is connected to the gate copper-clad ceramic substrate; the source of the MOSFET chip parallel group is connected to the source copper-clad ceramic substrate; the auxiliary source of the MOSFET chip parallel group is connected to the auxiliary source copper-clad ceramic substrate; the drain of the MOSFET chip parallel group is arranged on the copper clad of the drain copper-clad ceramic substrate;

[0011] The drain copper-clad ceramic substrate in the lower power module is connected to the source signal collection area in the upper power module.

[0012] Optionally, the drain signal collection area unit includes a first signal collection sub-area and a second signal collection sub-area;

[0013] The first signal collection sub-region is located on one side of one of the MOSFET chips on the upper power module, and the second signal collection sub-region is located on the other side of the MOSFET chip.

[0014] Optionally, the chip parallel unit further includes: a silicon carbide diode chip parallel group;

[0015] The parallel group of silicon carbide diode chips is arranged on the drain copper-clad ceramic substrate; the parallel group of silicon carbide diode chips includes n silicon carbide diode chips connected in parallel and arranged circumferentially; the anode of the parallel group of silicon carbide diode chips is connected to the source of the parallel group of MOSFET chips, the anode of the parallel group of silicon carbide diode chips is connected to the source copper-clad ceramic substrate, and the cathode of the parallel group of silicon carbide diode chips is arranged on the copper clad of the drain copper-clad ceramic substrate.

[0016] Optionally, the multi-chip parallel power module further includes: a signal terminal unit;

[0017] The signal terminal unit includes a gate drive signal terminal, a source power signal terminal, an auxiliary source drive signal terminal and a drain power signal terminal; the gate drive signal terminal is arranged in the gate signal collection area; the source power signal terminal is arranged in the source signal collection area; the auxiliary source drive signal terminal is arranged in the auxiliary source signal collection area; and the drain power signal terminal is arranged in the drain signal collection area.

[0018] Optionally, the gate drive signal terminal and the auxiliary source drive signal terminal are both flat structures; the source power signal terminal is a cylindrical structure; and the drain power signal terminal is a flat structure.

[0019] Optionally, the MOSFET chip parallel group includes 5 MOSFET chips connected in parallel and evenly arranged along the circumferential direction; the angle between two adjacent MOSFET chips is 45 degrees.

[0020] Optionally, the parallel group of silicon carbide diode chips includes 5 silicon carbide diode chips connected in parallel and evenly arranged along the circumferential direction; the angle between two adjacent silicon carbide diode chips is 45 degrees.

[0021] Optionally, the multi-chip parallel power module further includes: bonding wires;

[0022] The gate of the parallel group of MOSFET chips is connected to the gate copper-clad ceramic substrate through the bonding wire; the source of the parallel group of MOSFET chips is connected to the source copper-clad ceramic substrate through the bonding wire; the auxiliary source of the parallel group of MOSFET chips is connected to the auxiliary source copper-clad ceramic substrate through the bonding wire;

[0023] The drain copper-clad ceramic substrate in the lower power module is connected to the source signal collection area in the upper power module through the bonding wire;

[0024] The anode of the parallel group of silicon carbide diode chips is connected to the source of the parallel group of MOSFET chips through the bonding wire, and the anode of the parallel group of silicon carbide diode chips is connected to the source copper-clad ceramic substrate through the bonding wire.

[0025] Optionally, the parallel group of MOSFET chips and the diode chip are both welded on the drain copper-clad ceramic substrate.

[0026] Optionally, the gate drive signal terminal is welded in the gate signal collection area; the source power signal terminal is welded in the source signal collection area; the auxiliary source drive signal terminal is welded in the auxiliary source signal collection area; and the drain power signal terminal is welded in the drain signal collection area.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] The present invention proposes a multi-chip parallel power module, in which n metal-oxide semiconductor field-effect transistor (MOSFET) chips connected in parallel in an upper power module and a lower power module are arranged in a 180-degree semicircular layout, thereby improving the source symmetry of the parallel-connected MOSFET chips, reducing the distribution difference of the source stray inductance, and eliminating the influence of the common branch impedance coupling effect, thereby reducing the transient unbalanced current between the parallel chips and achieving better power module current sharing characteristics; the upper power module and the lower power module adopt an oblong structure, and the upper power module and the lower power module can be arranged in the same plane, reducing the complexity of the power module design and improving the convenience of installation. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0030] Figure 1 A structural diagram of a multi-chip parallel power module provided by an embodiment of the present invention;

[0031] Figure 2 A structural diagram of an upper power module provided in an embodiment of the present invention;

[0032] Figure 3 A structural diagram of a lower power module provided in an embodiment of the present invention;

[0033] Figure 4 A schematic diagram illustrating the principle of a double-pulse test circuit for a multi-chip parallel power module provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0034] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0035] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0036] Figure 1 This is a structural diagram of a multi-chip parallel power module provided by an embodiment of the present invention. Figure 1 The multi-chip parallel power module of this embodiment includes: an upper power module 1, a lower power module 2, and a drain signal collection area 14. The lower power module 2 has the same structure as the upper power module 1.

[0037] Figure 2 This is a structural diagram of the upper power module provided by an embodiment of the present invention. Figure 2 The upper power module includes a copper-clad ceramic substrate unit, a signal collection area unit and a chip parallel unit.

[0038] The copper-clad ceramic substrate unit includes a gate copper-clad ceramic substrate 10, an auxiliary source copper-clad ceramic substrate 11, a source copper-clad ceramic substrate 12 and a drain copper-clad ceramic substrate 13; the gate copper-clad ceramic substrate 10, the auxiliary source copper-clad ceramic substrate 11 and the drain copper-clad ceramic substrate 13 are all semi-annular structures, and the source copper-clad ceramic substrate 12 is a circular structure; the gate copper-clad ceramic substrate 10, the auxiliary source copper-clad ceramic substrate 11 and the drain copper-clad ceramic substrate 13 are concentric and arranged radially from the outside to the inside in sequence; the source copper-clad ceramic substrate 12 is located in an area semi-enclosed by the drain copper-clad ceramic substrate 13 and is spaced from the drain copper-clad ceramic substrate 13.

[0039] The signal collection area unit includes a gate signal collection area 16, a source signal collection area 15, and an auxiliary source signal collection area 17. The gate signal collection area 16 is located on the copper clad of the gate copper-clad ceramic substrate 10. The source signal collection area 15 is located at the center of the copper clad of the source copper-clad ceramic substrate 12. The auxiliary source signal collection area 17 is located on the copper clad of the auxiliary source copper-clad ceramic substrate 11. The signal collection area unit is used to connect the gate drive signal terminal 4, the auxiliary source drive signal terminal 5, and the power terminal 7. In the upper power module 1, the power terminal 7 is a source power signal terminal; in the lower power module 2, the power terminal 7 is a drain power signal terminal.

[0040] The drain signal collection area 14 is provided on the copper clad portion of the drain copper-clad ceramic substrate 13 of the upper power module 1 ; the drain signal collection area 14 is used to connect to the drain power signal terminal 6 .

[0041] The chip parallel unit includes a silicon carbide MOSFET chip parallel group 8; the MOSFET chip parallel group 8 includes n MOSFET chips connected in parallel and arranged circumferentially; the MOSFET chip parallel group 8 is disposed on the drain copper-clad ceramic substrate 13; the gate of the MOSFET chip parallel group 8 is connected to the gate copper-clad ceramic substrate 10 via a bonding wire 3; the auxiliary source of the MOSFET chip parallel group 8 is connected to the auxiliary source copper-clad ceramic substrate 11 via a bonding wire 3; the drain of the MOSFET chip parallel group 8 is disposed on the copper clad portion of the drain copper-clad ceramic substrate 13; and the source of the MOSFET chip parallel group 8 is connected to the source copper-clad ceramic substrate 12. In practical applications, the MOSFET chip parallel group 8 can include five MOSFET chips connected in parallel and evenly arranged circumferentially (evenly arranged over a semicircle of 180 degrees), with the angle between two adjacent MOSFET chips being 45 degrees; and the MOSFET chips can be silicon carbide MOSFET chips.

[0042] As an optional embodiment, the drain signal collection area unit 14 includes a first signal collection sub-area and a second signal collection sub-area; the first signal collection sub-area is located on one side of a MOSFET chip on the upper power module, and the second signal collection sub-area is located on the other side of the MOSFET chip. In actual application, when the MOSFET chip parallel group 8 includes five MOSFET chips, the drain signal collection area 14 is located on both sides of the third MOSFET chip on the copper clad surface of the drain copper-clad ceramic substrate 13, as shown in Figure 2.

[0043] As an optional embodiment, the chip parallel unit further includes: a silicon carbide diode chip parallel group 9; the silicon carbide diode chip parallel group is arranged on the drain copper-clad ceramic substrate 13; the silicon carbide diode chip parallel group 9 includes n silicon carbide diode chips connected in parallel and arranged circumferentially; the cathode of the silicon carbide diode chip parallel group 9 is arranged on the copper clad of the drain copper-clad ceramic substrate 13; the anode of the silicon carbide diode chip parallel group 9 is connected to the source copper-clad ceramic substrate 12 via a bonding wire 3; and the anode of the silicon carbide diode chip parallel group 9 is connected to the source of the MOSFET chip parallel group 8 via a bonding wire 3. In actual applications, the silicon carbide diode chip parallel group 9 can be five silicon carbide diode chips connected in parallel and evenly arranged circumferentially (evenly arranged in a semicircle of 180 degrees), and the angle between two adjacent silicon carbide diode chips is 45 degrees. The cathode of the parallel diode chip group 9 and the drain of the parallel MOSFET chip group 8 are both arranged on the copper clad of the drain copper-clad ceramic substrate 13, so the cathode of the parallel diode chip group 9 and the drain of the parallel MOSFET chip group 8 are electrically connected. Figure 2 As shown, the drains of the five MOSFET chips and the cathodes of the five diode chips are all welded on the copper clad of the drain copper-clad ceramic substrate 13 , so the drains of the MOSFET chips and the cathodes of the diode chips are connected.

[0044] As an optional embodiment, the multi-chip parallel power module further includes: a signal terminal unit; the signal terminal unit includes a gate drive signal terminal 4, an auxiliary source drive signal terminal 5, a drain power signal terminal 6 and a source power signal terminal; the gate drive signal terminal 4 is arranged in the gate signal collection area 16; the source power signal terminal is arranged in the source signal collection area 15; the auxiliary source drive signal terminal 5 is arranged in the auxiliary source signal collection area 17; the drain power signal terminal 6 is arranged in the drain signal collection area 14; the gate drive signal terminal 4, the auxiliary source drive signal terminal 5 and the drain power signal terminal 6 are flat structures; the source power signal terminal is a cylindrical structure. In actual applications, a square-structured gasket can be set on each signal terminal to facilitate the installation of screws.

[0045] As an optional embodiment, the parallel group of MOSFET chips 8 and the parallel group of silicon carbide diode chips 9 are both soldered to the drain copper-clad ceramic substrate 13. The gate drive signal terminal 4 is soldered within the gate signal collection area 16; the source power signal terminal is soldered within the source signal collection area 15; the auxiliary source drive signal terminal 5 is soldered within the auxiliary source signal collection area 17; and the drain power signal terminal 6 is soldered within the drain signal collection area 14.

[0046] Figure 3 This is a structural diagram of the lower power module provided by an embodiment of the present invention. Figure 3 The gate signal collection area 31 of the lower power module 2 is located on the copper clad portion of the gate copper-clad ceramic substrate 29 of the lower power module 2. The source signal collection area 24 of the lower power module 2 is located on the copper clad portion of the source copper-clad ceramic substrate 22 of the lower power module 2. The auxiliary source signal collection area 27 of the lower power module 2 is located on the copper clad portion of the auxiliary source copper-clad ceramic substrate 25 of the lower power module 2. The drain signal collection area of ​​the lower power module 2 is identical to the source signal collection area 15 of the upper power module 1, sharing the same power terminal. Therefore, the drain copper-clad ceramic substrate 19 of the lower power module 2 is connected to the source signal collection area of ​​the upper power module.

[0047] The MOSFET chip parallel group 23 of the lower power module 2 is five MOSFET chips connected in parallel and arranged in a 180-degree semicircular layout; the MOSFET chip parallel group 23 of the lower power module 2 is arranged on the drain copper-clad ceramic substrate 19 of the lower power module 2; the gate of the MOSFET chip parallel group 23 of the lower power module 2 is connected to the gate copper-clad ceramic substrate 29 of the lower power module 2 through a bonding wire 3; the source of the MOSFET chip parallel group 23 of the lower power module 2 is connected to the source copper-clad ceramic substrate 22 of the lower power module 2 through a bonding wire 3; the auxiliary source of the MOSFET chip parallel group 23 of the lower power module 2 is connected to the auxiliary source copper-clad ceramic substrate 25 of the lower power module 2 through a bonding wire 3; the drain of the MOSFET chip parallel group 23 of the lower power module 2 is arranged on the copper clad of the drain copper-clad ceramic substrate 19 of the lower power module 2. The diode chip parallel group 21 of the lower power module 2 comprises five silicon carbide diode chips connected in parallel and arranged in a 180-degree semicircular layout. The cathode of the diode chip parallel group 21 of the lower power module 2 is located on the drain copper-clad ceramic substrate 19 of the lower power module 2. The anode of the diode chip parallel group 21 of the lower power module 2 is connected to the source of the MOSFET chip parallel group 23 of the lower power module 2 via a bonding wire 3, and the anode of the diode chip parallel group 21 of the lower power module 2 is connected to the source copper-clad ceramic substrate 22 of the lower power module 2 via a bonding wire 3. The cathode of the diode chip parallel group 21 of the lower power module 2 and the drain of the MOSFET chip parallel group 23 of the lower power module 2 are both located on the copper clad of the drain copper-clad ceramic substrate 19 of the lower power module 2, so that the cathode of the diode chip parallel group 21 of the lower power module 2 and the drain of the MOSFET chip parallel group 23 of the lower power module 2 are electrically connected.

[0048] The gate drive signal terminal 30 of the lower power module 2 is located in the gate signal collection area 31 of the lower power module 2; the source power signal terminal 28 of the lower power module 2 is located in the source signal collection area 24 of the lower power module 2; the auxiliary source drive signal terminal 26 of the lower power module 2 is located in the auxiliary source signal collection area 27 of the lower power module 2; and the drain power signal terminal of the lower power module 2 is located in the drain signal collection area 20 of the lower power module 2. The gate drive signal terminal 30 of the lower power module 2 and the auxiliary source drive signal terminal 26 of the lower power module 2 are flat structures, and the drain power signal terminal of the lower power module 2 and the source power signal terminal 28 of the lower power module 2 are cylindrical structures. The angular spacing between the five MOSFET chips of the lower power module 2, which are connected in parallel and arranged in a 180-degree semicircular pattern, is 45 degrees, and the angular spacing between the five diode chips of the lower power module 2, which are connected in parallel and arranged in a 180-degree semicircular pattern, is 45 degrees.

[0049] In practical applications, the multi-chip parallel power module in the above embodiment can be laid out in the following manner:

[0050] A silicon carbide MOSFET chip area is set on the drain copper-clad ceramic substrate 13 of the upper power module 1; a gate signal collection area 16 is set on the copper clad of the gate copper-clad ceramic substrate 10 of the upper power module 1; a source signal collection area 15 is set on the copper clad of the source copper-clad ceramic substrate 12 of the upper power module 1; an auxiliary source signal collection area 17 is set on the copper clad of the auxiliary source copper-clad ceramic substrate 11 of the upper power module 1; and a drain signal collection area 14 is set on the copper clad of the drain copper-clad ceramic substrate 13 of the upper power module 1.

[0051] Five silicon carbide MOSFET chips connected in parallel and arranged in a 180-degree semicircular layout are welded in the silicon carbide MOSFET chip area of ​​the upper power module 1 .

[0052] The gate of the MOSFET chip of the upper power module 1 is connected to the gate copper-clad ceramic substrate 10 through a bonding wire 3; the auxiliary source of the MOSFET chip of the upper power module 1 is connected to the auxiliary source copper-clad ceramic substrate 11 through a bonding wire 3; the source of the MOSFET chip of the upper power module 1 is connected to the source copper-clad ceramic substrate 12 through a bonding wire 3; and the drain of the MOSFET chip of the upper power module 1 is welded to the copper clad of the drain copper-clad ceramic substrate 13.

[0053] A lower power module 2 having the same structure as the upper power module 1 is prepared; the drain signal collection area of ​​the lower power module 2 is the same as the source signal collection area 15 of the upper power module 1 and shares the same power terminal. Therefore, the drain copper-clad ceramic substrate 19 in the lower power module 2 is connected to the source signal collection area in the upper power module through a bonding wire 3.

[0054] In practical applications, it also includes:

[0055] A silicon carbide diode chip area is set on the drain copper-clad ceramic substrate 13 of the upper power module 1; five silicon carbide diode chips connected in parallel and arranged in a 180-degree semicircular layout are welded in the silicon carbide diode chip area; the anode of each silicon carbide diode chip is connected to the source of the MOSFET chip through a bonding wire 3, the anode of each silicon carbide diode chip is connected to the source copper-clad ceramic substrate 12 through a bonding wire 3, and the cathode of each silicon carbide diode chip is welded to the copper clad of the drain copper-clad ceramic substrate 13.

[0056] In practical applications, it also includes:

[0057] The gate drive signal terminal 5 is welded in the gate signal collection area 16 of the upper power module 1; the source power signal terminal is welded in the source signal collection area 15 of the upper power module 1; the auxiliary source drive signal terminal 4 is welded in the auxiliary source signal collection area 17 of the upper power module 1; the drain power signal terminal 6 is welded in the drain signal collection area 14; the gate drive signal terminal 4, the auxiliary source drive signal terminal 5 and the drain power signal terminal 6 are all welded into a flat structure, and the source power signal terminal is welded into a cylindrical structure.

[0058] In practical applications, the five MOSFET chips connected in parallel and arranged in a 180-degree semicircle are spaced 45 degrees apart.

[0059] In practical applications, the five diode chips connected in parallel and arranged in a 180-degree semicircle are spaced 45 degrees apart.

[0060] The five parallel silicon carbide MOSFET chips in the upper power module and the lower power module all adopt a 180-degree semicircular layout, ensuring the symmetrical distribution of the parallel silicon carbide MOSFET sources, reducing the distribution difference of the source stray inductance between chips, and thus improving the uniformity of current distribution.

[0061] The upper power module and the lower power module adopt an oblong structure, and the upper power module and the lower power module can be arranged in the same plane, which reduces the complexity of the power module design and improves the convenience of installation.

[0062] The multi-chip parallel power module of this embodiment can reduce the distribution difference of source stray inductance caused by circuit layout mismatch and common branch impedance coupling effect, and achieve better parallel current sharing characteristics of silicon carbide MOSFETs.

[0063] Figure 4 The schematic diagram of the double pulse test circuit principle of the multi-chip parallel power module provided by the embodiment of the present invention is shown in FIG. Figure 4 , V DC It is a DC voltage source used to power the power circuit of the power module. Figure 4 The circuit represented by the dotted line in the upper middle section is the power circuit, and the circuit represented by the dotted line in the lower middle section is the drive circuit. DC L is the busbar capacitor, used to maintain DC voltage stability. load is the load inductor, D is the five parallel silicon carbide diodes in the upper power module 1, used for freewheeling when the five parallel silicon carbide MOSFETs in the lower power module 2 are turned off. Q1~Q5 are the silicon carbide MOSFET chips of the silicon carbide MOSFET parallel group 23 in the lower power module 2, L d1 is the stray inductance on the drain side of Q1, L s1 is the source side stray inductance of Q1, L g1 is the gate stray inductance of Q1, L as1 is the auxiliary source stray inductance of Q1, L d2 is the stray inductance on the drain side of Q2, L s2 is the source side stray inductance of Q2, L g2 is the gate stray inductance of Q2, L as2 is the auxiliary source stray inductance of Q2, L d3 is the stray inductance on the drain side of Q3, L s3 is the source side stray inductance of Q3, L g3 is the gate stray inductance of Q3, L as3 is the auxiliary source stray inductance of Q3, L d4 is the stray inductance on the drain side of Q4, L s4 is the source side stray inductance of Q4, L g4 is the gate stray inductance of Q4, L as4 is the auxiliary source stray inductance of Q4, L d5 is the stray inductance of Q5 on the drain side, L s5 is the source side stray inductance of Q5, L g5 is the gate stray inductance of Q5, L as5 is the auxiliary source stray inductance of Q5, L d12 is the stray inductance between the drain-side branches of Q1 and Q2, L d23 is the stray inductance between the drain-side branches of Q2 and Q3, L d34is the stray inductance between the drain-side branches of Q3 and Q4, L d45 is the stray inductance between the drain-side branches of Q4 and Q5, i L is the current flowing through the load inductor, i d1 is the current flowing through Q1, i d2 is the current flowing through Q2, i d3 is the current flowing through Q3, i d4 is the current flowing through Q4, i d5 is the current flowing through Q5, i as1 is the auxiliary source current flowing through Q1, i as2 is the auxiliary source current flowing through Q2, i as3 is the auxiliary source current flowing through Q3, i as4 is the auxiliary source current flowing through Q4, i as5 is the auxiliary source current flowing through Q5. V driver It is the gate drive power supply, used to power the drive circuit, R g The following demonstrates how the power module utilizes an oblong circular layout to reduce the source stray inductance differences between parallel devices, thereby achieving better parallel current sharing characteristics for SiC MOSFETs.

[0064] The drain current of a silicon carbide MOSFET chip can be expressed as i d It can be expressed as follows

[0065]

[0066] Among them, g fs is the transconductance of the SiC MOSFET, V gs is the gate-source voltage, V th is the threshold voltage. V gs In the drive circuit, it can be expressed as follows

[0067]

[0068] Since SiC MOSFET is a voltage-controlled device, the required driving current is only a few hundred mA, while the drain current of a single SiC MOSFET chip is tens of amperes. Therefore, the current of the driving circuit is much smaller than the current of the power circuit, and the effect of the driving current on the gate inductance on V can be ignored. gs The impact of V gs It can be simplified to the following expression

[0069]

[0070] The unbalanced current of parallel SiC MOSFET chips can be expressed as follows:

[0071]

[0072] In the multi-chip parallel power module of this embodiment, the parallel silicon carbide MOSFET chips adopt a 180-degree semicircular layout, which ensures the symmetrical distribution of the parallel silicon carbide MOSFET sources, reduces the distribution difference of the source stray inductance between chips, and thus improves the uniformity of current distribution.

[0073] The above principle also applies to n chips. When n chips are connected in parallel, the parallel silicon carbide MOSFET chip group can also adopt a 180-degree semicircular layout to reduce the difference in chip source stray inductance and reduce the transient unbalanced current of parallel devices.

[0074] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0075] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The above examples are only intended to help understand the method and core concept of the present invention. At the same time, those skilled in the art will find that the specific implementation methods and application scopes may vary based on the concept of the present invention. In summary, the contents of this specification should not be construed as limiting the present invention.

Claims

1. A multi-chip parallel power module, characterized in that: include: Upper power module, lower power module and drain signal collection area; The upper power module includes a copper-clad ceramic substrate unit, a signal collection area unit and a chip parallel unit; the lower power module has the same structure as the upper power module; the upper power module and the lower power module adopt an oblong structure; The copper-clad ceramic substrate unit includes a gate copper-clad ceramic substrate, an auxiliary source copper-clad ceramic substrate, a drain copper-clad ceramic substrate and a source copper-clad ceramic substrate; the gate copper-clad ceramic substrate, the auxiliary source copper-clad ceramic substrate and the drain copper-clad ceramic substrate are all semi-annular structures, and the source copper-clad ceramic substrate is a circular structure; the gate copper-clad ceramic substrate, the auxiliary source copper-clad ceramic substrate and the drain copper-clad ceramic substrate are concentric and radially arranged in sequence from the outside to the inside; the source copper-clad ceramic substrate is located in an area semi-enclosed by the drain copper-clad ceramic substrate and is spaced from the drain copper-clad ceramic substrate; The signal collection area unit includes a gate signal collection area, an auxiliary source signal collection area, and a source signal collection area; the gate signal collection area is provided on the copper clad of the gate copper-clad ceramic substrate; the auxiliary source signal collection area is provided on the copper clad of the auxiliary source copper-clad ceramic substrate; the source signal collection area is provided on the copper clad of the source copper-clad ceramic substrate; the signal collection area unit is used to connect the gate drive signal terminal, the auxiliary source drive signal terminal, and the source power signal terminal; The drain signal collection area is provided on the copper clad portion of the drain copper-clad ceramic substrate of the upper power module; the drain signal collection area is used to connect the drain power signal terminal; The chip parallel unit includes a MOSFET chip parallel group located on the drain copper-clad ceramic substrate; the MOSFET chip parallel group includes n MOSFET chips connected in parallel and arranged circumferentially; the gate of the MOSFET chip parallel group is connected to the gate copper-clad ceramic substrate; the source of the MOSFET chip parallel group is connected to the source copper-clad ceramic substrate; the auxiliary source of the MOSFET chip parallel group is connected to the auxiliary source copper-clad ceramic substrate; the drain of the MOSFET chip parallel group is arranged on the copper clad of the drain copper-clad ceramic substrate; the MOSFET chips are arranged in a 180-degree semicircular layout; The drain copper-clad ceramic substrate in the lower power module is connected to the source signal collection area in the upper power module; The chip parallel unit further includes: a silicon carbide diode chip parallel group; The parallel group of silicon carbide diode chips is arranged on the drain copper-clad ceramic substrate; the parallel group of silicon carbide diode chips includes n silicon carbide diode chips connected in parallel and arranged circumferentially; the anode of the parallel group of silicon carbide diode chips is connected to the source of the parallel group of MOSFET chips, the anode of the parallel group of silicon carbide diode chips is connected to the source copper-clad ceramic substrate, and the cathode of the parallel group of silicon carbide diode chips is arranged on the copper clad of the drain copper-clad ceramic substrate.

2. The multi-chip parallel power module according to claim 1, characterized in that: The drain signal collection area unit includes a first signal collection sub-area and a second signal collection sub-area; The first signal collection sub-region is located on one side of one of the MOSFET chips on the upper power module, and the second signal collection sub-region is located on the other side of the MOSFET chip.

3. The multi-chip parallel power module according to claim 1, characterized in that: Also includes: Signal terminal unit; The signal terminal unit includes a gate drive signal terminal, a source power signal terminal, an auxiliary source drive signal terminal and a drain power signal terminal; The gate drive signal terminal is arranged in the gate signal collection area; the source power signal terminal is arranged in the source signal collection area; the auxiliary source drive signal terminal is arranged in the auxiliary source signal collection area; and the drain power signal terminal is arranged in the drain signal collection area.

4. The multi-chip parallel power module according to claim 3, characterized in that: The gate drive signal terminal and the auxiliary source drive signal terminal are both flat structures; the source power signal terminal is a cylindrical structure; and the drain power signal terminal is a flat structure.

5. The multi-chip parallel power module according to claim 1, characterized in that: The MOSFET chip parallel group includes five MOSFET chips connected in parallel and evenly arranged along the circumferential direction; the angle between two adjacent MOSFET chips is 45 degrees.

6. The multi-chip parallel power module according to claim 1, characterized in that: The parallel group of silicon carbide diode chips includes five silicon carbide diode chips that are connected in parallel and evenly arranged along the circumferential direction; the angle between two adjacent silicon carbide diode chips is 45 degrees.

7. The multi-chip parallel power module according to claim 1, characterized in that: Also includes: Bonding wires; The gate of the parallel group of MOSFET chips is connected to the gate copper-clad ceramic substrate through the bonding wire; the source of the parallel group of MOSFET chips is connected to the source copper-clad ceramic substrate through the bonding wire; the auxiliary source of the parallel group of MOSFET chips is connected to the auxiliary source copper-clad ceramic substrate through the bonding wire; The drain copper-clad ceramic substrate in the lower power module is connected to the source signal collection area in the upper power module through the bonding wire; The anode of the parallel group of silicon carbide diode chips is connected to the source of the parallel group of MOSFET chips through the bonding wire, and the anode of the parallel group of silicon carbide diode chips is connected to the source copper-clad ceramic substrate through the bonding wire.

8. The multi-chip parallel power module according to claim 1, characterized in that: The MOSFET chip parallel group and the diode chip are both welded on the drain copper-clad ceramic substrate.

9. The multi-chip parallel power module according to claim 3, characterized in that: The gate drive signal terminal is welded in the gate signal collection area; the source power signal terminal is welded in the source signal collection area; the auxiliary source drive signal terminal is welded in the auxiliary source signal collection area; and the drain power signal terminal is welded in the drain signal collection area.

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