Three-dimensional semiconductor memory device

Abstract

A three-dimensional semiconductor memory device is disclosed. The device may include: a substrate including a cell array region and a connection region provided at an end of the cell array region; an electrode structure extending from the cell array region to the connection region, the electrode structure including electrodes sequentially stacked on the substrate; an upper insulating layer provided on the electrode structure; a first horizontal insulating layer provided in the upper insulating layer and extending along the electrode; and a first contact plug provided on the connection region to penetrate the upper insulating layer and the first horizontal insulating layer. The first horizontal insulating layer may include a material having better etching resistance than the upper insulating layer.

Description

Technical Field

[0001] The present disclosure relates to a three-dimensional semiconductor memory device, and in particular, to a three-dimensional semiconductor memory device having improved electrical characteristics. Background Art

[0002] A higher integration of semiconductor devices may be required to meet consumer demand for excellent performance and low prices. In the case of semiconductor devices, since their integration is an important factor in determining product prices, an increased integration may be required. In the case of two-dimensional or planar semiconductor devices, since their integration is mainly determined by the area occupied by the unit memory cell, the integration is greatly affected by the level of fine pattern formation technology. However, the extremely expensive process equipment required to improve the fineness of the pattern may set practical restrictions on improving the integration of two-dimensional or planar semiconductor devices. Therefore, a three-dimensional semiconductor memory device including a three-dimensionally arranged memory cell has been recently proposed. Summary of the invention

[0003] Embodiments of the inventive concept provide a three-dimensional semiconductor memory device having improved electrical characteristics.

[0004] According to an embodiment of the present invention, a three-dimensional semiconductor memory device may include: a substrate including a cell array region and a connection region provided at an end of the cell array region; an electrode structure extending from the cell array region to the connection region, the electrode structure including electrodes sequentially stacked on the substrate; an upper insulating layer on the electrode structure; a first horizontal insulating layer in the upper insulating layer and extending along the electrode; and a first contact plug in the connection region penetrating the upper insulating layer and the first horizontal insulating layer. The first horizontal insulating layer may include a material having higher etching resistance than the upper insulating layer.

[0005] According to an embodiment of the present invention, a three-dimensional semiconductor memory device may include: a substrate including a cell array region and a connection region at an end of the cell array region; an electrode structure extending from the cell array region to the connection region, the electrode structure including electrodes sequentially stacked on the substrate; an interlayer insulating layer between the electrodes; an upper insulating layer on the electrode structure; a first horizontal insulating layer in the uppermost interlayer insulating layer of the interlayer insulating layers and extending along the electrode; a second horizontal insulating layer in the upper insulating layer and extending along the electrode; a vertical structure penetrating the electrode structure and the first horizontal insulating layer; and a first contact plug penetrating the upper insulating layer and the first horizontal insulating layer and the second horizontal insulating layer. The first horizontal insulating layer and the second horizontal insulating layer may be vertically spaced apart from each other. The concentration of a non-metallic element other than oxygen may be higher in the second horizontal insulating layer than in the upper insulating layer.

[0006] According to an embodiment of the present invention, a three-dimensional semiconductor memory device may include: a substrate including a cell array region, a peripheral circuit region including a peripheral circuit, and a connection region between the cell array region and the peripheral circuit region; an electrode structure extending from the cell array region to the connection region, the electrode structure including electrodes vertically stacked on the substrate; an interlayer insulating layer interposed between the electrodes; an upper insulating layer on the electrode structure; a horizontal insulating layer in the upper insulating layer and extending along the electrode; a vertical structure penetrating the electrode structure, the vertical structure including a data storage pattern, a vertical semiconductor pattern surrounded by the data storage pattern, and a conductive pad connected to the top of the vertical semiconductor pattern; a bit line provided on the upper insulating layer and electrically connected to the conductive pad of the vertical structure; first contact plugs, each of the first contact plugs on the connection region to penetrate the upper insulating layer, the horizontal insulating layer, and one of the interlayer insulating layer and connected to a corresponding one of the electrodes; a second contact plug on the peripheral circuit region to penetrate the upper insulating layer and the horizontal insulating layer and connected to the peripheral circuit; and a conductive line connected to the first contact plug and the second contact plug, respectively. The concentration of the non-metallic element other than oxygen may be higher in the horizontal insulating layer than in the upper insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings.The accompanying drawings depict non-limiting example embodiments as described herein.

[0008] Figure 1 is a circuit diagram schematically illustrating a cell array of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0009] Figure 2A is a plan view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0010] Figure 2B , Fig. 8A and Fig. 9A FIG. 1 is a diagram showing a three-dimensional semiconductor memory device according to an embodiment of the present inventive concept. Figure 2A A cross-sectional view taken along line II'.

[0011] Figure 2C , Figure 8B and Fig. 9B FIG. 1 is a diagram showing a three-dimensional semiconductor memory device according to an embodiment of the present inventive concept. Figure 2A A cross-sectional view taken along line II-II'.

[0012] Figure 3A and Figure 3B FIG. 1 is a diagram showing a portion of a three-dimensional semiconductor memory device according to an embodiment of the present inventive concept (eg Figure 2BA) is an enlarged cross-sectional view.

[0013] Figure 4A and Figure 4B FIG. 1 is a diagram showing a portion of a three-dimensional semiconductor memory device according to an embodiment of the present inventive concept (eg Figure 2B B) is an enlarged cross-sectional view.

[0014] Figure 5 FIG. 1 is a diagram showing a portion of a three-dimensional semiconductor memory device according to an embodiment of the present inventive concept (eg Figure 2B C) is an enlarged cross-sectional view.

[0015] Fig. 6A is a plan view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0016] Figure 6B and Figure 6C FIG. 1 is a diagram showing a three-dimensional semiconductor memory device according to an embodiment of the present inventive concept. Fig. 6A Cross-sectional views taken along lines II' and II-II'.

[0017] Figure 7 FIG. 1 is a diagram showing a three-dimensional semiconductor memory device according to an embodiment of the present inventive concept. Fig. 6A A cross-sectional view taken along line II'.

[0018] It should be noted that these drawings are intended to illustrate the general characteristics of the methods, structures and / or materials used in certain example embodiments and to supplement the written description provided below. However, these drawings are not drawn to scale and may not accurately reflect the precise structure or performance characteristics of any given embodiment and should not be interpreted as limiting or defining the range of values ​​or properties covered by the example embodiments. For example, the relative thickness and position of molecules, layers, regions and / or structural elements may be reduced or enlarged for clarity. The use of similar or identical reference numerals in the various drawings is intended to indicate the presence of similar or identical elements or features. DETAILED DESCRIPTION

[0019] Example embodiments of the inventive concepts will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown.

[0020] Figure 1 is a circuit diagram schematically illustrating a cell array of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0021] Reference Figure 1, a cell array of a three-dimensional semiconductor memory device may include a common source line CSL, a plurality of bit lines BL0 - BL2 , and a plurality of cell strings CSTR provided between the common source line CSL and the bit lines BL0 - BL2 .

[0022] The cell string CSTR may be arranged two-dimensionally in a first direction D1 and a second direction D2 that are not parallel to each other. In one embodiment, the second direction D2 may be perpendicular to the first direction D1. Each cell string CSTR may extend in a third direction D3. In one embodiment, the third direction D3 may be perpendicular to both the first direction D1 and the second direction D2. The bit lines BL0-BL2 may be spaced apart from each other in the first direction D1. Each of the bit lines BL0-BL2 may extend in the second direction D2.

[0023] A plurality of cell strings CSTR may be connected in parallel to each of the bit lines BL0-BL2. The cell strings CSTR may be commonly connected to a common source line CSL. That is, a plurality of cell strings CSTR may be provided between the bit lines BL0-BL2 and a single common source line CSL. In one embodiment, a plurality of common source lines CSL may be provided. The common source lines CSL may be arranged two-dimensionally. The common source lines CSL may be applied with the same voltage or may have independently controlled electrical states.

[0024] In one embodiment, each cell string CSTR may include first and second string selection transistors SST1 and SST2 connected in series, memory cell transistors MCT connected in series, a ground selection transistor GST, and an erase control transistor ECT. Each memory cell transistor MCT may include a data storage element.

[0025] As an example, each cell string CSTR may include a first string selection transistor SST1 and a second string selection transistor SST2 connected in series, and the second string selection transistor SST2 may be coupled to one of the bit lines BL0-BL2. As another example, each cell string CSTR may include one string selection transistor. As another example, in each cell string CSTR, similar to the first string selection transistor SST1 and the second string selection transistor SST2, the ground selection transistor GST may be composed of a plurality of metal oxide semiconductor (MOS) transistors connected in series.

[0026] Each cell string CSTR may include a plurality of memory cell transistors MCT located at a height different from the common source line CSL. The memory cell transistors MCT may be connected in series between the first string selection transistor SST1 and the ground selection transistor GST. The erase control transistor ECT may be provided between the ground selection transistor GST and the common source line CSL and connected to the ground selection transistor GST and the common source line CSL. In addition, each cell string CSTR may include a dummy cell transistor DMC, which is provided between the first string selection transistor SST1 and the topmost one of the memory cell transistors MCT and connected to them, and provided between the ground selection transistor GST and the bottommost one of the memory cell transistors MCT and connected to them.

[0027] In one embodiment, the first string selection transistor SST1 can be controlled by one of the first string selection lines SSL1-1, SSL1-2 and SSL1-3, and the second string selection transistor SST2 can be controlled by one of the second string selection lines SSL2-1, SSL2-2 and SSL2-3. The memory cell transistor MCT can be controlled by a plurality of word lines WL0-WLn, respectively, and the dummy cell transistor DMC can be controlled by the dummy word line DWL. The ground selection transistor GST can be controlled by one of the ground selection lines GSL0, GSL1 and GSL2, and the erase control transistor ECT can be controlled by the erase control line ECL. In one embodiment, the erase control transistor ECT can be provided in plurality. The common source line CSL can be commonly connected to the source of the erase control transistor ECT.

[0028] The gate electrodes of the memory cell transistors MCT located at substantially the same height from the common source line CSL may be commonly connected to one of the word lines WL0-WLn and may be in an equipotential state. Alternatively, even when the gate electrodes of the memory cell transistors MCT are located at substantially the same height from the common source line CSL, the gate electrodes constituting different rows or columns may be independently controlled.

[0029] The ground selection lines GSL0-GSL2, the first string selection lines SSL1-1, SSL1-2 and SSL1-3, and the second string selection lines SSL2-1, SSL2-2 and SSL2-3 may extend in the first direction D1 and be spaced apart from each other in the second direction D2. The ground selection lines GSL0-GSL2, the first string selection lines SSL1-1, SSL1-2 and SSL1-3, and the second string selection lines SSL2-1, SSL2-2 and SSL2-3 located at substantially the same height from the common source line CSL may be electrically separated from each other. In addition, the erase control transistors ECT in different cell strings included in the cell string CSTR may be commonly controlled by the erase control line ECL. During an erase operation of the memory cell array, the erase control transistor ECT may cause a gate induced drain leakage (GIDL). In one embodiment, during an erase operation of the memory cell array, an erase voltage may be applied to the bit lines BL0-BL2 and / or the common source line CSL, and in this case, a gate induced leakage current may be generated at the string selection transistors SST1 and SST2 and / or the erase control transistor ECT.

[0030] Figure 2A is a plan view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept. Figure 2B and Figure 2C 1 is a diagram showing a three-dimensional semiconductor memory device according to an embodiment of the present invention. Figure 2A Cross-sectional views taken along lines II' and II-II'.

[0031] Reference Figure 2A , Figure 2B and Figure 2C , the substrate 10 may include a cell array region CAR, a connection region CNR, a dummy region DMY, and a peripheral circuit region PCR. The connection region CNR may be located between the cell array region CAR and the peripheral circuit region PCR. The dummy region DMY may be adjacent to the cell array region CAR in a first direction D1 parallel to the top surface of the substrate 10. The dummy region DMY may be located between the cell array region CAR and the connection region CNR. The peripheral circuit region PCR may be adjacent to the connection region CNR in the first direction D1. The peripheral circuit region PCR may include a first peripheral circuit region PCR1 and a second peripheral circuit region PCR2, and in one embodiment, the first peripheral circuit region PCR1 may be closer to the cell array region CAR than the second peripheral circuit region PCR2. However, the inventive concept is not limited to this example, and in one embodiment, the substrate 10 may further include a boundary region between the peripheral circuit region PCR and the connection region CNR.

[0032] The substrate 10 may be a silicon substrate, a silicon germanium substrate, a germanium substrate, or a single crystal epitaxial layer grown on a single crystal silicon substrate. A device isolation layer 13 may be provided in a peripheral circuit region PCR of the substrate 10 to define a peripheral active region PACT. A peripheral logic circuit for writing data in a memory cell and reading data from a memory cell may be provided on the peripheral circuit region PCR of the substrate 10. The peripheral logic circuit may include a row decoder and a column decoder, a page buffer, and a control circuit. The peripheral logic circuit may include, for example, high voltage or low voltage transistors, resistors, and capacitors. In one embodiment, a high voltage transistor may be provided on a first peripheral circuit region PCR1 of the substrate 10, and a low voltage transistor may be provided on a second peripheral circuit region PCR2 of the substrate 10. The high voltage transistor may be closer to the cell array region CAR than the low voltage transistor.

[0033] The first peripheral gate stack PGS1 may be provided on the first peripheral circuit region PCR1, and the second peripheral gate stack PGS2 may be provided on the second peripheral circuit region PCR2. Each of the first peripheral gate stack PGS1 and the second peripheral gate stack PGS2 may be provided to cross a corresponding one of the peripheral active regions PACT. Each of the first peripheral gate stack PGS1 and the second peripheral gate stack PGS2 may include a gate conductive pattern PCP, a gate metal pattern PMP, and a peripheral hard mask pattern HMP sequentially stacked on the substrate 10, as shown in FIG. Figure 2B In addition, each of the first peripheral gate stack PGS1 and the second peripheral gate stack PGS2 may further include a gate spacer PSP, which covers both side surfaces of the gate conductive pattern PCP, both side surfaces of the gate metal pattern PMP and both side surfaces of the peripheral hard mask pattern HMP, as shown in FIG. Figure 2B The gate insulating layer 15 may be provided between the substrate 10 and the first peripheral gate stack PGS1 and the second peripheral gate stack PGS2 of the peripheral circuit region PCR. Figure 2B As shown. In addition, source / drain impurity regions may be provided in the peripheral active region PACT and on both sides of the first peripheral gate stack PGS1 and on both sides of the second peripheral gate stack PGS2. A peripheral circuit insulating layer 110 may be provided on the peripheral circuit region PCR to cover the top surface of the substrate 10, as shown. Figure 2B The peripheral circuit insulating layer 110 may be formed of or include at least one of silicon oxide and silicon oxynitride. The peripheral circuit insulating layer 110 may have a substantially flat top surface.

[0034] The electrode structure ST may be disposed on the cell array region CAR, the dummy region DMY, and the connection region CNR of the substrate 10. Figure 2A-2CAs shown. The electrode structure ST may extend from the cell array region CAR to the connection region CNR or in the first direction D1. The electrode structures ST may be spaced apart from each other in the second direction D2. The electrode structure ST may include electrodes EL and ELt and interlayer insulating layers ILDa and ILDb alternately stacked in a third direction D3 perpendicular to the top surface of the substrate 10, as shown in FIG. Figure 2B and Figure 2C Each electrode structure ST may have a substantially flat top surface on the cell array region CAR and the dummy region DMY. That is, in each electrode structure ST, a top surface ILDbt of the uppermost interlayer insulating layer ILDb may be parallel to the top surface of the substrate 10, as shown in FIG. Figure 2C The electrode structure ST may be provided to have a step structure on the connection region CNR, as shown in FIG. Figure 2B and Figure 2C The lengths of the electrodes EL and ELt of the electrode structure ST in the first direction D1 may decrease as the distance from the substrate 10 increases, and the height of the electrode structure ST may decrease as the distance from the cell array region CAR increases.

[0035] The electrodes EL and ELt may have side surfaces that are uniformly spaced apart from each other by a specific distance in the first direction D1 when viewed in a plan view. Among the electrodes EL and ELt, the uppermost electrode ELt may have the shortest length in the first direction D1 and the largest distance from the substrate 10 in the third direction D3, as shown in FIG. Figure 2B and Figure 2C As shown. In one embodiment, the electrodes EL and ELt may have substantially the same thickness in the third direction D3. The electrodes EL and ELt may be formed of, for example, at least one of a doped semiconductor material (e.g., doped silicon, etc.), a metal (e.g., tungsten, copper, aluminum, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), and a transition metal (e.g., titanium, tantalum, etc.), or include, for example, at least one of a doped semiconductor material (e.g., doped silicon, etc.), a metal (e.g., tungsten, copper, aluminum, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), and a transition metal (e.g., titanium, tantalum, etc.). Return to reference Figure 1 , the electrodes EL and ELt may be used as ground selection lines GSL0-GSL2, word lines WL0-WLn and DWL, first string selection lines SSL1-1, SSL1-2, and SSL1-3, and second string selection lines SSL2-1, SSL2-2, and SSL2-3.

[0036] The interlayer insulating layers ILDa and ILDb may extend from the cell array region CAR to the peripheral circuit region PCR and may cover the electrodes EL and ELt, respectively. Figure 2BAs shown. The uppermost interlayer insulating layer ILDb may be provided on the uppermost electrode ELt. When measured in the third direction D3, the uppermost interlayer insulating layer ILDb may be thicker than each interlayer insulating layer ILDa. The interlayer insulating layers ILDa and ILDb may be formed of insulating materials substantially the same as each other or insulating materials different from each other, or include insulating materials substantially the same as each other or insulating materials different from each other. For example, the interlayer insulating layers ILDa and ILDb may be formed of high-density plasma (HDP) oxide or tetraethyl orthosilicate (TEOS), or include high-density plasma (HDP) oxide or tetraethyl orthosilicate.

[0037] When viewed in a plan view, common source plugs CSP may be provided between the electrode structures ST, and each common source plug CSP may be surrounded by an insulating spacer SP. Each common source plug CSP may have a plate-like structure extending in the first direction D1 and the third direction D3. The common source plugs CSP may extend from the cell array region CAR to the connection region CNR in the first direction D1. The common source plugs CSP may be spaced apart from each other in the second direction D2. The common source plugs CSP may be connected to a common source region formed in the substrate 10. The common source region may be used as Figure 1 A common source line CSL.

[0038] The source structure SC may be interposed between the electrode structure ST and the substrate 10. The source structure SC may be parallel to the electrode structure ST and extend in the first direction D1. The source structure SC may include a first source conductive pattern SCP1 and a second source conductive pattern SCP2 sequentially stacked on the substrate 10. The thickness of the first source conductive pattern SCP1 in the third direction D3 may be greater than the thickness of the second source conductive pattern SCP2 in the third direction D3. The first source conductive pattern SCP1 may be in contact with the substrate 10, and the second source conductive pattern SCP2 may be in direct contact with the first source conductive pattern SCP1. The second source conductive pattern SCP2 may be provided between the first source conductive pattern SCP1 and the lowest one of the interlayer insulating layers ILDa and ILDb of the electrode structure ST. The first source conductive pattern SCP1 and the second source conductive pattern SCP2 may be formed of or include a doped semiconductor material. In one embodiment, the doping concentration may be higher in the first source conductive pattern SCP1 than in the second source conductive pattern SCP2.

[0039] The planarization insulating layer 130 may be provided on the substrate 10 to cover the electrode structure ST and the peripheral circuit insulating layer 110. The top surface 130t ( Figure 2C) may be substantially flat. The top surface 130t of the planarization insulating layer 130 may be substantially coplanar with the top surface ILDbt of the uppermost interlayer insulating layer ILDb. On the connection region CNR, the thickness of the planarization insulating layer 130 measured in the third direction D3 may increase in the first direction D1. The thickness of the planarization insulating layer 130 measured in the third direction D3 may have a maximum value on the peripheral circuit region PCR. The planarization insulating layer 130 may be formed of an insulating material different from the interlayer insulating layers ILDa and ILDb, or include an insulating material different from the interlayer insulating layers ILDa and ILDb. In one embodiment, the interlayer insulating layers ILDa and ILDb may be formed of a high-density plasma oxide or include a high-density plasma oxide, and the planarization insulating layer 130 may be formed of TEOS or include TEOS.

[0040] The first horizontal insulating layer IMP1 may be provided in the uppermost interlayer insulating layer ILDb and may extend in the first direction D1 along the electrodes EL and ELt. The first horizontal insulating layer IMP1 may extend into the planarizing insulating layer 130. Figure 4A and Figure 4B , the top surface IMP1t of the first horizontal insulating layer IMP1 may be located at a lower level than the top surface ILDbt of the uppermost interlayer insulating layer ILDb. The bottom surface of the first horizontal insulating layer IMP1 may be located at a higher level than the top surface of the uppermost electrode ELt. In other words, the first horizontal insulating layer IMP1 may be provided between the top surface of the uppermost electrode ELt and the top surface ILDbt of the uppermost interlayer insulating layer ILDb. For example, the distance from the top surface ILDbt of the uppermost interlayer insulating layer ILDb to the top surface IMP1t of the first horizontal insulating layer IMP1 may be 1000 nm. and The first horizontal insulating layer IMP1 may be formed of or include a material having a better etching resistance than the etching resistance of the uppermost interlayer insulating layer ILDb and the planarizing insulating layer 130 (that is, the material of the first horizontal insulating layer IMP1 has a higher etching resistance than the etching resistance of the material of the uppermost interlayer insulating layer ILDb and the planarizing insulating layer 130). Here, the etching resistance may refer to resistance to an etchant used in a wet etching process or a dry etching process. In one embodiment, the first horizontal insulating layer IMP1 may have a higher density than the uppermost interlayer insulating layer ILDb and the planarizing insulating layer 130. In one embodiment, the concentration of non-metallic elements other than oxygen may be higher in the first horizontal insulating layer IMP1 than in the uppermost interlayer insulating layer ILDb and the planarizing insulating layer 130. In one embodiment, the concentration of the non-metallic element may continuously change at the boundary between the first horizontal insulating layer IMP1 and the uppermost interlayer insulating layer ILDb and at the boundary between the first horizontal insulating layer IMP1 and the planarizing insulating layer 130. For example, the first horizontal insulating layer IMP1 may include at least one non-metallic element selected from nitrogen (N), carbon (C), boron (B), phosphorus (P), helium (He), and argon (Ar). An ion implantation process may be performed on the uppermost interlayer insulating layer ILDb and the planarization insulating layer 130 to form the first horizontal insulating layer IMP1. In one embodiment, a heat treatment process may be further performed after the ion implantation process. In one embodiment, the heat treatment process may be a rapid thermal annealing (RTP) process. If the ion implantation process is performed under the condition of a large ion implantation amount, the first horizontal insulating layer IMP1 may have improved etching resistance.

[0041] In one embodiment, a plurality of first horizontal insulating layers IMP1 may be provided. Figure 4B , at least two first horizontal insulating layers IMP1a may be provided between the top surface of the uppermost electrode ELt and the top surface ILDbt of the uppermost interlayer insulating layer ILDb. The first horizontal insulating layers IMP1a may be spaced apart from each other in the third direction D3. In one embodiment, the first horizontal insulating layer IMP1a may be formed of or include materials different from each other. The first horizontal insulating layer IMP1a may be formed by performing an ion implantation process at least twice on the uppermost interlayer insulating layer ILDb and the planarization insulating layer 130. The ion implantation process may be performed using ions of different elements. In addition, the ion implantation process may be performed under process conditions where the ion implantation energy or the ion implantation amount is different from each other. In one embodiment, after the ion implantation process, a heat treatment process may be further performed. The position of the first horizontal insulating layer IMP1a may be changed by adjusting the ion implantation energy in the ion implantation process and the heating method in the heat treatment process.

[0042] A plurality of first vertical structures VS1 may be provided on the cell array region CAR and the dummy region DMY to penetrate the electrode structure ST, the source structure SC, and a portion of the substrate 10. The first vertical structure VS1 may penetrate the uppermost interlayer insulating layer ILDb and the first horizontal insulating layer IMP1 provided in the uppermost interlayer insulating layer ILDb. Return to reference Figure 1 The first vertical structure VS1 may be used as a channel region of the erase control transistor ECT, a channel region of the first and second string selection transistors SST1 and SST2, a channel region of the ground selection transistor GST, and a channel region of the memory cell transistor MCT.

[0043] Each of the first vertical structures VS1 may include a data storage pattern DSP, a first vertical semiconductor pattern VSP1, and a first conductive pad PAD1. Figure 4A , Figure 4B and Figure 5 The data storage pattern DSP may include a blocking insulating layer BLK, a charge storage layer CIL, and a tunnel insulating layer TIL that are sequentially stacked. Each of the first vertical structures VS1 may further include a buried insulating pattern VI surrounded by the first vertical semiconductor pattern VSP1 and the first conductive pad PAD1. The top surface IMP1t of the first horizontal insulating layer IMP1 may be located at a lower height than the bottom surface PAD1b of the first conductive pad PAD1, as shown in FIG. Figure 4A However, in one embodiment, Figure 4A Unlike shown, a top surface IMP1t of the first horizontal insulating layer IMP1 may be substantially coplanar with a bottom surface PAD1b of the first conductive pad PAD1.

[0044] The first vertical semiconductor pattern VSP1 may be surrounded by the data storage pattern DSP. A portion of the side surface of the first vertical semiconductor pattern VSP1 may be in contact with the source structure SC. For example, the first vertical semiconductor pattern VSP1 may be in contact with the first source conductive pattern SCP1 of the source structure SC and may be spaced apart from the second source conductive pattern SCP2. Each first vertical structure VS1 may also include a lower data storage pattern DSPr. The lower data storage pattern DSPr may have a substantially "U"-shaped cross-section. The lower data storage pattern DSPr may be spaced apart from the data storage pattern DSP, and the first source conductive pattern SCP1 in contact with the first vertical semiconductor pattern VSP1 may be inserted between the lower data storage pattern DSPr and the data storage pattern DSP. The lower data storage pattern DSPr may be provided below the top surface of the substrate 10. The first conductive pad PAD1 may be connected to the top of the first vertical semiconductor pattern VSP1. The top surface of the first conductive pad PAD1 may be substantially coplanar with the top surface of the data storage pattern DSP and the top surface of the first vertical semiconductor pattern VSP1, such as Figure 4A The first conductive pad PAD1 may be formed of, or include, a doped semiconductor material or a conductive material.

[0045] The data storage pattern DSP and the first vertical semiconductor pattern VSP1 may be formed by etching the electrode structure ST, depositing an insulating material or a semiconductor material using a chemical vapor deposition (CVD) or atomic layer deposition (ALD) method, and performing a planarization process to expose a top surface of the electrode structure ST.

[0046] A plurality of second vertical structures VS2 may be provided on the connection region CNR to penetrate the planarization insulating layer 130, the electrode structure ST, the source structure SC, and a portion of the substrate 10. The second vertical structure VS2 may penetrate the stepped structure of the electrode structure ST, such as Figure 2C The second vertical structure VS2 may penetrate the first horizontal insulating layer IMP1 provided in the planarizing insulating layer 130, as shown in FIG. Figure 2C Each second vertical structure VS2 may include a data storage pattern DSP, a second vertical semiconductor pattern VSP2, and a second conductive pad PAD2. Each second vertical structure VS2 may have substantially the same structure as the first vertical structure VS1 and may be formed by substantially the same method as that used for the first vertical structure VS1.

[0047] When viewed in a plan view, the first vertical structure VS1 and the second vertical structure VS2 may be arranged in a zigzag shape. In each of the first vertical structure VS1 and the second vertical structure VS2, the data storage pattern DSP may have a hollow tube shape or a macaroni shape. The first vertical semiconductor pattern VSP1 and the second vertical semiconductor pattern VSP2 of the first vertical structure VS1 and the second vertical structure VS2 may have a tube shape or a macaroni shape with a closed bottom. The first vertical semiconductor pattern VSP1 and the second vertical semiconductor pattern VSP2 may be formed of at least one of semiconductor materials (e.g., silicon (Si) and germanium (Ge)), or include at least one of semiconductor materials (e.g., silicon (Si) and germanium (Ge)). In one embodiment, the first vertical semiconductor pattern VSP1 and the second vertical semiconductor pattern VSP2 may be formed of a doped semiconductor material, an intrinsic semiconductor material, or a polycrystalline semiconductor material, or include a doped semiconductor material, an intrinsic semiconductor material, or a polycrystalline semiconductor material. For example, the top surface of the first vertical structure VS1 and the top surface of the second vertical structure VS2 may have a circular shape, an elliptical shape, or a bar shape. In one embodiment, the width of the second vertical structure VS2 may be greater than the width of the first vertical structure VS1. In one embodiment, the first vertical structure VS1 and the second vertical structure VS2 may have substantially the same length in the third direction D3. The bottom surface of the first vertical structure VS1 and the bottom surface of the second vertical structure VS2 may be located at a height lower than the top surface of the substrate 10. For example, the first vertical structure VS1 and the second vertical structure VS2 may be connected to the substrate 10. At least one of the first vertical structure VS1 and the second vertical structure VS2 may be a dummy vertical structure including a dummy data storage pattern DSPd.

[0048] like Figure 2B and Figure 2C As shown, an upper insulating layer 150 may be provided on the electrode structure ST and the planarization insulating layer 130. The upper insulating layer 150 may cover the top surface ILDbt of the uppermost interlayer insulating layer ILDb and the top surface 130t of the planarization insulating layer 130. The upper insulating layer 150 may be provided to have substantially the same thickness in the third direction D3 on the cell array region CAR, the connection region CNR, and the peripheral circuit region PCR. In one embodiment, the upper insulating layer 150 may be formed of an insulating material substantially the same as the planarization insulating layer 130, or include an insulating material substantially the same as the planarization insulating layer 130. As an example, the upper insulating layer 150 may be formed of an insulating material different from the uppermost interlayer insulating layer ILDb, or include an insulating material different from the uppermost interlayer insulating layer ILDb.

[0049] The second horizontal insulating layer IMP2 may be provided in the upper insulating layer 150 and may extend along the electrodes EL and ELt in the first direction D1. Figure 3A and Figure 3B , the top surface IMP2t of the second horizontal insulating layer IMP2 may be located at a lower height than the top surface 150t of the upper insulating layer 150. The bottom surface of the second horizontal insulating layer IMP2 may be located at a higher height than the top surface 130t of the planarizing insulating layer 130. In other words, the second horizontal insulating layer IMP2 may be provided between the top surface 130t of the planarizing insulating layer 130 and the top surface 150t of the upper insulating layer 150. For example, the distance from the top surface 150t of the upper insulating layer 150 to the top surface IMP2t of the second horizontal insulating layer IMP2 may be 1000 m / s. and The second horizontal insulating layer IMP2 may be formed of a material having better etching resistance than that of the upper insulating layer 150, or include a material having better etching resistance than that of the upper insulating layer 150. Etching resistance may indicate resistance to an etchant used in a dry etching process. In one embodiment, the second horizontal insulating layer IMP2 may have a higher density than the upper insulating layer 150. In one embodiment, the concentration of non-metallic elements other than oxygen may be higher in the second horizontal insulating layer IMP2 than in the upper insulating layer 150. In one embodiment, the concentration of the non-metallic elements may vary continuously at a boundary between the second horizontal insulating layer IMP2 and the upper insulating layer 150. For example, the second horizontal insulating layer IMP2 may include at least one non-metallic element selected from nitrogen (N), carbon (C), boron (B), phosphorus (P), helium (He), and argon (Ar). In one embodiment, the second horizontal insulating layer IMP2 may have substantially the same chemical composition as the first horizontal insulating layer IMP1. In some embodiments, the second horizontal insulating layer IMP2 may include a non-metallic element that is not included in the first horizontal insulating layer IMP1. The second horizontal insulating layer IMP2 may be formed by performing an ion implantation process on the upper insulating layer 150. In one embodiment, a heat treatment process may be further performed after the ion implantation process. The method of forming the second horizontal insulating layer IMP2 may be substantially the same as the method for the first horizontal insulating layer IMP1.

[0050] In one embodiment, a plurality of second horizontal insulating layers IMP2 may be provided. Figure 3B, at least two second horizontal insulating layers IMP2a may be provided between the top surface 130t of the planarization insulating layer 130 and the top surface 150t of the upper insulating layer 150. The second horizontal insulating layers IMP2a may be spaced apart from each other in the third direction D3. In one embodiment, the second horizontal insulating layers IMP2a may be formed of or include materials different from each other. The second horizontal insulating layer IMP2a may be formed by performing an ion implantation process twice on the upper insulating layer 150. The position of the second horizontal insulating layer IMP2a may be changed by adjusting the ion implantation energy in the ion implantation process and the heating method in the heat treatment process. The method of forming the second horizontal insulating layer IMP2a may be the same as that of reference 1. Figure 4B The described method of forming the first horizontal insulating layer IMP1a is substantially the same.

[0051] A plurality of bit lines BL may be provided on the cell array region CAR, may extend in the second direction D2, and may be spaced apart from each other in the first direction D1. Figure 1 , FIG. 2A to FIG. 2C The bit line BL can be used as Figure 1 The bit lines BL0-BL2 are provided on the upper insulating layer 150. The bit lines BL may be respectively connected to the first vertical structure VS1 through the bit line contact plugs BPLG. The bit line contact plugs BPLG may be provided to penetrate the upper insulating layer 150 and the second horizontal insulating layer IMP2. The bit lines BL and the bit line contact plugs BPLG may be formed of at least one of the conductive materials or include at least one of the conductive materials.

[0052] A plurality of conductive lines CL may be provided on the connection region CNR and the peripheral circuit region PCR, and in one embodiment, the conductive lines CL may extend in the second direction D2 and may be spaced apart from each other in the first direction D1. The conductive lines CL may be provided on the upper insulating layer 150. The conductive lines CL on the connection region CNR may be respectively connected to the electrodes EL of the electrode structure ST through the cell contact plugs CPLG. The cell contact plugs CPLG may be provided to penetrate the upper insulating layer 150, the second horizontal insulating layer IMP2, the planarization insulating layer 130, the first horizontal insulating layer IMP1, and the interlayer insulating layer ILDa of the electrode structure ST. The conductive lines CL on the peripheral circuit region PCR may be respectively connected to the first peripheral gate stack PGS1 and the second peripheral gate stack PGS2 through the peripheral contact plugs PPLG. Specifically, each peripheral contact plug PPLG may be in contact with the gate metal pattern PMP. The peripheral contact plug PPLG may be provided to penetrate the upper insulating layer 150 , the second horizontal insulating layer IMP2 , the planarization insulating layer 130 , the first horizontal insulating layer IMP1 , the peripheral circuit insulating layer 110 , and the peripheral hard mask pattern HMP.

[0053] Figure 3A and Figure 3B FIG. 1 is a diagram showing a portion of a three-dimensional semiconductor memory device according to an embodiment of the present inventive concept (eg Figure 2B A) is an enlarged cross-sectional view.

[0054] Will refer to Figure 3A One of the cell contact plugs CPLG is described, but the remaining cell contact plugs CPLG and the peripheral contact plugs PPLG on the peripheral circuit region PCR may also have substantially the same features as the cell contact plugs CPLG to be described here. As described above, each cell contact plug CPLG may be provided to penetrate the upper insulating layer 150, the second horizontal insulating layer IMP2, and the planarizing insulating layer 130.

[0055] The width of the cell contact plug CPLG measured in the first direction D1 may increase from the top surface 150t of the upper insulating layer 150 to the top surface IMP2t of the second horizontal insulating layer IMP2, and may be increased from the bottom surface of the second horizontal insulating layer IMP2 to the substrate 10 (see, for example, Figure 2B ) is reduced. Specifically, the cell contact plug CPLG may have a maximum width W1m greater than a width W1 of the cell contact plug CPLG at its top surface CPLGt. In addition, the maximum width W1m of the cell contact plug CPLG may be greater than widths W1t and W1b of the cell contact plug CPLG at the top height and the bottom height of the second horizontal insulating layer IMP2. The maximum width W1m of the cell contact plug CPLG may be greater than about to about In one embodiment, the cell contact plug CPLG may have a maximum width W1m at an intermediate height of the second horizontal insulating layer IMP2 along the third direction D3. The first distance L1 from the top surface CPLGt of the cell contact plug CPLG to the portion having the maximum width W1m may be within a range from about to about within the range.

[0056] Since the second horizontal insulating layer IMP2 is provided in the upper insulating layer 150, the maximum width W1m of the cell contact plug CPLG can be reduced. The reduction of the maximum width W1m of the cell contact plug CPLG may be due to the fact that the etching resistance of the second horizontal insulating layer IMP2 is better than that of the upper insulating layer 150. Due to the reduction of the maximum width W1m of the cell contact plug CPLG, a short circuit may be prevented from being formed between adjacent cell contact plugs in the cell contact plug CPLG. In addition, by controlling process conditions (e.g., ion implantation energy and ion implantation amount) in the ion implantation process, the maximum width W1m of the cell contact plug CPLG and the first distance L1 from the top surface CPLGt of the cell contact plug CPLG to the portion having the maximum width W1m may be controlled.

[0057] Table 1 below shows the maximum width W1m of the cell contact plug CPLG formed under different conditions regarding ion implantation energy and ion implantation amount.

[0058] [Table 1]

[0059]

[0060] Referring to Table 1, in the case where the second horizontal insulating layer IMP2 is not provided (ie, the ion implantation process is not performed) (Ref), the maximum width W1m of the cell contact plug CPLG is approximately In addition, in the case where the second horizontal insulating layer IMP2 is formed by the ion implantation process, the maximum width W1m of the cell contact plug CPLG is reduced. Compared with the case where the ion implantation process is not performed (Ref), the maximum width W1m of the cell contact plug CPLG is reduced by about 5%-6%. In this case, a short circuit is prevented from being formed between adjacent cell contact plugs in the cell contact plug CPLG. Ref Figure 3B , a plurality of second horizontal insulating layers IMP2a may be provided in the upper insulating layer 150. In one embodiment, the second horizontal insulating layers IMP2a may have different thicknesses T1a when measured in the third direction D3. Specifically, the difference in thickness T1a between the second horizontal insulating layers IMP2a may be achieved by adjusting process conditions (e.g., ion implantation energy and ion implantation amount) in at least two ion implantation processes. Since the second horizontal insulating layer IMP2a is provided in the upper insulating layer 150, the maximum width W1m of the cell contact plug CPLG may be less than Figure 3A The maximum width in .

[0061] Figure 4A and Figure 4B FIG. 1 is a diagram showing a portion of a three-dimensional semiconductor memory device according to an embodiment of the present inventive concept (eg Figure 2B B) is an enlarged cross-sectional view.

[0062] Will refer to Figure 4A One of the first vertical structures VS1 is described, but the remaining first vertical structures VS1 and the second vertical structure VS2 on the connection region CNR may also have substantially the same features as the first vertical structure VS1 to be described here. As described above, the first vertical structure VS1 may be provided to penetrate the uppermost interlayer insulating layer ILDb, the first horizontal insulating layer IMP1, and the uppermost electrode ELt.

[0063] The width of the first vertical structure VS1 measured in the first direction D1 may increase from the top surface ILDbt of the uppermost interlayer insulating layer ILDb to the top surface IMP1t of the first horizontal insulating layer IMP1, and may be increased from the bottom surface of the first horizontal insulating layer IMP1 to the substrate 10 (see, for example, FIG. 1 ). Figure 2B ) is reduced. Specifically, the first vertical structure VS1 may have a maximum width W2m greater than the width W2 of the first vertical structure VS1 at the top surface VS1t thereof. In addition, the maximum width W2m of the first vertical structure VS1 may be greater than the widths W2t and W2b of the first vertical structure VS1 at the top level and the bottom level of the first horizontal insulating layer IMP1. The maximum width W2m of the first vertical structure VS1 may be greater than about to about In one embodiment, the first vertical structure VS1 may have a maximum width W2m at an intermediate height of the first horizontal insulating layer IMP1 along the third direction D3. The second distance L2 from the top surface VS1t of the first vertical structure VS1 to the portion having the maximum width W2m may be within a range from about to about within the range.

[0064] Since the first horizontal insulating layer IMP1 is provided in the uppermost interlayer insulating layer ILDb, the maximum width W2m of the first vertical structure VS1 can be reduced. The reduction of the maximum width W2m of the first vertical structure VS1 can be due to the fact that the etching resistance of the first horizontal insulating layer IMP1 is better than that of the uppermost interlayer insulating layer ILDb. Due to the reduction of the maximum width W2m of the first vertical structure VS1, a short circuit can be prevented from being formed between adjacent first vertical structures in the first vertical structure VS1. In addition, by controlling the ion implantation energy and the ion implantation amount in the ion implantation process, the maximum width W2m of the first vertical structure VS1 and the second distance L2 from the top surface VS1t of the first vertical structure VS1 to the portion having the maximum width W2m can be controlled.

[0065] Reference Figure 4B, a plurality of first horizontal insulating layers IMP1a may be provided in the uppermost interlayer insulating layer ILDb. When measured in the third direction D3, the first horizontal insulating layers IMP1a may have different thicknesses T2a. Specifically, the difference in thickness T2a between the first horizontal insulating layers IMP1a may be achieved by adjusting process conditions (e.g., ion implantation energy and ion implantation amount) in at least two ion implantation processes. Since a plurality of first horizontal insulating layers IMP1a are provided, the maximum width W2m of the first vertical structure VS1 may be less than Figure 4A The maximum width in .

[0066] Figure 5 FIG. 1 is a diagram showing a portion of a three-dimensional semiconductor memory device according to an embodiment of the present inventive concept (eg Figure 2B C) is an enlarged cross-sectional view.

[0067] Will refer to Figure 5 The source structure SC and one of the first vertical structures VS1 are described, but the remaining first vertical structures VS1 may also have substantially the same features as those described herein. As described above, the source structure SC may include a first source conductive pattern SCP1 and a second source conductive pattern SCP2, and each of the first vertical structures VS1 may include a data storage pattern DSP, a first vertical semiconductor pattern VSP1, a buried insulating pattern VI, and a lower data storage pattern DSPr.

[0068] The first source conductive pattern SCP1 of the source structure SC may contact the first vertical semiconductor pattern VSP1, and the second source conductive pattern SCP2 may be spaced apart from the first vertical semiconductor pattern VSP1 with the data storage pattern DSP interposed therebetween. The first source conductive pattern SCP1 may be spaced apart from the buried insulating pattern VI with the first vertical semiconductor pattern VSP1 interposed therebetween.

[0069] Specifically, the first source conductive pattern SCP1 may include a protruding portion SCP1bt located at a height higher than the bottom surface SCP2b of the second source conductive pattern SCP2 or located at a height lower than the bottom surface SCP1b of the first source conductive pattern SCP1. However, the protruding portion SCP1bt may be located at a height lower than the top surface SCP2a of the second source conductive pattern SCP2. A surface of the protruding portion SCP1bt, for example, contacting the data storage pattern DSP or the lower data storage pattern DSPr, may have a curved shape.

[0070] Fig. 6A is a plan view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept. Figure 6B and Figure 6CFIG. 1 is a diagram showing a three-dimensional semiconductor memory device according to an embodiment of the present inventive concept. Fig. 6A For the sake of simplicity, the previous reference Figures 2A to 5 Described elements may be identified by the same reference numerals without repeating their repeated descriptions.

[0071] Reference Fig. 6A , Figure 6B and Figure 6C , a three-dimensional semiconductor memory device may include a peripheral circuit structure PS and a cell array structure CS on the peripheral circuit structure PS.

[0072] The peripheral circuit structure PS may include a first substrate 10, a peripheral circuit PTR integrated on the top surface of the first substrate 10, and a peripheral insulating layer 30 covering the peripheral circuit PTR. The first substrate 10 may be a silicon substrate, a silicon germanium substrate, a germanium substrate, or a single crystal epitaxial layer grown on a single crystal silicon substrate. The first substrate 10 may have an active region defined by a device isolation layer 11.

[0073] The peripheral circuit PTR may include, for example, a row decoder and a column decoder, a page buffer, a control circuit, etc. Specifically, each peripheral circuit PTR may include a peripheral gate electrode 21, a peripheral gate insulating layer 23, a peripheral covering pattern 25, a peripheral gate spacer 27, and a peripheral source / drain region 29. The peripheral gate insulating layer 23 may be provided between the peripheral gate electrode 21 and the first substrate 10. The peripheral covering pattern 25 may be provided on the peripheral gate electrode 21. The peripheral gate spacer 27 may cover the side surface of the peripheral gate electrode 21, the side surface of the peripheral gate insulating layer 23, and the side surface of the peripheral covering pattern 25. The peripheral source / drain region 29 may be provided in a portion of the substrate 10 located on both sides of the peripheral gate electrode 21. The peripheral circuit line 33 may be electrically connected to the peripheral circuit PTR through the peripheral contact plug 31. As an example, the peripheral contact plug 31 and the peripheral circuit line 33 may be connected to the transistor on the first substrate 10. For example, the transistor on the first substrate 10 may include an NMOS, a PMOS, or a surrounding gate transistor. The peripheral insulating layer 30 may be provided on the top surface of the first substrate 10. In one implementation, a peripheral insulating layer 30 may be provided on the first substrate 10 to cover the peripheral circuit PTR, the peripheral contact plug 31, and the peripheral circuit line 33. The peripheral insulating layer 30 may include a plurality of insulating layers stacked on the substrate 10. For example, the peripheral insulating layer 30 may be formed of or include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k dielectric material.

[0074] The cell array structure CS may be provided on the peripheral insulating layer 30, and in one embodiment, the cell array structure CS may include a second substrate 100, an electrode structure ST on the second substrate 100, a planarization insulating layer 130 provided on the second substrate 100 to cover the electrode structure ST, and an upper insulating layer 150 covering the electrode structure ST and the planarization insulating layer 130. The cell array structure CS may further include: a first horizontal insulating layer IMP1 provided in the uppermost interlayer insulating layer ILDb of the electrode structure ST and extending along the electrodes EL and ELt; and a second horizontal insulating layer IMP2 provided in the upper insulating layer 150 and extending along the electrodes EL and ELt.

[0075] The connection structure ICS may be provided to connect the cell array structure CS to the peripheral circuit structure PS. The connection structure ICS may include one of the conductive lines CL on the upper insulating layer 150, a cell contact plug CPLG, and a through plug TPLG. The through plug TPLG may be provided to penetrate the upper insulating layer 150, the planarization insulating layer 130, the first and second horizontal insulating layers IMP1 and IMP2, the second substrate 100, and a portion of the peripheral insulating layer 30. The through plug TPLG may be connected to at least one of the peripheral circuit lines 33. Although not shown, a plurality of through plugs TPLG may be provided and may be respectively connected to the peripheral circuit lines 33.

[0076] Figure 7 FIG. 1 is a diagram showing a three-dimensional semiconductor memory device according to an embodiment of the present inventive concept. Fig. 6A For the sake of simplicity, the previous reference FIG. 2A to FIG. 6C Described elements may be identified by the same reference numerals without repeating their repeated descriptions.

[0077] Reference Figure 7, each electrode structure ST may include a first electrode structure ST1 and a second electrode structure ST2. The first electrode structure ST1 may include first electrodes EL1 sequentially stacked on a substrate 10 and a first interlayer insulating layer ILD1a provided between the first electrodes EL1. The second electrode structure ST2 may include second electrodes EL2 sequentially stacked on a substrate 10 and second interlayer insulating layers ILD2a and ILD2b provided between the second electrodes EL2. The first electrode structure ST1 may be provided on the source structure SC, and the second electrode structure ST2 may be provided on the first electrode structure ST1. Specifically, the second electrode structure ST2 may be provided on the top surface of the uppermost one of the first interlayer insulating layers ILD1a of the first electrode structure ST1. Therefore, the lowermost one of the second interlayer insulating layers ILD2a and ILD2b of the second electrode structure ST2 may contact the uppermost one of the first interlayer insulating layers ILD1a of the first electrode structure ST1.

[0078] The first vertical channel CH1 may be provided to penetrate the first electrode structure ST1 and expose a portion of the second substrate 100. The second vertical channel CH2 may be provided to penetrate the second electrode structure ST2 and expose the first vertical channel CH1. The first vertical channel CH1 and the second vertical channel CH2 may be connected to each other. The lower diameter of the second vertical channel CH2 may be smaller than the upper diameter of the first vertical channel CH1. The first vertical structure VS1 may be provided in the first vertical channel CH1 and the second vertical channel CH2. Each of the first vertical structures VS1 may include a data storage pattern DSP, a first vertical semiconductor pattern VSP1, and a first conductive pad PAD1. The data storage pattern DSP may be provided to conformally cover the side surfaces of the first vertical channel CH1 and the side surfaces of the second vertical channel CH2.

[0079] Fig. 8A and Fig. 9A FIG. 1 is a diagram showing a three-dimensional semiconductor memory device according to an embodiment of the present inventive concept. Figure 2A A cross-sectional view taken along line II'. Figure 8B and Fig. 9B FIG. 1 is a diagram showing a three-dimensional semiconductor memory device according to an embodiment of the present inventive concept. Figure 2A For the sake of simplicity, the previous reference Figures 2A to 5 Described elements may be identified by the same reference numerals without repeating their repeated descriptions.

[0080] Reference Fig. 8A and Figure 8B , the three-dimensional semiconductor memory device may include an upper insulating layer 150 including the second horizontal insulating layer IMP2 without the first horizontal insulating layer IMP1. Fig. 9A and Fig. 9B , the three-dimensional semiconductor memory device may include an uppermost interlayer insulating layer ILDb including a first horizontal insulating layer IMP1 without a second horizontal insulating layer IMP2. The first horizontal insulating layer IMP1 may extend from the uppermost interlayer insulating layer ILDb into the planarization insulating layer 130. In other words, Figure 2B and Figure 2C One of the first horizontal insulating layer IMP1 and the second horizontal insulating layer IMP2 may be omitted, and the other may be provided.

[0081] According to an embodiment of the inventive concept, a three-dimensional semiconductor memory device may include an insulating layer formed by an ion implantation process to have a portion with improved etching resistance, which makes it possible to reduce the maximum width of a contact with a high aspect ratio. Therefore, it is possible to prevent a short circuit from being formed between contacts and improve electrical characteristics of the three-dimensional semiconductor memory device.

[0082] While example embodiments of the present inventive concepts have been particularly shown and described, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the scope of the appended claims.

[0083] This patent application claims the priority of Korean Patent Application No. 10-2019-0155598 filed in the Korean Intellectual Property Office on November 28, 2019, the entire contents of which are incorporated herein by reference.

Claims

1. A three-dimensional semiconductor memory device, comprising: a substrate including a cell array region and a connection region at an end of the cell array region; an electrode structure extending from the cell array region to the connection region, the electrode structure comprising electrodes sequentially stacked on the substrate; an upper insulating layer on the electrode structure; a first horizontal insulating layer in the upper insulating layer and extending along the electrode; as well as a first contact plug in the connection region, which penetrates the upper insulating layer and the first horizontal insulating layer and extends to a corresponding electrode among the electrodes, wherein a top surface of the first horizontal insulating layer is at a height lower than a top surface of the first contact plug, and The first horizontal insulating layer includes a material having higher etching resistance than that of the upper insulating layer. 2 . The device according to claim 1 , wherein the first horizontal insulating layer comprises a plurality of first horizontal insulating layers provided in the upper insulating layer and vertically spaced apart from each other with a portion of the upper insulating layer interposed therebetween.

3. The device according to claim 1, further comprising: An interlayer insulating layer, wherein the interlayer insulating layer and the electrodes are alternately stacked; and a second horizontal insulating layer in an uppermost one of the interlayer insulating layers, extending along the electrode, The second horizontal insulating layer is between the uppermost one of the electrodes and the first horizontal insulating layer.

4. The device according to claim 3, wherein the second horizontal insulating layer extends from the uppermost one of the interlayer insulating layers toward the connection region, and The first contact plug penetrates the second horizontal insulating layer.

5. The device according to claim 3, further comprising a vertical structure penetrating the electrode structure, Wherein a top surface of the second horizontal insulating layer is at a height lower than a top surface of the vertical structure. 6 . The device of claim 5 , wherein each of the vertical structures comprises a data storage pattern, a vertical semiconductor pattern surrounded by the data storage pattern, and a conductive pad connected to a top of the vertical semiconductor pattern. 7 . The device of claim 5 , wherein each of the vertical structures has a width that increases from a top surface of the uppermost one of the interlayer insulating layers to the second horizontal insulating layer and decreases from the second horizontal insulating layer to the substrate.

8. The device according to claim 1, wherein the substrate further comprises a peripheral circuit region, the peripheral circuit region comprising a peripheral circuit thereon, The device also includes a second contact plug penetrating the upper insulating layer and the first horizontal insulating layer in the peripheral circuit region, and wherein the second contact plug is connected to the peripheral circuit. 9 . The device of claim 8 , wherein each of the first contact plug and the second contact plug has a width that increases from a top surface of the upper insulating layer to the first horizontal insulating layer and decreases from the first horizontal insulating layer to the substrate.

10. The device according to claim 1, wherein the distance from the top surface of the upper insulating layer to the first horizontal insulating layer is within and between. 11 . The device of claim 1 , wherein the first horizontal insulating layer comprises a material containing at least one of nitrogen (N), carbon (C), boron (B), phosphorus (P), helium (He), and argon (Ar).

12. The device according to claim 1, further comprising: a peripheral circuit structure below the substrate, the peripheral circuit structure comprising a peripheral circuit and a peripheral line connected to the peripheral circuit; and at least one third contact plug adjacent to the connection region, which penetrates the upper insulating layer, the first horizontal insulating layer, and a portion of the substrate, wherein one of the peripheral lines is connected to the at least one third contact plug.

13. A three-dimensional semiconductor memory device, comprising: a substrate including a cell array region and a connection region at an end of the cell array region; An electrode structure extending from the cell array region to the connection region, the electrode structure comprising electrodes and interlayer insulating layers alternately stacked on the substrate; a first horizontal insulating layer in an uppermost one of the interlayer insulating layers, extending along the electrode; a vertical structure penetrating the electrode structure and the first horizontal insulating layer; an upper insulating layer on the electrode structure and the vertical structure; a second horizontal insulating layer in the upper insulating layer, extending along the electrode; as well as a first contact plug penetrating the upper insulating layer and the first and second horizontal insulating layers, wherein the first horizontal insulating layer and the second horizontal insulating layer are vertically spaced apart from each other, wherein a top surface of the first horizontal insulating layer is at a height lower than a top surface of the vertical structure, wherein a top surface of the second horizontal insulating layer is at a height lower than a top surface of the first contact plug, and The concentration of the non-metallic element except oxygen is higher in the second horizontal insulating layer than in the upper insulating layer.

14. The device according to claim 13, wherein the non-metal element is one selected from nitrogen (N), carbon (C), boron (B), phosphorus (P), helium (He), and argon (Ar).

15. The device of claim 13 , wherein each of a first distance from a top surface of the uppermost one of the interlayer insulating layers to a top surface of the first horizontal insulating layer and a second distance from a top surface of the upper insulating layer to a top surface of the second horizontal insulating layer is within and between.

16. The device according to claim 13, wherein the substrate further comprises a peripheral circuit region, the peripheral circuit region comprising a peripheral circuit thereon, The device also includes a second contact plug in the peripheral circuit region, the second contact plug penetrating the upper insulating layer and the first and second horizontal insulating layers, and wherein the second contact plug is connected to the peripheral circuit. 17 . The device of claim 13 , wherein a concentration of the non-metallic element other than oxygen is higher in the first horizontal insulating layer than in the uppermost one of the interlayer insulating layers.

18. The device according to claim 13, further comprising: a peripheral circuit structure below the substrate, the peripheral circuit structure comprising a peripheral circuit and a peripheral line connected to the peripheral circuit; and at least one third contact plug adjacent to the connection region, penetrating the upper insulating layer, the first horizontal insulating layer, the second horizontal insulating layer, and a portion of the substrate, wherein one of the peripheral lines is connected to the at least one third contact plug.

19. A three-dimensional semiconductor memory device, comprising: a substrate including a cell array region, a peripheral circuit region including a peripheral circuit, and a connection region between the cell array region and the peripheral circuit region; An electrode structure extending from the cell array region to the connection region, the electrode structure comprising electrodes and interlayer insulating layers vertically and alternately stacked on the substrate; a vertical structure penetrating the electrode structure, the vertical structure comprising a data storage pattern, a vertical semiconductor pattern surrounded by the data storage pattern, and a conductive pad connected to a top of the vertical semiconductor pattern; an upper insulating layer on the electrode structure and the vertical structure; a horizontal insulating layer in the upper insulating layer, extending along the electrode; a bit line on the upper insulating layer and electrically connected to the conductive pad of the vertical structure; a plurality of first contact plugs, wherein each first contact plug is on the connection region and penetrates the upper insulating layer, the horizontal insulating layer, and one of the interlayer insulating layers, and extends to and is connected to a corresponding one of the electrodes; a plurality of second contact plugs on the peripheral circuit region, which penetrate the upper insulating layer and the horizontal insulating layer and are connected to the peripheral circuit; as well as conductive lines connected to the first contact plug and the second contact plug, respectively, wherein a top surface of the horizontal insulating layer is at a height lower than top surfaces of the first contact plug and the second contact plug, and The concentration of the non-metallic element except oxygen is higher in the horizontal insulating layer than in the upper insulating layer. 20 . The device of claim 19 , wherein the horizontal insulating layer comprises a plurality of horizontal insulating layers provided in the upper insulating layer and vertically spaced apart from each other with a portion of the upper insulating layer interposed therebetween.

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