Buck converter circuit, integrated chip, integrated circuit and buck conversion method

Abstract

The present disclosure provides a buck converter circuit and a buck conversion method. In some embodiments, the buck converter circuit includes a first switching device, a second switching device, an inductor, and a controller. The inductor is electrically coupled to a node at which a source / drain terminal of the first switching device and a source / drain terminal of the second switching device are electrically coupled. The controller is configured to cause the first switching device to alternately change between being turned on and off, and is further configured to cause the second switching device to alternately change between being turned on and off. When the second switching device is turned on, the first switching device is turned off. Immediately before or after the second switching device is changed between being turned on and off, the first switching device is partially turned on.

Description

[0001] The present invention is a divisional application of the invention patent application with application number 201910543322.3 filed on June 21, 2019 and invention name “Buck Converter Circuit and Buck Conversion Method”. Technical Field

[0002] The present invention relates to a buck converter circuit and a buck conversion method, and in particular to a buck converter circuit and a buck conversion method capable of reducing dead time conduction loss. Background Art

[0003] A buck converter is a DC to DC power converter that steps down the voltage from its input to its output (while stepping up the current). A buck converter is a type of switching converter that includes at least two semiconductor devices and at least one energy storage element. For example, a buck converter may include two transistors and an inductor. Switching converters are more efficient, especially compared to linear regulators, so switching converters are often used in integrated circuits. Summary of the invention

[0004] According to an embodiment of the present disclosure, a buck converter circuit includes a first switching device, a second switching device, an inductor, and a controller. The inductor is electrically coupled to a node at which a first source / drain of the first switching device is electrically coupled to a first source / drain of the second switching device. The controller is configured to cause the first switching device to alternately change between being turned on and off, and is further configured to cause the second switching device to alternately change between being turned on and off. When the second switching device is turned on, the first switching device is turned off. Immediately before or after the second switching device is changed between being turned on and off, the first switching device is partially turned on.

[0005] According to an embodiment of the present disclosure, a buck converter circuit includes a first switching device, a second switching device, an inductor, a loss prevention circuit, and a controller. The first switching device and the second switching device are coupled to the inductor at a node. The controller is configured to apply a first pulse train and a second pulse train to the gate terminals of the first switching device and the second switching device, respectively, so that the first switching device and the second switching device alternately change between a first state and a second state. The loss prevention circuit is electrically coupled to the gate terminals of the first switching device and the second switching device, and is configured to provide a voltage bias to the gate terminal of the first switching device that is less than a threshold voltage of the first switching device when transitioning between the first state and the second state.

[0006] According to an embodiment of the present disclosure, a step-down conversion method includes: applying a first pulse train to a first switching device to cause the first switching device to alternately change between being on and being off; applying a second pulse train to a second switching device to cause the second switching device to alternately change between being on and being off, wherein when the first switching device is on, the second switching device is off, and when the second switching device is on, the first switching device is off; charging an inductor from a node at which the source / drain regions of the first switching device and the second switching device are electrically coupled, wherein the charging is performed when the second switching device is on; discharging the inductor when the second switching device is off; and immediately after detecting that the first pulse train is low and the second pulse train is high, biasing the gate of the first switching device with a voltage less than a threshold voltage of the first switching device. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1A Circuit diagrams showing some embodiments of buck converter circuits including conduction loss reduction circuits.

[0009] Figure 1B Show Figure 1A Circuit diagrams of various alternative embodiments of the circuit diagrams.

[0010] Figure 2 Cross-sectional views of some embodiments of buck converter circuits including conduction loss reduction circuits are shown.

[0011] Figure 3 Shown including from Figure 1A , Figure 1B or Figure 2 A timing diagram of some embodiments of the operation of a buck converter circuit of a conduction loss reduction circuit.

[0012] Figure 4 A graph illustrating current-voltage (IV) characteristics for an intrinsic diode within a first switch device of a buck converter circuit according to some embodiments of the present disclosure is shown.

[0013] Figures 5 to 9 Non-limiting example voltages and currents are used to illustrate the various states of Figure 2 Circuit diagram of a buck converter circuit.

[0014] Fig.10 A block diagram illustrating some embodiments of a method of using a buck converter circuit including a conduction loss reduction circuit.

[0015] Description of Figure Numbers

[0016] 100a, 100b, 500, 600, 700, 800, 900: circuit diagram;

[0017] 102. Q1: a first switch device;

[0018] 102a: a first intrinsic body diode;

[0019] 104: reference node;

[0020] 106. VLX: first node;

[0021] 108. Q2: second switch device;

[0022] 108a: a second intrinsic diode;

[0023] 110, VDD: power supply;

[0024] 112: Inductor;

[0025] 114. Vout: second node;

[0026] 116: load;

[0027] 118: Capacitor;

[0028] 120: controller;

[0029] 122, VGL, VGL2: first pulse wave;

[0030] 124: Low-side gate driver circuit;

[0031] 126. VGH: second pulse wave;

[0032] 128: High-side gate driver circuit;

[0033] 130: Conduction loss reduction circuit;

[0034] 132. VGL1: stepped pulse wave;

[0035] 134. VDD5V: second power supply;

[0036] 136: resistor;

[0037] 138: Level shifter;

[0038] 140, M1: fifth transistor;

[0039] 141: filter;

[0040] 142: high side power supply;

[0041] 144: a first transistor;

[0042] 146: a second transistor;

[0043] 150: a second plurality of filters;

[0044] 152: low side power supply;

[0045] 154, M2: a third transistor;

[0046] 156: fourth transistor;

[0047] 160: sixth transistor;

[0048] 200: cross-sectional view;

[0049] 202: gate electrode;

[0050] 203: Anti-corrosion protective oxide layer;

[0051] 204: sidewall spacer;

[0052] 206: gate dielectric;

[0053] 208: second source / drain region;

[0054] 210: lightly doped N-type region;

[0055] 212: high voltage P-type implantation region;

[0056] 214: N-type drain drift;

[0057] 216: deep P well;

[0058] 218: N-buried layer;

[0059] 220: substrate;

[0060] 221: Shallow P well;

[0061] 222: shallow N-well;

[0062] 224: Isolation structure;

[0063] 226: first contact area;

[0064] 228: second contact area;

[0065] 230: third contact area;

[0066] 232: first source / drain region;

[0067] 242: third current path;

[0068] 244: second current path;

[0069] 246: first current path;

[0070] 250: NPN transistor;

[0071] 252: internal diode;

[0072] 260, PVDD: the third power supply;

[0073] 300: timing diagram;

[0074] 302: first time frame;

[0075] 304: second time frame;

[0076] 306: third time frame;

[0077] 308: fourth time frame;

[0078] 310: fifth time frame;

[0079] 312: first pulse wave curve graph;

[0080] 314: second pulse wave curve graph;

[0081] 316: third pulse wave curve graph;

[0082] 318: first control signal curve graph;

[0083] 320: a second control signal curve graph;

[0084] 322: first node voltage curve graph;

[0085] 322a: a first voltage line;

[0086] 322b: second voltage line;

[0087] 324: Inductor current graph;

[0088] 400: IV curve;

[0089] 502: first position;

[0090] 1000: block diagram;

[0091] 1002, 1004, 1006, 1008, 1010, 1012: action;

[0092] GND: reference voltage;

[0093] i1: first average current;

[0094] i2: second average current;

[0095] i3: third current;

[0096] i4: fourth current;

[0097] i b : base current;

[0098] i c : Collector current;

[0099] i d : Intrinsic diode current;

[0100] i e : emitter current;

[0101] i L : inductor current;

[0102] i Q1 : The first switch current;

[0103] i Q2 : The second switch current;

[0104] t: time;

[0105] t0: initial time;

[0106] t1: first time;

[0107] t2: second time;

[0108] t3: third time;

[0109] t4: fourth time;

[0110] t5: fifth time;

[0111] Vcontrol1: first control signal;

[0112] Vcontrol2: second control signal;

[0113] V f1 : First forward bias;

[0114] V f2 : Second forward bias. DETAILED DESCRIPTION

[0115] The present disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are just examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature is formed in direct contact with the second feature, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0116] Additionally, for ease of description, spatially relative terms such as "below," "below," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another element or feature(s) as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0117] The buck converter may include a p-type metal-oxide-semiconductor field-effect transistor (MOSFET) and an n-type MOSFET electrically coupled to an inductor at a first node. The n-type MOSFET is gated using a first input signal supplied by a low-side gate driver of a control circuit. The p-type MOSFET is gated using a second input signal supplied by a low-side gate driver of a control circuit. The source of the p-type MOSFET is electrically coupled to a power supply of a first voltage domain, and the source of the n-type MOSFET is electrically coupled to a reference node (e.g., ground). The control circuit supplies the first input signal and the second input signal to alternately change the p-type MOSFET and the n-type MOSFET between being turned on and off. When the n-type MOSFET is turned on, the p-type MOSFET is turned off, thereby defining a first state. When the n-type MOSFET is turned off, the p-type MOSFET is turned on, thereby defining a second state. Depending on which of the n-type MOSFET and the p-type MOSFET is in the on state, the inductor is charged or discharged. A dead-time segment occurs immediately before and after a transition from the first state to the second state, or vice versa. The control circuit ensures that both the n-type MOSFET and the p-type MOSFET are turned off during the dead time period. The dead time period ensures that the power supply is not shorted to ground when transitioning between the first state and the second state. The challenge of the buck converter is the conduction power loss during the dead time period.

[0118] During the dead time period, the body diode in the n-type MOSFET is forward biased, whereby current flows through the body diode. The current flowing through the body diode will trigger a parasitic NPN power loss in the substrate between the power supply terminal and the drain of the N-type MOSFET. Therefore, a method for overcoming the conduction power loss may be to reduce the elapsed time that the buck converter remains in the dead time period. Reducing the elapsed time in the dead time period will result in less power loss because the current will spend less time flowing through the body diode. However, reducing the elapsed time too much may result in a failure to protect the power supply from shorting to the reference node when transitioning between the first state and the second state.

[0119] Various embodiments of the present disclosure are directed to a buck converter including a conduction loss prevention circuit configured to reduce the voltage of a body diode of an n-type MOSFET. In some embodiments, the conduction loss prevention circuit includes a transistor, a pull-up resistor, and a level shifter. A first source / drain region of the transistor is electrically coupled to a reference node, and a second source / drain region is electrically coupled to a gate terminal of the n-type MOSFET. The pull-up resistor is electrically coupled to the gate terminal of the n-type MOSFET from a second power supply of a second voltage domain. The level shifter is electrically coupled from the gate terminal of the p-type MOSFET to the gate terminal of the transistor. The conduction loss prevention circuit is configured to bias the gate terminal of the n-type MOSFET with a voltage less than a threshold voltage of the n-type MOSFET during a dead time period. A weak reverse current flows through a conductive channel formed in the n-type MOSFET. The weak reverse current is connected in parallel with the current flowing through the body diode, thereby effectively reducing the voltage of the body diode and reducing the conduction power loss in the buck converter.

[0120] refer to Figure 1A, a circuit diagram 100a of some embodiments of a buck converter circuit is provided. A first switching device 102 (e.g., Q1) has a first source / drain terminal electrically coupled to a reference node 104 (e.g., ground), and further has a second source / drain terminal electrically coupled to a first node 106 (e.g., VLX). In some embodiments, the first switching device 102 includes a first intrinsic body diode 102a electrically coupled between the first source / drain terminal and the second source / drain terminal. A second switching device 108 (e.g., Q2) has a third source / drain terminal electrically coupled to the first node 106, and further has a fourth source / drain terminal electrically coupled to a power source 110 (e.g., VDD). In some embodiments, the second switching device 108 includes a second intrinsic diode 108a electrically coupled between the third source / drain terminal and the fourth source / drain terminal. The first switch device 102 and the second switch device 108 may be, for example, metal oxide semiconductor field effect transistors (MOSFETs), some other suitable metal oxide semiconductor (MOS) devices, or some other suitable insulated-gate field-effect-transistor (IGFET). In some embodiments, the first switch device 102 is an n-channel MOS device and the second switch device 108 is a p-channel MOS device. In some embodiments, the first switch device 102 is a p-channel MOS device and the second switch device 108 is an n-channel MOS device. The power supply 110 may be, for example, a direct current (DC) voltage source and / or may apply, for example, 5 volts, 6 volts, 12 volts, or some other suitable voltage to the fourth source / drain terminal of the second switch device 108.

[0121] The inductor 112 is electrically coupled from the first node 106 to the second node 114 (e.g., Vout), and the load 116 is electrically coupled from the second node 114 to the reference node 104. In some embodiments, the capacitor 118 is also electrically coupled from the second node 114 to the reference node 104. During use of the buck converter circuit, the inductor 112 is charged when the second switching device 108 is in the on state, and is discharged when the second switching device 108 is in the off state. Similarly, the capacitor 118 is charged when the second switching device 108 is in the on state, and is discharged when the second switching device 108 is in the off state.

[0122] The controller 120 (e.g., dead time control) is configured to generate a first pulse wave (or string) 122 (e.g., VGL) provided to the gate of the first switching device 102. In some embodiments, the first pulse wave 122 is provided to the gate of the first switching device 102 via a low-side gate driver circuit 124. The first pulse wave 122 causes the first switching device 102 to switch alternately between an on state and an off state. For example, in the case where the first switching device 102 is an n-channel MOS device, the first switching device 102 may be in an on state at each pulse and may be in an off state between pulses. In addition, the controller 120 is configured to generate a second pulse wave (or string) 126 (e.g., VGH) provided to the gate of the second switching device 108. In some embodiments, the second pulse wave 126 is provided to the gate of the second switching device 108 via a high-side gate driver circuit 128. The second pulse wave 126 causes the second switching device 108 to switch alternately between an on state and an off state. For example, in the case where the second switch device 108 is a p-channel MOS device, the second switch device 108 may be in an off state at each pulse and may be in an on state between pulses. In some embodiments, the duty cycle of the second pulse wave 126 is greater than the duty cycle of the first pulse wave 122, the second pulse wave 126 has a phase offset relative to the first pulse wave 122, the frequency of the second pulse wave 126 is the same as the frequency of the first pulse wave 122, or any combination of the foregoing.

[0123] The high-side gate driver circuit 128 includes a plurality of filters 141, a high-side power supply 142, a first transistor 144, and a second transistor 146. The plurality of filters 141 are electrically coupled between a first output of the controller 120 and gate terminals of the first transistor 144 and the second transistor 146. A first source / drain terminal of the first transistor 144 is electrically coupled to a gate of the second switching device 108. A first source / drain terminal of the second transistor 146 is electrically coupled to the high-side power supply 142, and a second source / drain terminal of the second transistor 146 is electrically coupled to a gate of the second switching device 108. In some embodiments, the first transistor 144 is an n-type MOS device and the second transistor 146 is a p-type MOS device, or vice versa.

[0124] The low-side gate driver circuit 124 includes a second plurality of filters 150, a low-side power supply 152, a third transistor 154 (e.g., M2), and a fourth transistor 156. The second plurality of filters 150 are electrically coupled between the second output of the controller 120 and the gate terminals of the third transistor 154 and the fourth transistor 156. The first source / drain terminal of the third transistor 154 is electrically coupled to the gate of the first switching device 102. The first source / drain terminal of the fourth transistor 156 is electrically coupled to the low-side power supply 152, and the second source / drain terminal of the fourth transistor 156 is electrically coupled to the gate of the first switching device 102. In some embodiments, the third transistor 154 is an n-type MOS device, and the fourth transistor 156 is a p-type MOS device, or vice versa.

[0125] In some embodiments, the high-side power supply 142 supplies a high voltage relative to the low-side power supply 152. For example, in some embodiments, the high-side power supply 142 may supply 20 volts or more, while the low-side power supply 152 may supply 5 volts or less. However, other voltages may be used. In addition, in some embodiments, the high-side power supply 142 is the same as the power supply 110. The high-side power supply 142 and the low-side power supply 152 may be, for example, DC power supplies or some other suitable power supplies.

[0126] The first pulse wave 122 and the second pulse wave 126 are generated so that the first switch device 102 and the second switch device 108 are not turned on at the same time. Turning on the first switch device 102 and the second switch device 108 at the same time will cause the power supply 110 to be electrically shorted to the reference node 104, which may damage and / or destroy the power supply 110. Therefore, the first switch device 102 and the second switch device 108 are not turned on at the same time, and the first pulse wave 122 is coordinated with the second pulse wave 126, so there is a dead time (or transient) period immediately before and immediately after each pulse of the first pulse wave 122. During the dead time period, the first pulse wave 122 and the second pulse wave 126 are generated, so the first switch device 102 and the second switch device 108 are disconnected.

[0127] In some embodiments where the first switch device 102 is an n-channel MOS device and the second switch device 108 is a p-channel MOS device, the dead time period is generated by: 1) generating the first pulse wave 122 and the second pulse wave 126 having the same frequency; 2) generating the second pulse wave 126 having a larger duty cycle than the first pulse wave 122; and 3) introducing a phase shift into the first pulse wave 122 or the second pulse wave 126 so that each pulse of the first pulse wave 122 is centered or approximately centered on the corresponding pulse of the second pulse wave 126. In these embodiments, the dead time period is generated where the second pulse wave 126 is high and the first pulse wave 122 is low. For example, the dead time period may occur immediately before the second pulse wave 126 transitions from high to low (i.e., immediately before the falling edge of the second pulse wave 126). As another example, the dead-band period may occur immediately after the second pulse wave 126 transitions from low to high (ie, immediately after a rising edge of the second pulse wave 126 ).

[0128] If both the first switching device 102 and the second switching device 108 are completely turned off during the dead time period, conduction power loss may occur due to the current from the inductor 112 traveling through the first intrinsic body diode 102a of the first switching device 102 to the reference node 104. The current flowing through the first intrinsic body diode 102a of the first switching device 102 triggers additional conduction power loss through an NPN junction (not shown) within a substrate (not shown) between the power source 110 and the first node 106. A conduction loss reduction circuit 130 (e.g., a loss prevention circuit) is electrically coupled to the gate of the first switching device 102 to reduce or eliminate the conduction power loss.

[0129] The conduction loss reduction circuit 130 includes a second power supply 134 (e.g., VDD5V), a resistor 136, a level shifter 138, and a fifth transistor 140 (e.g., M1). The resistor 136 is electrically coupled between the second power supply 134 and the gate of the first switching device 102. The fifth transistor 140 has a fifth source / drain terminal electrically coupled to the reference node 104, a sixth source / drain terminal electrically coupled to the gate of the first switching device 102, and a gate terminal electrically coupled to the level shifter 138. The level shifter 138 is electrically coupled between the gate of the second switching device 108 and the gate of the fifth transistor 140. The second power supply 134 may be, for example, a direct current (DC) voltage source, and / or may apply, for example, 5 volts, 6 volts, 12 volts, or some other suitable voltage to the resistor 136. The fifth transistor 140 may be, for example, a MOSFET, some other suitable MOS device, or some other suitable IGFET. In some embodiments, the fifth transistor 140 is an n-channel MOS device or a p-channel MOS device. In some embodiments, the low-side power supply 152 is the same as the second power supply 134 , and / or the second power supply 134 supplies a voltage that is lower than the voltage of the power supply 110 .

[0130] The conduction loss reduction circuit 130 monitors the dead time period and biases the gate of the first switching device 102 during the dead time period so that the first switching device 102 is partially turned on. In some embodiments, the bias applied to the gate of the first switching device 102 can be adjusted by the resistance value of the resistor 136, the voltage value on the fifth transistor 140 (e.g., M1) when operating in the on state, the voltage value on the third transistor 154 (e.g., M2) when operating in the on state, or any combination of the foregoing. By partially turning on, it means that the voltage of the gate of the first switching device 102 is biased with a voltage bias that is less than the threshold voltage of the first switching device 102. As a result, the gate of the first switching device 102 is driven by a step-shaped pulse wave 132 (e.g., VGL), which is a combination of the first pulse wave 122 and the bias from the conduction loss reduction circuit 130. By causing the first switching device 102 to become partially turned on during the dead time period, the current from the inductor 112 can travel to the reference node 104 through both the first intrinsic body diode 102a of the first switching device 102 and the selective conductive channel of the first switching device 102. This has the effect of reducing conduction power losses. For example, the two parallel paths can reduce the overall resistance value from the inductor 112 to the reference node 104, which can reduce the forward bias of the first intrinsic body diode 102a and thereby reduce power losses. In addition, because the first switching device 102 is only partially turned on, the power supply 110 does not suffer damage due to an electrical short circuit to the reference node 104.

[0131] refer to Figure 1B,supply Figure 1A 100b of some alternative embodiments of the circuit diagram of the present invention, wherein the level shifter 138 is omitted and the conduction loss reduction circuit 130 includes a sixth transistor 160 in place of the resistor 136. A first source / drain terminal of the sixth transistor 160 is electrically coupled to the reference node 104, and a second source / drain terminal of the sixth transistor 160 is electrically coupled to the gate of the first switching device 102. A first source / drain terminal of the fifth transistor 140 is electrically coupled to the second power supply 134, and a second source / drain terminal of the fifth transistor 140 is electrically coupled to the gate of the first switching device 102. Gate terminals of the fifth transistor 140 and the sixth transistor 160 are electrically coupled between the plurality of filters 141 and gate terminals of the first transistor 144 and the second transistor 146. In some embodiments, the fifth transistor 140 is a p-type MOS device and the sixth transistor 160 is an n-type MOS device, or vice versa. A first control signal Vcontrol1 is defined between the plurality of filters 141 and the gate terminals of the first transistor 144 and the second transistor 146. A second control signal Vcontrol2 is defined between the second plurality of filters 150 and the gate terminals of the third transistor 154 and the fourth transistor 156 .

[0132] refer to Figure 2 , a cross-sectional view 200 of some embodiments of a buck converter circuit is provided. In some embodiments, the cross-sectional view 200 shows a circuit according to Figure 1A 1. An additional embodiment of the circuit 100a of FIG. 1. Connections are shown between substrate 220 and terminals and / or nodes. Although not shown, the connections between substrate 220 and terminals and / or nodes may be achieved, for example, by a back-end-of-line (BEOL) interconnect structure overlying substrate 220. Substrate 220 may be, for example, a bulk substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, or some other suitable substrate. In some embodiments, substrate 220 is P-type or N-type.

[0133] An N-buried layer (NBL) 218 ​​is formed in the substrate 220 directly below the deep P-well (DPW) 216, the shallow N-well (SHN) 222, and the shallow P-well (SHP) 221. An N-type drain drift (NDD) 214 is formed directly above the DPW 216. An isolation structure 224 extends into the upper or top surface of the substrate 220 to provide electrical isolation between the source / drain and contact regions within the substrate 220. In some embodiments, the isolation structure 224 includes a plurality of sections each including a dielectric material, and / or is a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, or some other suitable isolation structure.

[0134] The first contact region 226 includes a P-type dopant and has a high doping concentration relative to the substrate 220. The first contact region 226 provides electrical coupling to the substrate 220, and the substrate 220 includes a P-type dopant. The second contact region 228 (e.g., an NBL pickup ring) includes an N-type dopant and has a high doping concentration relative to the SHN 222. The second contact region 228 provides electrical coupling to the SHN 222 and the NBL 218. The second contact region 228 is electrically coupled to the power supply 110. The third contact region 230 (e.g., a reference or ground pickup ring) includes a P-type dopant and has a high doping concentration relative to the SHP 221. The third contact region 230 provides electrical coupling to the SHP 221. The third contact region 230 is electrically coupled to the reference node 104.

[0135] The first switch device 102 includes a gate electrode 202, a gate dielectric 206, a first source / drain region 232, a second source / drain region 208, a high voltage P-type implanted (HVPB) region 212, an NDD 214, and a sidewall spacer 204. The gate electrode 202 overlies the gate dielectric 206 and is electrically coupled to a low-side gate driver ( Figure 1A 124) and conduction loss reduction circuit ( Figure 1A130) so that a first pulse train (e.g., VGL) is applied to the gate electrode 202. The sidewall spacer 204 includes two sections so that the gate electrode 202 is sandwiched between the two sections. The anti-corrosion protective oxide layer 203 is disposed over one of the two sections of the sidewall spacer 204, a portion of the gate electrode 202, and a portion of the gate dielectric 206. The second source / drain region 208 is disposed on a first side of the gate electrode 202 and is sandwiched between two lightly doped N-type regions 210. The second source / drain region 208 includes an N-type dopant and has a high doping concentration relative to the lightly doped N-type region 210. The second source / drain region 208 is adjacent to the HVPB region 212. The second source / drain region 208 is electrically coupled to the reference node 104. The first source / drain region 232 is disposed on a second side of the gate electrode 202 and directly contacts a section of the isolation structure 224. The first source / drain region 232 is laterally offset from the second side of the gate electrode 202. The first source / drain region 232 includes N-type dopants and has a higher doping concentration than the NDD 214. The first source / drain region 232 provides electrical coupling to the NDD 214. The first source / drain region 232 is electrically coupled to the first node 106.

[0136] The third source / drain terminal of the second switch device 108 is electrically coupled to the first node 106, and the fourth source / drain terminal of the second switch device 108 is electrically coupled to the third power supply 260 (e.g., PVDD). In some embodiments, the power supply 110 and the third power supply 260 are the same. Low-side gate driver circuit ( Figure 1A 124) and conduction loss reduction circuit ( Figure 1A 130 ) is electrically coupled to the gate electrode of the second switching device 108 so that the first pulse wave (eg, VGH) is applied to the gate electrode of the second switching device 108 .

[0137] A first internal NPN junction exists between SHN 222, SHP 221, and NDD 214. Under certain operating conditions, the first internal NPN junction functions as an NPN transistor 250, wherein a first current path 246 exists between the second contact region 228 and the first source / drain region 232 along the NPN transistor 250. The second contact region 228 and SHN 222 function as a collector of the NPN transistor 250, the third contact region 230 and SHP 221 function as a base of the NPN transistor 250, and the first source / drain region 232 and NDD 214 function as an emitter of the NPN transistor 250. An internal diode 252 of the NPN transistor 250 exists between the SHP 221 and the NDD 214, thereby directing current toward the NDD 214. When the voltage at the emitter of NPN transistor 250 is less than the voltage at the base of NPN transistor 250, and the voltage at the collector of NPN transistor 250 is greater than the voltage at the emitter and base of NPN transistor 250, NPN transistor 250 is turned on and current will be conducted through first current path 246. It will be appreciated that NPN transistor 250 is drawn for convenience, an actual NPN junction is used as NPN transistor 250 and current does not necessarily follow the path of NPN transistor 250 shown.

[0138] The first intrinsic body diode 102a of the first switching device 102 is positioned between the HVPB region 212 and the NDD 214 below the second source / drain region 208. Under certain operating conditions, the first intrinsic body diode 102a is forward biased and current flows along the second current path 244 from the second source / drain region 208 to the first source / drain region 232. Under certain operating conditions, such as during a triode mode or a subthreshold mode, the first switching device 102 is turned on or partially turned on, respectively, and current flows along a third current path 242 between the second source / drain region 208 and the first source / drain region 232. In some embodiments, the third current path 242 represents a conductive channel formed between the second source / drain region 208 and the first source / drain region 232. In some embodiments, when the first switching device 102 is partially turned on and the second switching device 108 is turned off, the second current path 244 is connected in parallel with the third current path 242. The parallel path between the second current path 244 and the third current path 242 has the effect of reducing conduction power loss.

[0139] During operation of the first switching device 102, when a voltage value higher than the threshold voltage of the first switching device 102 is applied to the gate electrode 202, then the first switching device 102 is operated in a triode mode and is considered to be turned on, and a conductive channel is formed in the HVPB region 212 so that the majority carriers (e.g., electrons) flow from the second source / drain region 208 to the first source / drain region 232 along the third current path 242. If the voltage value applied to the gate electrode 202 is less than the threshold voltage of the first switching device 102, then the first switching device 102 is operated in a partial turn-on mode, a subthreshold mode, or a weak inversion mode, and a smaller conductive channel will be formed in the HVPB region 212 so that the majority carriers (e.g., electrons) flow from the second source / drain region 208 to the first source / drain region 232 along the third current path 242. The current through the small conductive channel will increase as the voltage value increases to the threshold voltage. However, when operating in the weak inversion mode, the small conduction channel allows a smaller current to flow than the conduction channel formed in the triode mode.

[0140] refer to Figure 3 , operation according to Figure 1A , Figure 1B as well as Figure 2 300 of some embodiments of a buck converter circuit. The timing diagram 300 provides an example of operating conditions that apply to a buck converter circuit. However, it should be understood that other operating conditions may apply and the timing diagram 300 is only an example. The first pulse wave graph 312 shows the second pulse wave VGH ( Figure 1A 126). The second pulse wave graph 314 shows a step-shaped pulse wave VGL1 ( Figure 1A The third pulse wave graph 316 shows the first pulse wave VGL2 (eg Figure 1A The third pulse wave graph 316 shows an additional embodiment of the invention. The third pulse wave graph 316 shows an additional embodiment of the invention. Figure 1A The first switching device of the buck converter (130) Figure 1A The first pulse wave VGL2 (102) of the gate Figure 1A 122), wherein the first switch device ( Figure 1A 102) remains disconnected during the dead time period. The first control signal graph 318 shows the first control signal Vcontrol1. The second control signal graph 320 shows the second control signal Vcontrol2. The inductor current graph 324 shows the current through the inductor ( Figure 1A The current i of 112) L .

[0141] The first node voltage graph 322 shows the first node VLX ( Figure 1AThe first node voltage curve diagram 322 shows the voltage value at the first node VLX ( Figure 1A The first voltage line 322a corresponds to the voltage of the first node VLX (106) caused by the step-shaped pulse wave VGL1. The second voltage line 322b corresponds to the voltage of the first node VLX (106) caused by the first pulse wave VGL2. Figure 1A During the dead time period associated with the step-shaped pulse wave VGL1, the first forward bias voltage V f1 Applied to the first intrinsic body diode ( Figure 1A During the dead time period associated with the first pulse wave VGL2, the second forward bias voltage V f2 Applied in a circuit without conduction loss reduction ( Figure 1A The first intrinsic body diode of the buck converter (130) Figure 1A 102a). The first forward bias voltage V f1 Less than the second forward bias voltage V f2 In some embodiments, the first forward bias voltage V f1 than the second forward bias voltage V f2 Approximately 50 percent smaller. The second forward bias voltage V f2 To the first forward bias V f1 The reduction of has the effect of reducing the conduction power loss. In some embodiments, the first forward bias voltage V f1 In the range of approximately -0.3 volts to approximately -0.9 volts. In some embodiments, the second forward bias voltage V f2 In the range of approximately -0.7 volts to approximately -1.9 volts.

[0142] During each of the time frames outlined above, the conduction loss reduction circuit ( Figure 1A 130) processes the first control signal Vcontrol1 and the second control signal Vcontrol2 to determine whether it will cause the first switching device 102 and the second switching device 108 to be disconnected, thereby generating a dead time period. If the conduction loss reduction circuit ( Figure 1A 130) determines that the dead time period will occur, so the conduction loss reduction circuit ( Figure 1A 130) will bias the gate of the first switching device 102, thereby Figure 1A 122) is enhanced into a step-shaped pulse wave VGL1 (for example Figure 1A 132), thereby partially turning on the first switching device 102.

[0143] During the first time frame 302, i.e., between the initial time t0 and immediately before the first time t1, the first control signal Vcontrol1 is low (eg, off) and the second control signal Vcontrol2 is low. VGH is high (eg, on), so the second switch device ( Figure 1A 108) is disconnected. VGL1 is high, so the first switching device ( Figure 1A 102) is turned on. The first node VLX ( Figure 1A The voltage at 106) is at a first constant value and the inductor ( Figure 1A In some embodiments, the first constant value is approximately 0 volts.

[0144] At the first time t1, the second control voltage Vcontrol2 goes high. During the second time frame 304, i.e., between the first time t1 and immediately before the second time t2, the first control signal Vcontrol1 and the second control signal Vcontrol2 are low and high, respectively, thereby generating a first dead time period. Therefore, the conduction loss reduction circuit ( Figure 1A 130) detects the first dead time period and causes the first switching device ( Figure 1A The gate voltage of the first switching device ( Figure 1A In some embodiments, the first switch device ( Figure 1A The threshold voltage of the first switch device (102) is approximately 1.2 volts. Figure 1A The gate of the first switching device ( 102 ) is biased at approximately 0.8 volts. Therefore, the device is partially turned on and the third power supply 260 will not short the reference node 104. Therefore, VGL1 is partially high and the first switching device ( Figure 1A The first node VLX ( Figure 1A The voltage at 106) is at a second constant value, and the inductor ( Figure 1A In some embodiments, the second constant value is negative and / or less than the first constant value. The first average current i1 is conducted through the inductor ( Figure 1A 112). The first dead time conduction loss P1 is equal to P1 = V f1 *i1.

[0145] At the second time t2, the first control voltage Vcontrol1 goes high. During the third time frame 306 between the second time t2 and immediately before the third time t3, the first control signal Vcontrol1 and the second control signal Vcontrol2 are high. VGH is low, so the second switch device ( Figure 1A108) is turned on. VGL1 is low, so the first switching device ( Figure 1A 102) is disconnected. The first node VLX ( Figure 1A The voltage at the inductor 106 increases rapidly at the beginning of the third time frame 306 and settles to a constant value during the remainder of the third time frame 306. Figure 1A 112) is charged in the third time frame 306. The voltage at the first node VLX is greater than the first forward bias voltage V during the third time frame 306. f1 .

[0146] At the third time t3, the first control voltage Vcontrol1 becomes low. During the fourth time frame 308 between the third time t3 and immediately before the fourth time t4, the first control signal Vcontrol1 and the second control signal Vcontrol2 are low and high, respectively, thereby generating a second dead time period. Therefore, the conduction loss reduction circuit ( Figure 1A 130) detects the second dead time period and causes the first switching device ( Figure 1A The gate of 102) is smaller than the gate of the first switching device ( Figure 1A Therefore, VGL1 is partially high, and the first switching device ( Figure 1A 102) is partially turned on. VGH is high, so the second switching device ( Figure 1A During the initial time of the fourth time frame 308, the first node VLX ( Figure 1A The voltage at 106) decreases to a second constant value, and the inductor ( Figure 1A 112) is discharging. In some embodiments, the second constant value is negative and / or less than the first constant value. The second average current i2 is conducted through the inductor ( Figure 1A 112). The second dead time conduction loss P2 is equal to P2 = V f1 *i2.

[0147] At the fourth time t4, the second control voltage Vcontrol2 goes low. During the fifth time frame 310 between the fourth time t4 and immediately before the fifth time t5, the first control signal Vcontrol1 and the second control signal Vcontrol2 are low. VGH is high, so the second switch device ( Figure 1A 108) is disconnected. VGL1 is high, so the first switching device ( Figure 1A 102) is turned on. The first node VLX ( Figure 1A The voltage at 106) is at a first constant value, and the inductor ( Figure 1A 112) is discharging.

[0148] Figure 4 The present invention includes a conduction loss reduction circuit (as previously shown and described in Figure 1A 400 of an embodiment of an intrinsic diode within a first switching device of a buck converter circuit of FIG. 400 reflects the first intrinsic body diode ( Figure 1A When the first forward bias voltage V is applied, f1 When the first intrinsic body diode ( Figure 1A 102a) is less than the first forward current when the second forward bias voltage V is applied. f2 Therefore, the second forward bias voltage V f2 Reduced to the first forward bias V f1 Reducing the conduction loss reduction circuit during the dead time period of the buck converter with the first intrinsic body diode ( Figure 1A The power loss on 102a).

[0149] refer to Figures 5 to 9 , using non-limiting example voltages and currents to provide various states Figure 2 Circuit diagrams 500 to 900 of some embodiments of buck converter circuits. Figure 5 Show according to Figure 3 In a first time frame 302 of the timing diagram 300 , a current flowing in the buck converter circuit in a first discharge state is shown. Figure 6 Show according to Figure 3 3. The current flowing in the buck converter circuit during the first dead time period of the second time frame 304 of the timing diagram 300 of FIG. Figure 7 Show according to Figure 3 In the third time frame 306 of the timing diagram 300 of FIG. 4 , a current flowing in the buck converter circuit in the charging state. Figure 8 Show according to Figure 3 3. The current flowing in the buck converter circuit during the second dead time period in the fourth time frame 308 of the timing diagram 300 of FIG. Fig. 9 Show according to Figure 3 In the fifth time frame 310 of the timing diagram 300 of FIG. 4 , a current flowing in the buck converter circuit during the second discharge state.

[0150] By specific reference Figure 5 In the circuit diagram 500 of FIG. 5 , the second switching device 108 is open and therefore current does not flow between the third power source 260 and the first node 106 , effectively resulting in an open circuit at the first location 502 . LThe inductor 112 induces a current i flowing from the inductor 112 to the second node 114 and through the capacitor 118 and the load 116 to the reference node 104. L , thereby causing the third current i3 to flow from the reference node 104 to the second source / drain region 208 . The third current i3 flows through the third current path 242 , thereby generating a fourth current i4 that will flow from the first source / drain region 232 to the inductor 112 .

[0151] By specific reference Figure 6 In the circuit diagram 600 of FIG. 5 , the second switching device 108 is open and therefore current does not flow between the third power source 260 and the first node 106, effectively causing an open circuit at the first location 502. The first switching device 102 is partially turned on. In some embodiments, the power source 110 is biased at approximately 20 volts, the reference node 104 is biased at approximately 0 volts, and the first node 106 is biased in the range of approximately -0.3 volts to approximately -0.9 volts. The inductor current i L The inductor 112 induces a current i flowing from the inductor 112 to the second node 114 and through the capacitor 118 and the load 116 to the reference node 104. L , so that the third current i3 flows from the reference node 104 to the second source / drain region 208. The first switch current i Q1 The third current path 242 flows through the small conductive channel formed in the first switching device 102 to the first source / drain region 232. The intrinsic diode current i d The base current i flows through the first intrinsic body diode 102a via the second current path 244. b The collector current i flows into the third contact region 230 and reaches the first source / drain region 232 along the first current path 246 through the NPN transistor 250. c The base current i flows into the second contact region 228 and reaches the first source / drain region 232 along the first current path 246 through the NPN transistor 250. b With collector current i c Combined into emitter current i e , where i e =i b +i c The first switch current i Q1 , intrinsic diode current i d and the emitter current i e are connected in parallel, so the fourth current i4 is equal to the sum of the above currents, where i4 = i Q1 +i d +i eThe first dead time conduction loss P1 is equal to P1 = V f1 * i4. In some embodiments, the fourth current i4 is in the range of approximately 1 mA and approximately 100 mA.

[0152] By specific reference Figure 7 700, the second switching device 108 is turned on and thus the second switching current i Q2 Flows between the third power source 260 and the first node 106, thereby charging the inductor 112. The first switching device 102 is open and therefore current does not flow from the first source / drain region 232 to the first node 106, effectively resulting in a short circuit at the second location 702. The inductor current i L From the inductor 112, current flows to the second node 114 and through the capacitor 118 and the load 116 to the reference node 104. In some embodiments, the third power source 260 is approximately 20 volts.

[0153] By specific reference Figure 8 In the circuit diagram 800 of FIG. 5 , the second switching device 108 is open and therefore current does not flow between the third power source 260 and the first node 106, effectively causing an open circuit at the first location 502. The first switching device 102 is partially turned on. In some embodiments, the power source 110 is approximately 20 volts, the reference node 104 is approximately 0 volts, and the first node 106 is in the range of approximately -0.3 volts to approximately -0.9 volts. The inductor current i L The inductor 112 induces a current i flowing from the inductor 112 to the second node 114 and through the capacitor 118 and the load 116 to the reference node 104. L , so that the third current i3 flows from the reference node 104 to the second source / drain region 208. The first switch current i Q1 The third current path 242 flows through the small conductive channel formed in the first switching device 102 to the first source / drain region 232. The intrinsic diode current i d The base current i flows through the first intrinsic body diode 102a via the second current path 244. b The collector current i flows into the third contact region 230 and reaches the first source / drain region 232 along the first current path 246 through the NPN transistor 250. c The base current i flows into the second contact region 228 and reaches the first source / drain region 232 along the first current path 246 through the NPN transistor 250. b With collector current i c Combined into emitter current i e , where i e =i b +ic The first switch current i Q1 , intrinsic diode current i d and the emitter current i e are connected in parallel, so the fourth current i4 is equal to the sum of the above currents, where i4 = i Q1 +i d +i e The conduction loss P2 during the second dead time is equal to P2 = V f1 * i4. In some embodiments, the fourth current i4 is in the range of approximately 1 mA and approximately 100 mA.

[0154] By specific reference Fig. 9 In the circuit diagram 900 of FIG. 1 , the second switching device 108 is open and therefore current does not flow between the third power source 260 and the first node 106 , effectively resulting in an open circuit at the first location 502 . L The inductor 112 induces a current i flowing from the inductor 112 to the second node 114 and through the capacitor 118 and the load 116 to the reference node 104. L , thereby causing the third current i3 to flow from the reference node 104 to the second source / drain region 208 . The third current i3 flows through the third current path 242 , thereby generating a fourth current i4 that will flow from the first source / drain region 232 to the inductor 112 .

[0155] refer to Fig.10 , provide use Figure 1A A block diagram 1000 of some embodiments of a buck converter method.

[0156] At 1002 , a buck converter including a first switching device, a second switching device, and an inductor is provided and connected to a node. Figure 1A Circuit 100a corresponding to some embodiments of act 1002 is shown.

[0157] At 1004, a first pulse train is applied to a first switching device to alternate the first switching device between on and off. Figures 5 to 9 Circuits 500 through 900 are shown corresponding to some embodiments of action 1004 .

[0158] At 1006 , a second pulse train is applied to the second switching device to alternate the second switching device between on and off, the second switching device being off when the first switching device is on, and the first switching device being off when the second switching device is on. Figures 5 to 9 Circuits 500 through 900 are shown corresponding to some embodiments of action 1006 .

[0159] At 1008 , the inductor is charged from a node at which respective source / drain regions of the first and second switching devices are electrically coupled, the charging being performed when the second switching device is turned on. Figure 7 Circuit 700 is shown corresponding to some embodiments of act 1008 .

[0160] At 1010 , when the second switching device is turned off, the inductor is discharged. Figure 5 , Figure 6 , Figure 8 as well as Fig. 9 Circuit 500 , circuit 600 , circuit 800 , and circuit 900 are shown corresponding to some embodiments of act 1010 .

[0161] At 1012 , immediately after detecting that the first pulse train is low and the second pulse train is high, the gate of the first switching device is biased at a voltage less than a threshold voltage of the first switching device. Figure 6 and Figure 8 Circuit 600 and circuit 800 are shown corresponding to some embodiments of act 1012 .

[0162] Although block diagram 1000 is shown and described herein as a series of actions or events, it will be appreciated that the order in which such actions or events are shown should not be construed in a limiting sense. For example, in addition to the actions or events shown and / or described herein, some actions may occur in a different order and / or simultaneously with other actions or events. Furthermore, not all of the actions shown are required to implement one or more aspects or embodiments described herein, and one or more of the actions depicted herein may be performed in one or more than one individual action and / or stage.

[0163] Thus, in some embodiments, the present disclosure is directed to a buck converter including a loss prevention circuit configured to bias a switching device of the buck converter at a voltage less than a threshold of the switching device during a dead time period.

[0164] In some embodiments, the present disclosure provides a buck converter circuit comprising: a first switching device; a second switching device; an inductor electrically coupled to a node at which a source / drain of the first switching device and a source / drain of the second switching device are electrically coupled; and a controller configured to cause the first switching device to alternately change between on and off, and further configured to cause the second switching device to alternately change between on and off, wherein when the second switching device is turned on, the first switching device is turned off, and wherein the first switching device is partially turned on immediately before or after the second switching device transitions between on and off.

[0165] In some embodiments, when partially turned on, a voltage of the gate of the first switching device is biased at a voltage less than a threshold voltage of the first switching device.

[0166] In some embodiments, the first switching device is partially turned on immediately before the second switching device transitions from off to on.

[0167] In some embodiments, the first switching device is partially turned on immediately after the second switching device transitions from on to off.

[0168] In some embodiments, the controller further includes a loss prevention circuit. The loss prevention circuit is electrically coupled to a gate terminal of the first switching device and a gate terminal of the second switching device. The loss prevention circuit is configured to determine a first time frame immediately before the second switching device transitions from off to on, and determine a second time frame immediately after the second switching device transitions from on to off. The loss prevention circuit partially turns on the first switching device during the first time frame and the second time frame.

[0169] In some embodiments, the duration of the first time frame and the second time frame are respectively defined by a period during which both the first switching device and the second switching device are off. The first switching device is partially on during the entire duration.

[0170] In some embodiments, during a first time frame and a second time frame, the buck converter includes a first current path and a second current path. The first current path is located between a second source / drain of the first switching device and a node. The first current path conducts through an internal diode of the first switching device. The second current path is located between a second source / drain of the first switching device and a node. The second current path conducts through a conductive channel formed in the first switching device. The first current path is connected in parallel with the second current path.

[0171] In some embodiments, the present disclosure provides a buck converter circuit, comprising: a first switching device; a second switching device; an inductor, wherein the first switching device and the second switching device are coupled to the inductor at a node; a controller, configured to apply a first pulse train and a second pulse train to the gate terminals of the first switching device and the second switching device, respectively, so that the first switching device and the second switching device alternately change between a first state and a second state; and a loss prevention circuit, electrically coupled to the gate terminals of the first switching device and the second switching device, and configured to bias the gate terminal of the first switching device with a voltage less than a threshold voltage of the first switching device when transitioning between the first state and the second state.

[0172] In some embodiments, in the first state, the first switching device is turned on and the second switching device is turned off. In the second state, the first switching device is turned off and the second switching device is turned on.

[0173] In some embodiments, the loss prevention circuit is further configured to: detect when the first switching device and the second switching device are in a third state, wherein the third state occurs when transitioning from the first state to the second state or when transitioning from the second state to the first state, and wherein the first switching device and the second switching device are disconnected in the third state; and during the third state, enhance the first pulse train to partially turn on the first switching device.

[0174] In some embodiments, during the third state, the buck converter includes a first current path, a second current path, and a third current path. The first current path is between the power rail and the node. The second current path is between the source / drain of the first switching device and the node. The second current path conducts through an internal diode of the first switching device. The third current path is between the source / drain terminal and the node. The third current path conducts through a conductive channel formed in the first switching device. The third current path is connected in parallel with the second current path.

[0175] In some embodiments, the first current path and the second current path each exist along an NPN junction within the substrate.

[0176] In some embodiments, during the third state, current flows through the first current path, the second current path, and the third current path.

[0177] In some embodiments, the first switching device is an n-channel metal oxide semiconductor device, and wherein the second switching device is a p-channel metal oxide semiconductor device.

[0178] In some embodiments, the loss prevention circuit includes a third switching device, a pull-up resistor, and a level shifter. The third switching device is electrically coupled to ground and a gate terminal of the first switching device. The pull-up resistor is electrically coupled to a power rail and a gate terminal of the first switching device. The level shifter is electrically coupled from the gate terminal of the first switching device to the gate terminal of the third switching device.

[0179] In some embodiments, the present disclosure provides a method for operating a buck converter circuit, comprising: applying a first pulse train to a first switching device to cause the first switching device to alternately change between being on and being off; applying a second pulse train to a second switching device to cause the second switching device to alternately change between being on and being off, wherein when the first switching device is on, the second switching device is off, and when the second switching device is on, the first switching device is off; charging an inductor from a node at which respective source / drain regions of the first switching device and the second switching device are electrically coupled, wherein the charging is performed when the second switching device is on; discharging the inductor when the second switching device is off; and immediately after detecting that the first pulse train is low and the second pulse train is high, biasing the gate of the first switching device with a voltage less than a threshold voltage of the first switching device.

[0180] In some embodiments, the first pulse train has a first duty cycle and the second pulse train has a second duty cycle greater than the first duty cycle. The first pulse train has a phase offset relative to the second pulse train.

[0181] In some embodiments, immediately after detecting that the first pulse train and the second pulse train are low and high respectively, the buck conversion method further includes: forming a conductive channel in the first switching device, wherein a weak reverse current flows through the conductive channel to the node.

[0182] In some embodiments, the weak reverse current is in parallel with the current flowing through the internal diode of the first switching device.

[0183] In some embodiments, the first switching device is an n-channel metal oxide semiconductor device, and wherein the second switching device is a p-channel metal oxide semiconductor device.

[0184] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A buck converter circuit, comprising: a first switch device; a second switch device; an inductor electrically coupled to a node where the first source / drain region of the first switching device is electrically coupled to the first source / drain region of the second switching device; as well as A controller configured to cause the first switching device to alternately change between being turned on and off, and further configured to cause the second switching device to alternately change between being turned on and off, wherein when the second switching device is turned on, the first switching device is turned off, wherein immediately before or after the second switching device transitions between being turned on and off, the first switching device is partially turned on, wherein when the first switching device is turned on, the gate of the first switching device is biased at a threshold voltage, and when partially turned on, the gate of the first switching device is biased at a subthreshold voltage, wherein the subthreshold voltage is lower than the threshold voltage.

2. The buck converter circuit of claim 1 , wherein the first switching device comprises a second source / drain region, wherein the first source / drain region and the second source / drain region of the first switching device are disposed within a substrate on opposite sides of the gate of the first switching device, and wherein when the first switching device is partially turned on, a conductive channel is formed directly beneath the substrate and between the first source / drain region and the second source / drain region. 3 . The buck converter circuit of claim 1 , wherein the first switching device is partially turned on immediately before the second switching device transitions from off to on. 4 . The buck converter circuit of claim 1 , wherein the first switching device is partially turned on immediately after the second switching device transitions from being turned on to being turned off.

5. The buck converter circuit of claim 1 , the controller further comprising: A loss prevention circuit is electrically coupled to the gate of the first switching device and the gate of the second switching device, wherein the loss prevention circuit is configured to determine a first time frame immediately before the second switching device transitions from off to on, and to determine a second time frame immediately after the second switching device transitions from on to off, and wherein the loss prevention circuit partially turns on the first switching device during the first time frame and the second time frame.

6. The buck converter circuit of claim 5, wherein the durations of the first and second time frames are respectively defined by periods during which the first and second switching devices are both off, and wherein the first switching device is partially on throughout the durations.

7. The buck converter circuit of claim 6, wherein during the first time frame and the second time frame, the buck converter comprises: a first current path between a second source / drain region of the first switching device and the node, wherein the first current path conducts through an internal diode of the first switching device; as well as A second current path is located between the second source / drain region of the first switch device and the node, wherein the second current path conducts through a conductive channel formed in the first switch device, and wherein the first current path is connected in parallel with the second current path.

8. A buck converter circuit comprising: a first switch device; a second switch device; an inductor, wherein the first switching device and the second switching device are coupled to the inductor at a node; a controller configured to apply a first pulse train and a second pulse train to a gate terminal of the first switching device and a gate terminal of the second switching device, respectively, so that the first switching device and the second switching device are alternately changed between a first state and a second state; as well as a loss prevention circuit electrically coupled to the gate terminal of the first switching device and the gate terminal of the second switching device and configured to provide a voltage bias to the gate terminal of the first switching device that is less than a threshold voltage of the first switching device when transitioning between the first state and the second state, wherein the loss prevention circuit comprises: a third switching device electrically coupled to ground and the gate terminal of the first switching device; a pull-up resistor electrically coupled to a power source and the gate terminal of the first switching device; and A level shifter is electrically coupled from the gate terminal of the first switching device to the gate terminal of the third switching device.

9. The buck converter circuit of claim 8, wherein in the first state, the first switching device is turned on and the second switching device is turned off, and wherein in the second state, the first switching device is turned off and the second switching device is turned on.

10. The buck converter circuit of claim 8, wherein the loss prevention circuit is further configured to: detecting when the first switching device and the second switching device are in a third state, wherein the third state occurs upon transitioning from the first state to the second state or upon transitioning from the second state to the first state, and wherein the first switching device and the second switching device are open in the third state; and During the third state, the first pulse train is enhanced to partially turn on the first switching device.

11. The buck converter circuit of claim 10, wherein during the third state, the buck converter comprises: a first current path located between the power source and the node; a second current path between a source / drain terminal of the first switching device and the node, wherein the second current path conducts through an internal diode of the first switching device; as well as A third current path is located between the source / drain terminal and the node, wherein the third current path is conducted through a conductive channel formed in the first switch device, and wherein the third current path is connected in parallel with the second current path. 12 . The buck converter circuit of claim 11 , wherein the first current path and the second current path exist along NPN junctions within a substrate, respectively. 13 . The buck converter circuit of claim 11 , wherein during the third state, current flows through the first current path, the second current path, and the third current path.

14. The buck converter circuit of claim 8, wherein the first switching device is an n-channel metal oxide semiconductor device, and wherein the second switching device is a p-channel metal oxide semiconductor device.

15. A step-down conversion method, comprising: applying a first pulse train to a first switching device to cause the first switching device to alternately change between being on and being off, so that the first switching device is in a triode mode when being on; applying a second pulse train to a second switching device to cause the second switching device to alternately change between being on and being off, wherein when the first switching device is on, the second switching device is off, and when the second switching device is on, the first switching device is off; charging an inductor from a node electrically coupled between source / drain regions of the first switching device and the second switching device, respectively, wherein the charging is performed when the second switching device is turned on; discharging the inductor when the second switching device is turned off; as well as Immediately after detecting that the first pulse train is low and the second pulse train is high, the gate of the first switching device is biased with a subthreshold voltage that is less than a threshold voltage of the first switching device, wherein the first switching device is biased with the subthreshold voltage in a subthreshold mode so that the subthreshold mode is between the cutoff mode of the first switching device and the triode mode of the first switching device, and wherein the subthreshold voltage is not zero.

16. The buck conversion method according to claim 15, wherein the first pulse train has a first duty cycle and the second pulse train has a second duty cycle greater than the first duty cycle, and wherein the first pulse train has a phase offset relative to the second pulse train.

17. The step-down conversion method according to claim 16, immediately after detecting that the first pulse string and the second pulse string are low and high respectively, the step-down conversion method further comprises: A conductive channel is formed in the first switching device, wherein a weak reverse current flows through the conductive channel to the node.

18. The buck conversion method of claim 17, wherein the weak reverse current is connected in parallel with a current flowing through an internal diode of the first switching device.

19. The buck conversion method of claim 15, wherein the first switching device is an n-channel metal oxide semiconductor device, and wherein the second switching device is a p-channel metal oxide semiconductor device.

20. The buck conversion method of claim 16, wherein the gate of the first switching device is biased with the subthreshold voltage less than the threshold voltage, and a conductive channel is formed in the first source / drain region and the second source / drain region of the first switching device, wherein: The conductive channel is directly below the gate of the first switching device.

21. An integrated circuit comprising: a first switch device; a second switch device; an inductor electrically coupled to a node where the first source / drain region of the first switching device is electrically coupled to the first source / drain region of the second switching device; as well as a controller configured to cause the first switch device and the second switch device to alternately change between a first state and a second state, wherein before or after the second switch device changes between the first state and the second state, the first switch device is in a third state, wherein a subthreshold voltage is applied to the first gate of the first switch device during the third state, so that the third state is between a cutoff mode of the first switch device and a triode mode of the first switch device, The first switching device includes a second source / drain region, wherein the first source / drain region and the second source / drain region of the first switching device are arranged in the substrate on opposite sides of the first gate, and wherein during the third state, a conductive channel is laterally between the first source / drain region and the second source / drain region of the first switching device and is arranged directly below the substrate.

22. The integrated circuit of claim 21, wherein the subthreshold voltage is non-zero.

23. The integrated circuit of claim 21, wherein the subthreshold voltage is lower than a threshold voltage of the first switching device and is non-zero.

24. The integrated circuit of claim 21, wherein the first gate is biased at a threshold voltage in the first state, and wherein the subthreshold voltage is lower than the threshold voltage.

25. The integrated circuit of claim 21, wherein the first switch device is in a third state immediately before the second switch device transitions from the second state to the first state.

26. The integrated circuit of claim 21, wherein the subthreshold voltage is greater than a voltage applied to the first gate during the second state and less than a voltage applied to the first gate during the first state.

27. An integrated chip, comprising: a first transistor; a second transistor; an inductor coupled to the first transistor and the second transistor at a node; a controller configured to make the first transistor and the second transistor alternately change between a first state and a second state respectively; as well as A conduction loss reduction circuit is electrically coupled to the gate terminal of the first transistor and the gate terminal of the second transistor and is configured to bias the gate terminal of the first transistor with a subthreshold voltage less than a threshold voltage of the first transistor when transitioning between the first state and the second state, wherein the conduction loss reduction circuit includes a third transistor directly electrically coupled to ground and directly electrically coupled to the gate terminal of the first transistor.

28. The integrated chip according to claim 27, wherein the subthreshold voltage is not zero.

29. The integrated chip according to claim 27, wherein the conduction loss reduction circuit further comprises: A level shifter is electrically coupled from the gate terminal of the second transistor to the gate terminal of the third transistor.

30. The integrated chip according to claim 27, wherein the conduction loss reduction circuit further comprises: The fourth transistor is electrically coupled to a power source and the gate terminal of the first transistor.

31. The integrated chip of claim 30, wherein the third transistor is an n-channel metal oxide semiconductor transistor, and wherein the fourth transistor is a p-channel metal oxide semiconductor transistor.

32. The integrated chip according to claim 27, wherein when the gate terminal of the first transistor is biased with the subthreshold voltage, the integrated chip comprises: a first current path between a power source and the node; a second current path between a first source / drain region of the first transistor and the node, wherein the second current path is conducted via an internal diode of the first transistor; as well as A third current path between the first source / drain region and the second source / drain region of the first transistor, wherein the first source / drain region and the second source / drain region are arranged in the substrate on opposite sides of the gate structure of the first transistor, wherein the third current path is conducted laterally between the first source / drain region and the second source / drain region and is arranged directly below the gate structure.

33. The integrated chip according to claim 32, wherein the third current path is connected in parallel with the second current path.

34. A step-down conversion method, comprising: applying a first pulse train and a second pulse train to a first transistor and a second transistor, respectively, so that the first transistor and the second transistor are alternately changed between a first state and a second state, wherein in the first state, the first transistor is turned on and the second transistor is turned off, and wherein in the second state, the first transistor is turned off and the second transistor is turned on; During the second state, the inductor is charged by a node electrically coupled between the source / drain regions of the first transistor and the second transistor; Immediately after detecting that the first pulse train is low and the second pulse train is high, the gate of the first transistor is biased with a subthreshold voltage so that the first transistor is in a subthreshold mode, wherein during the subthreshold mode, the first transistor is between being turned on and off, wherein when the subthreshold voltage biases the gate of the first transistor, a first current path is conducted through an internal diode of the first transistor, and a second current path is conducted between a pair of source / drain regions of the first transistor.

35. The buck conversion method of claim 34, wherein the first pulse train is between low and high when the gate of the first transistor is biased with the sub-threshold voltage.

36. The step-down conversion method of claim 34, wherein the subthreshold voltage is lower than a threshold voltage of the first transistor and is non-zero.

37. The buck conversion method of claim 34, wherein the inductor is discharged when the second transistor is turned off.

38. The step-down conversion method according to claim 34, wherein the frequency of the first pulse string is equal to the frequency of the second pulse string, wherein the second pulse string has a duty cycle, the duty cycle of the second pulse string is greater than the duty cycle of the first pulse string, and wherein the second pulse string has a phase offset relative to the first pulse string.

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