Gate-level circuit partitioning method based on cut sets and vertex features

Abstract

The present invention proposes a gate-level circuit partitioning method based on cut sets and vertex features, including: step S1: preprocessing the driving matrix of the gate-level circuit and converting it into a standard adjacency matrix; step S2: preliminary partitioning based on the weak connectivity of the directed graph, dividing it into at least one independent primary unit; step S3: taking the largest unit among all units and dividing it into one or more secondary units, if there are multiple units, go to step S4, if there is one, go to step S5; step S4: repeating step S3 until the largest unit among all units currently does not meet the effective partitioning conditions, go to step S5; step S5: output the vertex vectors and adjacency matrices of all units after partitioning. Compared with the prior art, the present invention can reduce the number of connecting lines between each subset after partitioning, and make the number of gate circuits contained in each subset relatively balanced, thereby improving the speed of parallel simulation of gate-level circuits.

Description

Technical Field

[0001] The invention relates to circuit partitioning of gate-level circuit simulation, in particular to a gate-level circuit partitioning method based on cut sets and vertex features. Background Art

[0002] Gate-level simulation (Gate-Level Simulation) is an important verification process in electronic design automation (EDA). As the complexity of very large-scale integration (VLSI) continues to increase, the running time of gate-level simulation becomes very long. In order to increase the speed of gate-level simulation, gate-level simulation parallelization has become a trend, that is, dividing the gate-level circuit into multiple smaller parts, so that they can be simulated in parallel using distributed machines.

[0003] Most of the existing circuit partitioning algorithms are applied to the physical design of VLSI, which divides the circuit composed of logic gates or standard cells into multiple subsets. It usually requires that the number of components contained in each subset is balanced, and the goal is generally to minimize the number of wire network connections between these subsets. Partitioning algorithms include iterative improvement methods based on movement, multi-level partitioning methods, etc. After the above algorithm is divided, the number of connecting lines between subsets is still large, and as the scale of the circuit increases, the number of connecting lines increases significantly.

[0004] There are few existing circuit partitioning methods for gate-level simulation parallelization, and fully parallel simulation is very sensitive to the number of connection lines between subsets in gate-level circuit causal partitioning. The increase in the number of connection lines will greatly increase the computing resource overhead of fully parallel simulation. Therefore, reducing the number of connection lines between subsets and making the number of gate circuits contained in each subset relatively balanced is a topic worth studying in circuit partitioning for gate-level simulation.

[0005] Therefore, how to design a gate-level circuit partitioning method that can reduce the number of connection lines between subsets and make the number of gate circuits contained in each subset relatively balanced is a technical problem that needs to be solved urgently in the industry. Summary of the invention

[0006] In view of the technical problems in the prior art that each subset has a large number of connection lines after division and the number of gate circuits contained in each subset is unbalanced, the present invention proposes a gate-level circuit division method based on cut sets and vertex features.

[0007] The technical solution of the present invention is to propose a gate-level circuit partitioning method based on cut sets and vertex features, comprising:

[0008] Step S1: preprocessing the driving matrix of the gate-level circuit and converting it into a standard adjacency matrix;

[0009] Step S2: preliminarily partitioning the directed graph based on its weak connectivity into at least one independent primary unit;

[0010] Step S3: Take the largest unit among all units and divide it into one or more secondary units. If there are multiple units, go to step S4; if there is only one unit, go to step S5.

[0011] Step S4: repeat step S3 until the largest unit among all the current units does not meet the valid division condition, and then go to step S5;

[0012] Step S5: Output the vertex vectors and adjacency matrices of all divided units.

[0013] Furthermore, the preprocessing of the driving matrix of the gate-level circuit to convert it into a standard adjacency matrix includes:

[0014] Step S11: setting all non-zero elements in the driving matrix to 1;

[0015] Step S12: merging multiple rows of matrix elements corresponding to multiple driving ports of the same gate circuit in the driving matrix into one row.

[0016] Further, the preliminary division based on weak connectivity of the directed graph into at least one independent primary unit includes:

[0017] Calculate all weakly connected branches of the directed graph based on breadth-first exploration to obtain at least one independent primary unit;

[0018] Create a global block storage variable to store all of the primary units.

[0019] Furthermore, the method of taking the largest unit among all units and dividing it into one or more secondary units includes:

[0020] Step S31: reducing the dimension of the maximum unit and weighting it, and degenerating it into its basic graph;

[0021] Step S32: Find all k-cut sets in the base graph, discard the cut sets at the edge of the graph, and determine whether there is a cut set that meets the constraint conditions. If so, select the optimal cut set from the remaining cut sets. If not, go to step S5;

[0022] Step S33: determining a minimum cut edge combination according to the optimal cut set, and determining specific disconnected connection lines according to the minimum cut edge combination, and disconnecting them to obtain a plurality of secondary units.

[0023] Furthermore, the step of reducing the dimension of the maximum unit and weighting it to degenerate it into its basic graph includes:

[0024] The single-input single-output gate circuit link in the directed graph is reduced to a directed edge, and a weight is set for the directed edge, wherein the value of the weight is the number of gate circuits constituting the gate circuit link plus 1.

[0025] Further, the discarding of the cut sets located at the edge of the graph and judging whether there is a cut set satisfying the constraint condition comprises:

[0026] The cut sets at the edge of the graph are discarded through constraint conditions, and it is determined whether there are still cut sets satisfying the constraint conditions, wherein the constraint conditions include: the degree of each neighbor of each vertex in the cut set of the maximum unit is greater than 2, and the eigenvector centrality of each vertex is greater than or equal to the vertex centrality threshold.

[0027] Further, the selecting the optimal cut set from the remaining cut sets includes:

[0028] The eigenvector centralities of all k-cut sets are calculated, and the cut set with the largest eigenvector centrality is selected as the optimal cut set. The eigenvector centrality of the cut set is the sum of the eigenvector centralities of all vertices in the cut set.

[0029] Further, determining the minimum cut edge combination according to the optimal cut set includes:

[0030] Step S331: Assume that the minimum cut edge combination includes m edges, whose initial value is 1, and proceed to step S332.

[0031] Step S332: Enumerate all edge cutting combinations containing m edges and proceed to step S333.

[0032] Step S333: For one of the edge cutting combinations, delete it from the unit and determine whether the unit is a connected graph. If not, determine that the edge cutting combination is the minimum edge cutting combination and proceed to step S335; if yes, determine that the edge cutting combination is not the minimum edge cutting combination and proceed to step S334.

[0033] Step S334: re-add the trimming combination to the unit. If there are other trimming combinations, re-select other trimming combinations and repeat step S333; if there are no other trimming combinations, m is increased by 1 and the process goes to step S332.

[0034] Step S335: record the trimming combination, add it to the unit again, and terminate the determination.

[0035] Further, the step of not satisfying the valid division condition until the largest unit does not satisfy the valid division condition includes:

[0036] Step S41: updating the global block storage variable, saving all the secondary units obtained by division and the undivided primary units, and obtaining the maximum unit among the updated primary units and secondary units;

[0037] Step S42: Determine whether the largest unit among the updated primary units and secondary units meets the valid division condition, that is, determine whether the ratio of the number of vertices of the multiple secondary units obtained by division is greater than or equal to the threshold. If so, the valid division condition is met, otherwise it is not met.

[0038] Compared with the prior art, the present invention has at least the following beneficial effects:

[0039] 1. Perform preliminary division based on weak connectivity, and separate independent circuit blocks that have no connection lines between each other in the gate-level circuit. There is no causal relationship between them, and they can be simulated independently and in parallel.

[0040] 2. The chain formed by connecting multiple single-input and single-output gate circuits in the VLSI gate-level structure is reduced to a directed weighted edge in the directed graph, which reduces the number of vertices of the directed graph, reduces the computational complexity, and does not affect the partitioning.

[0041] 3. A proposition about cut sets is proposed, and a partitioning method based on cut sets is given to reduce the number of connecting lines between units.

[0042] 4. An optimal cut set selection method based on eigenvector centrality is proposed to make the number of gate circuits contained in each unit relatively balanced after division. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0044] Figure 1 It is a flow chart of the gate-level circuit partitioning method based on cut sets and vertex features.

[0045] Figure 2 It is a schematic diagram of the driving matrix preprocessing process.

[0046] Figure 3 It is a schematic diagram of the dimensionality reduction weighting process.

[0047] Figure 4 This is a diagram of the proof of a proposition about cut sets.

[0048] Figure 5 is the pseudo code for the algorithm to determine the minimum cut edge combination. DETAILED DESCRIPTION

[0049] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0050] Thus, a feature indicated in this specification will be used to illustrate one of the features of an embodiment of the present invention, rather than implying that each embodiment of the present invention must have the described feature. In addition, it should be noted that this specification describes many features. Although some features can be combined together to illustrate possible system designs, these features can also be used in other combinations that are not explicitly described. Thus, unless otherwise stated, the described combinations are not intended to be limiting.

[0051] The principle and structure of the present invention are described in detail below with reference to the accompanying drawings and embodiments.

[0052] The present invention proposes a gate-level circuit partitioning method based on cut sets and vertex features, which includes:

[0053] Step S1: preprocessing the driving matrix of the gate-level circuit and converting it into a standard adjacency matrix;

[0054] Step S2: preliminarily partitioning the directed graph based on its weak connectivity into at least one independent primary unit;

[0055] Step S3: Take the largest unit among all units and divide it into one or more secondary units. If there are multiple units, go to step S4; if there is only one unit, go to step S5.

[0056] Step S4: repeat step S3 until the largest unit among all the current units does not meet the valid division condition, and then go to step S5;

[0057] Step S5: Output the vertex vectors and adjacency matrices of all divided units.

[0058] See also Figure 2, which is a schematic diagram of the process of preprocessing the drive matrix in step S1, wherein U1, U2, and U3 are gate circuits, and the drive port Z of gate circuit U1 is connected to the input terminal AN and input terminal C of gate circuit U2, and the drive port Q and drive port QN of gate circuit U2 are connected to the input terminal A and input terminal B of gate circuit U3. The drive matrix corresponding to the gate-level circuit is drive matrix, which includes a matrix part, as well as drive ports U1_Z, U2_Q, U2_QN, U3_Q, U3_QN and the names of gate circuits U1, U2, and U3. This method uses the drive matrix, name vector, and drv vector as inputs to convert the drive matrix into a standard adjacency matrix. Since the elements in the drive matrix have letters for recording the names of the driven input ports, and the drive matrix is ​​generally not a square matrix (because a gate circuit can have multiple drive ports), the drive matrix is ​​not a standard adjacency matrix, so it is necessary to preprocess the drive matrix first and convert it into a standard adjacency matrix for the convenience of subsequent steps.

[0059] Specifically, it includes step S11: setting all non-zero elements in the driving matrix to 1;

[0060] Step S12: merging multiple rows of matrix elements corresponding to multiple driving ports of the same gate circuit in the driving matrix into one row.

[0061] Step S11 corresponds to Step 1 in the figure, which sets all non-zero elements such as C, AN, A, and B in the driving matrix to 1, but the matrix is ​​not a square matrix and needs to be further processed. Step S12 corresponds to Step 2 in the figure. It can be found from the driving matrix that gate circuit U1 has only one driving port, while gate circuit U2 and gate circuit U3 both have two driving ports. Therefore, the matrix rows corresponding to the two driving ports U2_Q and U2_QN of gate circuit U2 are added and merged, and the resulting 2 is set to 1; the matrix rows corresponding to the two driving ports U3_Q and U3_QN of gate circuit U3 are added and merged. Finally, a standard adjacency matrix is ​​obtained.

[0062] Here, since each column in the driving matrix corresponds to the name of a gate circuit, there are as many columns as there are gate circuits, and each row corresponds to the name of a driving port, that is, there are as many rows as there are driving ports. After merging multiple driving ports of the same gate circuit, it is equivalent to one gate circuit corresponding to only one matrix row. Therefore, the number of rows and columns of the matrix obtained after the merger must be the same, that is, it must be a square matrix. The adjacency matrix in the figure is the adjacency matrix obtained after the merger.

[0063] After converting it into a standard adjacency matrix, it needs to be preliminarily divided to obtain at least one independent primary unit. In order not to affect the simulation results, the preliminary division is performed here based on the weak connectivity of the directed graph. After the division, when the input and output signal lines are not considered, each primary module is an independent circuit block without a connection line, and there is no causal relationship, and it can be simulated independently and in parallel. (It should be noted here that the weakly connected branches correspond to the unconnected parts of the gate-level circuit, and there is no causal relationship between them. The strongly connected branches correspond to the parts with feedback relationships in the gate-level circuit, that is, the output of one gate circuit is the input of another gate circuit, and the output of another gate circuit is in turn given to the gate circuit as input, and there is a causal relationship between them, so the preliminary division is performed for weak connectivity in this application). Here, the preliminary division is performed based on the weak connectivity of the directed graph, and all the weakly connected branches of the directed graph are calculated based on the breadth-first search (BFS), so as to obtain at least one independent primary unit, and there is no causal relationship between each primary unit, and they can be simulated independently and in parallel.

[0064] Before the division, it is also necessary to create a global block storage variable, which is used to store all primary units after the preliminary division and is continuously updated in subsequent steps. After each division, secondary units will be obtained, and the corresponding number of units will change, and the maximum unit will also change. At this time, the global block storage variable needs to be updated to store all secondary units and primary units after the division, so as to re-determine the maximum unit.

[0065] After the update, the largest unit needs to be divided, which includes: step S31: reducing the dimension of the largest unit and weighting it, and degenerating it into its basic graph;

[0066] Step S32: Find all k-cut sets in the base graph, discard the cut sets at the edge of the graph, and determine whether there is a cut set that meets the constraint conditions. If so, select the optimal cut set from the remaining cut sets. If not, go to step S5;

[0067] Step S33: determining a minimum cut edge combination according to the optimal cut set, and determining specific disconnected connection lines according to the minimum cut edge combination, and disconnecting them to obtain a plurality of secondary units.

[0068] Since there are a certain number of chains of single-input single-output gate circuits such as inverter chains in the gate-level structure of VLSI, if such a structure needs to be disconnected in the subsequent partitioning process, it does not matter much where in the chain it is disconnected. Figure 3, which consists of three gate circuits connected end to end, and the output of each gate circuit is connected to the input of another gate circuit. When dividing, no matter which connection line of the structure is disconnected, there is no big difference. However, when multiple gate circuits are connected end to end, multiple vertices will appear in the directed graph. Therefore, in this application, the structure is reduced in dimension and weighted, and converted into a directed edge, which reduces the number of vertices and reduces the complexity of calculation.

[0069] The specific method is to reduce the dimension of the single-input single-output gate circuit link in the directed graph to a directed edge, and set a weight for this directed edge. The value of the weight is the number of gate circuits that make up the gate circuit link plus 1 (in order to distinguish it from the "1" representing the connection in the adjacency matrix, even if the chain consists of only one single-input single-output gate circuit, its weight is 2). Figure 3 The number of gate circuits in the figure is 3. After converting it into a directed edge, its weight is weight = 4 = 3 + 1. If the edge generated by dimensionality reduction weighting is to be disconnected in the subsequent partitioning process, the weight can be used to determine which specific connection line of the gate circuit link should be disconnected.

[0070] Since it is necessary to find the cut set in the primary unit in subsequent operations, it is necessary to first degenerate the weighted directed graph after dimensionality reduction of the maximum unit into its basic graph, and then find the cut set.

[0071] This application uses Kanevsky's algorithm to find cut sets. The time complexity of the sequential implementation of this algorithm is O(2 k n 3 ), where n is the number of vertices in the graph and k is the connectivity of the graph, i.e. the number of vertices in the minimum cut set. The algorithm finds all k-cut sets in the graph by setting the value of parameter k, which can be set before the application creates a global block storage variable.

[0072] After finding all the k-cut sets, it is necessary to find the optimal cut set in all the k-cut sets for partitioning to ensure that the number of gate circuits in multiple sub-units after partitioning is relatively balanced. However, in actual circuit partitioning, the vertex sets corresponding to some gate circuits near the input and output of the gate-level circuit are often cut sets, and these cut sets are located at the edge of the graph, which leads to the imbalance of the number of gate circuits in each sub-unit obtained by partitioning with these cut sets. Therefore, it is necessary to abandon the cut sets located at the edge of the graph. Here, the cut sets are screened by neighbor constraints and vertex centrality constraints. The neighbor constraint is that the degree of each neighbor of each vertex in the cut set must be greater than 2, and the degree of the vertex is the number of edges associated with the vertex. The vertex centrality constraint is that the value of the eigenvector centrality of each vertex in the cut set must be greater than or equal to the vertex centrality threshold. The larger the value of the eigenvector centrality of a vertex, the more important this vertex is and the closer it is to the center of the graph. By setting the vertex centrality threshold ρ, the cut sets located at the edge of the graph can be further abandoned.

[0073] If there is no cut set that satisfies the constraints among all k cut sets, the constraints refer to the neighbor constraints and the vertex centrality constraints, which means that there is no cut set located at the center of the graph, so the division cannot be performed. At this time, the recursion stops and the vertex vectors and adjacency matrices of each primary unit and secondary unit after the current division are output, which can be simulated in parallel.

[0074] When there are cut sets that meet the constraints, the optimal cut set is selected for division. To ensure the balance of the number of gate circuits between the secondary units after division, the optimal cut set needs to be as close to the center of the graph as possible. Therefore, the present application proposes an optimal cut set selection method based on the maximum eigenvector centrality, which calculates the eigenvector centrality of all k cut sets and selects the cut set with the largest eigenvector centrality as the optimal cut set. The eigenvector centrality of the cut set is the sum of the eigenvector centralities of all vertices in the cut set.

[0075] It should be noted that eigenvector centrality is a vertex-level feature that not only measures the importance of the vertex itself, but also takes into account the importance of the vertex’s neighbors. u The larger the value of is, the more important the vertex is and the closer it is to the center of the graph. Define the eigenvector centrality e of the cut set S S is the sum of the eigenvector centralities of all vertices in the cut set:

[0076]

[0077] Therefore, by calculating the eigenvector centrality of each cut set and selecting the cut set with the largest value, that is, the cut set closest to the center of the graph, that is, the optimal cut set.

[0078] After obtaining the optimal cut set, it is necessary to determine the minimum combination of cut edges to minimize the number of disconnected connections. According to the definition of the cut set, the cut set and the edges associated with all vertices in the cut set must be deleted to increase the number of connected branches of the graph. However, the number of vertices in the cut set is very small. If the gate-level circuit corresponding to the cut set is divided out as an independent sub-block, the number of gate circuits in each block will be extremely unbalanced. Therefore, the division cannot be based on the definition of the cut set.

[0079] See also Figure 4 , this application proposes a proposition about cut sets and proves it as follows: Let G = (V, E) be an undirected graph. If S is a cut set, then and

[0080] So that ω(GE′)>ω(G).

[0081] Proof. According to the definition of cut set, we can delete the cut set S and the edges associated with all vertices in the cut set from G to obtain G′, then ω(G′)>ω(G). Now let each connected branch CC in G[S] i Any vertex u in (may be only one or more) is connected back to a vertex v in G′ through an edge, and (u,v)∈E, and we get G″. Since connecting back to an edge will only make each CC i It becomes a whole with G′ without producing any other influence, so ω(G″)=ω(G′)>ω(G). The existence of G″ can prove the existence of E′ in the proposition. The proof is complete.

[0082] From the above proposition, we can see that based on the partition of the cut set, disconnecting some but not all edges between S and VS can increase the number of connected branches of the graph. Therefore, according to the above proposition, we can find the smallest E′, which is the combination with the least cut edges.

[0083] See also Figure 5 , the method for determining the minimum cut edge combination includes: step S331: assuming that the minimum cut edge combination includes m edges, its initial value is 1, and proceeding to step S332.

[0084] Step S332: Enumerate all edge cutting combinations containing m edges and proceed to step S333.

[0085] Step S333: For one of the edge cutting combinations, delete it from the unit and determine whether the unit is a connected graph. If not, determine that the edge cutting combination is the minimum edge cutting combination and proceed to step S335; if yes, determine that the edge cutting combination is not the minimum edge cutting combination and proceed to step S334.

[0086] Step S334: re-add the trimming combination to the unit. If there are other trimming combinations, re-select other trimming combinations and repeat step S333; if there are no other trimming combinations, m is increased by 1 and the process goes to step S332.

[0087] Step S335: record the trimming combination, add it to the unit again, and terminate the determination.

[0088] Among them, for the largest unit B max With its optimal cut set S0, find the associated edge set of S0 It contains a total of n edges. Assume that the minimum cut edge combination contains m edges, and its initial value is 1. All edges can be enumerated. By repeatedly selecting any combination c and deleting it from the optimal cut set S0, the maximum unit B max Whether it is connected or not can be judged and the combination with the least cut edges can be selected.

[0089] Figure 5 In step 1, the initial value of m is set to 1, and step 5 is to remove the edge combination c from the largest unit B max In step 6, it is determined whether the largest unit after removal is connected. If it is not connected, the cut edge combination is determined to be the minimum cut edge combination c0 and it is re-added to the largest unit B through step 9. max If the largest unit after removal is determined to be connected, then go to step 12 to add c back to the largest unit B. max , change to another combination, and re-execute steps 5 and 6 until there is no other combination, then enter step 17 to set m=m+1, and restart the judgment cycle until the minimum cutting edge combination is found.

[0090] After determining the minimum edge cutting combination, since the dimensionality reduction weighted processing has been performed before, the determined edge cutting may be the edge generated by the dimensionality reduction weighted processing, so the weight is used to determine which specific connection line of the chain should be disconnected. Since there is no big difference in which connection line of the gate circuit link is disconnected, this application chooses to disconnect the connection line in the middle of the chain.

[0091] Before partitioning, it is also necessary to evaluate the partitioning performance. This step is the second judgment condition for recursive termination, which includes step S42: judging whether the ratio of the number of vertices of the multiple secondary units obtained by partitioning is greater than or equal to the threshold value. If so, partitioning is performed and the step S41 is entered. Otherwise, the vertex vectors and adjacency matrices of all primary units and secondary units stored in the current global block storage variable are output, that is, step S5 is entered. The threshold is the sub-block unit vertex ratio threshold τ, which is used to judge whether the number of gate circuits of each unit obtained by partitioning with the optimal cut set is balanced. It is judged whether the ratio of the number of vertices of each unit obtained by partitioning is greater than or equal to the threshold τ. If the condition is met, it is determined that the number of gate circuits of each unit obtained is balanced and the partition is performed. Otherwise, it is determined that the number of gate circuits of each unit obtained is unbalanced, and the largest unit cannot be partitioned anymore, then the recursion is terminated, and the vertex vectors and adjacency matrices of all primary units and secondary units in the global block storage variable are output. In this application, the sub-block unit vertex ratio threshold τ, the vertex centrality threshold ρ and the cut set parameter k are set together before creating the global block storage variable.

[0092] After the first division is completed, the global block storage variable is updated, where the largest block of the primary unit and the secondary unit may still be able to be divided again. At this time, it is necessary to return to step S31 again and determine whether the largest unit in the global block storage variable after division can still be divided. If it can continue to be divided, the division step is executed. If it cannot continue to be divided, enter step S5 to output the vertex vectors and adjacency matrices of all units in the current global block storage variable for gate-level parallel simulation.

[0093] The steps executed after the recursion terminates are to output the vertex vectors and adjacency matrix of each unit after partitioning. The two can be used to reconstruct the gate-level netlist of each block after partitioning for parallel simulation.

[0094] See also Figure 1 This is a flow chart of the gate-level circuit partitioning method based on cut sets and vertex features of this application. Specifically, it takes the driving matrix, name vector, and drv vector as inputs, and pre-processes the driving matrix after setting the sub-block unit vertex number ratio threshold τ and vertex centrality threshold ρ and the cut set parameter k, converts it into a standard adjacency matrix, and creates a global block storage variable for storing all units. Then, a preliminary partition is performed based on the weak connectivity of the directed graph to obtain at least one mutually independent primary unit, and the global block storage variable is updated to store the primary unit after the partition. Take the global maximum unit from the global block storage variable, and degenerate it into its basic graph after dimensionality reduction and weighting. Find all the k-cut sets in the graph, discard the cut sets at the edge of the graph, and determine whether there are still cut sets that meet the constraints. If not, output the vertex vectors and adjacency matrices of all the units after the division. If so, select the optimal cut set through the maximum eigenvector, and determine the minimum cut edge combination through the algorithm, determine the specific disconnected connection line through the weight, and determine whether the ratio of the number of vertices of the multiple units obtained by the division is greater than or equal to the sub-block unit vertex ratio threshold τ. If so, it is a valid division and the division is executed, otherwise output the vertex vectors and adjacency matrix of all the units after the division.

[0095] from Figure 1 It can be found that this method is a recursive algorithm, which continuously selects the largest unit from all primary units and secondary units for division. After each division, the global block storage variable is updated once, and the largest unit is continuously selected for division until the largest unit cannot be divided, that is, there is no cut set that meets the constraint conditions, or the division based on the optimal cut set is not a valid division. The recursion terminates and outputs the vertex vectors and adjacency matrices of all current primary units and secondary units for parallel simulation. This method can continuously divide the largest unit until the largest unit cannot be divided, and the number of gate circuits in the resulting unit is relatively balanced.

[0096] Compared with the prior art, the present invention reduces the number of connection lines between subsets after division, improves the speed of gate-level parallel simulation, and at the same time, the number of gate circuits in each unit obtained after division is relatively balanced, meeting the current needs of gate-level parallel simulation circuit division.

[0097] The above are only partial or preferred embodiments of the present invention. Neither the text nor the drawings can limit the scope of protection of the present invention. All equivalent structural changes made by using the contents of the present invention specification and drawings under the overall concept of the present invention, or direct / indirect application in other related technical fields are included in the scope of protection of the present invention.

Claims

1. A gate-level circuit partitioning method based on cut sets and vertex features, characterized in that: include: Step S1: preprocessing the driving matrix of the gate-level circuit and converting it into a standard adjacency matrix; Step S2: preliminarily partitioning the directed graph based on its weak connectivity into at least one independent primary unit; Step S3: Take the largest unit among all units and divide it into one or more secondary units. If there are multiple units, go to step S4; if there is only one unit, go to step S5. Step S4: repeat step S3 until the largest unit among all the current units does not meet the valid division condition, and then go to step S5; Step S5: output the vertex vectors and adjacency matrices of all the divided units; The method of taking the largest unit among all units and dividing it into one or more secondary units includes: Step S31: reducing the dimension of the maximum unit and weighting it, and degenerating it into its basic graph; Step S32: Find all k-cut sets in the base graph, discard the cut sets at the edge of the base graph, and determine whether there is a cut set that meets the constraint conditions. If so, select the optimal cut set among the remaining cut sets. If not, go to step S5; Step S33: determining a minimum cut edge combination according to the optimal cut set, and determining specific disconnected connection lines according to the minimum cut edge combination, and disconnecting them to obtain a plurality of secondary units.

2. The gate-level circuit partitioning method based on cut sets and vertex features according to claim 1, characterized in that: The preprocessing of the driving matrix of the gate-level circuit to convert it into a standard adjacency matrix includes: Step S11: setting all non-zero elements in the driving matrix to 1; Step S12: merging multiple rows of matrix elements corresponding to multiple driving ports of the same gate circuit in the driving matrix into one row.

3. The gate-level circuit partitioning method based on cut sets and vertex features according to claim 1, characterized in that: The preliminary division based on weak connectivity of the directed graph into at least one independent primary unit includes: Calculate all weakly connected branches of the directed graph based on breadth-first exploration to obtain at least one independent primary unit; Create a global block storage variable to store all of the primary units.

4. The gate-level circuit partitioning method based on cut sets and vertex features according to claim 1, characterized in that: The step of reducing the dimension of the maximum unit and weighting it to degenerate it into its basic graph includes: The single-input single-output gate circuit link in the directed graph is reduced to a directed edge, and a weight is set for the directed edge, wherein the value of the weight is the number of gate circuits constituting the gate circuit link plus 1.

5. The gate-level circuit partitioning method based on cut sets and vertex features according to claim 1, characterized in that: The discarding of the cut sets located at the edge of the graph and judging whether there is a cut set satisfying the constraint condition comprises: The cut sets at the edge of the graph are discarded through constraint conditions, and it is determined whether there are still cut sets satisfying the constraint conditions, wherein the constraint conditions include: the degree of each neighbor of each vertex in the cut set of the maximum unit is greater than 2, and the eigenvector centrality of each vertex is greater than or equal to the vertex centrality threshold.

6. The gate-level circuit partitioning method based on cut sets and vertex features according to claim 1, characterized in that: The selecting the optimal cut set from the remaining cut sets comprises: The eigenvector centralities of all k-cut sets are calculated, and the cut set with the largest eigenvector centrality is selected as the optimal cut set. The eigenvector centrality of the cut set is the sum of the eigenvector centralities of all vertices in the cut set.

7. The gate-level circuit partitioning method based on cut sets and vertex features according to claim 1, characterized in that: Determining the minimum cut edge combination according to the optimal cut set includes: Step S331: Assume that the minimum cut edge combination includes m edges, its initial value is 1, and proceed to step S332; Step S332: enumerate all edge cutting combinations containing m edges, and proceed to step S333; Step S333: For one of the edge cutting combinations, delete it from the unit, and determine whether the unit is a connected graph. If not, determine that the edge cutting combination is the minimum edge cutting combination, and proceed to step S335; if yes, determine that the edge cutting combination is not the minimum edge cutting combination, and proceed to step S334; Step S334: re-add the trimming combination to the unit; if there are other trimming combinations, re-select other trimming combinations and repeat step S333; if there are no other trimming combinations, increase m by 1 and go to step S332; Step S335: record the trimming combination, add it to the unit again, and terminate the determination.

8. The gate-level circuit partitioning method based on cut sets and vertex features according to claim 1, characterized in that: The process of not meeting the valid division condition for the largest unit includes: Step S41: updating the global block storage variable, saving all the secondary units obtained by division and the undivided primary units, and obtaining the maximum unit among the updated primary units and secondary units; Step S42: Determine whether the largest unit among the updated primary units and secondary units meets the valid division condition, that is, determine whether the ratio of the number of vertices of the multiple secondary units obtained by division is greater than or equal to the threshold. If so, the valid division condition is met, otherwise it is not met.

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