Chip packaging structure and manufacturing method thereof

Abstract

The present invention provides a chip packaging structure and a manufacturing method thereof. By setting an insulating layer and a solder resist layer that are indented inward along the side of the chip substrate, in an uncut wafer, the insulating layer and the solder resist layer expose the cutting path. On the one hand, when cutting and separating each chip, the silicon substrate of the wafer can be directly cut to avoid cutting the insulating layer and the solder resist layer, thereby avoiding the formation of micro cracks at the edges of the two layers due to the cutting action; on the other hand, the insulating layer and the solder resist layer form a complete continuous film layer structure on the surface of the substrate, and there will be no situation in which stress is generated on one side in the cut film layer and cannot be compensated. The solder resist layer extends to the outside of the insulating layer, covers the insulating layer and is combined with the substrate, which can completely seal and protect the insulating layer, thereby slowing down the erosion of the insulating layer by water vapor, etc. At the same time, part of the stress of the solder resist layer can be directly borne by the substrate. When there is no delamination between the solder resist layer and the substrate, the insulating layer will only be subjected to a small amount of stress.

Description

Technical Field

[0001] The present invention relates to the field of packaging technology, and in particular to a chip packaging structure and a manufacturing method thereof. Background Art

[0002] Based on the material properties of each layer of the chip packaging structure, such as film defects, density, thermal expansion coefficient, etc., different stresses will be generated within and between each layer of material. The stress influence of the material used in the solder mask layer is the greatest, especially during the hot and cold shock process of chip reliability testing, the stress changes are more drastic. The chip base silicon material and the insulation layer are relatively brittle materials, and are most likely to delaminate during stress changes.

[0003] In the prior art, an insulating layer and a solder mask layer are usually formed on the surface of the wafer to completely cover the wafer, and then a single chip is cut. The chip obtained by this method, on the one hand, will have unavoidable micro cracks at its edge due to cutting, and on the other hand, the film layer is disconnected at the edge of the chip, and the stress is not compensated by the other side, so that the edge of the chip substrate is subjected to greater stress. Therefore, when delamination occurs, it often starts from the chip substrate or the insulating layer at the edge of the chip and then extends to the inside. Summary of the invention

[0004] The object of the present invention is to provide a chip packaging structure and a manufacturing method thereof.

[0005] The present invention provides a chip packaging structure, wherein the chip comprises a substrate having a first surface, a second surface opposite to the first surface, and a plurality of side surfaces connecting the first surface and the second surface, an insulating layer, a metal wiring layer and a solder resist layer are sequentially arranged on the first surface of the substrate, and a soldering protrusion electrically connected to the metal wiring layer is arranged on the solder resist layer, characterized in that:

[0006] The edge of the insulating layer and the edge of the solder resist layer are respectively retracted inwardly along the side surface of the substrate by a first distance a and a second distance b, wherein 0 nm ≤ b < a;

[0007] The insulating layer is located inside the solder resist layer, and the portion of the solder resist layer located outside the insulating layer covers the substrate and wraps around the side of the insulating layer.

[0008] As a further improvement of the present invention, the side surface of the substrate is provided with a groove recessed inwardly along the first surface of the substrate, and the groove is distributed along the length direction of the side surface of the substrate.

[0009] As a further improvement of the present invention, the groove forms a step structure on the side of the substrate, having a groove side wall and a groove bottom, and a third distance c is spaced between the top of the groove side wall and the side of the substrate on the same side, wherein c≤b.

[0010] As a further improvement of the present invention, a buffer layer is provided between the insulating layer and the metal wiring layer.

[0011] As a further improvement of the present invention, a soldering pad is provided on the second surface of the substrate, a through hole is provided on the first surface of the substrate extending toward the second surface thereof, the soldering pad is exposed at the bottom of the through hole, and the metal wiring layer extends along the side wall of the through hole to the soldering pad and is electrically connected thereto.

[0012] The present invention also provides a chip packaging structure manufacturing method, comprising the steps of:

[0013] Providing a wafer, wherein the wafer has a first surface and a second surface opposite to each other, a plurality of chip substrates are arranged in an array on the wafer, and cutting paths are distributed between adjacent substrates;

[0014] An insulating layer is formed on the first surface of the substrate, and the insulating layers are independently distributed at intervals on each of the substrates, and the edge of the insulating layer on each of the substrates is retracted inwardly by a first distance a along the cutting path;

[0015] A metal wiring layer and a solder resist layer are sequentially formed on the insulating layer, and the solder resist layers are independently distributed at intervals on each of the substrates, and the edge of the solder resist layer on each of the substrates is retracted inwardly along the cutting path by a second distance b, wherein 0nm≤b<a, and the portion of the solder resist layer located outside the insulating layer covers the substrate and wraps around the side of the insulating layer;

[0016] Opening a through hole on the solder resist layer to expose the metal wiring layer, and forming a soldering protrusion in the through hole that is electrically connected to the metal wiring layer;

[0017] The wafer is cut along the cutting lines to obtain multiple independent chip packaging structures.

[0018] As a further improvement of the present invention, before “forming an insulating layer on the first surface of the substrate”, the step of:

[0019] A full groove is formed on the first surface of the wafer and is located above the scribe line. The width of the full groove is greater than the width of the scribe line.

[0020] As a further improvement of the present invention, the full groove has a groove side wall and a groove bottom, and the top of the groove side wall and the edge of the cutting road on the same side are separated by a third distance c, wherein c≤b, and the groove bottom at least completely exposes the cutting road.

[0021] As a further improvement of the present invention, before “forming a metal wiring layer and a solder resist layer in sequence on the insulating layer”, the following steps are also included:

[0022] A buffer layer is formed on the insulating layer.

[0023] As a further improvement of the present invention, before “forming an insulating layer on the first surface of the substrate”, the following steps are also included:

[0024] A through hole extending toward the second surface of the wafer is formed on the first surface of the wafer, and the bottom of the through hole exposes the bonding pad disposed on the second surface of the wafer.

[0025] The beneficial effects of the present invention are as follows: by setting an insulating layer and a solder resist layer that are indented inward along the side edge of the chip substrate, in an uncut wafer, the insulating layer and the solder resist layer expose the cutting path. On the one hand, when cutting and separating each chip, the silicon substrate part of the wafer can be directly cut to avoid cutting the insulating layer and the solder resist layer, thereby avoiding the formation of microcracks at the edges of the two layers due to the cutting action; on the other hand, the insulating layer and the solder resist layer form a complete continuous film layer structure on the substrate surface, and there will be no situation in which stress is generated on one side in the cut film layer and cannot be compensated.

[0026] In addition, the solder resist layer extends to the outside of the insulating layer, covers the insulating layer and is combined with the substrate. On the one hand, the solder resist layer can completely seal and protect the insulating layer, thereby slowing down the erosion of the insulating layer by water vapor and the like; on the other hand, part of the stress of the solder resist layer can be directly borne by the substrate. When there is no delamination between the solder resist layer and the substrate, the insulating layer will only be subjected to a small amount of stress, further improving the reliability of the chip packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic diagram of the chip packaging structure in the first embodiment of the present invention.

[0028] Figure 2 It is a schematic diagram of the chip packaging structure before being cut and separated in the first embodiment of the present invention.

[0029] Figure 3 yes Figure 1 A magnified schematic diagram of center A.

[0030] Figure 4 It is a schematic diagram of the chip packaging structure in the second embodiment of the present invention.

[0031] Figure 5 It is a schematic diagram of the chip packaging structure before being cut and separated in the second embodiment of the present invention.

[0032] Figure 6 yes Figure 4 A magnified schematic diagram of point B in the middle.

[0033] Figure 7 It is a schematic diagram of the chip packaging structure in the third embodiment of the present invention.

[0034] Figure 8It is a schematic diagram of the chip packaging structure before being cut and separated in the third embodiment of the present invention.

[0035] Fig. 9 yes Figure 7 Enlarged schematic diagram of point C in the middle.

[0036] Fig.10 yes Figure 8 Enlarged schematic diagram of point D in the middle.

[0037] Fig.11 It is a schematic diagram of the manufacturing process of the chip packaging structure in one embodiment of the present invention.

[0038] Figures 12 to 16 It is a schematic diagram of each step of the chip packaging structure manufacturing process in one embodiment of the present invention. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in combination with the specific implementation methods of this application and the corresponding drawings. Obviously, the described implementation methods are only part of the implementation methods of this application, not all of the implementation methods. Based on the implementation methods in this application, all other implementation methods obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0040] The embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0041] For ease of explanation, this document uses terms that represent relative positions in space for description, such as "above", "below", "back", "front", etc., to describe the relationship of one unit or feature shown in the drawings relative to another unit or feature. Terms of relative positions in space can include different orientations of the device in use or operation other than the orientation shown in the figure. For example, if the device in the figure is turned over, the unit described as being "below" or "above" other units or features will be located "below" or "above" the other units or features. Therefore, the exemplary term "below" can encompass both the spatial orientations of below and above.

[0042] like Figures 1 to 10As shown, the present invention provides a chip packaging structure, the chip includes a substrate 1, which has a first surface 11, a second surface 12 opposite to the first surface 11, and a side surface 13 connecting the first surface 11 and the second surface 12, an insulating layer 2, a metal wiring layer 3 and a solder resist layer 4 are sequentially provided on the first surface 11 of the substrate 1, and a soldering protrusion 6 electrically connected to the metal wiring layer 3 is provided on the solder resist layer 4.

[0043] The insulating layer 2 is SiO2, Si3N4, etc., which is formed on the surface of the chip substrate 1 by vapor deposition, and a metal wiring layer 3 for at least electrically connecting the chip is formed on the insulating layer 2. The metal wiring layer 3 is located within the insulating layer 2 in projection, and the formation method of the metal wiring layer 3 includes a sequence of processes such as metal film deposition, photolithography, copper plating, film stripping, and copper / titanium etching. The solder resist layer 4 covers the surface of the chip to play the role of insulation and sealing protection.

[0044] The chip may be a MEMS chip or an image sensor chip, etc. According to different chip types, the chip may also be provided with a protective cover plate 5 and other structures, and the protective cover plate 5 is attached to the second surface 12 of the substrate 1 .

[0045] Depending on the chip type, in some embodiments, a solder pad is provided on the second side 12 of the chip substrate 1, a through hole is provided on the first side 11 of the substrate 1 extending toward the second side 12 thereof, the solder pad is exposed at the bottom of the through hole, and the metal wiring layer 3 extends along the side wall of the through hole to the solder pad and is electrically connected thereto.

[0046] Furthermore, in some embodiments, a buffer layer 7 may be further provided between the buffer layer 7 and the metal wiring layer to relieve stress between the insulating layer 2 and the metal wiring layer 3 .

[0047] like Figure 2 As shown, the chip is obtained by cutting and separating the wafer 1', and the wafer 1' has a first surface and a second surface opposite to each other, that is, corresponding to the first surface 11 and the second surface 12 of the chip substrate 1. A plurality of chip substrates 1 are arranged in an array on the wafer 1', and a cutting path 8 is distributed between adjacent chip substrates 1. After the subsequent packaging process and testing are completed, the single chip is cut and separated along the cutting path 8. It should be noted that the cutting path 8 between two adjacent chip substrates 1 is only a blank area reserved for cutting between the two chip substrates 1, and there is no actual boundary line between the cutting path 8 and the chip substrates 1 on both sides.

[0048] Since a certain amount of loss is inevitable when the wafer 1 ′ is cut by laser or mechanical means, the cutting path 8 has a certain width d, that is, the width of the cut when the wafer 1 ′ is cut along the cutting path 8 .

[0049] The edge of the insulating layer 2 and the edge of the solder resist layer 4 are respectively retracted inward along the side 13 of the substrate 1 by a first distance a and a second distance b, wherein 0nm≤b<a. That is, the side of the chip insulating layer 2 and the side 13 of the substrate 1 on the same side are spaced by a first distance a, and the side of the solder resist layer 4 and the side 13 of the substrate 1 on the same side are spaced by a second distance b.

[0050] It should be noted that when the chip is not cut and separated from the wafer 1 ′, the first distance a and the second distance b mentioned here are the distances between the edge of the insulating layer 2 , the edge of the solder resist layer 4 and the edge of the adjacent scribe line 8 .

[0051] In the manufacturing process, the insulating layer 2 and the solder resist layer 4 are formed on the wafer 1' with an interval distribution through a mask plate corresponding to the shape of the insulating layer 2 and the solder resist layer 4. The insulating layer 2 is located inside the solder resist layer 4, and the part of the solder resist layer 4 located outside the insulating layer 2 covers the substrate 1 and covers the side of the insulating layer 2.

[0052] like Figures 1 to 3 As shown, in Example 1, the second length b is 0 nm, that is, the side of the solder resist layer 4 is flush with the side 13 of the substrate 1. At this time, preferably, in the uncut wafer 1', the solder resist layers 4 on the adjacent chip substrates 1 are spaced apart, and the spacing width is consistent with the width of the cutting path 8, so that the solder resist layer 4 exposes the cutting path 8. On the one hand, when cutting and separating each chip, the silicon substrate part of the wafer 1' can be directly cut to avoid cutting the insulating layer 2 and the solder resist layer 4, thereby avoiding the formation of microcracks at the edges of the two layers due to the cutting action; on the other hand, the insulating layer 2 and the solder resist layer 4 form a complete continuous film layer structure on the surface of the substrate 1, and there will be no situation in which stress is generated on one side in the cut film layer and cannot be compensated.

[0053] Furthermore, since the solder resist layer 4 extends to the outside of the insulating layer 2, it covers the insulating layer 2 and is combined with the substrate 1. On the one hand, the solder resist layer 4 can completely seal and protect the insulating layer 2, thereby slowing down the erosion of the insulating layer 2 by water vapor and the like; on the other hand, part of the stress of the solder resist layer 4 can be directly borne by the substrate 1. When there is no delamination between the solder resist layer 4 and the substrate 1, the insulating layer 2 will only be subjected to a small amount of stress, thereby further improving the reliability of the chip packaging structure.

[0054] In addition, since the second length b is less than the first length a, that is, there is a certain distance between the edge of the insulating layer 2 and the solder resist layer 4, even when delamination occurs between the substrate 1 and the solder resist layer 4, there is a delamination transition distance, which makes it difficult for the delamination to extend into the interior of the insulating layer 2.

[0055] In other embodiments of Example 1, when the stress of the solder resist layer 4 is low enough, the insulating layer 2 can be retracted inward to form an insulating layer 2 distributed at intervals, forming a complete solder resist layer 4 on the surface of the wafer 1', and the solder resist layer 4 is cut together with the wafer 1' during the cutting process.

[0056] like Figures 4 to 6 As shown, in the second embodiment, the difference from the first embodiment is that the second length b is greater than 0 nm, that is, in the uncut wafer 1', there is a gap between the edge of the solder resist layer 4 and the side of the substrate 1, and by setting the edge of the solder resist layer 4 away from the edge of the cutting path 8, the stress of the solder resist layer 4 will not directly act on the side of the substrate 1 and tear the substrate 1 from the side.

[0057] The first length a and the second length b can be adjusted according to the chip size and functional requirements without any special restrictions, as long as the second length b is smaller than the first length a.

[0058] Furthermore, in some embodiments of the present invention, the side surface 13 of the substrate 1 is provided with a groove 9 recessed inwardly along the first surface 11 of the substrate 1 , and the groove 9 is distributed along the length direction of the side surface 13 of the substrate 1 .

[0059] like Figures 7 to 10 As shown, in the third embodiment, the difference from the second embodiment is that the chip further includes a groove 9, the groove 9 forms a step structure on the side surface 13 of the substrate 1, and has a groove 9 side wall surface 91 and a groove 9 bottom surface 92, and a third distance c is spaced between the top of the groove 9 side wall surface 91 and the side surface 13 of the substrate 1 on the same side thereof, wherein c≤b, i.e., the side surface of the solder resist layer 4 is flush with the side wall surface 91 of the groove 9, or the edge of the solder resist layer 4 is retracted inwardly along the side wall surface 91 of the groove 9 by a certain distance.

[0060] In the uncut wafer 1', a full groove 9' is formed above the cutting street 8 to cover it. The full groove 9' opens upward. After cutting to obtain a single chip, the full groove 9' is cut along with the chip, and a groove 9 that opens upward and to the side is formed on the side 13 of the substrate 1. The top of the side wall surface 91 of the single-sided groove 9 is spaced from the edge of the cutting street 8 by a third distance c, and the width of the full groove 9' at the opening is d+2c, and the bottom surface 92 of the full groove 9' at least completely exposes the cutting street 8.

[0061] The groove 9 is formed by etching before cutting. By setting a groove 9 with a width greater than the cutting road 8 and a certain depth above the cutting road 8, the initial position of the cutting is lower and some margins are retained on both sides, thereby enhancing the strength of the single chip substrate 1 at the corner after cutting, allowing it to withstand greater stress and further enhance the reliability of the chip.

[0062] Before cutting, the longitudinal cross-section of the groove 9 can be rectangular, or inverted trapezoidal, etc., as long as the cutting path 8 can be exposed. The depth of the cutting path 8 has no special limitation and can be adjusted according to the process capability and chip design space.

[0063] like Fig.11 As shown, the present invention also provides a chip packaging structure manufacturing method, comprising the steps of:

[0064] S1: Fig.12 As shown, a wafer 1 ′ is provided. The wafer 1 ′ has a first surface 11 and a second surface 12 opposite to each other. A plurality of chip substrates 1 are arranged in an array on the wafer 1 ′. Cutting lanes 8 are distributed between adjacent chip substrates 1 . The width of the cutting lanes 8 is d.

[0065] Furthermore, in some embodiments of the present invention, a step of forming a groove 9 is also included.

[0066] S11 : forming a full trench 9 ′ located above the scribe line 8 on the first surface 11 of the wafer 1 ′, wherein the width of the full trench 9 ′ is greater than the width of the scribe line 8 .

[0067] Specifically, the full groove 9' is formed by etching, and the full groove 9' has a groove 9 side wall surface 91 and a groove 9 bottom surface 92, and a third distance c is spaced between the top of the full groove 9' side wall surface 91 and the edge of the cutting road 8 on the same side thereof, that is, after subsequent cutting, the full groove 9' is cut into a groove 9 located on the side surface 13 of the substrate 1.

[0068] There is a third distance c between the top of the side wall 91 of the groove 9 and the side surface 13 of the substrate 1 on the same side. The width of the upper end surface of the groove 9 is d+2c. The bottom surface 92 of the groove 9 at least exposes the cutting path 8. The longitudinal section of the groove 9 can be rectangular, or inverted trapezoidal, etc.

[0069] Furthermore, depending on the type of chip, after forming the full groove 9 ′, a through hole extending toward the second surface 12 of the wafer 1 ′ is formed on the first surface 11 of the wafer 1 ′, and the bottom of the through hole exposes the pad disposed on the second surface 12 of the wafer 1 ′.

[0070] Alternatively, the method may further include attaching a protective cover plate 5 to the second surface 12 of the substrate 1 .

[0071] S2: Fig.13 As shown, an insulating layer 2 is formed on the first surface 11 of the chip substrate 1 , and insulating layers 2 are independently distributed at intervals on each substrate 1 . The edge of the insulating layer 2 on each substrate 1 is retracted inwardly along the cutting path 8 by a first distance a.

[0072] Specifically, the insulating layer 2 is formed by a vapor deposition technique, and the insulating layer 2 is formed on the substrate 1 through a mask plate corresponding to the plane shape of the insulating layer 2 .

[0073] The metal wiring layer 3 is formed by a sequence of processes including metal film deposition, photolithography, copper plating, film stripping, and copper / titanium etching. The projection of the metal wiring layer 3 in the vertical direction is located within the insulating layer 2 .

[0074] Furthermore, in some embodiments of the present invention, after forming the insulating layer 2 , a buffer layer 7 is formed on the insulating layer 2 .

[0075] S3: Fig.14 As shown, a metal wiring layer 3 and a solder resist layer 4 are sequentially formed on the insulating layer 2, and independently spaced solder resist layers 4 are formed on each substrate 1. The edge of the solder resist layer 4 on each substrate 1 is retracted inwardly along the cutting path 8 by a second distance b, wherein 0nm≤c≤b<a, and the portion of the solder resist layer 4 located outside the insulating layer 2 covers the substrate 1 and wraps around the side of the insulating layer 2.

[0076] Specifically, the method for forming the solder resist layer 4 includes a sequence of processes such as deposition, photolithography, and chemical plating, and the solder resist layer 4 is formed on the substrate 1 through a mask plate corresponding to the plane shape of the solder resist layer 4 .

[0077] S4: Fig.15 As shown, a through hole exposing the metal wiring layer 3 is opened on the solder resist layer 4, and a soldering protrusion 6 electrically connected to the metal wiring layer 3 is formed in the through hole.

[0078] S5: Fig.16 As shown, the wafer 1' is cut along the cutting lines 8 to obtain a plurality of independent chip packaging structures.

[0079] It should be understood that although this specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each implementation mode may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

[0080] The series of detailed descriptions listed above are only specific descriptions of feasible implementation methods of the present invention and are not intended to limit the scope of protection of the present invention. All equivalent implementation methods or changes that do not deviate from the technical spirit of the present invention should be included in the scope of protection of the present invention.

Claims

1. A chip packaging structure, the chip comprising a substrate having a first surface, a second surface opposite to the first surface, and a plurality of side surfaces connecting the first surface and the second surface, an insulating layer, a metal wiring layer and a solder resist layer are sequentially arranged on the first surface of the substrate, and a soldering protrusion electrically connected to the metal wiring layer is arranged on the solder resist layer, characterized in that: The edge of the insulating layer and the edge of the solder resist layer are respectively retracted inwardly along the side surface of the substrate by a first distance a and a second distance b, wherein 0 nm ≤ b < a; The metal wiring layer is located within the insulating layer in projection; The insulating layer is located inside the solder resist layer, and the portion of the solder resist layer located outside the insulating layer covers the substrate and directly contacts and covers the side edge of the insulating layer.

2. The chip packaging structure according to claim 1, characterized in that: The side surface of the substrate is provided with a groove which is recessed inwardly along the first surface of the substrate, and the groove is distributed along the length direction of the side surface of the substrate.

3. The chip packaging structure according to claim 2, characterized in that: The groove forms a step structure on the side surface of the substrate, having a groove side wall surface and a groove bottom surface, and a third distance c is spaced between the top of the groove side wall surface and the side surface of the substrate on the same side thereof, wherein c≤b.

4. The chip packaging structure according to claim 1, characterized in that: A buffer layer is provided between the insulating layer and the metal wiring layer.

5. The chip packaging structure according to claim 1, characterized in that: The second surface of the substrate is provided with a pad, the first surface of the substrate is provided with a through hole extending toward the second surface thereof, the bottom of the through hole exposes the pad, and the metal wiring layer extends along the side wall of the through hole to the pad and is electrically connected thereto.

6. A method for manufacturing a chip packaging structure, characterized in that: Includes steps: Providing a wafer, wherein the wafer has a first surface and a second surface opposite to each other, a plurality of chip substrates are arranged in an array on the wafer, and cutting paths are distributed between adjacent substrates; An insulating layer is formed on the first surface of the substrate, and the insulating layers are independently distributed at intervals on each of the substrates, and the edge of the insulating layer on each of the substrates is retracted inwardly by a first distance a along the cutting path; A metal wiring layer and a solder resist layer are sequentially formed on the insulating layer, and the solder resist layers are independently distributed at intervals on each of the substrates, and the edge of the solder resist layer on each of the substrates is retracted inwardly along the cutting path by a second distance b, wherein 0nm≤b<a, and the portion of the solder resist layer located outside the insulating layer covers the substrate and wraps around the side of the insulating layer; The insulating layer is formed by vapor deposition technology, and the insulating layer is formed on the substrate by a mask plate corresponding to the plane shape of the insulating layer; the solder resist layer is formed on the substrate by a mask plate corresponding to the plane shape of the solder resist layer; Opening a through hole on the solder resist layer to expose the metal wiring layer, and forming a soldering protrusion in the through hole that is electrically connected to the metal wiring layer; The wafer is cut along the cutting lines to obtain multiple independent chip packaging structures.

7. The chip packaging structure manufacturing method according to claim 6, characterized in that: Before "forming an insulating layer on the first surface of the substrate", the method further includes the following steps: A full groove is formed on the first surface of the wafer and is located above the scribe line. The width of the full groove is greater than the width of the scribe line.

8. The chip packaging structure manufacturing method according to claim 7, characterized in that: The full groove has a groove sidewall and a groove bottom, and a third distance c is spaced between the top of the groove sidewall and the edge of the cutting road on the same side thereof, wherein c≤b, and the groove bottom at least completely exposes the cutting road.

9. The method for manufacturing a chip packaging structure according to claim 6, characterized in that: The step of “forming a metal wiring layer and a solder resist layer in sequence on the insulating layer” also includes the following steps: A buffer layer is formed on the insulating layer.

10. The method for manufacturing a chip packaging structure according to claim 6, characterized in that: Before "forming an insulating layer on the first surface of the substrate", the following steps are also included: A through hole extending toward the second surface of the wafer is formed on the first surface of the wafer, and the bottom of the through hole exposes the bonding pad disposed on the second surface of the wafer.

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