Electrostatic protection device

Abstract

The embodiment of the present invention provides an electrostatic protection device, comprising: a non-connected pin, located on a package; a virtual pad, located on a bare die, the bare die is located in the package, the virtual pad is electrically connected to the non-connected pin; a power pad and a ground pad, the virtual pad is electrically coupled with the power pad and the ground pad through an electrostatic discharge circuit; the virtual pad is located above the first well of the bare die, the power pad is located above the second well of the bare die, the ground pad is located above the substrate of the bare die, the first well is located in the substrate, and the second well is located in the first well. The technical solution of the present invention can improve the electrostatic protection capability of the chip.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an electrostatic protection device. Background Art

[0002] As the manufacturing process of modern semiconductors becomes more and more advanced, semiconductor devices become smaller, junction depth becomes shallower, and oxide layers become thinner. The challenges faced by the reliability of semiconductor integrated circuits are becoming greater and greater, especially electrostatic protection becomes more and more important.

[0003] Conventional integrated circuit products usually have electrostatic protection designs. Usually all pads have corresponding electrostatic protection devices. The protection circuit is as follows: Figure 1 As shown, these protection circuits can ensure that all pads can quickly discharge static electricity when encountering ESD (electrostatic discharge), thereby protecting integrated circuit products from damage by electrostatic discharge.

[0004] For products such as DRAM (Dynamic Random-Access Memory) packaged in a BGA (Ball Grid Array) structure, there are usually non-connection pins NC Pins. Figure 2 As shown in the figure, the white circle is the common pin 101, and the black circle is the non-connection pin NC Pin 102. Since these non-connection pins NC Pin (NCPin) are completely suspended and have no electrostatic discharge channel, when these NC Pins encounter ESD, they usually cause ESD problems in DRAM products. The pin distribution of HBM (Human Body Model) ESD failure is as follows: Figure 3 Among them, the shaded one is the fault pin 301.

[0005] How to solve the electrostatic discharge problem of non-connected pins NC Pins in a suspended state is a technical problem that urgently needs to be solved.

[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0007] An object of the embodiments of the present invention is to provide an electrostatic protection device, thereby improving the electrostatic protection capability of a chip at least to a certain extent.

[0008] Other features and advantages of the present invention will become apparent from the following detailed description, or may be learned in part by practice of the present invention.

[0009] According to a first aspect of an embodiment of the present invention, an electrostatic protection device is provided, comprising: a non-connected pin, located on a package body; a virtual pad, located on a bare die, the bare die being located in the package body, the virtual pad being electrically connected to the non-connected pin; a power pad and a ground pad, the virtual pad being electrically coupled to the power pad and the ground pad through an electrostatic discharge circuit; the virtual pad being located above a first well of the bare die, the power pad being located above a second well of the bare die, the ground pad being located above a substrate of the bare die, the first well being located in the substrate, and the second well being located in the first well.

[0010] In some embodiments, the first well is a deep N-well, the second well is a P-well, and the substrate is a P-type substrate.

[0011] In some embodiments, the first well includes a first N-type heavily doped region and a first P-type heavily doped region, and the virtual pad is electrically connected to both the first N-type heavily doped region and the first P-type heavily doped region; the second well includes a second N-type heavily doped region and a second P-type heavily doped region, and the power pad is electrically connected to both the second N-type heavily doped region and the second P-type heavily doped region; the P-type substrate includes a third P-type heavily doped region, and the ground pad is electrically connected to the third P-type heavily doped region.

[0012] In some embodiments, the first P-type heavily doped region, the deep N-well, and the P-well form a first PNP transistor; the deep N-well, the P-well, and the second N-type heavily doped region form a first NPN transistor.

[0013] In some embodiments, a first resistor is formed between the first N-type heavily doped region and the P-well; and a second resistor is formed between the second P-type heavily doped region and the deep N-well.

[0014] In some embodiments, a first diode is formed between the P-well and the deep N-well.

[0015] In some embodiments, the first P-type heavily doped region, the deep N-well, and the P-type substrate form a second PNP transistor; the P-type substrate further includes a third N-type heavily doped region, and the deep N-well, the P-type substrate, and the third N-type heavily doped region form a second NPN transistor.

[0016] In some embodiments, a third resistor is formed between the first N-type heavily doped region and the P-type substrate; and a fourth resistor is formed between the third P-type heavily doped region and the deep N-well.

[0017] In some embodiments, a second diode is formed between the P-type substrate and the deep N-well.

[0018] In some embodiments, the electrostatic discharge circuit includes a first circuit, a first diode connected in parallel with the first circuit, a second circuit, and a second diode connected in parallel with the second circuit; the first circuit includes a first resistor, a second resistor, a first PNP transistor, and a first NPN transistor, the base of the first PNP transistor is connected to the collector of the first NPN transistor and is connected to the virtual pad through the first resistor, the emitter of the first PNP transistor is connected to the virtual pad, the collector of the first PNP transistor is connected to the base of the first NPN transistor and is connected to the power pad through the second resistor, and the emitter of the first NPN transistor is connected to the power pad; the positive electrode of the first diode The first circuit includes a third resistor, a fourth resistor, a second PNP transistor and a second NPN transistor, the base of the second PNP transistor is connected to the collector of the second NPN transistor and is connected to the virtual pad through the third resistor, the emitter of the second PNP transistor is connected to the virtual pad, the collector of the second PNP transistor is connected to the base of the second NPN transistor and is connected to the ground pad through the fourth resistor, and the emitter of the second NPN transistor is connected to the ground pad; the anode of the second diode is connected to the ground pad, and the cathode of the second diode is connected to the virtual pad.

[0019] The technical solution provided by the embodiment of the present invention may have the following beneficial effects:

[0020] In the technical solutions provided in some embodiments of the present invention, virtual pads are used to be electrically coupled with power pads and ground pads through electrostatic discharge circuits to provide a discharge path for electrostatic discharge, thereby achieving static discharge in different discharge modes and improving the electrostatic protection capability of the chip.

[0021] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings herein are incorporated into and constitute a part of the specification, showing embodiments consistent with the present invention, and together with the specification, are used to explain the principles of the present invention. Obviously, the accompanying drawings described below are only some embodiments of the present invention, and for those of ordinary skill in the art, other accompanying drawings can be obtained based on these accompanying drawings without creative work. In the accompanying drawings:

[0023] Figure 1 The structure of an electrostatic protection device in the related art is schematically shown;

[0024] Figure 2 A schematic diagram schematically shows the pin distribution of a BGA package in the related art;

[0025] Figure 3 A schematic diagram schematically shows a pin with a fault in the related art;

[0026] Figure 4 A schematic diagram showing the connection between a virtual pad and a non-connected pin in an embodiment of the present invention is shown;

[0027] Figure 5 A schematic diagram of an electrostatic protection device according to an embodiment of the present invention is schematically shown;

[0028] Figure 6 Another schematic diagram of an electrostatic protection device according to an embodiment of the present invention is schematically shown;

[0029] Figure 7 A schematic diagram of another embodiment of the present invention with an electrostatic protection device is schematically shown;

[0030] Figure 8 A schematic diagram of another embodiment of the present invention with an electrostatic protection device is schematically shown;

[0031] Fig. 9 The circuit diagram of the electrostatic discharge circuit in the embodiment of the present invention is schematically shown. DETAILED DESCRIPTION

[0032] The exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the present invention will be more comprehensive and complete and fully convey the concepts of the exemplary embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted.

[0033] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as the direction of the examples described in the drawings. It is understood that if the modules of the illustration are flipped upside down, the component described as "upper" will become the component "lower". Other relative terms, such as "high", "low", "top", "bottom", "left", "right", etc., also have similar meanings. When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0034] The terms "a", "an", and "said" are used to indicate the presence of one or more elements / components / etc.; the terms "comprising" and "having" are used to indicate an open-ended inclusive meaning and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.

[0035] In the related art, products using BGA packaging usually have non-connection pins NC Pins. These non-connection pins NCPin do not have electrostatic discharge channels, and may damage integrated circuit products when encountering ESD.

[0036] To solve the above problem, an embodiment of the present invention provides an electrostatic protection device to protect a chip with a non-connection pin NC Pin from being damaged by electrostatic discharge.

[0037] Figure 4 The schematic diagram of the connection between the virtual pad Dummy PAD and the non-connection pin NC Pin in the embodiment of the present invention is shown. Figure 4 As shown, the non-connected pin NC Pin is connected to the virtual pad Dummy PAD through a bonding wire and a package substrate. In this way, the static electricity contacted by the non-connected pin NC Pin will be transferred to the virtual pad Dummy PAD and the static discharge circuit connected to the virtual pad Dummy PAD, thereby achieving static discharge. Among them, a normal pad 501 is arranged around the virtual pad Dummy PAD.

[0038] Figure 5 A schematic diagram of an electrostatic protection device according to an embodiment of the present invention is shown schematically. Figure 4 As shown, the electrostatic protection device provided by the embodiment of the present invention includes: a non-connection pin NC Pin, located on the package body; a dummy pad Dummy PAD, located on the bare die, the bare die is located in the package body, and the dummy pad Dummy PAD is electrically connected to the non-connection pin NC Pin; and a power pad VDD and a ground pad VSS. Figure 5 As shown, the virtual pad Dummy PAD is electrically coupled with the power pad VDD and the ground pad VSS through an electrostatic discharge circuit; the virtual pad Dummy PAD is located above the first well 620 of the die, the power pad VDD is located above the second well 630 of the die, the ground pad VSS is located above the substrate 610 of the die, the first well 620 is located in the substrate 610, and the second well 630 is located in the first well 620.

[0039] In the technical solution of the embodiment of the present invention, the virtual pad Dummy PAD is electrically coupled with the power pad VDD and the ground pad VSS through an electrostatic discharge circuit, and static electricity can be discharged in different discharge modes; the non-connected pin NCPIN is changed from a pin in a suspended state to a pin with electrostatic protection, thereby realizing electrostatic protection for the non-connected pin NC PIN.

[0040] Here, the first well 620 may be a deep N-well, the second well 630 may be a P-well, and the substrate 610 may be a P-type substrate.

[0041] like Figure 5 As shown, the first well 620 includes a first N-type heavily doped region 622 and a first P-type heavily doped region 621, and the dummy pad Dummy PAD is electrically connected to the first N-type heavily doped region 622 and the first P-type heavily doped region 621; the second well 630 includes a second N-type heavily doped region 634 and a second P-type heavily doped region 633, and the power pad VDD is electrically connected to the second N-type heavily doped region 634 and the second P-type heavily doped region 633; ​​the P-type substrate 610 includes a third P-type heavily doped region 615, and the ground pad VSS is electrically connected to the third P-type heavily doped region 615.

[0042] Thus, the first P-type heavily doped region 621, the deep N-well 620, and the P-well 630 form a first PNP transistor Q1; the deep N-well 620, the P-well 630, and the second N-type heavily doped region 634 form a first NPN transistor Q2. At the same time, a first resistor R1 is formed between the first N-type heavily doped region 621 and the P-well 630; and a second resistor R2 is formed between the second P-type heavily doped region 633 and the deep N-well 620.

[0043] like Figure 5 The figure shows the positive polarity electrostatic discharge mode (PD-mode) from the dummy pad Dummy PAD to the power pad VDD. In this mode, the first PNP transistor Q1 and the first NPN transistor Q2 are turned on at the same time, and the electrostatic pulse introduced by the dummy pad Dummy PAD is released to the positive pole of the power supply through the turned-on first PNP transistor Q1 and the first NPN transistor Q2. The dotted line with an arrow represents the release path of the electrostatic pulse. The positive pole of the power supply has a complete ESD protection circuit, such as Figure 1 As shown, the NC Pin is incorporated into the ESD protection network of the entire chip.

[0044] like Figure 6 As shown, a first diode D1 is formed between the P well 630 and the deep N well 620. Figure 6The figure shows the negative polarity electrostatic discharge mode (ND-mode) from the dummy pad Dummy PAD to the power pad VDD. In this mode, the first PNP transistor Q1 and the first NPN transistor Q2 are not turned on, and the electrostatic pulse of the positive pole of the power supply is released to the dummy pad Dummy PAD via the first diode D1. The dotted line with an arrow represents the release path of the electrostatic pulse.

[0045] like Figure 7 As shown, the first P-type heavily doped region 621, the deep N-well 620, and the P-type substrate 610 form a second PNP transistor Q3; the P-type substrate further includes a third N-type heavily doped region 616, and the deep N-well 620, the P-type substrate 610, and the third N-type heavily doped region 616 form a second NPN transistor Q4. At the same time, a third resistor R3 is formed between the first N-type heavily doped region 622 and the P-type substrate 610; and a fourth resistor R4 is formed between the third P-type heavily doped region 615 and the deep N-well 620.

[0046] like Figure 7 The figure shows the positive polarity discharge mode (PS-mode) from the dummy pad Dummy PAD to the ground pad VSS. In this mode, the second PNP transistor Q3 and the second NPN transistor Q4 are turned on at the same time, and the electrostatic pulse introduced by the dummy pad Dummy PAD is released to the power ground through the turned-on second PNP transistor Q3 and the second NPN transistor Q4. The dotted line with an arrow represents the release path of the electrostatic pulse. The power ground has a complete ESD protection circuit, such as Figure 1 As shown, the NC Pin is incorporated into the ESD protection network of the entire chip.

[0047] like Figure 8 As shown, a second diode D2 is formed between the P-type substrate 610 and the deep N-well 620. Figure 8 The figure shows the negative polarity electrostatic discharge mode (NS-mode) from the dummy pad Dummy PAD to the ground pad VSS. In this mode, the second PNP transistor Q3 and the second NPN transistor Q4 are not turned on, and the electrostatic pulse introduced by the power ground is released to the dummy pad Dummy PAD via the second diode D2. The dotted line with an arrow represents the release path of the electrostatic pulse.

[0048] When ESD occurs, the non-contact pin NC PIN can discharge static electricity through the electrostatic discharge circuit. The virtual pad Dummy PAD may be in four modes during electrostatic discharge, including: positive electricity is applied from the virtual pad Dummy PAD to the power pad VDD, and the discharge path is the first PNP transistor Q1 and the first NPN transistor Q2; negative electricity is applied from the virtual pad Dummy PAD to the power pad VDD, and the discharge path is the first diode D1; positive electricity is applied from the virtual pad Dummy PAD to the ground pad VSS, and the discharge path is the second PNP transistor Q3 and the second NPN transistor Q4; negative electricity is applied from the virtual pad Dummy PAD to the ground pad VSS, and the discharge path is the second diode D2. The technical solution of the embodiment of the present invention can realize electrostatic protection for these four modes.

[0049] like Fig. 9 As shown, the electrostatic discharge circuit includes a first circuit 410, a first diode D1 connected in parallel with the first circuit, a second circuit 420 and a second diode D2 connected in parallel with the second circuit; the first circuit 410 includes a first resistor R1, a second resistor R2, a first PNP transistor Q1 and a first NPN transistor Q2, the base of the first PNP transistor Q1 is connected to the collector of the first NPN transistor Q2 through the first resistor R1, the emitter of the first PNP transistor Q1 is connected to the virtual pad Dummy PAD, the collector of the first PNP transistor Q1 is connected to the base of the first NPN transistor Q2 and is connected to the power pad VDD through the second resistor R2, and the emitter of the first NPN transistor Q2 is connected to the power pad VDD; the anode of the first diode D1 is connected to the power pad VDD, and the cathode of the first diode D1 is connected to the virtual pad Dummy PAD is connected; the second circuit 420 includes a third resistor R3, a fourth resistor R4, a second PNP transistor Q3 and a second NPN transistor Q4, the base of the second PNP transistor Q3 is connected to the collector of the second NPN transistor Q4 and is connected to the virtual pad Dummy PAD through the third resistor R3, the emitter of the second PNP transistor Q3 is connected to the virtual pad Dummy PAD, the collector of the second PNP transistor Q3 is connected to the base of the second NPN transistor Q4 and is connected to the ground pad VSS through the fourth resistor R4, and the emitter of the second NPN transistor Q4 is connected to the ground pad VSS; the anode of the second diode D2 is connected to the ground pad VSS, and the cathode of the second diode D2 is connected to the virtual pad Dummy PAD.

[0050] The thyristor is equivalent to a combination of a PNP and an NPN transistor. The static pulse introduced by the dummy pad Dummy PAD can saturate and conduct both transistors of the thyristor in a very short time. Taking the first circuit 410 as an example, after the trigger conduction is achieved, the static pulse can be released from the first PNP transistor and the first NPN transistor.

[0051] When working normally, the first circuit 410 or the second circuit 420 connected to the non-connection pin NC Pin, the power pad VDD and the ground pad VSS is in the off state. At the same time, there is no connection relationship between this non-connection pin NC PIN and the internal circuit of the chip, so it will not affect the normal function of the entire chip.

[0052] In the electrostatic protection device of the embodiment of the present invention, a dummy pad Dummy PAD is used to be electrically coupled with the power pad VDD and the ground pad VSS through an electrostatic discharge circuit, providing a discharge path for electrostatic discharge, thereby realizing the discharge of static electricity in different discharge modes and improving the electrostatic protection capability of the chip.

[0053] Those skilled in the art will readily appreciate other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses or adaptations of the present invention that follow the general principles of the present invention and include common knowledge or customary techniques in the art that are not disclosed by the present invention. The specification and examples are to be considered exemplary only, and the true scope and spirit of the present invention are indicated by the following claims.

[0054] It should be understood that the present invention is not limited to the exact construction that has been described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

Claims

1. An electrostatic protection device, It is characterized in that include: Non-connected pins, located on the package body; a virtual pad, located on a bare die, the bare die being located in the package, the virtual pad being electrically connected to the non-connection pin; A power pad and a ground pad, wherein the virtual pad is electrically coupled with the power pad and the ground pad through an electrostatic discharge circuit; The dummy pad is located above a first well of the die, the power pad is located above a second well of the die, the ground pad is located above a substrate of the die, the first well is located in the substrate, and the second well is located in the first well.

2. The electrostatic protection device according to claim 1, It is characterized in that The first well is a deep N-well, the second well is a P-well, and the substrate is a P-type substrate.

3. The electrostatic protection device according to claim 2, It is characterized in that The first well includes a first N-type heavily doped region and a first P-type heavily doped region, and the dummy pad is electrically connected to both the first N-type heavily doped region and the first P-type heavily doped region; The second well comprises a second N-type heavily doped region and a second P-type heavily doped region, and the power pad is electrically connected to both the second N-type heavily doped region and the second P-type heavily doped region; The P-type substrate includes a third P-type heavily doped region, and the ground pad is electrically connected to the third P-type heavily doped region.

4. The electrostatic protection device according to claim 3, It is characterized in that The first P-type heavily doped region, the deep N-well, and the P-well form a first PNP transistor; The deep N-well, the P-well, and the second N-type heavily doped region form a first NPN transistor.

5. The electrostatic protection device according to claim 3, It is characterized in that A first resistor is formed between the first N-type heavily doped region and the P-well; A second resistor is formed between the second P-type heavily doped region and the deep N-well.

6. The electrostatic protection device according to claim 3, It is characterized in that A first diode is formed between the P-well and the deep N-well.

7. The electrostatic protection device according to claim 3, It is characterized in that The first P-type heavily doped region, the deep N-well, and the P-type substrate form a second PNP transistor; The P-type substrate further includes a third N-type heavily doped region, and the deep N-well, the P-type substrate, and the third N-type heavily doped region form a second NPN transistor.

8. The electrostatic protection device according to claim 3, It is characterized in that A third resistor is formed between the first N-type heavily doped region and the P-type substrate; A fourth resistor is formed between the third P-type heavily doped region and the deep N-well.

9. The electrostatic protection device according to claim 3, It is characterized in that A second diode is formed between the P-type substrate and the deep N-well.

10. The electrostatic protection device according to claim 1, It is characterized in that The electrostatic discharge circuit includes a first circuit, a first diode connected in parallel with the first circuit, a second circuit, and a second diode connected in parallel with the second circuit; The first circuit includes a first resistor, a second resistor, a first PNP transistor and a first NPN transistor, the base of the first PNP transistor is connected to the collector of the first NPN transistor and connected to the virtual pad through the first resistor, the emitter of the first PNP transistor is connected to the virtual pad, the collector of the first PNP transistor is connected to the base of the first NPN transistor and connected to the power pad through the second resistor, and the emitter of the first NPN transistor is connected to the power pad; the anode of the first diode is connected to the power pad, and the cathode of the first diode is connected to the virtual pad; The second circuit includes a third resistor, a fourth resistor, a second PNP transistor and a second NPN transistor, the base of the second PNP transistor is connected to the collector of the second NPN transistor and is connected to the virtual pad through the third resistor, the emitter of the second PNP transistor is connected to the virtual pad, the collector of the second PNP transistor is connected to the base of the second NPN transistor and is connected to the ground pad through the fourth resistor, and the emitter of the second NPN transistor is connected to the ground pad; the anode of the second diode is connected to the ground pad, and the cathode of the second diode is connected to the virtual pad.

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