Sequential logic gate circuits and sensor devices

Abstract

The present invention provides a sequential logic gate circuit and a sensing device, wherein the sequential logic gate circuit includes: a preset sequence setting circuit, a shift register circuit and a signal sequence output circuit, wherein the shift register circuit is connected to the preset sequence setting circuit and the signal sequence output circuit respectively; the preset sequence setting circuit is used to generate a preset digital sequence; the shift register circuit is used to receive a target function signal, and after receiving a trigger signal in the target function signal, transmit the preset digital sequence to the signal sequence output circuit; the signal sequence output circuit outputs the preset digital sequence. This sequential logic gate circuit can realize the output of the preset digital sequence without the need for single chips, memory and other components, thereby realizing the representation of target function events, with low hardware cost, high reliability, simple structure and fast development process.

Description

Technical Field

[0001] The present invention relates to the technical field of digital circuits, and in particular to a sequential logic gate circuit and a sensor device. Background Art

[0002] With the increasing bandwidth of the Internet and the continuous reduction in the production costs of electronic devices such as chips, memory, and passive components, more and more sensing devices such as sensors and environmental perception devices are entering an interconnected era, building an omnipresent Internet of Things ecosystem.

[0003] In addition to the sensor element, most of these sensor devices need to add a single chip and flash memory or other memory such as static, dynamic, synchronous dynamic, etc. to support the operation of the single chip in order to realize basic functions such as identification, communication interaction, and alarm. Although the production cost of these sensor devices is decreasing, if the required functions are relatively simple, if the complex method of adding a single chip or memory is still used to achieve the required functions, it will waste resources and will not be conducive to further reducing costs. Moreover, the complex method of adding a single chip or memory to achieve the required functions is more complicated, and the development process is slower.

[0004] Therefore, a simple-to-design, low-cost sequential logic gate circuit to solve the problems in the prior art is particularly important. Summary of the invention

[0005] The present invention provides a sequential logic gate circuit and a sensor device to solve the defects in the prior art.

[0006] The present invention provides a sequential logic gate circuit, comprising: a preset sequence setting circuit, a shift register circuit and a signal sequence output circuit, wherein the shift register circuit is connected to the preset sequence setting circuit and the signal sequence output circuit respectively;

[0007] The preset sequence setting circuit is used to generate a preset digital sequence, and the preset digital sequence is used to represent the target functional event;

[0008] The shift register circuit is used to receive a target function signal, wherein the target function signal includes a trigger signal, and the trigger signal is used to indicate that the target function event is triggered;

[0009] The shift register circuit is further configured to transmit the preset digital sequence to the signal sequence output circuit after receiving the trigger signal;

[0010] The signal sequence output circuit is used to output the preset digital sequence.

[0011] According to a sequential logic gate circuit provided by the present invention, the shift register circuit further comprises: an input terminal and a plurality of stages of D-type flip-flops connected in series;

[0012] The input end is used to receive the target function signal; the D-type flip-flop includes a clock pin, a preset pin, a clear pin, a data pin and an output pin;

[0013] When the preset pin and the clear pin are in different levels, the output pin and the clear pin are in the same level;

[0014] The preset pin and the clear pin are both in a high level state and when the clock pin has a rising edge of a timing pulse, the level of the output pin is consistent with the level of the data pin.

[0015] According to a sequential logic gate circuit provided by the present invention, the shift register circuit further comprises: an input terminal and at least two stages of D-type flip-flops connected in series;

[0016] The input end is used to receive the target function signal;

[0017] The output pin of the previous D-type flip-flop in two adjacent stages is connected to the data pin of the next D-type flip-flop.

[0018] According to a sequential logic gate circuit provided by the present invention, the D-type trigger comprises a first type D-type trigger and a second type D-type trigger;

[0019] The preset pin of the first type D-type flip-flop is connected to the input terminal, and the clear pin of the first type D-type flip-flop is connected to the power supply;

[0020] A clear pin of the second type D-type flip-flop is connected to the input end, and a preset pin of the second type D-type flip-flop is connected to the power supply.

[0021] According to a sequential logic gate circuit provided by the present invention, in the at least two stages of D-type flip-flops connected in series, the reverse output pin of the first stage of the D-type flip-flops is used as a signal sequence output terminal to output the preset digital sequence;

[0022] Accordingly, the signal sequence output circuit includes a triode and a light emitting diode;

[0023] The base of the transistor is connected to the input end, the emitter of the transistor is connected to the signal sequence output end, the collector of the transistor is connected to the power supply, and the light emitting diode is connected between the collector of the transistor and the power supply.

[0024] According to a sequential logic gate circuit provided by the present invention, the signal sequence output circuit further includes a first current limiting resistor and a second current limiting resistor;

[0025] The first current limiting resistor is connected between the emitter of the transistor and the inverting output pin of the first-stage D-type flip-flop, and the second current limiting resistor is connected between the base of the transistor and the input terminal.

[0026] According to a sequential logic gate circuit provided by the present invention, the target function signal further includes a non-trigger signal, and the non-trigger signal is used to indicate that the target function event is not triggered;

[0027] Correspondingly, the preset sequence setting circuit is specifically used to generate the preset digital sequence after the shift register circuit receives the non-trigger signal.

[0028] According to a sequential logic gate circuit provided by the present invention, the trigger signal is a high level signal.

[0029] According to a sequential logic gate circuit provided by the present invention, the target functional event is an alarm event.

[0030] The present invention also provides a sensor device, comprising: the sequential logic gate circuit described above.

[0031] The sequential logic gate circuit and sensor device provided by the present invention include: a preset sequence setting circuit, a shift register circuit and a signal sequence output circuit, wherein the shift register circuit is connected to the preset sequence setting circuit and the signal sequence output circuit respectively; the preset sequence setting circuit is used to generate a preset digital sequence; the shift register circuit is used to receive a target function signal, and after receiving a trigger signal in the target function signal, transmit the preset digital sequence to the signal sequence output circuit; the signal sequence output circuit outputs the preset digital sequence. This sequential logic gate circuit can realize the output of the preset digital sequence without the need for single chips, memory and other components, thereby realizing the characterization of target function events, with low hardware cost, high reliability, simple structure and fast development process. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0033] Figure 1 It is one of the structural schematic diagrams of the sequential logic gate circuit provided by the present invention;

[0034] Figure 2 It is a structural schematic diagram of a D-type flip-flop included in the sequential logic gate circuit provided by the present invention;

[0035] Figure 3 It is a structural schematic diagram of a D-type flip-flop with a preset high potential output included in the sequential logic gate circuit provided by the present invention;

[0036] Figure 4 It is a structural schematic diagram of a D-type flip-flop with a preset low potential output included in the sequential logic gate circuit provided by the present invention;

[0037] Figure 5 It is a structural schematic diagram of a shift register circuit in a sequential logic gate circuit provided by the present invention;

[0038] Figure 6 This is the second structural schematic diagram of the sequential logic gate circuit provided by the present invention;

[0039] Figure 7 It is a simulation schematic diagram of the sequential logic gate circuit provided by the present invention;

[0040] Figure 8 It is a structural schematic diagram of the sensing device provided by the present invention. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0042] Since most of the sensing devices in the prior art need to add a single chip and flash memory or other memories such as static, dynamic, synchronous dynamic, etc. to support the operation of the single chip in addition to the sensing element, there will be a waste of resources, which is not conducive to further reducing costs. Moreover, the complex method of adding a single chip or memory to achieve the required functions is relatively complex, and the development process is slow. Therefore, the sequential logic gate circuit (Sequential Logic) that can be realized by a simple logic gate still has the advantages of low price, low circuit complexity, high reliability and fast development process. In some application scenarios of sensing devices, the sensing device only needs to generate a uniquely identifiable alarm signal. Using a single-chip solution for this type of application scenario seems to be a bit overkill, and it also pays too high a hardware cost. To this end, a sequential logic gate circuit is provided in an embodiment of the present invention.

[0043] Figure 1 FIG. 1 is a schematic diagram of a sequential logic gate circuit provided in an embodiment of the present invention. Figure 1 As shown, the sequential logic gate circuit includes: a preset sequence setting circuit 2, a shift register circuit 1 and a signal sequence output circuit 3, wherein the shift register circuit 1 is connected to the preset sequence setting circuit 2 and the signal sequence output circuit 3 respectively;

[0044] The preset sequence setting circuit 2 is used to generate a preset digital sequence 21, and the preset digital sequence 21 is used to represent the target functional event;

[0045] The shift register circuit 1 is used to receive a target function signal, wherein the target function signal includes a trigger signal, and the trigger signal is used to indicate that the target function event is triggered;

[0046] The shift register circuit 1 is also used to transmit the preset digital sequence 21 to the signal sequence output circuit 3 after receiving the trigger signal;

[0047] The signal sequence output circuit 3 is used to output the preset digital sequence.

[0048] Specifically, the sequential logic gate circuit provided in the embodiment of the present invention can also be called a sequential logic gate circuit. The sequential logic gate circuit includes a preset sequence setting circuit 2, a shift register circuit 1, and a signal sequence output circuit 3. The shift register circuit 1 is used to receive a target function signal, and the target function signal is used to characterize whether the target function event is triggered. The target function signal may include a trigger signal and a non-trigger signal, the trigger signal is used to characterize that the target function event is triggered, and the non-trigger signal is used to characterize that the target function event is not triggered. Among them, the trigger signal can be a high-level signal, that is, a high level is used to indicate that the target function event is triggered; correspondingly, the non-trigger signal is a low-level signal, that is, a low level is used to indicate that the target function event is not triggered. The trigger signal can also be a low-level signal, that is, a low level is used to indicate that the target function event is triggered; correspondingly, the non-trigger signal is a high-level signal, that is, a high level is used to indicate that the target function event is not triggered. This is not specifically limited in the embodiment of the present invention, and the following is only described by taking the trigger signal as a high-level signal as an example. Since the trigger signal is a high-level signal or a low-level signal, it may cause the subsequent circuit structure to change, but this change can be obtained according to the circuit principle, so this embodiment of the present invention will not be repeated.

[0049] The trigger signal may be a basic functional signal such as an alarm signal, an identification signal or a communication interaction. When the trigger signal is an alarm signal, the target functional event is an alarm event. Figure 1In the embodiment, the shift register circuit 1 further includes a clock pin 12 for receiving a timing pulse signal.

[0050] The preset sequence setting circuit 2 can be used to generate a preset digital sequence 21. The generated preset digital sequence 21 can be used to represent the target functional event. The preset digital sequence 21 can be set as needed, as long as it can represent the target functional event.

[0051] After receiving the trigger signal in the target function signal, the shift register circuit 1 can transmit the preset digital sequence 21 generated by the preset sequence setting circuit 2 to the signal sequence output circuit 3. The signal sequence output circuit 3 performs a preset digital sequence output 31. The output can be a light-emitting display or can be output to a remote end through a cable, so that the remote end can use the preset data sequence for subsequent processing.

[0052] The sequential logic gate circuit provided in the embodiment of the present invention includes: a preset sequence setting circuit, a shift register circuit and a signal sequence output circuit, wherein the shift register circuit is connected to the preset sequence setting circuit and the signal sequence output circuit respectively; the preset sequence setting circuit is used to generate a preset digital sequence; the shift register circuit is used to receive the target function signal, and after receiving the trigger signal in the target function signal, transmit the preset digital sequence to the signal sequence output circuit; the signal sequence output circuit outputs the preset digital sequence. This sequential logic gate circuit can realize the output of the preset digital sequence without the need for single chips, memory and other components, thereby realizing the representation of the target function event, with low hardware cost, high reliability, simple structure and fast development process.

[0053] On the basis of the above-mentioned embodiments, the sequential logic gate circuit provided in the embodiments of the present invention, the shift register circuit comprises: an input end and a plurality of stages of D-type flip-flops connected in series;

[0054] The input end is used to receive the target function signal; the D-type flip-flop includes a clock pin, a preset pin, a clear pin, a data pin and an output pin;

[0055] When the preset pin and the clear pin are in different levels, the output pin and the clear pin are in the same level;

[0056] The preset pin and the clear pin are both in a high level state and when the clock pin has a rising edge of a timing pulse, the level of the output pin is consistent with the level of the data pin.

[0057] Specifically, the shift register circuit used in the embodiment of the present invention includes an input end and several stages of D-type flip-flops connected in series, and the input end is used to receive the target function signal. Several stages of D-type flip-flops connected in series refer to several D-type flip-flops connected in series, and each D-type flip-flop is used as a first-level D-type flip-flop. The D-type flip-flop with the rising edge trigger of the timing pulse can specifically realize shift register circuits such as serial-in-serial-out (SISO), parallel-in-parallel-out (PIPO), serial-in-parallel-out (SIPO) and parallel-in-serial-out (PISO). In the embodiment of the present invention, a parallel-in-serial-out circuit implemented by a D-type flip-flop with a preset / clear function is proposed as a shift register circuit, so that when an alarm event occurs in the sensor device, the target function event represented by a preset digital sequence is triggered by the rising edge of the timing pulse.

[0058] like Figure 2 As shown, each D-type flip-flop includes a clock pin (CLK), a preset pin Output pin (Q), clear pin Reverse output pin As well as a data pin (D), a preset pin for inputting a preset signal (SET), an output pin for data output (DATA_OUT), a data pin for data input (DATA_IN), a clear pin for a reset signal (RESET), a reverse output pin for reverse data output (~DATA_OUT), and a clock pin (CLK) for receiving a timing pulse signal.

[0059] Table 1 is a truth table of a D-type flip-flop used in an embodiment of the present invention.

[0060] Table 1 D-type flip-flop truth table

[0061]

[0062] In the embodiment of the present invention, if a D-type flip-flop is used, its preset pin With clear pin When the level is different, that is, is high level 1, then Is low level 0, if is high level 1, then When it is low level 0, regardless of whether CLK has a rising edge of timing pulse, its output pin (Q) and clear pin The level of High level 1, When it is low level 0, Q is low level 0. High level 1, When it is low level 0, Q is high level 1.

[0063] If a D-type flip-flop is used, its preset pin With clear pin When both are in high level state, and When both are high level 1 and the clock pin (CLK) has a rising edge of the timing pulse, the level of the data pin (D) will be maintained at the output pin (Q), that is, the level of the output pin (Q) is consistent with the level of the data pin (D), that is, the level of Q is determined by the level of D. If D is high level 1, Q is also high level, if D is low level 0, Q is also low level 0.

[0064] If a D-type flip-flop is used, its preset pin With clear pin When both are in the low level state, and The level of the output pin (Q) is uncertain, and the shift register circuit needs to avoid the D-type flip-flop in this connection mode.

[0065] D-type flip-flop at preset pin Low level, clear pin When the clock pin (CLK) and data pin (D) are high, the output pin (Q) and clear pin are both high level; otherwise, at the preset pin High level, clear pin When the output pin (Q) is low, it is always low. In this way, on a D-type flip-flop, you can use the preset pins with different levels. With clear pin Configuration, set the level of the output pin (Q) of the D-type flip-flop. Assuming that the input end of the shift register circuit is a high-level trigger, when the target function signal is a low level, that is, a non-trigger signal, the preset pin Clear Pin The level of the output pin (Q) is configured for each D-type flip-flop connected in series in the shift register circuit.

[0066] Specifically, when there is no trigger signal, the low-level input terminal is connected to the preset pin Will clear the pin Connect to power supply V CC The output pin (Q) of the D-type flip-flop can be set at a high level, such as Figure 3 Similarly, when there is no trigger signal, connect the low level input terminal to the clear pin. Preset pins Connect to V CCThe output pin (Q) of the D-type flip-flop can be set at a low level, such as Figure 4 When a trigger signal is received, the input terminal is high level, forming a preset pin With clear pin The level of the data pin (D) of the D-type flip-flop is output to the output pin (Q) at the rising edge of the timing pulse signal (CLK); the output pin (Q) maintains the level obtained at the rising edge of the previous timing pulse signal (CLK) when the timing pulse signal (CLK) is low, and maintains this level until the next rising edge of the timing pulse arrives. This is the memory characteristic of the D-type flip-flop.

[0067] By using the memory characteristics of the D-type flip-flop and connecting the output pin (Q) of the previous D-type flip-flop in series with the data pin (D) of the next D-type flip-flop, a basic shift register is realized. The potential of the data pin (D) of the previous D-type flip-flop will move to the data pin (D) of the next D-type flip-flop in succession according to the timing pulse signal. Therefore, a shift register circuit can be formed by connecting multiple such shift registers in series. Figure 5 , which is a schematic diagram of the structure of a shift register circuit provided in an embodiment of the present invention, wherein three D-type flip-flops 12 are included.

[0068] Among them, the truth table of the shift register circuit is shown in Table 2.

[0069] Table 2 Shift register circuit truth table

[0070]

[0071] In an embodiment of the present invention, a parallel-input and serial-output circuit implemented by using a D-type flip-flop with a preset / clear function is provided as a shift register circuit, which can enable a sequential logic gate circuit to output a target functional event represented by a preset digital sequence without a single chip.

[0072] On the basis of the above embodiments, a sequential logic gate circuit is provided in an embodiment of the present invention, wherein the shift register circuit comprises: an input end and at least two stages of D-type flip-flops connected in series; the input end is used to receive the target function signal; the output pin of the previous stage of the D-type flip-flops in two adjacent stages of the D-type flip-flops is connected to the data pin of the next stage of the D-type flip-flops, wherein the output pin of the last stage of the D-type flip-flops is connected back to the data pin of the first stage of the D-type flip-flops, so as to realize the circular series connection of all the D-type flip-flops contained in the shift register circuit.

[0073] On the basis of the above embodiments, in the sequential logic gate circuit provided in the embodiments of the present invention, the D-type flip-flop includes a first type D-type flip-flop and a second type D-type flip-flop;

[0074] The preset pin of the first type D-type flip-flop is connected to the input terminal, and the clear pin of the first type D-type flip-flop is connected to the power supply;

[0075] A clear pin of the second type D-type flip-flop is connected to the input end, and a preset pin of the second type D-type flip-flop is connected to the power supply.

[0076] Specifically, the first type of D-type flip-flop refers to a D-type flip-flop with a preset high potential output. Connected to the input, clear pin of the first type D-type flip-flop Connected to the power supply Vcc; the second type of D-type flip-flop refers to a D-type flip-flop with a preset low potential output, and the clear pin of the second type of D-type flip-flop Connected to the input, the preset pin of the second type D-type flip-flop Connect to power supply Vcc.

[0077] In the embodiment of the present invention, the first type of D-type flip-flop and the second type of D-type flip-flop are used to respectively realize the preset high potential output and low potential output of each level of D-type flip-flop in the shift register circuit, so that the obtained sequential logic gate circuit is more flexible.

[0078] On the basis of the above embodiment, in the sequential logic gate circuit provided in the embodiment of the present invention, in the at least two stages of D-type flip-flops connected in series, the reverse output pin of the first stage of the D-type flip-flops is used as a signal sequence output terminal to output the preset digital sequence;

[0079] Accordingly, the signal sequence output circuit includes a triode and a light emitting diode;

[0080] The base of the transistor is connected to the input end, the emitter of the transistor is connected to the signal sequence output end, the collector of the transistor is connected to the power supply, and the light emitting diode is connected between the collector of the transistor and the power supply.

[0081] Specifically, Figure 6 As shown, the shift register circuit includes an input terminal 11 and five stages of D-type flip-flops connected in series, the first-stage D-type flip-flop, the third-stage D-type flip-flop and the fourth-stage D-type flip-flop are all first-type D-type flip-flops 12, and the second-stage D-type flip-flop and the fifth-stage D-type flip-flop are all second-type D-type flip-flops 13.

[0082] Accordingly, the signal sequence output circuit 3 includes a transistor 31 and a light emitting diode (LED) 32. The transistor 31 may be an NPN transistor. The base of the transistor 31 is connected to the input terminal 11, and the emitter of the transistor 31 is connected to the reverse output pin of the first stage D-type flip-flop 12. That is, the signal sequence output end is connected, the collector of the transistor 31 is connected to the power supply Vcc, and the light emitting diode 32 is connected between the collector of the transistor 31 and the power supply Vcc.

[0083] Five D-type flip-flops with preset and clear functions are connected in sequence from the first to the fifth stage to form a ring-shaped series shift register circuit. The alarm signal gate is connected to the preset pins of the first, third and fourth stage D-type flip-flops. Clear pins of the first-stage D-type flip-flop, the third-stage D-type flip-flop, and the fourth-stage D-type flip-flop Both connected to the power supply V CC When the alarm event is not triggered, that is, the input terminal 11 is in a low level state, such a connection sets the output pins (Q) of these D-type flip-flops to a high level. Similarly, the target function signal is connected to the clear pins of the second-stage D-type flip-flop and the fourth-stage D-type flip-flop respectively. The preset pins of these two D-type flip-flops Connect to power supply V CC Therefore, when the alarm event is not triggered, that is, in the no-alarm state, the output pins (Q) of the first to fifth-stage D-type flip-flops are 1-0-1-1-0, respectively, which are used to represent the preset digital sequence. When the alarm event is triggered, that is, in the alarm state, the preset pins of the first to fifth-stage D-type flip-flops are With clear pin All connected to high level, this sequence is shifted to the output pin (Q) of the first stage D-type flip-flop along with the external input timing pulse signal (CLK), and due to the ring series connection of the D-type flip-flop, the preset digital sequence will be repeated until the alarm signal gate returns to low level. The specific simulation process is as follows Figure 7 shown.

[0084] In the embodiment of the present invention, a triode and a light emitting diode are introduced, and whether a target function event is triggered can be directly determined by whether the light emitting diode emits light.

[0085] like Figure 6 As shown, based on the above embodiment, the sequential logic gate circuit provided in the embodiment of the present invention, the signal sequence output circuit also includes a first current limiting resistor R1 and a second current limiting resistor R2. The resistance value of R1 can be 100Ω, and the resistance value of R2 can specifically be 100KΩ. The first current limiting resistor R1 is connected to the emitter of the transistor 31 and the reverse output pin of the lowest level D-type flip-flop 12. The second current limiting resistor R2 is connected between the base of the transistor 31 and the input terminal 11 .

[0086] The light-emitting diode 32 is used as a light-emitting device for optical signals, and a triode is used. A current-limiting resistor is connected in series between the base and input terminal of the triode, and between its emitter and the signal sequence output terminal to protect the device and control power consumption. In the trigger state, that is, when the input terminal is at a high level, the base of the triode 31 is also at a high level, and the brightness of the light-emitting diode 32 is controlled by the signal sequence output terminal. When the signal sequence output terminal is at a low level, the light-emitting diode 32 is turned on and lit. On the contrary, when the signal sequence output terminal is at a high level, the light-emitting diode 32 is extinguished. In this way, when the light-emitting diode 32 is in the trigger state, the sequence of brightness corresponds to the potential on the output pin (Q) of the first-stage D-type flip-flop, and the sequence of light-off-on-on-off is represented at the five moments of t0-t1-t2-t3-t4 by the timing pulse signal, and this cycle is repeated every 5 pulses thereafter until the input terminal 11 returns to a low level.

[0087] In the embodiment of the present invention, the introduction of the first current limiting resistor and the second current limiting resistor can make the sequential logic gate circuit safer, avoid danger caused by excessive current in the circuit and extend the service life of the light emitting diode 32.

[0088] On the basis of the above-mentioned embodiment, in the sequential logic gate circuit provided in the embodiment of the present invention, the signal sequence output circuit further comprises: a cable connected to the signal sequence output end; the cable is used to transmit the differential signal.

[0089] Specifically, the signal sequence output circuit in the embodiment of the present invention may further include: a cable, through which the preset digital sequence output by the signal sequence output terminal can be transmitted to a remote end in the form of an electrical signal for subsequent application.

[0090] On the basis of the above-mentioned embodiment, the sequential logic gate circuit provided in the embodiment of the present invention, the signal sequence output circuit may further include: a differential signal conversion circuit and a cable, the differential signal conversion circuit is respectively connected to the signal sequence output terminal and the cable;

[0091] The differential signal conversion circuit is used to convert the preset digital sequence from a single-ended signal to a differential signal, and the cable is used to transmit the differential signal to a remote end.

[0092] Specifically, the signal sequence output circuit in the embodiment of the present invention also includes: a differential signal conversion circuit and a cable. The differential signal conversion circuit is connected to the signal sequence output end and the cable respectively. The differential signal conversion circuit can convert the preset digital sequence from a single-ended signal to a differential signal, and the differential signal can be transmitted to a remote end through the cable for subsequent application.

[0093] On the basis of the above embodiment, in the sequential logic gate circuit provided in the embodiment of the present invention, the target function signal further includes a non-trigger signal, and the non-trigger signal is used to indicate that the target function event is not triggered;

[0094] Correspondingly, the preset sequence setting circuit is specifically used to generate the preset digital sequence after the shift register circuit receives the non-trigger signal.

[0095] Specifically, in an embodiment of the present invention, the input end of the shift register circuit is also used to receive a non-trigger signal, and the non-trigger signal is used to indicate that the target function event is not triggered. The level of the non-trigger signal is different from that of the trigger signal, that is, when the trigger signal is a high-level signal, the non-trigger signal is a low-level signal. On this basis, the preset sequence setting circuit generates a preset digital sequence when the input end of the shift register circuit receives a non-trigger signal.

[0096] In the embodiment of the present invention, a timing for generating a preset digital sequence is provided to prevent a conflict between the generation of the preset digital sequence and the transmission of the preset digital sequence to the signal sequence output circuit.

[0097] On the basis of the above-mentioned embodiment, in the sequential logic gate circuit provided in the embodiment of the present invention, the trigger signal is a high level signal.

[0098] On the basis of the above-mentioned embodiment, in the sequential logic gate circuit provided in the embodiment of the present invention, the target functional event is an alarm event.

[0099] In summary, the sequential logic gate circuit provided in the embodiment of the present invention adopts a shift register circuit composed of several stages of D-type flip-flops connected in series, and cooperates with the preset sequence setting circuit to preset and clear the D-type flip-flops, and outputs a preset digital sequence when the trigger signal in the target function signal occurs. The sequential logic gate circuit provided in the embodiment of the present invention does not require complex circuits such as single chips and storage devices, and outputs a set of preset digital sequences according to the timing pulse signal when the external line of the target function signal gate is enabled. In particular, it is used in the sensor Internet of Things trusted background to process the alarm signal of the sensor device. The sensor end only needs to output a preset digital sequence when the alarm event is triggered through a timing circuit composed of simple logic gates, so that the Internet of Things trusted background can identify the source or type of the alarm. Through the preset sequence setting circuit, when the alarm event is not triggered, that is, when the alarm signal gate is at a low level, a set of preset digital sequences is provided for the shift register circuit composed of multiple shift registers. And when the alarm event is triggered, that is, when the alarm signal gate is at a high level, the preset digital sequence is triggered according to the rising edge of the timing pulse, and the signal sequence output circuit is driven to output the preset digital sequence. After the alarm signal is output, it can be used to light up the LED and sent to the remote end via the optical cable, or it can be further converted into a differential signal and sent to the remote end via the cable. Finally, through the ring connection of the D-type flip-flop, the preset digital sequence is continuously and repeatedly sent in the alarm signal gate to facilitate the identification and processing of the IoT trusted background. A simple, effective, low-cost and reliable alarm event generation method is achieved.

[0100] like Figure 8 As shown, based on the above embodiments, a sensing device 81 is provided in an embodiment of the present invention, and the sensing device 81 includes the sequential logic gate circuit 82 provided in the above embodiments. The sensing device is used to sense environmental parameters to generate a sensing signal, and input the sensing signal to the input end of the shift register circuit so as to use the sensing signal as a target function signal for subsequent processing.

[0101] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0102] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0103] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A sequential logic gate circuit, characterized in that: include: A preset sequence setting circuit, a shift register circuit and a signal sequence output circuit, wherein the shift register circuit is connected to the preset sequence setting circuit and the signal sequence output circuit respectively; The preset sequence setting circuit is used to generate a preset digital sequence, and the preset digital sequence is used to represent the target functional event; The shift register circuit is used to receive a target function signal, wherein the target function signal includes a trigger signal, and the trigger signal is used to indicate that the target function event is triggered; The shift register circuit is further configured to transmit the preset digital sequence to the signal sequence output circuit after receiving the trigger signal; The signal sequence output circuit is used to output the preset digital sequence; The shift register circuit comprises: an input terminal and a plurality of stages of D-type flip-flops connected in series; The input end is used to receive the target function signal; the D-type flip-flop includes a clock pin, a preset pin, a clear pin, a data pin and an output pin; When the preset pin and the clear pin are in different levels, the output pin and the clear pin are in the same level; The preset pin and the clear pin are both in a high level state and when the clock pin has a rising edge of a timing pulse, the level of the output pin is consistent with the level of the data pin; The D-type flip-flop includes a first type D-type flip-flop and a second type D-type flip-flop; The preset pin of the first type D-type flip-flop is connected to the input terminal, and the clear pin of the first type D-type flip-flop is connected to the power supply; A clear pin of the second type D-type flip-flop is connected to the input end, and a preset pin of the second type D-type flip-flop is connected to the power supply.

2. The sequential logic gate circuit according to claim 1, characterized in that: The shift register circuit comprises: at least two stages of D-type flip-flops connected in series; The input end is used to receive the target function signal; The output pin of the previous D-type flip-flop in two adjacent stages is connected to the data pin of the next D-type flip-flop.

3. The sequential logic gate circuit according to claim 2, characterized in that: In the at least two stages of D-type flip-flops connected in series, the reverse output pin of the first stage of the D-type flip-flop is used as a signal sequence output terminal to output the preset digital sequence; Accordingly, the signal sequence output circuit includes a triode and a light emitting diode; The base of the transistor is connected to the input end, the emitter of the transistor is connected to the signal sequence output end, the collector of the transistor is connected to the power supply, and the light emitting diode is connected between the collector of the transistor and the power supply.

4. The sequential logic gate circuit according to claim 3, characterized in that: The signal sequence output circuit also includes a first current limiting resistor and a second current limiting resistor; The first current limiting resistor is connected between the emitter of the transistor and the inverting output pin of the first-stage D-type flip-flop, and the second current limiting resistor is connected between the base of the transistor and the input terminal.

5. The sequential logic gate circuit according to any one of claims 1 to 4, characterized in that: The target function signal also includes a non-trigger signal, and the non-trigger signal is used to indicate that the target function event is not triggered; Correspondingly, the preset sequence setting circuit is specifically used to generate the preset digital sequence after the shift register circuit receives the non-trigger signal.

6. The sequential logic gate circuit according to any one of claims 1 to 4, characterized in that: The trigger signal is a high level signal.

7. The sequential logic gate circuit according to any one of claims 1 to 4, characterized in that: The target functional event is an alarm event.

8. A sensing device, characterized in that: include: A sequential logic gate circuit as claimed in any one of claims 1 to 7.

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