Device and method for ZQ calibration

Abstract

The present invention relates to an apparatus and method for ZQ calibration. In an example semiconductor device, voltage / temperature conditions of the semiconductor device and associated calibration codes for multiple instances of ZQ calibration are pre-stored in a register array. When the pre-stored voltage / temperature conditions occur again, ZQ calibration is not performed. Instead, the associated pre-stored calibration code is retrieved from the register array and provided to an IO circuit. When the voltage / temperature conditions of the semiconductor device do not match any pre-stored voltage / temperature conditions in the register array, ZQ calibration is performed. When the ZQ calibration is performed, a register in the register array is selected according to an update strategy and the register is updated by the calibration code most recently provided by the ZQ calibration together with the voltage / temperature conditions when the ZQ calibration was performed.

Description

Technical Field

[0001] The present invention relates to a device and a method for ZQ calibration. Background Art

[0002] A semiconductor memory device such as a DRAM (dynamic random access memory) includes a memory cell array each having a memory cell disposed at an intersection between a word line and a bit line. Various conditions in the memory device, such as operating temperature and voltage in a power supply, etc., may affect the performance of the memory device. For example, the impedance of an input / output (IO) circuit may be affected by different power supply voltages or temperatures. Thus, impedance calibration (e.g., ZQ calibration) is periodically performed in the memory device to compensate for changes in the impedance of the IO circuit. However, when the ZQ calibration is performed, a higher power voltage may be required, and the performance of the semiconductor device may be adversely affected. Summary of the invention

[0003] In one aspect, the present invention relates to an apparatus comprising: an input / output (IO) circuit; a ZQ calibration circuit configured to: perform ZQ calibration to provide a ZQ calibration code in response to a valid ZQ calibration control signal; and not perform ZQ calibration in response to an invalid ZQ calibration control signal; and a ZQ calibration control circuit coupled to the IO circuit and the ZQ calibration circuit and configured to: provide the invalid ZQ calibration control signal when a voltage / temperature condition matches a voltage / temperature condition stored in a register array; or provide the valid ZQ calibration control signal when the voltage / temperature condition does not match any voltage / temperature condition stored in the register array in response to the ZQ calibration signal.

[0004] In another aspect, the present invention relates to a method comprising: in response to a ZQ calibration signal: performing ZQ calibration to provide a ZQ calibration code when a voltage / temperature condition of a semiconductor device does not match any pre-stored voltage / temperature condition in a register array; and not performing the ZQ calibration when the voltage / temperature condition of the semiconductor device matches the pre-stored voltage / temperature condition in the register array.

[0005] In another aspect, the present invention relates to an apparatus comprising: an input / output (IO) circuit; and a ZQ calibration control circuit coupled to the IO circuit and configured to respond to a ZQ calibration signal: when a voltage / temperature condition does not match any voltage / temperature condition in a register array: activate the ZQ calibration circuit to provide a ZQ calibration code to the IO circuit; and when the voltage / temperature condition matches a voltage / temperature condition in the register array: retrieve a ZQ calibration code associated with the matching voltage / temperature condition from the register array; and provide the retrieved ZQ calibration code to the IO circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a block diagram of a semiconductor device according to some examples described in the present invention.

[0007] Figure 2 : is a block diagram showing an output buffer in an input / output circuit, in which a portion allocated to one data input / output terminal DQ is shown.

[0008] Figure 3 is a diagram of a ZQ calibration control circuit according to some examples described in the present invention.

[0009] Figure 4A and 4B is an example of memory contents in a content-addressable memory according to some examples described in the present invention.

[0010] Figure 5A is an example representation of voltage changes according to some examples described in the present invention.

[0011] Figure 5B is a diagram of an example voltage encoder circuit for converting a voltage into a voltage code according to some examples described in the present disclosure.

[0012] Figure 6 is a diagram of a circuit implementing a voltage comparator according to some examples described in the present invention.

[0013] Figure 7 is a flow chart of performing a ZQ calibration operation according to some examples described in the present invention.

[0014] Figure 8 is a diagram showing states of periodic ZQ calibration according to some examples described in the present invention.

[0015] Fig. 9 is a diagram of an example register control circuit according to some examples described in this disclosure. DETAILED DESCRIPTION

[0016] In some embodiments of the present invention, in a semiconductor device such as a memory device, an impedance calibration command (e.g., a ZQ calibration command) is periodically provided to a ZQ calibration circuit to perform an impedance calibration operation (e.g., a ZQ calibration operation). Periodically performing the calibration operation can compensate for impedance changes in the IO circuit due to voltage and / or temperature changes in the semiconductor device. The semiconductor device may pre-store multiple calibration codes from a previous ZQ calibration or initial back-end test in a register array together with associated voltage changes or temperature values. When a ZQ calibration signal is received, the semiconductor device may compare the current voltage / temperature condition of the device with the pre-stored voltage / temperature condition in the register array. When the current voltage / temperature condition matches the pre-stored voltage / temperature condition in the register array, the semiconductor device may skip the ZQ calibration by applying the pre-stored calibration code associated with the matching pre-stored voltage / temperature condition to the IO circuit. Conversely, when the current voltage / temperature condition does not match any pre-stored voltage / temperature condition in the register array, the semiconductor device may perform a ZQ calibration to provide the ZQ calibration code to the IO circuit. The semiconductor may also select a register in the register array and replace the contents of the selected register with the most recently generated ZQ calibration code along with the current voltage / temperature conditions of the device. In some examples, the registers in the register array are selected according to an update strategy. An example update strategy may select registers where the voltage / temperature conditions are least frequently matched in response to previous ZQ calibration commands.

[0017] Figure 1 1 is a block diagram of a semiconductor device 10 according to some examples described in the present invention. In some embodiments of the present invention, the semiconductor device 10 may be a dynamic random access memory (DRAM). The semiconductor device 10 includes a memory cell array 11. The memory cell array 11 includes a plurality of word lines WL and a plurality of bit lines BL intersecting each other, wherein memory cells (MC) are disposed at the intersections. The selection of the word line WL is implemented by a row decoder circuit 12, and the selection of the bit line BL is implemented by a column decoder circuit 13.

[0018] Further references Figure 1 , sense amplifier 18 is coupled to corresponding bit line BL and to local IO line pair LIOT / B. Local IO line pair LIOT / B is coupled to main IO line pair MIOT / B via transfer gate TG 19 used as a switch of read / write amplifier and buffer 15. Turning to the explanation of multiple external terminals included in semiconductor device 10, multiple external terminals include command and address terminal 21, clock terminal 23, data terminal 24, and power supply terminals 25 and 26.

[0019] The command and address terminal 21 is supplied with a command and address signal CA. The CA signal supplied to the command and address terminal 21 includes a command and an address. The address included in the CA signal is transmitted to the address decoder circuit 32 via the command / address input circuit 31. The address decoder circuit 32 receives the address and supplies a decoded row address signal RA to the row decoder circuit 12, and supplies a decoded column address signal COL to the column decoder circuit 13.

[0020] The command included in the CA signal provided to the command and address terminal 21 is input to the command decoder circuit 34 via the command / address input circuit 31. The command decoder circuit 34 decodes the command to provide various internal command signals. For example, the command decoder 34 decodes the command signal to generate various internal commands, including a row command signal ACT for selecting a word line and a column command signal read / write (R / W) such as a read command or a write command for selecting a bit line; and a refresh command signal REF.

[0021] When a row activation command is issued and the row address is supplied in time with the activation command and the column address is supplied in time with the read command, read data is read from the memory cell MC in the memory cell array 11 indicated by these row addresses and column addresses. More specifically, the row decoder circuit 12 selects the word line WL indicated by the row address RA so that the associated memory cell MC is then connected to the bit line BL. The read data DQ is output to the outside from the data terminal 24 via the read / write amplifier 15 and the input / output circuit 17. Similarly, when a row activation command is issued and the row address is supplied in time with the activation command and the column address is supplied in time with the write command, the IO circuit 17 can receive the write data DQ at the data terminal 24. The write data DQ is supplied to the memory cell array 11 via the IO circuit 17 and the read / write amplifier 15 and written in the memory cell MC indicated by the row address and the column address.

[0022] The clock terminals 23 are supplied with external clock signals CK_t and CK_c, respectively. These external clock signals CK_t and CK_c are complementary to each other and are supplied to the clock input circuit 35. The clock input circuit 35 receives the external clock signals CK_t and CK_c and provides an internal clock signal ICLK. The internal clock signal ICLK is supplied to the internal clock generator 36, and a phase-controllable internal clock signal LCLK is provided based on the received internal clock signal ICLK and the clock enable signal CKE from the command / address input circuit 31. In a non-limiting example, the DLL circuit may be included in the internal clock generator 36. The phase-controllable internal clock signal LCLK is supplied to the input / output circuit 17 and is used as a timing signal for determining the output timing of the read data DQ.

[0023] The power supply terminal 25 is supplied with power supply voltages VDD1, VDD2 (collectively referred to as VDD) and VSS. The power supply voltages VDD1, VDD2 and VSS are supplied to the internal voltage generator circuit 39. The internal voltage generator circuit 39 provides various internal voltages VPP, VARY, VPERI, VEQ and VCCP.

[0024] The internal potential VCCP is a potential mainly used in the row decoder circuit 12. The internal potentials VARY and VEQ are potentials to be used by the sense amplifier 18, the transfer gate 19, and / or the read / write amplifier 15. When the sense amplifier 18 is activated, the read data read out is amplified by driving one of the paired bit lines to the VARY level and the other to the VSS level. The internal potential VPERI is used as a power supply potential for most peripheral circuits such as the command / address input circuit 31. By using the internal potential VPERI having a lower potential than the external potential VDD as the power supply potential for these peripheral circuits, it is possible to reduce the power consumption of the semiconductor device 10.

[0025] Power supply terminal 26 is supplied with power supply voltages VDDQ and VSSQ. These power supply voltages VDDQ and VSSQ are supplied to IO circuit 17. Power supply voltages VDDQ and VSSQ may be the same voltages as power supply voltages VDD2 and VSS, respectively, supplied to power supply terminal 25. However, dedicated power supply voltages VDDQ and VSSQ may be used for IO circuit 17 so that power supply noise generated by IO circuit 17 is not propagated to other circuit blocks of device 10.

[0026] In the semiconductor device 10, a calibration terminal ZQ is provided. The calibration terminal ZQ is coupled to a power supply potential VDDQ via a reference resistor RZQ disposed on a memory module substrate or a motherboard. The reference resistor RZQ includes a resistor referenced during a calibration operation. The impedance of the reference resistor RZQ is used as a reference impedance of a ZQ calibration circuit 40. In some examples, a voltage generator circuit 39 provides a reference potential ZQVREF signal to the ZQ calibration circuit 40. When the calibration circuit 40 is activated by the calibration signal DOZQCAL, the calibration circuit 40 performs a calibration operation by referencing the impedance of the external reference resistor RZQ and the reference potential ZQVREF. When performing the calibration operation, the ZQ calibration circuit 40 may provide a ZQ calibration code ZQCODE to the IO circuit 17. In some examples, the ZQ calibration code may include a plurality of bits specifying the impedance of a corresponding pull-up or pull-down circuit in the IO circuit 17.

[0027] In some examples, the semiconductor device 10 may include a ZQ calibration control circuit 42 coupled to the ZQ calibration circuit 40 and the IO circuit 17. The command decoder circuit 34 may provide a ZQ calibration command ZQCAL to the ZQ calibration control circuit 42. Upon arrival of each ZQCAL command, the ZQ calibration control circuit 42 may be configured to provide a ZQ calibration code ZQCODE1 to the IO circuit 17. In some examples, ZQCODE1 may be a ZQ calibration code ZQCODE provided by the ZQ calibration circuit 40 and directly supplied to the IO circuit 17 by the ZQ calibration control circuit 42. Alternatively and / or in addition, ZQCODE1 may be a pre-stored ZQ calibration code retrieved by the ZQ calibration control circuit to be provided to the IO circuit 17. In other words, the ZQ calibration control circuit may be configured to activate the ZQ calibration and supply the calibration code provided by the ZQ calibration circuit 40 to the IO circuit 17 or to skip the ZQ calibration and retrieve a pre-stored calibration code to be provided to the IO circuit 17.

[0028] In some examples, the ZQ calibration control circuit 42 may pre-store a plurality of ZQ calibration codes provided by the ZQ calibration circuit 40 from a previous calibration or an initial calibration table obtained in a back-end test. In some examples, the ZQ calibration control circuit 42 may be provided with a voltage signal and a temperature signal TEMP indicating a voltage condition and a temperature condition of the semiconductor device, respectively. For example, the voltage signal may indicate a power supply voltage of the semiconductor device 10, such as VDD2 or VDDQ. The temperature signal TEMP may indicate an operating temperature of the semiconductor device 10. For example, the temperature signal TEMP may be provided by a temperature sensor 43. When the ZQ calibration code is pre-stored, the ZQ calibration control circuit 42 may also store operating conditions, such as voltage / temperature conditions associated with the ZQ calibration code.

[0029] In some examples, the voltage / temperature condition may include a voltage condition and / or a temperature condition. The voltage condition may include a voltage value represented by a voltage signal. The temperature condition may include a temperature value represented by a temperature signal. In some examples, the voltage / temperature condition may include a voltage value and a temperature value when the ZQ calibration is performed. For example, the voltage value may be a power supply voltage of the semiconductor device when the ZQ calibration is performed. The temperature value may be an operating temperature of the semiconductor device when the ZQ calibration is performed. Alternatively, the voltage value may be a voltage change relative to a reference voltage when the ZQ calibration is performed, for example, 5% or -5% of the reference voltage. A plurality of ZQ calibration codes may be pre-stored in a register array, each calibration code being associated with a corresponding voltage / temperature condition when an example of a ZQ calibration operation is performed, for example, by the ZQ calibration circuit 40 to provide a corresponding calibration code.

[0030] In some examples, in response to the ZQ calibration command ZQCAL, the ZQ calibration control circuit 42 may be configured to determine whether to perform ZQ calibration or skip ZQ calibration. In some examples, if the current voltage / temperature condition of the semiconductor device does not match any of the pre-stored voltage / temperature conditions in the register array, the ZQ calibration control circuit 42 may provide a valid DOZQCAL signal to activate the ZQ calibration circuit 40. The ZQ calibration circuit 40 may provide a ZQ calibration code, for example, ZQCODE. The ZQ calibration control circuit 42 may provide the calibration code ZQCODE provided by the ZQ calibration circuit to the IO circuit 17 as ZQCODE1. In some examples, if the current voltage / temperature condition matches the pre-stored voltage / temperature condition in the register array, the ZQ calibration control circuit 42 may skip ZQ calibration by deactivating the ZQ calibration circuit 40 by providing an invalid DOZACAL signal. Alternatively, the ZQ calibration control circuit 42 may retrieve a pre-stored calibration code associated with the matched voltage / temperature condition and provide the retrieved calibration code to the IO circuit 17 as ZQCODE1.

[0031] In some examples, the calibration code signals ZQCODE, ZQCODE1 may include a first portion CODEPU and a second portion CODEPD. For example, ZQCODE and ZQCODE1 may each include 14 bits, where the first portion (e.g., 7 bits) may include CODEPU and the second portion (e.g., 7 bits) may include CODEPD. CODEPU and CODEPD may be used to calibrate the pull-up and pull-down circuits in the IO circuit 17, respectively. Thus, the impedance of the output buffer OB in the IO circuit 17 is adjusted. This reference Figure 2 Further explanation is given.

[0032] Figure 2 is a block diagram showing an output buffer in an input / output circuit. Figure 2 The output buffer OB is used for one data input / output terminal DQ. In some instances, the output buffer OB includes 7 pull-up units PU0 to PU6 and 7 pull-down units PD0 to PD6 for one data input / output terminal DQ. The output nodes of the pull-up units PU0 to PU6 and the pull-down units PD0 to PD6 are commonly coupled to the corresponding data input / output terminal DQ via a resistor R. The pull-up units PU0 to PU6 have the same circuit configuration and are collectively referred to as "pull-up units PU" when no distinction is required. Similarly, the pull-down units PD0 to PD6 have the same circuit configuration and are collectively referred to as "pull-down units PD" when no distinction is required.

[0033] The pull-up unit PUi (i=0 to 6) is paired with the pull-down unit PDi (i=0 to 6). The number of unit pairs to be used is specified by the mode signal MODE output from the mode register. The internal data DATA is supplied from the FIFO circuit to the pull-up units PU0 to PU6 and the pull-down units PD0 to PD6. If the internal data DATA is at a high logic level, one or more pull-up units specified by the mode signal MODE among the pull-up units PU0 to PU6 will be activated. Therefore, the data input / output terminal DQ is driven to a high logic level. When the internal data DATA indicates a low level, one or more pull-down units specified by the mode signal MODE among the pull-down units PD0 to PD6 will be activated. Therefore, the data input / output terminal DQ is driven to a low level.

[0034] The impedance of each of the activated pull-up units PU0 to PU6 is specified by the code signal CODEPU. Similarly, the impedance of each of the activated pull-down units PD0 to PD6 is specified by the code signal CODEPD.

[0035] According to various embodiments, the impedance target value of the pull-up units PU0 to PU6 is 2RZQ, where RZQ is the resistance of the reference resistor. The impedance target value of the pull-down units PD0 to PD6 is RZQ. Therefore, if j pairs of units are used as specified by the mode signal MODE, the impedance at the high level output is 2RZQ / j, and the impedance at the low level output is RZQ / j. In this way, the impedance of the pull-up unit PU and the pull-down unit PD are adjusted based on the code signals CODEPU and CODEPD, respectively.

[0036] Figure 3 3 is a diagram of a ZQ calibration control circuit according to some examples described in the present invention. In some examples, the ZQ calibration control circuit 300 can be a ZQ calibration control circuit 42 (in Figure 1 3. The ZQ calibration control circuit 300 may include a voltage comparator 302, a temperature comparator 304, and a switching circuit 310. The voltage comparator 302 may be provided with a voltage signal, such as a power supply voltage such as VDD2, VDDQ. The power supply voltage may be provided from a power supply terminal of a semiconductor device. The temperature comparator 304 may be provided with a temperature signal TEMP. The temperature signal TEMP may be provided from a power supply terminal of a semiconductor device configured to monitor a semiconductor device (e.g., Figure 1 The temperature sensor of the operating temperature of 10) is provided. The temperature signal may include a temperature value in the form of one or more data bits.

[0037] Further references Figure 3, the ZQ calibration control circuit 300 may further include a register control circuit 306 coupled to the voltage comparator 302 and the temperature comparator 304. The register control circuit 306 may be configured to retrieve a pre-stored calibration code along with an associated pre-stored voltage / temperature condition. The voltage / temperature condition may include a semiconductor device (e.g., Figure 1 10) of the semiconductor device. For example, the voltage condition may include a voltage value indicating a power supply of the semiconductor device, such as VDD2, VDDQ. Alternatively and / or in addition, the voltage condition may include a voltage change relative to a reference voltage. The temperature signal obtained from the temperature sensor may include a temperature value indicating a temperature condition. In some examples, the temperature value may indicate an operating temperature of the semiconductor device. In some examples, the calibration code and the associated voltage / temperature condition may be stored in a register array 308 coupled to the register control circuit 306. The contents of the register array 308 are further described with reference to FIG. 4.

[0038] Figure 4A and 4B is an example of memory contents in a register array according to some examples described in the present invention. Figure 4A In FIG. 4 , register array 400 may be implemented in register array 308. Register control circuit 306 (in Figure 3 ) can be configured to control data write and read operations of register array 400. In some examples, register array 400 may include multiple registers, such as Reg 0, Reg 1, ..., Reg N. Each of the registers may include information represented by multiple bits, such as Figure 4B In the Figure 4B , register 420 may be an example data configuration of registers in register array 400. Register 420 may include a first portion (voltage field) storing a voltage condition (e.g., a voltage value or a voltage change value), a second portion (temperature field) storing a temperature condition (e.g., a temperature), and a third portion (ZQ code field) storing a ZQ calibration code associated with the voltage / temperature condition. For an example of ZQ calibration, for a given voltage and temperature change of a semiconductor device, a ZQ calibration circuit (e.g., Figure 140) can provide a corresponding ZQ calibration code. The ZQ calibration code can be stored in register 420 together with the voltage / temperature conditions when the ZQ calibration code is generated. For example, the voltage and temperature changes when the ZQ calibration is performed and the corresponding calibration code provided by the ZQ calibration are stored in the register and associated together. Each register in the register array 308 can store a ZQ calibration code associated with a unique voltage / temperature condition. A suitable number of registers can be included in the register array. Additional details of retrieving data from the register and writing data to the register can be described in the context of the operation of the ZQ calibration control circuit 300.

[0039] Return to Figure 3 , the register control circuit 306 may be configured to save the voltage / temperature condition to the register array 308 or retrieve the voltage / temperature condition from the register array 308. The voltage / temperature condition may include a voltage condition and / or a temperature condition, such as a voltage change and / or a temperature value. The register array 308 may provide the pre-stored voltage / temperature condition to the voltage comparator 302 and the temperature comparator 304 via the VTINFO signal line. The VTINFO signal on the VTINFO signal line may include a first portion and a second portion, which respectively include the voltage condition and the temperature condition stored in one or more registers in the register array (e.g., 308). The voltage comparator 302 and the temperature comparator 304 may be configured to determine whether there is a match between the current voltage / temperature condition (e.g., VDD2 / VDDQ, TEMP) of the semiconductor device and any pre-stored voltage / temperature condition provided in the VTINFO signal. If the current voltage / temperature condition of the semiconductor device does not match any pre-stored voltage / temperature condition in the register in the register array, then the valid calibration signal DOZQCAL is provided by the ZQ calibration control circuit 300. If the current voltage / temperature condition of the semiconductor device matches the pre-stored voltage / temperature condition in the register in the register array, then the de-asserted DOZQCAL signal is provided.

[0040] Further references Figure 3 , the operation of the voltage comparator 302 and the temperature comparator 304 is now explained. In some examples, the temperature comparator 304 can be coupled to the voltage comparator 302 and configured to provide the control signal TEMP_MATCH to the voltage comparator. The temperature comparator 304 can also be coupled to a command decoder circuit (e.g., Figure 134) to receive a ZQ calibration command, such as ZQCAL, from the command decoder circuit. The temperature comparator 304 may be configured to compare the temperature value in the temperature signal TEMP provided by the temperature sensor with the temperature condition in the VTINFO signal in response to the ZQCAL command to provide a match signal TEMP_MATCH. The VTINFO signal may include pre-stored voltage conditions and / or temperature conditions in one or more registers in the register array (e.g., 308). If the temperature value in the temperature signal matches the temperature condition in one or more registers in the register array 308, the temperature comparator may provide a valid signal TEMP_MATCH indicating that the temperature provided by the sensor matches one or more pre-stored temperature values. The valid TEMP_MATCH signal may then activate the voltage comparator 302. If the temperature condition in the VTINFO signal does not match the temperature value in the TEMP signal, the temperature comparator 304 may provide an invalid TEMP_MATCH signal indicating that the current temperature does not match any pre-stored temperature value in the register array. The invalid TEMP_MATCH signal then deactivates the voltage comparator 302.

[0041] When the temperature condition in the VTINFO signal does not match the temperature value in the TEMP signal, the temperature comparator 304 may provide a valid calibration signal DOZQCAL. The valid calibration signal DOZQCAL is provided to the ZQ calibration circuit (eg, Figure 1 In other words, if none of the pre-stored temperature conditions in register array 308 matches the temperature value in TEMP signal, ZQ calibration control circuit 300 is configured to activate ZQ calibration operation and provide a ZQ calibration code provided by the ZQ calibration circuit to IO circuit (e.g., Figure 1 17).

[0042] In some examples, the temperature value in the TEMP signal and the temperature condition in VTINFO may include any suitable number of bits. For example, the TEMP signal provided to the temperature comparator 304 and the temperature field of the register (in Figure 4B ) may include a semiconductor device (eg, Figure 1 In some examples, the 8-bit temperature signal can be used to represent -89°C to 167°C with 1°C resolution. In some examples, the TEMP and temperature fields of the registers (in Figure 4B The 7 bits corresponding to the 7 most significant bits of the digital output of the temperature sensor may be included while leaving out the least significant bit. This will produce the same temperature range as the original 8-bit digital output, but with a 2°C reduction in temperature resolution.

[0043] In some examples, the temperature comparator 304 may be implemented in a content addressable memory (CAM). The CAM may also contain a register array 308. The CAM is typically configured to allow searching by content. For example, the registers in the CAM may be searched by the temperature value in the temperature field. Once one or more registers are found to match the temperature value being searched, the associated voltage condition of the matched temperature value may be made available to the voltage comparator via the VTINFO signal line.

[0044] When the pre-stored temperature value matches the temperature value in the TEMP signal, the voltage comparator 302 in the ZQ calibration control circuit 300 is activated in response to the active TEMP_MATCH signal. The voltage comparator 302 may be configured to compare the voltage value in the voltage signal provided to the voltage comparator with the voltage condition pre-stored in the register array 308 via the VTINFO signal line. The voltage signal may include a current voltage condition of the semiconductor device, such as VDD2 / VDDQ. The voltage condition in the VTINFO signal may correspond to a voltage condition in one or more registers in the register array 308, wherein the one or more registers contain the matched temperature condition from the temperature comparator 304. In some examples, the voltage field of the register may include a voltage change (e.g., a deviation of a power supply voltage such as VDD2 / VDDQ relative to a reference voltage) and be represented in a voltage code. This reference Figures 5A to 5B Further explanation is given.

[0045] Figure 5A is an example representation of voltage variation according to some examples described in the present invention. In some examples, voltage variation can be represented by region. For example, a typical voltage variation range (e.g., semiconductor device (e.g., Figure 1 The -5% to 5% range that is usually allowed in the power supply in 10) can be divided into four regions, each of which is contained in the voltage field or register of the VTINFO signal (for example, Figure 4B The three-digit voltage code in the voltage field in 420) is represented as Figure 5A As shown in FIG. 1 , region 1 defines a 2.5% to 5% voltage variation range and is represented by a voltage code of “110”. Similarly, region 2 defines a 0 to 2.5% range and is represented by a voltage code of “010”; region 3 defines a -2.5% to 0 range and is represented by “000”; and region 4 defines a -5% to -2.5% range and is represented by “001”. Figure 5A Only examples of regions and assignments of voltage codes are shown. It should be appreciated that various configurations of regions can be used to provide various assignments of voltage codes in a similar manner. Similarly, various numbers of bits in the voltage code can be used to represent a region.

[0046] Figure 5B5 is a diagram of an example voltage encoder circuit for converting a voltage into a voltage code according to some examples described in the present invention. The voltage encoder circuit 500 may be implemented in a voltage comparator (e.g., Figure 3 302 in the embodiment and configured to convert the voltage signal into a voltage code, such as indicating Figure 5A . In some examples, the voltage encoder circuit 500 may include a plurality of amplifiers 502, 504, 506. Each amplifier may be provided with a voltage signal, such as a power supply VDD2 / VDDQ, at one input terminal, and provided with a reference voltage for measuring voltage changes at another input terminal. For example, a first terminal (e.g., a non-inverting terminal) of amplifiers 502 and 504 may be provided with a power supply voltage VDD2 / VDDQ. A reference voltage Vref is provided to a second terminal (e.g., an inverting terminal) of amplifier 504. In some examples, Vref may be a reference voltage provided by a voltage generator circuit (e.g., Figure 1 39) provided by the ZQ reference voltage (e.g., ZQVREF). In some examples, the reference voltage Vref may be a bandgap voltage reference. For example, the reference voltage may be a voltage generated by a voltage generator circuit (e.g., Figure 1 39) provided by the amplifier 502, such as half or one third of VDDQ. The amplifiers 502 and 506 may be provided with voltages higher and lower than the reference voltage Vref, respectively. For example, the amplifier 502 may be provided with a reference voltage 2.5% higher than the reference voltage Vref at the inverting terminal. The amplifier 506 may be provided with a reference voltage 2.5% lower than the reference voltage Vref at the non-inverting terminal.

[0047] The multiple amplifiers may be configured to provide a voltage code of voltage variation by forming a multi-bit voltage code at the output of the multiple amplifiers. In a non-limiting example, the outputs of amplifiers 502, 504, 506ABC may represent a 3-bit voltage code. For example, if the voltage VDD2 / VDDQ is higher than Vref but has a variation of less than 2.5% (see Figure 5A 2 in region 2), then amplifier 504 is turned on while amplifiers 502 and 506 are turned off. Therefore, ABC will have code 010. In another example, if the voltage VDD2 / VDDQ has a negative voltage variation greater than 2.5% (meaning the voltage is less than the reference voltage, see Figure 5A 4 in region 4), then amplifiers A and B are off and amplifier 506 is on, so ABC will have code 001. In another example, if voltage VDD2 / VDDQ is above 2.5% of the voltage variation (see Figure 5A1), then amplifiers A and B will be turned on and amplifier C will be turned off, so ABC will have code 110. In another example, if voltage VDD2 / VDDQ is lower than the reference voltage but has a negative voltage variation of less than 2.5% (see Figure 5A If the voltage code is formed in region 3 in the voltage encoder circuit, then all amplifiers 502, 504, 506 will be turned off. The ABC code will be 0 (000). It will be appreciated that any suitable number of bits may be used to represent a voltage code that has been similarly formed, wherein the number of bits in the voltage code corresponds to the number of amplifiers in the voltage encoder circuit.

[0048] Return to Figure 3 , the voltage field in the VTINFO signal may also have the same number of bits (e.g., Figure 5A When comparing the current voltage condition (e.g., VDD2 / VDDQ) with the voltage condition in VTINFO, the voltage comparator 302 may be configured to convert the voltage signal into a multi-bit voltage code, such as ABC (in Figure 5B ), and then compares the voltage code of the voltage signal with the voltage field in VTINFO. In some examples, if the difference between the voltage code of the voltage signal and the voltage code contained in the voltage field of VTINFO is not greater than one voltage variation region, the voltage comparator 302 may determine that the voltage condition in the current voltage signal matches the voltage condition in the VTINFO signal. Conversely, if the difference between the voltage code of the voltage signal and the voltage code contained in the voltage field of VTINFO is greater than one voltage variation region, the voltage comparator 302 may determine that the voltage signal does not match VTINFO.

[0049] In some instances, reference Figure 5A , if the voltage signal is converted to the voltage code (110) of zone 1 and the voltage field of VTINFO contains the voltage code (010) of zone 2, or vice versa, then the difference between the voltage signal and the voltage condition in the VTINFO signal is one voltage change zone. Then, the voltage conditions in the two signals are considered to match. Conversely, if the difference between the voltage signal and the voltage condition in the VTINFO signal is greater than one voltage change zone (e.g., zone 1 and zone 4; zone 2 and zone 4; or zone 1 and zone 3, etc.), then the voltage conditions in the two signals are considered to not match.

[0050] Figure 6 6 is a diagram of a circuit that implements at least a portion of a voltage code comparator according to some examples described in the present invention. The voltage code comparator 600 may be implemented in a voltage comparator (e.g., Figure 3 In 302) and configured to compare a first voltage change and a second voltage change, both represented by a voltage code. Example voltage code Figure 5AIt will be appreciated that other voltage code assignments may be possible. Figure 6 , the first voltage code may be represented by ABC, and the second voltage code may be represented by A'B'C'. The voltage code comparator 600 may include a first group of logic gates, such as AA', BB', and CC'. As indicated by the annotations of the logic gates, the logic gate AA' is coupled to the first corresponding bits A and A' of the first and second voltage codes, respectively. The logic gate BB' is coupled to the second corresponding bits B and B' of the first and second voltage codes, respectively. The logic gate CC' is coupled to the third corresponding bits C and C' of the first and second voltage codes, respectively.

[0051] In some examples, each of the logic gates of the first group is an XOR gate that provides an output indicating whether corresponding bits in the first and second voltage codes are the same. For example, logic gate AA' (e.g., an XOR gate) is configured to provide a high logic state output when the input terminals have opposite logic states. In a non-limiting example, if A and A' contain different bits, such as 01 or 10, then logic gate AA' provides a high logic state output. If A and A' contain the same bit, such as 00 or 11, then logic gate AA' provides a low logic state output.

[0052] Further references Figure 6 , the outputs of the logic gates of the first group are further provided to the logic gates of the second group coupled to the logic gates of the first group. Examples of the logic gates of the second group include logic gates 602, 604, and 606. In some examples, each of the logic gates in the second group may be a NAND gate. Each NAND gate in the logic gates of the second group may be coupled to the outputs of two logic gates in the logic gates of the first group. For example, the outputs of logic gates AA' and BB' are coupled to logic gate 602; the outputs of logic gates BB' and CC' are coupled to logic gate 604; and the outputs of logic gates AA' and CC' are coupled to logic gate 606. For each NAND gate 602, 604, 606, when both input signals are in a high logic state, the output is in a low logic state; otherwise, the output of the NAND gate is in a high logic state. The voltage code comparator 600 may further include an additional NAND gate 608 coupled to the logic gates of the second group. For example, the input of the additional NAND gate 608 is coupled to the output of the logic gates of the second group. The output of the additional NAND gate 608 is coupled to a ZQ calibration circuit (eg, Figure 1 40) to provide the DOZQCAL signal to the ZQ calibration circuit.

[0053] Further references Figure 6As described above, the voltage code comparator 600 is now configured to provide a valid DOZQCAL signal when at least two pairs of corresponding bits in the first and second voltage codes (eg, ABC and A'B'C') have different bits. For example, when ABC=110 (corresponding to Figure 5A Area 1 in the table) and A'B'C'=000 (corresponding to Figure 5A 3 in region 1), both the first and second corresponding bits in ABC and A'B'C' are different. This results in the outputs of logic gates AA' and BB' being in a high logic state and the output of logic gate CC' being in a low logic state, which results in the output of logic gate 602 being in a low logic state. This causes additional logic gate 608 to provide a high logic state output - an active DOZQCAL signal. In another example, when ABC=110 (corresponding to Figure 5A Area 1 in the Figure 5A 1), only the first corresponding bit in ABC and A'B'C' is different. This causes the output of logic gate AA' to be in a high logic state and the outputs of logic gates BB' and CC' to be low. Therefore, the outputs of all gates 602, 604, 606 are in a high logic state, causing the output of additional logic gate 608 to provide a low logic state output - an inactive DOZQCAL signal.

[0054] The following table shows the reference Figures 3 to 6 The voltage changes of various embodiments described and the corresponding DOZQCAL signal cases. (See Figure 5A zoning and voltage code assignment in ).

[0055]

[0056] Return to Figure 3 In some examples, if the difference between the voltage code of VDD2 / VDDQ and the voltage field in VTINFO (or in any register) is not greater than one zone, then the voltage comparator 304 may determine that there is a voltage match. In the above table, zone changes between zone 1 and zone 2, zone 2 and zone 3, and zone 3 and zone 4 all result in one zone change. In this case, the power supply, such as VDD2 / VDDQ, and the voltage conditions in VTINFO (or pre-stored voltage conditions in register array 308) are considered to match. As shown in the above table, all zone pairs that result in one zone change correspond to a maximum range of 5% (e.g., 0% to 5% for zone 1 and zone 2; -2.5% to 2.5% for zone 2 and zone 3; and -5% to 0% for zone 3 and zone 4). It should be understood that in some embodiments, other zone changes may be defined and may be used to determine a voltage match.

[0057] Recall that voltage comparator 302 is activated in response to an active TEMP_MATCH signal. This means that when there is a voltage match, both the temperature and voltage corresponding to the previous calibration have been matched. Figure 3 and 6 As shown in FIG. 1 , in response to the voltage match, the voltage comparator 302 in the ZQ calibration control circuit 300 may provide an invalid DOZQCAL signal to the ZQ calibration circuit (eg, Figure 1 In response to the inactive DOZQCAL signal, register control circuit 306 may be configured to retrieve a pre-stored calibration code associated with the matched voltage / temperature condition and provide the retrieved calibration code as C2.

[0058] Further references Figure 3 In some examples, the switching circuit 310 may be a multiplexer. The switching circuit 310 may be coupled to the register control circuit 306 at one terminal (to receive the pre-stored calibration code C2) and also coupled to the ZQ calibration circuit (e.g., Figure 1 40) to receive the calibration code ZQCODE provided by the ZQ calibration circuit. When there is a voltage match, the invalid DOZQCAL signal can cause the switching circuit 310 to provide the pre-stored calibration code C2 as ZQCODE1 to the IO circuit (eg, Figure 1 17).

[0059] In some examples, when there is no voltage match, the voltage comparator 302 can provide an active DOZQCAL signal on the DOZQCAL signal line. The DOZQCAL signal line can be coupled to the ZQ calibration circuit (at Figure 1 ) so that a valid DOZQCAL signal can activate the ZQ calibration circuit (e.g., Figure 1 40) to cause the ZQ calibration circuit to provide the calibration code ZQCODE. The valid DOZQCAL signal can also control the switching circuit 310 to supply the ZQCODE provided by the ZQ calibration circuit as ZQCODE1 to the IO circuit (eg, Figure 1 17).

[0060] Further references Figure 3 When there is no temperature match or voltage match, the ZQ calibration control circuit 300 is configured to provide an active DOZQCAL signal, which will cause the register control circuit 306 to use the ZQ calibration circuit (e.g., Figure 1The register is updated with a new ZQCODE provided by 40). The ZQCODE is provided to the register control circuit 306 as code C1. In some examples, code C1 can be uploaded to the register array 308 via the control of the register control circuit 306. When uploading the new calibration code to the register, the register control circuit 306 can implement an update strategy to determine which register in the register array will be replaced with the new calibration code. This reference Figure 4A Further description is given.

[0061] refer to Figure 4A , the register array may include a plurality of counters, e.g., counters 0, 1, 2, ..., each counter being associated with a corresponding register in the register array. For example, counter 0 is associated with register 0, counter 1 is associated with register 1, and so on. In some examples, each counter is configured to count the number of times that the voltage / temperature condition in the associated register matches the voltage / temperature condition (e.g., VDD2 / VDDQ and TEMP) of the semiconductor device. In other words, the count value in each counter also indicates that the calibration code pre-stored in the associated register is calibrated by the ZQ calibration control circuit (e.g., Figure 3 300) retrieved and provided to the IO circuit (e.g., Figure 1 17) times. In operation, the voltage and temperature of the semiconductor device may have a swing range. The higher the counter in the register array, the more likely it is that the voltage / temperature condition stored in the register associated with the counter will be accessed again in future swings. Thus, the update strategy may include keeping the register with the higher count and replacing the register with the lower count.

[0062] refer to Figure 3 In an example embodiment, when DOZQCAL becomes active, register control circuit 306 may select a register whose associated counter contains the lowest count among the other counters in the register array. Register control circuit 306 may then use the registers generated by the ZQ calibration circuit (e.g., Figure 1The calibration code in the selected register is replaced by a new ZQCODE provided by 40) in the register control circuit 306. The register control circuit 306 can also replace the voltage and temperature fields in the register with the current voltage / temperature condition of the semiconductor device at the time of ZQ calibration. For example, the voltage field of the selected register can be replaced with the voltage code of the current voltage. The temperature field can be replaced with the current temperature value. The counter associated with the selected register can then be reset, for example, to 0 or 1, or an initial value. In some examples, when DOZQCAL becomes invalid, the calibration code is retrieved from the register array and supplied to the IO circuit instead of being provided by the ZQ calibration circuit. In this case, the counter associated with the register storing the retrieved calibration code is incremented by one count. Thus, the frequency at which any voltage / temperature condition matches during operation of the ZQ calibration control circuit is appropriately stored.

[0063] Fig. 9 900 is a diagram of an example register control circuit according to some examples described in the present invention. In some examples, register control circuit 900 may be implemented in register control circuit 306 (in Figure 3 ). Register control circuit 900 may be coupled to register array 910. Register array 910 may be implemented in register array 308 (in Figure 3 For example, register array 910 may include a plurality of registers, such as registers 0 to 7 (or other suitable number of registers). Register array 910 may also include a plurality of counters, such as counters 0 to 7 (or other suitable number of counters). Each of the counters may be associated with a respective register of the plurality of registers. Examples of configurations of registers and counters are described in the present disclosure with reference to Figure 4A Description. In response to the ZQCAL command, the register control circuit 900 may retrieve a pre-stored calibration code (eg, C2) from a matching register in the register array via the code output buffer 904. Retrieval of the pre-stored calibration code previously referenced Figures 3 to 6 Detailed description.

[0064] Further references Fig. 9 In some examples, the register control circuit 900 may include a counter comparator 902 configured to compare the values ​​in each of the plurality of counters in the register array 910 and determine the prioritization of the registers based on the counter values. In a non-limiting example, the counter comparator 902 may be configured to implement an update strategy. For example, when storing a new calibration code in the register array, the counter comparator 902 may determine the registers that are frequently accessed by comparing the values ​​in the counters associated with the registers. The counter comparator 902 may then determine to keep the registers with the higher counts. Conversely, the counter comparator 902 may determine to replace the registers with the lower counts with the new calibration code.

[0065] In some examples, counter comparator 902 may provide a REG_SEL signal to register array 910, where the REG_SEL signal indicates a pointer to a register / counter in the register array. In the above example, REG_SEL indicates which register is selected to have its contents replaced with a new calibration code. Register control circuit 900 may be configured to receive a REG_SEL signal from a ZQ calibration circuit (e.g., Figure 1 The calibration code (e.g., code C1) obtained by the calibration code 40 in FIG. 40 is obtained, and the calibration code is stored in the selected register indicated by the REG_SEL signal. Subsequently, the voltage / temperature condition in the selected register may also be replaced by the current voltage / temperature condition (e.g., VDD2 / VDDQ / TEMP) of the semiconductor device. In addition, the counter associated with the selected register may be reset (e.g., reset to a value of 0 or 1).

[0066] Return to Figure 3 , register array 308 and temperature comparator 304 may be implemented in a CAM. In some instances, voltage comparator 302 may also be implemented in a CAM. For example, registers in a CAM may be searched by voltage / temperature values ​​in voltage and temperature fields. Once a register is found to match the voltage / temperature value being searched, the calibration code stored in the found register may be output. Using a CAM to store calibration codes may reduce circuit system complexity in register control circuits or voltage comparators or temperature comparators because some search / comparison functions may be built into the CAM. Thus, without departing from the scope of the present invention, Figure 3 Variations of the embodiments described in may be possible. For example, in an example implementation, the voltage and temperature fields in each register are searched together, where each register in the register array contains a combination of voltage and temperature codes, such as Figure 4B 420 shown in the video.

[0067] In a non-limiting example, reference Figure 4B The voltage stored in the voltage field may include a 3-digit voltage code indicating a voltage change region. The temperature in the temperature field may include a temperature sensor (e.g., Figure 143) obtained in the CAM register array. When the combination of voltage and temperature conditions of the semiconductor device matches the pre-stored combination of voltage / temperature in the CAM register array, then DOZQCAL becomes invalid, and the associated ZQCODE in the matching register is retrieved as C2 and provided to the IO circuit as ZQCODE1. When the combination of voltage and temperature conditions of the semiconductor device does not match any register in the register array, then DOZQCAL becomes valid, and ZQ calibration will then be performed. In another example embodiment, either the voltage field or the temperature field in each register is searched. In some configurations, separate CAMs may be used for the voltage comparator and the temperature comparator.

[0068] Figure 7 is a flowchart of an example process for performing a ZQ calibration operation according to some examples described in the present invention. In some examples, Figure 7 The example process 700 in FIG. 700 may be implemented in various configurations, for example, Figure 3 The process 700 for performing a ZQ calibration operation may include receiving a ZQ calibration command at operation 706, for example, ZQCAL (at Figure 1 and 3 The ZQCAL command may be generated by a command decoder circuit (e.g., Figure 1 In response to receiving the ZQCAL command, process 700 may compare the temperature signal with a register array (e.g., Figure 3 The temperature signal may indicate the operating temperature of the semiconductor device. The temperature field in the register may contain the temperature condition, such as a temperature value. In some examples, operations 706 to 710 may be implemented in, for example, Figure 3 The temperature comparator 304 in the temperature comparator, and in a similar manner to that in Figure 3 The method is performed in the manner described in the embodiments.

[0069] If the temperature signal matches the temperature condition pre-stored in the register array at operation 710, process 700 may compare the power supply voltage of the semiconductor device with the voltage condition in the register containing the matched temperature condition at operation 712. The voltage condition may contain a voltage code, such as Figure 5AIf, at operation 714, the voltage of the power supply does not match the voltage field in the register, then process 700 may continue with ZQ calibration at operation 720. If, at operation 714, the power supply voltage matches the voltage field of the register, then process 700 may determine to skip the ZQ calibration operation and apply the pre-stored calibration code to the IO circuit instead. When the ZQ calibration operation is skipped, process 700 may deactivate ZQ calibration at operation 715. In a non-limiting example, operation 715 may include providing an invalid DOZQCAL signal to the ZQ calibration circuit (e.g., Figure 1 40) to deactivate the ZQ calibration circuit. Operations 712 to 714 may be implemented, for example, Figure 3 The voltage comparator 302 in the voltage comparator, and in a manner similar to that in Figure 3 The method is performed in the manner described in the embodiments.

[0070] Continue to refer Figure 7 , process 700 may further apply the pre-stored ZQ calibration code in the register to the IO circuit at operation 716. Operation 716 may be similar to that described in various embodiments with reference to Figure 3 For example, operation 716 may be performed via register control circuit 306 (in Figure 3 Operation 716 may further control the switching circuit (e.g., Figure 3 The switching circuit 310 in ) is used to provide the retrieved pre-stored ZQ calibration code to the IO circuit.

[0071] Concurrently with the retrieval of the pre-stored ZQ calibration code, process 700 may further increment a counter associated with the retrieved ZQ calibration code at operation 718. In some examples, the counter is implemented in register array 308 associated with storing the retrieved ZQ calibration code (in Figure 3 The count in the counter indicates the frequency at which the retrieved ZQ calibration code is retrieved. The count in the counter also indicates the frequency at which the corresponding voltage / temperature condition is matched, such as in operations 708 and 712.

[0072] Further references Figure 7 When there is no temperature match at operation 710 or no voltage match at operation 714, process 700 may provide a valid DOZQCAL signal to the ZQ calibration circuit (eg, Figure 1 40 in operation 720). At operation 720, the process may perform ZQ calibration in response to the valid DOZQCAL signal. This is similar to the Figure 3Operation 720 may further provide the ZQ calibration code from the ZQ calibration operation to the IO circuit via the switching circuit. For example, referring to Figure 3 , the switching circuit 310 can be controlled to provide the calibration code ZQCODE from the ZQ calibration circuit to the IO circuit in response to the active DOZQCAL signal.

[0073] In some examples, process 700 may further upload the ZQ calibration code provided by the ZQ calibration circuit to the register array at operation 722. The operation may be similar to that described in various embodiments with reference to Figure 3 For example, the update strategy may be used to select registers to be updated, via register control circuitry (e.g., Figure 3 The contents of the selected registers may also be updated by the voltage / temperature conditions when the ZQ calibration operation is performed (eg, operation 720). Figure 3 In the embodiment in, the counter associated with the updated register may also be reset at operation 724.

[0074] Return to Figure 4A , the ZQ calibration code may be initially stored in register array 400 and based on reference Figures 1 to 7 In some examples, an initial calibration table including multiple voltage / temperature conditions and associated calibration codes may be obtained from back-end testing. The calibration table may be burned into a fuse array of the semiconductor device. When the semiconductor device is powered on, the calibration table in the fuse array may be loaded into a register array such as a CAM (e.g., Figure 3 In a non-limiting example, the initial calibration table may include several voltage / temperature conditions that occur most frequently during back-end testing of semiconductor devices and a ZQ calibration code for each voltage / temperature condition. The size of the calibration table may be any suitable number of registers and associated counters, such as 7, 8, or other number of registers and associated counters.

[0075] In some examples, in the back end test, the test process may set the power supply of the semiconductor VDDQ to a normal high voltage, such as 5 volts. The test process may vary the temperature of the semiconductor device and generate an initial calibration code by performing multiple ZQ calibration operations to swing the pull-up and / or pull-down codes. In some examples, the calibration code may include the pull-up and / or pull-down codes. In a non-limiting example, when generating the pull-down calibration code, the test process may start at a higher temperature, such as 125°C, and reduce the temperature by a certain amount, such as 25°C per run. At each temperature, the maximum swing range may be set to the pull-down code of the previous temperature.

[0076] In some examples, at an initial temperature of 125°C, the test process may increase the pull-down calibration code from 0 all the way to a value when Ron approaches 240 ohms, where Ron = VDDQ / Ion (Ion is the current flowing through resistor RZQ). At the next temperature, for example, 100°C, the pull-down calibration code may be adjusted from the calibration code obtained from the previous test performed at 125°C and reduced until Ron approaches 240 ohms again. The calibration code for the next temperature, for example 75°C, may start from the calibration code obtained from the previous test, and so on and so forth. In this way, because lower temperatures reduce resistance, the calibration code range may become increasingly narrower as the temperature decreases. This will enable faster tuning to obtain the initial calibration code. Given that a process for obtaining an initial calibration table is described, it should be understood that other processes may also be available. Similarly, a similar process may be performed to obtain an initial voltage.

[0077] like Figures 1 to 7 In various embodiments described in the description, it is shown that in response to the ZQCAL command, ZQ calibration does not need to be always performed. Voltage / temperature conditions (indicative of voltage and / or temperature conditions of the semiconductor device) and associated calibration codes for multiple instances of ZQ calibration are pre-stored in a register array. When the voltage / temperature conditions when the previous ZQ calibration was performed occur again, the corresponding pre-stored calibration code is retrieved from the register array and provided to the IO circuit. Therefore, ZQ calibration can be skipped. This reduces power consumption due to the high power required for the ZQ calibration operation and thus improves the performance of the semiconductor device. In addition, the pre-stored calibration code can be immediately retrieved and applied to the IO circuit, so that the impedance of the IO circuit can be accurately adjusted.

[0078] Figure 8 is a diagram showing the states of periodic ZQ calibration according to some examples described in the present invention. Various voltage / temperature conditions are e.g. Figure 1 The example semiconductor device may include a semiconductor device 10 shown in FIG. Figures 1 to 7 A ZQ calibration circuit operates under the control of the ZQ calibration control circuit described in various embodiments of the present invention. In a non-limiting example, during a time period T1, a voltage / temperature (VT) change reaches a threshold TH, and a ZQ calibration is performed. Here, a VT change may refer to a voltage change relative to a reference voltage, a temperature change relative to a reference temperature, or a combination of a voltage change and a temperature change. The threshold TH may refer to a combination of a voltage change threshold and a temperature change threshold. Alternatively, the threshold TH may refer to a voltage change threshold or a temperature change threshold. During the time period T1, a ZQ calibration code is provided by the ZQ calibration circuit and is pre-stored in a register array (e.g., Figure 3 308).

[0079] Further references Figure 8 , during time periods T2, T4, T6, the VT variation is below the threshold TH and the semiconductor device is in normal operation (without ZQ calibration). During time period T3, the VT variation reaches the threshold TH again. However, at this time, the voltage / temperature conditions match the pre-stored voltage / temperature conditions from the previous calibration. Thus, the ZQ calibration is skipped. Subsequently, the pre-stored ZQ calibration code associated with the matched voltage / temperature is retrieved and applied to the IO circuits of the semiconductor device (e.g., Figure 1 17 in). During time period T5, the VT variation is above the threshold, however, it does not match any of the pre-stored voltage / temperature conditions from the previous calibration. A ZQ calibration is then performed, and the register array is updated under the update strategy such that registers in the register array are selected to be updated with the calibration code provided in the ZQ calibration.

[0080] It should be understood from the foregoing that specific embodiments of the present invention have been described herein for illustrative purposes, but various modifications may be made without departing from the spirit and scope of the present invention. For example, the register array may be a CAM or other type of memory. The update strategy for updating the register array may also use other rules, such as first-in-first-out, first-in-last-out or other strategies. Therefore, the scope of the present invention should not limit any of the specific embodiments described herein.

[0081] Certain details are set forth below to provide a full understanding of the examples of various embodiments of the present invention. However, it should be appreciated that the examples described herein may be practiced without these specific details. In addition, the specific examples of the present invention described herein should not be construed as limiting the scope of the present invention to these specific examples. In other examples, well-known circuits, control signals, timing protocols, and software operations are not shown in detail to avoid unnecessarily obscuring the embodiments of the present invention. In addition, terms such as "coupled" mean that two components may be electrically coupled directly or indirectly. Indirect coupling may imply that two components are coupled through one or more intermediate components.

Claims

1. A device comprising: Input / output IO circuit; A ZQ calibration circuit configured to: performing a ZQ calibration to provide a ZQ calibration code in response to an active ZQ calibration control signal; and not performing a ZQ calibration in response to an invalid ZQ calibration control signal; and A ZQ calibration control circuit coupled to the IO circuit and the ZQ calibration circuit and configured to respond to a ZQ calibration signal: providing the invalid ZQ calibration control signal when the voltage / temperature condition matches the voltage / temperature condition stored in the register array; or The valid ZQ calibration control signal is provided when the voltage / temperature condition does not match any voltage / temperature condition stored in the register array.

2. The apparatus of claim 1 , wherein the ZQ calibration control circuit is further configured to, when the voltage / temperature condition matches the voltage / temperature condition in the register array: retrieving a ZQ calibration code associated with the voltage / temperature condition in the register array; and The retrieved ZQ calibration code is provided to the IO circuit.

3. The apparatus of claim 1 , wherein the ZQ calibration control circuit comprises a temperature comparator configured to receive a temperature signal from a temperature sensor and to provide the valid ZQ calibration control signal if a temperature value in the temperature signal does not match any temperature condition in the register array.

4. The apparatus of claim 3 , wherein the ZQ calibration control circuit further comprises a voltage comparator coupled to the temperature comparator, and wherein the temperature comparator is further configured to activate the voltage comparator when the temperature value in the temperature signal matches one or more temperature conditions stored in the register array.

5. The apparatus of claim 4, wherein the voltage comparator comprises: a plurality of amplifiers configured to receive a voltage signal and provide a voltage code of the voltage signal; and a voltage code comparator coupled to the plurality of amplifiers and configured to: providing the valid ZQ calibration control signal if the voltage code of the voltage signal does not match any voltage condition associated with the one or more temperature conditions in the register array; otherwise providing the invalid ZQ calibration control signal; The voltage conditions in the register array are also represented by corresponding voltage codes.

6. The apparatus of claim 5, wherein each of the plurality of amplifiers is coupled to a voltage line to receive the voltage signal and to a reference voltage line to receive a corresponding change in a reference voltage, wherein outputs of the plurality of amplifiers form the voltage code of the voltage signal.

7. The apparatus of claim 5, wherein the ZQ calibration control circuit further comprises a switching circuit coupled to the voltage comparator, the temperature comparator, and the IO circuit and configured to: providing the ZQ calibration code provided by the ZQ calibration circuit to the IO circuit in response to the valid ZQ calibration control signal; and In response to the invalid ZQ calibration control signal, a ZQ calibration code stored in the register array is provided to the IO circuit.

8. The apparatus of claim 1, wherein the register array comprises a plurality of registers that each contain a respective voltage / temperature condition and an associated ZQ calibration code from a previous ZQ calibration.

9. The apparatus of claim 8, wherein the register array further comprises a plurality of counters each associated with a corresponding register of the plurality of registers, wherein: When the voltage / temperature condition matches the voltage / temperature condition in the register array, a counter associated with a register containing the voltage / temperature condition in the register array is configured to increment.

10. The apparatus of claim 9, wherein the ZQ calibration control circuit is further configured to, when the voltage / temperature condition does not match any voltage / temperature condition in the register array: selecting a register in the register array; and The selected register is updated with the ZQ calibration code and the voltage / temperature conditions provided by the ZQ calibration circuit.

11. A method comprising, in response to a ZQ calibration signal: performing a ZQ calibration to provide a ZQ calibration code when a voltage / temperature condition of the semiconductor device does not match any pre-stored voltage / temperature condition in the register array; and When the voltage / temperature condition of the semiconductor device matches the pre-stored voltage / temperature condition in the register array, the ZQ calibration is not performed.

12. The method of claim 11, further comprising when the voltage / temperature condition matches the pre-stored voltage / temperature condition in the register array: retrieving a pre-stored ZQ calibration code associated with the pre-stored voltage / temperature condition in the register array; and The retrieved pre-stored ZQ calibration code is provided to an input / output IO circuit of the semiconductor device.

13. The method of claim 11, further comprising determining that the voltage / temperature condition of the semiconductor device does not match any pre-stored voltage / temperature condition in the register array if a temperature value in a temperature signal from a temperature sensor does not match any pre-stored temperature condition in the register array.

14. The method of claim 13 , further comprising determining that the voltage / temperature condition of the semiconductor device matches the pre-stored voltage / temperature condition in the register array if the temperature value in the temperature signal from the temperature sensor matches one or more pre-stored temperature conditions in the register array and the voltage condition of the semiconductor device also matches the pre-stored voltage condition in the register array, wherein the pre-stored voltage condition is associated with a pre-stored temperature condition in the one or more pre-stored temperature conditions.

15. The method of claim 14, wherein determining that the voltage signal matches the pre-stored voltage condition in the register array comprises: Converting the voltage signal into a voltage code; and A determination is made that a difference between the converted voltage code and the pre-stored voltage condition in the register array is below a zone threshold, wherein the pre-stored voltage condition is represented in a voltage code.

16. An apparatus comprising: Input / output IO circuit; and A ZQ calibration control circuit coupled to the IO circuit and configured to respond to a ZQ calibration signal: When the voltage / temperature condition does not match any of the voltage / temperature conditions in the register array: activating a ZQ calibration circuit to provide a ZQ calibration code to the IO circuit; and When the voltage / temperature condition matches the voltage / temperature condition in the register array: retrieving from the register array a ZQ calibration code associated with the voltage / temperature condition in the register array; and The retrieved ZQ calibration code is provided to the IO circuit.

17. The apparatus of claim 16, wherein the ZQ calibration control circuit comprises: a temperature comparator configured to receive a temperature signal from a temperature sensor; and a voltage comparator configured to receive a voltage signal indicative of a power supply voltage; The temperature comparator and the voltage comparator are configured to: determining that the voltage / temperature condition matches the voltage / temperature condition in the register array if a temperature value in the temperature signal matches a temperature condition in the register array and a voltage value in the voltage signal also matches a voltage condition in the register array associated with the temperature condition in the register array; and If the temperature in the temperature signal and the voltage value in the voltage signal together do not match any voltage / temperature condition in the register array, then it is determined that the voltage / temperature condition does not match any voltage / temperature condition in the register array.

18. The apparatus of claim 17, wherein the ZQ calibration control circuit further comprises a switching circuit coupled to the voltage comparator and the temperature comparator and configured to: supplying the ZQ calibration code provided by the ZQ calibration circuit to the IO circuit when the voltage / temperature condition does not match the voltage / temperature condition in the register array; and When the voltage / temperature condition matches any voltage / temperature condition in the register array, the retrieved ZQ calibration code is provided to the IO circuit.

19. The apparatus of claim 18, further comprising a fuse array containing a plurality of voltage / temperature conditions and associated ZQ calibration codes, wherein the register array is uploaded with the plurality of voltage / temperature conditions and the associated ZQ calibration codes at power up.

20. The apparatus of claim 19, wherein the register array and the temperature comparator comprise at least a portion of a content addressable memory (CAM).

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