Delay compensation method capable of configuring peripheral input and output pins and related product

Abstract

The embodiment of the invention provides a delay compensation method for a configurable peripheral input and output pin and a related product. The method comprises the steps that an input and output delay adjustment circuit detects whether a delay compensation requirement for the configurable peripheral input and output pin exists or not currently; and when the configurable peripheral input / output pin has a delay compensation requirement, the input / output delay adjustment circuit adjusts the delay of the configurable peripheral input / output pin. According to the embodiment of the invention, the delay of the input and output pins of the configurable peripheral can be adjusted through the input and output delay adjusting circuit, so that the flexibility of wiring design of a user circuit board can be ensured, and the reliability of data communication with the high-speed peripheral can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of pin delay compensation, and in particular to a delay compensation method for configurable peripheral input and output pins and related products; wherein the related products include a delay compensation device for configurable peripheral input and output pins, an electronic device and a computer-readable storage medium. Background Art

[0002] The peripheral modules of microcontroller chips can traditionally be connected to one or more fixed chip pins through pin multiplexing circuits. In order to improve flexibility and facilitate user use, a new design has emerged that allows users to relocate the pins of peripherals to any GPIO (General-Purpose Input / Output) chip pins. However, this design that allows the arbitrarily configured peripheral input and output pins has an adverse effect on the normal communication of high-speed peripherals.

[0003] On the user circuit board, although the convenience of peripheral routing is improved, the routing differences of each pin of the peripheral may increase, and the delay differences of the pin signals will also increase, causing errors in the microcontroller chip or peripheral when latching input and output data. Summary of the invention

[0004] In view of the above problems, a method for delay compensation of configurable peripheral input / output pins, a device for delay compensation of configurable peripheral input / output pins, an electronic device and a computer-readable storage medium are proposed to overcome the above problems or at least partially solve the above problems, including:

[0005] A delay compensation method for a configurable peripheral input / output pin is applied to a microcontroller chip, wherein the microcontroller chip is provided with a configurable peripheral input / output pin and an input / output delay adjustment circuit, and the configurable peripheral input / output pin is connected to a peripheral chip; the method comprises:

[0006] The input / output delay adjustment circuit detects whether there is a delay compensation requirement for the configurable peripheral input / output pins;

[0007] When there is a delay compensation requirement for the configurable peripheral input / output pin, the input / output delay adjustment circuit adjusts the delay of the configurable peripheral input / output pin.

[0008] Optionally, the detecting whether there is currently a delay compensation requirement for the configurable peripheral input / output pin includes:

[0009] detecting whether an input / output pin delay adjustment command for the configurable peripheral input / output pin is input;

[0010] When an input / output pin delay adjustment command for the configurable peripheral input / output pin is received, it is determined that there is currently a delay compensation requirement for the configurable peripheral input / output pin.

[0011] Optionally, the configurable peripheral input / output pins include a plurality of pins, and the step of adjusting the delay of the configurable peripheral input / output pins includes:

[0012] According to the input / output pin delay adjustment command, determining the input / output pin to be adjusted from a plurality of configurable peripheral input / output pins; and a first adjustment step size;

[0013] According to the first adjustment step size, delay compensation is performed on the input and output pins to be adjusted.

[0014] Optionally, the input pin and the output pin of the peripheral chip are connected to the configurable peripheral input and output pins, and the input pin and the output pin of the peripheral chip are connected to an oscilloscope;

[0015] The oscilloscope is used to display the input and output waveforms of the peripheral chip.

[0016] Optionally, the method further comprises:

[0017] Determining a first delay adjustment value currently for the configurable peripheral input / output pin;

[0018] When a save command for the configurable peripheral input / output pin is received, the first delay adjustment value is saved in a preset non-volatile memory.

[0019] Optionally, the detecting whether there is currently a delay compensation requirement for the configurable peripheral input / output pin includes:

[0020] Detect whether the clock rising edge and signal transition edge of the latched data are within the preset latch window;

[0021] When the rising edge of the clock of the latched data and the signal transition edge are not within the preset latch window, it is determined that there is a delay compensation requirement for the configurable peripheral input / output pin.

[0022] Optionally, adjusting the delay of the configurable peripheral input / output pin includes:

[0023] In a preset clock cycle, the clock delay or data delay of the configurable peripheral input / output pin is adjusted according to a second adjustment step size.

[0024] Optionally, adjusting the delay of the configurable peripheral input / output pin includes:

[0025] Determine the target timing window;

[0026] Using the delay intermediate value of the target timing window as a second delay adjustment value;

[0027] The delay of the configurable peripheral input / output pin is adjusted according to the second delay adjustment value.

[0028] Optionally, the configurable peripheral input and output pins include a plurality of pins, and the method further includes:

[0029] determining a second delay adjustment value for each configurable peripheral input / output pin;

[0030] The second delay adjustment value is stored in a preset non-volatile memory.

[0031] The embodiment of the present invention further provides a delay compensation device for a configurable peripheral input / output pin, which is applied to a microcontroller chip. The microcontroller chip is provided with a configurable peripheral input / output pin and an input / output delay adjustment circuit, and the configurable peripheral input / output pin is connected to a peripheral chip; the device comprises:

[0032] A detection module, used for the input / output delay adjustment circuit to detect whether there is a delay compensation requirement for the configurable peripheral input / output pins;

[0033] The adjustment module is used for adjusting the delay of the configurable peripheral input / output pin by the input / output delay adjustment circuit when there is a delay compensation requirement for the configurable peripheral input / output pin.

[0034] Optionally, the detection module is used to detect whether an input / output pin delay adjustment command for the configurable peripheral input / output pin is input; when the input / output pin delay adjustment command for the configurable peripheral input / output pin is received, it is determined that there is currently a delay compensation requirement for the configurable peripheral input / output pin.

[0035] Optionally, the configurable peripheral input / output pins include multiple ones, and the adjustment module is used to determine the input / output pin to be adjusted from the multiple configurable peripheral input / output pins according to the input / output pin delay adjustment command; and a first adjustment step size; and according to the first adjustment step size, perform delay compensation on the input / output pin to be adjusted.

[0036] Optionally, the input pins and output pins of the peripheral chip are connected to the configurable peripheral input and output pins, and the input pins and output pins of the peripheral chip are connected to an oscilloscope; the oscilloscope is used to display the input and output waveforms of the peripheral chip.

[0037] Optionally, the device further comprises:

[0038] The first saving module is used to determine a first delay adjustment value for the configurable peripheral input / output pin; when receiving a save command for the configurable peripheral input / output pin, the first delay adjustment value is saved in a preset non-volatile memory.

[0039] Optionally, the detection module is used to detect whether the clock rising edge and signal transition edge of the latched data are within a preset latch window; when the clock rising edge and signal transition edge of the latched data are not within the preset latch window, it is determined that there is currently a delay compensation requirement for the configurable peripheral input and output pins.

[0040] Optionally, the adjustment module is used to adjust the clock delay or data delay of the configurable peripheral input / output pin according to a second adjustment step size within a preset clock cycle.

[0041] Optionally, the adjustment module is used to determine a target timing window; use a delay intermediate value of the target timing window as a second delay adjustment value; and adjust the delay of the configurable peripheral input and output pins according to the second delay adjustment value.

[0042] Optionally, the configurable peripheral input and output pins include a plurality of pins, and the device further includes:

[0043] The second storage module is used to determine the second delay adjustment value of each configurable peripheral input and output pin; and save the second delay adjustment value in a preset non-volatile memory.

[0044] An embodiment of the present invention also provides an electronic device, including a processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein when the computer program is executed by the processor, the delay compensation method for configurable peripheral input and output pins as described above is implemented.

[0045] An embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the delay compensation method for configurable peripheral input and output pins is implemented as described above.

[0046] The embodiments of the present invention have the following advantages:

[0047] In the embodiment of the present invention, the input-output delay adjustment circuit detects whether there is a delay compensation requirement for the configurable peripheral input-output pin; when there is a delay compensation requirement for the configurable peripheral input-output pin, the input-output delay adjustment circuit adjusts the delay of the configurable peripheral input-output pin. Through the embodiment of the present invention, the delay of the configurable peripheral input-output pin can be adjusted by the input-output delay adjustment circuit, thereby ensuring the flexibility of the user's circuit board routing design and improving the reliability of data communication with high-speed peripherals. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solution of the present invention, the accompanying drawings required for use in the description of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0049] Figure 1a It is a flowchart of the steps of a delay compensation method for configurable peripheral input and output pins according to an embodiment of the present invention;

[0050] Figure 1b is a schematic diagram of a scenario in an embodiment of the present invention;

[0051] Figure 2 It is a flowchart of the steps of another method for delay compensation of configurable peripheral input and output pins according to an embodiment of the present invention;

[0052] Figure 3a It is a flowchart of the steps of another method for delay compensation of configurable peripheral input and output pins according to an embodiment of the present invention;

[0053] Figure 3b is another scenario schematic diagram of an embodiment of the present invention;

[0054] Figure 4 is a flowchart of the steps of another method for delay compensation of configurable peripheral input and output pins according to an embodiment of the present invention;

[0055] Figure 5 It is a flowchart of the steps of another method for delay compensation of configurable peripheral input and output pins according to an embodiment of the present invention;

[0056] Figure 6 is a flowchart of manual adjustment steps in an embodiment of the present invention;

[0057] Figure 7 is a flowchart of an automatic adjustment step of an embodiment of the present invention;

[0058] Figure 8is another flow chart of manual adjustment steps according to an embodiment of the present invention;

[0059] Fig. 9 The present invention is a block diagram of a delay compensation device capable of configurable peripheral input and output pins. DETAILED DESCRIPTION

[0060] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0061] On the user circuit board, although the convenience of peripheral routing is improved, the design of arbitrarily configurable peripheral input and output pins increases the delay difference of input and output signals, causing latch timing errors of high-speed peripheral input and output data. In view of this, it is necessary to perform delay compensation on the configurable peripheral input and output pins according to the differences in user circuit boards to ensure the reliability of bidirectional communication between high-speed peripherals and microcontroller chips.

[0062] Specifically, an embodiment of the present invention provides a delay compensation method for a configurable peripheral input and output pin, which adjusts the delay of the configurable peripheral input and output pin through an input and output delay adjustment circuit, thereby ensuring the flexibility of the user's circuit board routing design and improving the reliability of data communication with high-speed peripherals.

[0063] Reference Figure 1a , shows a flowchart of the steps of a delay compensation method for configurable peripheral input and output pins according to an embodiment of the present invention.

[0064] like Figure 1a As shown, the delay compensation method of the configurable peripheral input and output pins may include the following steps:

[0065] Step 101: The input / output delay adjustment circuit detects whether there is a delay compensation requirement for a configurable peripheral input / output pin.

[0066] In the embodiment of the present invention, Figure 1b As shown, the application PCB (Printed Circuit Board) includes a microcontroller chip and a peripheral chip; wherein the microcontroller chip may include configurable peripheral input and output pins (such as Figure 2As shown, the configurable peripheral input and output pins include pin 1, pin 2, pin 3, pin 4, pin 5, pin 6, pin 7, pin 8, pin 9 and pin 10), an IO configuration circuit and a peripheral controller; the IO configuration circuit connects the signal line of the peripheral controller to the configurable peripheral input and output pins through the IO configuration circuit, such as connecting to pin 1 and pin 9.

[0067] Among them, the configurable peripheral input and output pins can be used to connect peripheral chips, and the serial input pin 11 can be used to receive instructions.

[0068] In some feasible embodiments, the microcontroller chip may also be provided with an input / output delay adjustment circuit, which may be used to adjust the delay of configurable peripheral input / output pins, thereby improving the reliability of data communication between the microcontroller chip and high-speed peripherals.

[0069] Specifically, the input / output delay adjustment circuit may first detect whether there is a delay compensation requirement for the configurable peripheral input / output pins; illustratively, the delay compensation requirement may refer to a situation where the configurable peripheral input / output pins have a large clock delay or data delay.

[0070] When no delay compensation requirement for the configurable peripheral input / output pin is detected, it may continue to be detected whether there is a delay compensation requirement for the configurable peripheral input / output pin.

[0071] Step 102: When there is a delay compensation requirement for the configurable peripheral input / output pin, the input / output delay adjustment circuit adjusts the delay of the configurable peripheral input / output pin.

[0072] In an embodiment of the present invention, when it is detected that there is a delay compensation requirement for a configurable peripheral input / output pin, the input / output delay adjustment circuit can perform delay compensation on the configurable peripheral input / output pin to improve the reliability of data communication with high-speed peripherals.

[0073] In the embodiment of the present invention, the input-output delay adjustment circuit detects whether there is a delay compensation requirement for the configurable peripheral input-output pin; when there is a delay compensation requirement for the configurable peripheral input-output pin, the input-output delay adjustment circuit adjusts the delay of the configurable peripheral input-output pin. Through the embodiment of the present invention, the delay of the configurable peripheral input-output pin can be adjusted by the input-output delay adjustment circuit, thereby ensuring the flexibility of the user's circuit board routing design and improving the reliability of data communication with high-speed peripherals.

[0074] Reference Figure 2, shows a flowchart of another method for delay compensation of configurable peripheral input and output pins according to an embodiment of the present invention, which may include the following steps:

[0075] Step 201: The input / output delay adjustment circuit detects whether an input / output pin delay adjustment command for a configurable peripheral input / output pin is input.

[0076] In some feasible embodiments, when the user needs to adjust the delay of the configurable peripheral input / output pin, he can input an input / output pin delay adjustment command for the configurable peripheral input / output pin to the input / output delay adjustment circuit through a specific serial input pin.

[0077] The input / output pin delay adjustment command may be a command generated by a user on a host computer and input to the input / output delay adjustment circuit for adjusting the delay of a configurable peripheral input / output pin.

[0078] The input / output delay adjustment circuit can detect whether an input / output pin delay adjustment command for a configurable peripheral input / output pin is currently input.

[0079] In actual applications, if no input / output pin delay adjustment command input to the configurable peripheral input / output pin is detected, it can be determined that there is currently no delay compensation requirement for the configurable peripheral input / output pin.

[0080] Step 202: When an input / output pin delay adjustment command for a configurable peripheral input / output pin is received, it is determined that there is currently a delay compensation requirement for the configurable peripheral input / output pin.

[0081] In some feasible embodiments, when the input / output delay adjustment circuit receives the input / output pin delay adjustment command for the configurable peripheral input / output pin, it can determine that there is currently a delay compensation requirement for the configurable peripheral input / output pin. At this time, step 203 can be continued to meet the delay compensation requirement of the configurable peripheral input / output pin.

[0082] Step 203: There are multiple configurable peripheral input / output pins. When there is a delay compensation requirement for the configurable peripheral input / output pins, the input / output delay adjustment circuit determines the input / output pin to be adjusted from the multiple configurable peripheral input / output pins according to the input / output pin delay adjustment command; and a first adjustment step size.

[0083] In some feasible embodiments, the configurable peripheral input and output pins may include multiple ones, for example: pin 1, pin 2, pin 3, pin 4, pin 5, pin 6, pin 7, pin 8, pin 9 and pin 10.

[0084] In actual applications, the user can generate a corresponding input / output pin delay adjustment command for a specific configurable peripheral input / output pin, and adjust the first adjustment step size of the configurable peripheral input / output pin.

[0085] Exemplarily, the first adjustment step size can be an increased delay compensation size or a decreased delay compensation size; it can be identified by characters; for example: A, B, and C are used to represent the three increased delay step sizes of the output pin, and X, Y, and Z are used to represent the three decreased delay step sizes of the output pin. The embodiments of the present invention do not impose any restrictions on this.

[0086] After receiving the input / output pin delay adjustment command, the input / output delay adjustment circuit may first analyze the input / output pin delay adjustment command to determine the input / output pin to be adjusted whose delay is to be adjusted from a plurality of configurable peripheral input / output pins.

[0087] In addition, the input and output pin delay adjustment command may be analyzed to obtain the first adjustment step size.

[0088] Step 204: Perform delay compensation on the input and output pins to be adjusted according to the first adjustment step size.

[0089] After determining the first adjustment step size and the input / output pin to be adjusted, the input / output delay adjustment circuit may perform delay compensation on the input / output pin to be adjusted according to the first adjustment step size.

[0090] In an embodiment of the present invention, an input / output delay adjustment circuit detects whether an input / output pin delay adjustment command for a configurable peripheral input / output pin is input; when an input / output pin delay adjustment command for a configurable peripheral input / output pin is received, it is determined that there is currently a delay compensation requirement for the configurable peripheral input / output pin; the configurable peripheral input / output pin includes multiple, and when there is a delay compensation requirement for the configurable peripheral input / output pin, the input / output delay adjustment circuit determines the input / output pin to be adjusted from the multiple configurable peripheral input / output pins according to the input / output pin delay adjustment command; and a first adjustment step size; according to the first adjustment step size, the input / output pin to be adjusted is delayed compensated. Through the embodiment of the present invention, the delay of the configurable peripheral input / output pin can be adjusted by the input / output delay adjustment circuit, thereby ensuring the flexibility of the user's circuit board routing design and improving the reliability of data communication with high-speed peripherals.

[0091] Reference Figure 3a , shows a flowchart of another method for delay compensation of configurable peripheral input and output pins according to an embodiment of the present invention, which may include the following steps:

[0092] Step 301: An input / output delay adjustment circuit detects whether an input / output pin delay adjustment command for a configurable peripheral input / output pin is input.

[0093] When the user needs to adjust the delay of the configurable peripheral input / output pin, the user can input an input / output pin delay adjustment command for the configurable peripheral input / output pin to the input / output delay adjustment circuit through a specific serial input pin.

[0094] If no input / output pin delay adjustment command input to the configurable peripheral input / output pin is detected, it can be determined that there is currently no delay compensation requirement for the configurable peripheral input / output pin.

[0095] Step 302: When an input / output pin delay adjustment command for a configurable peripheral input / output pin is received, it is determined that there is currently a delay compensation requirement for the configurable peripheral input / output pin.

[0096] When the input / output delay adjustment circuit receives the input / output pin delay adjustment command for the configurable peripheral input / output pin, it can determine that there is a delay compensation requirement for the configurable peripheral input / output pin. At this time, step 303 can be continued to meet the delay compensation requirement for the configurable peripheral input / output pin.

[0097] Step 303: When there is a delay compensation requirement for the configurable peripheral input / output pin, the input / output delay adjustment circuit determines the input / output pin to be adjusted from the plurality of configurable peripheral input / output pins according to the input / output pin delay adjustment command; and the first adjustment step size.

[0098] In actual applications, the user can generate a corresponding input / output pin delay adjustment command for a specific configurable peripheral input / output pin, and adjust the first adjustment step size of the configurable peripheral input / output pin.

[0099] After receiving the input / output pin delay adjustment command, the input / output delay adjustment circuit may first analyze the input / output pin delay adjustment command to determine the input / output pin to be adjusted whose delay is to be adjusted from a plurality of configurable peripheral input / output pins.

[0100] In addition, the input and output pin delay adjustment command may be analyzed to obtain the first adjustment step size.

[0101] Step 304: Perform delay compensation on the input and output pins to be adjusted according to the first adjustment step size.

[0102] After determining the first adjustment step size and the input / output pin to be adjusted, the input / output delay adjustment circuit may perform delay compensation on the input / output pin to be adjusted according to the first adjustment step size.

[0103] Step 305: Determine a first delay adjustment value currently for the configurable peripheral input / output pin.

[0104] In some feasible embodiments, after completing the delay compensation adjustment of the configurable peripheral input / output pin, the first delay adjustment value for the configurable peripheral input / output pin can be determined; the first delay adjustment value can refer to the total value of the delay adjustment during the entire delay compensation adjustment process.

[0105] Step 306: When a save command for the configurable peripheral input / output pin is received, the first delay adjustment value is saved in a preset non-volatile memory.

[0106] In actual applications, after completing all configurable peripheral input and output pins, the user can input a save command to the input and output delay adjustment circuit.

[0107] When receiving a save command for a configurable peripheral input / output pin, the input / output delay adjustment circuit can save the first delay adjustment value corresponding to each configurable peripheral input / output pin into a preset non-volatile memory.

[0108] When the power is turned on next time, the first delay adjustment value may be obtained from the non-volatile memory for use, which is not limited in the embodiment of the present invention.

[0109] In one embodiment of the present invention, the input pins and output pins of the peripheral chip are connected to the configurable peripheral input and output pins, and the input pins and output pins of the peripheral chip are connected to an oscilloscope; the oscilloscope is used to display the input and output waveforms of the peripheral chip.

[0110] In some feasible embodiments, the input pins and output pins of the peripheral chip are connected to the configurable peripheral input and output pins, and the input pins and output pins of the peripheral chip are connected to an oscilloscope. Before inputting the input and output pin delay adjustment command, the user can first observe the oscilloscope, so as to judge whether to input the input and output pin delay adjustment command for the configurable peripheral input and output pin based on the input and output waveforms of the peripheral chip displayed on the oscilloscope.

[0111] like Figure 3b As shown, the application PCB (Printed Circuit Board) includes a microcontroller chip and a peripheral chip; wherein the microcontroller chip may include configurable peripheral input and output pins (such as Figure 2As shown, the configurable peripheral input and output pins include pin 1, pin 2, pin 3, pin 4, pin 5, pin 6, pin 7, pin 8, pin 9 and pin 10); the IO configuration circuit connects the signal line of the peripheral controller to the configurable peripheral input and output pins through the IO configuration circuit, such as connecting to pin 1 and pin 9.

[0112] Among them, the configurable peripheral input and output pins can be used to connect the peripheral chip, and the serial input pin 11 is connected to the host computer and can be used to receive instructions.

[0113] The input pins and output pins of the peripheral chip are connected to the configurable peripheral input and output pins, and the input pins and output pins of the peripheral chip are connected to an oscilloscope.

[0114] In an embodiment of the present invention, an input / output delay adjustment circuit detects whether an input / output pin delay adjustment command for a configurable peripheral input / output pin is input; when an input / output pin delay adjustment command for a configurable peripheral input / output pin is received, it is determined that there is currently a delay compensation requirement for the configurable peripheral input / output pin; when there is a delay compensation requirement for the configurable peripheral input / output pin, the input / output delay adjustment circuit determines the input / output pin to be adjusted from a plurality of configurable peripheral input / output pins according to the input / output pin delay adjustment command; and a first adjustment step size; according to the first adjustment step size, delay compensation is performed on the input / output pin to be adjusted; the first delay adjustment value for the configurable peripheral input / output pin is determined; when a save command for the configurable peripheral input / output pin is received, the first delay adjustment value is saved in a preset non-volatile memory. Through the embodiment of the present invention, the delay of the configurable peripheral input / output pin can be adjusted by the input / output delay adjustment circuit, thereby ensuring the flexibility of the user's circuit board routing design and improving the reliability of data communication with high-speed peripherals.

[0115] Reference Figure 4 , shows a flowchart of the steps of another method for delay compensation of configurable peripheral input and output pins according to an embodiment of the present invention, which may include the following steps:

[0116] Step 401: The input / output delay adjustment circuit detects whether the clock rising edge and the signal transition edge of the latched data are within a preset latch window.

[0117] In some feasible embodiments, the input / output delay adjustment circuit can detect whether the clock rising edge and the signal transition edge of the latched data are within a preset latch window.

[0118] The latch window refers to a period of time before and after the rising edge of the clock, during which the input data must remain stable. Specifically:

[0119] Setup Time: The minimum time that the input data must remain stable before the rising edge of the clock.

[0120] Hold Time: The minimum time that the input data must remain stable after the rising edge of the clock.

[0121] If the time relationship between the signal transition edge and the clock rising edge meets the requirements of setup time and hold time, the signal is considered to be within the latch window; otherwise, the signal is considered to be not within the latch window.

[0122] Signal refers to the input data signal (i.e. the input signal of the latch). Signal transition edge refers to the moment when the input data signal changes (for example, from 0 to 1, or from 1 to 0), while clock rising edge refers to the moment when the latch clock signal changes from low level to high level.

[0123] Input data refers to the signal received by the input terminal of the latch, usually marked as D (Data). Input data is the external data captured by the latch when the clock signal triggers.

[0124] Latched data refers to the input data that the latch captures and stores when the clock signal triggers.

[0125] Step 402: When the rising edge of the clock and the signal transition edge of the latched data are not within the preset latch window, it is determined that there is a delay compensation requirement for the configurable peripheral input / output pin.

[0126] In some feasible embodiments, if the clock rising edge and signal transition edge of the latched data are within the preset latch window, the input-output delay adjustment circuit can continue to detect whether the clock rising edge and signal transition edge of the latched data are within the preset latch window.

[0127] On the contrary, if the input / output delay adjustment circuit detects that the clock rising edge and the signal transition edge of the latched data are not within the preset latch window, it can be determined that there is a delay compensation requirement for the configurable peripheral input / output pins.

[0128] Step 403: When there is a delay compensation requirement for the configurable peripheral input / output pin, the input / output delay adjustment circuit adjusts the clock delay or data delay of the configurable peripheral input / output pin according to the second adjustment step size within a preset clock cycle.

[0129] When it is determined that there is a delay compensation requirement for the configurable peripheral input / output pin, the input / output delay adjustment circuit can adjust the clock delay or data delay of the configurable peripheral input / output pin according to the second adjustment step size within a preset clock cycle.

[0130] Exemplarily, if the delay of the latch clock signal is large, the data delay of the data input signal is increased; if the delay of the data input signal is large, the clock delay of the latch clock signal is increased, and the embodiment of the present invention is not limited to this.

[0131] In an embodiment of the present invention, an input / output delay adjustment circuit detects whether the rising edge of the clock and the signal transition edge of the latched data are within a preset latch window; when the rising edge of the clock and the signal transition edge of the latched data are not within the preset latch window, it is determined that there is currently a delay compensation requirement for the configurable peripheral input / output pin; when there is a delay compensation requirement for the configurable peripheral input / output pin, the input / output delay adjustment circuit adjusts the clock delay or data delay of the configurable peripheral input / output pin according to the second adjustment step size within the preset clock cycle. Through the embodiment of the present invention, the delay of the configurable peripheral input / output pin can be adjusted by the input / output delay adjustment circuit, thereby ensuring the flexibility of the user's circuit board routing design and improving the reliability of data communication with high-speed peripherals.

[0132] Reference Figure 5 , shows a flowchart of the steps of another method for delay compensation of configurable peripheral input and output pins according to an embodiment of the present invention, which may include the following steps:

[0133] Step 501: The input / output delay adjustment circuit detects whether the clock rising edge and the signal transition edge of the latched data are within a preset latch window.

[0134] In some feasible embodiments, the input / output delay adjustment circuit can detect whether the clock rising edge and the signal transition edge of the latched data are within a preset latch window.

[0135] Step 502: When the rising edge of the clock and the signal transition edge of the latched data are not within the preset latch window, it is determined that there is a delay compensation requirement for the configurable peripheral input / output pin.

[0136] In some feasible embodiments, if the clock rising edge and signal transition edge of the latched data are within the preset latch window, the input-output delay adjustment circuit can continue to detect whether the clock rising edge and signal transition edge of the latched data are within the preset latch window.

[0137] On the contrary, if the input / output delay adjustment circuit detects that the clock rising edge and the signal transition edge of the latched data are not within the preset latch window, it can be determined that there is a delay compensation requirement for the configurable peripheral input / output pins.

[0138] Step 503: When there is a delay compensation requirement for the configurable peripheral input / output pins, the input / output delay adjustment circuit determines a target timing window.

[0139] When it is determined that there is a delay compensation requirement for the configurable peripheral input / output pins, the input / output delay adjustment circuit may first determine a target timing window.

[0140] Exemplarily, if the delay is large and the input data is a known special sequence, such as 'H55aa', the input-output delay adjustment circuit may first determine a target timing window that can correctly latch the special data sequence.

[0141] Step 504: Use the delay median value of the target timing window as the second delay adjustment value.

[0142] Then, the input-output delay adjustment circuit can take the delay middle value of the target timing window as the second delay adjustment value.

[0143] Step 505: Adjust the delay of the configurable peripheral input and output pins according to the second delay adjustment value.

[0144] After determining the second delay adjustment value, the input / output delay adjustment circuit may adjust the delay of the configurable peripheral input / output pin according to the second delay adjustment value.

[0145] In an embodiment of the present invention, the configurable peripheral input and output pins include multiple ones, and the above method may further include the following steps:

[0146] Determine the second delay adjustment value of each configurable peripheral input and output pin; and save the second delay adjustment value in a preset non-volatile memory.

[0147] In some feasible embodiments, the configurable peripheral input / output pins may include multiple ones; after determining the second delay adjustment value of each configurable peripheral input / output pin, the second delay adjustment value may be saved in a preset non-volatile memory.

[0148] Exemplarily, if the delays of all configurable peripheral input / output pins are adjusted, the maximum clock delay value plus the first-level latch delay can be taken as the delay value of the second-level latch circuit of all configurable peripheral input / output pins of the peripheral chip, i.e., the second delay adjustment value.

[0149] If there is no secondary latch, the maximum value of the clock delay is used as the final delay adjustment value of the latch clock; the sum of the delay adjustment values ​​of all configurable peripheral input and output pins and the clock delay adjustment value is taken as the final delay adjustment value of all configurable peripheral input and output pins, that is, the second delay adjustment value.

[0150] In an embodiment of the present invention, an input-output delay adjustment circuit detects whether the rising edge of the clock and the signal transition edge of the latched data are within a preset latch window; when the rising edge of the clock and the signal transition edge of the latched data are not within the preset latch window, it is determined that there is currently a delay compensation requirement for the configurable peripheral input-output pin; when there is a delay compensation requirement for the configurable peripheral input-output pin, the input-output delay adjustment circuit determines the target timing window; the delay intermediate value of the target timing window is used as the second delay adjustment value; according to the second delay adjustment value, the delay of the configurable peripheral input-output pin is adjusted. Through the embodiment of the present invention, the delay of the configurable peripheral input-output pin can be adjusted by the input-output delay adjustment circuit, thereby ensuring the flexibility of the user's circuit board routing design and improving the reliability of data communication with high-speed peripherals.

[0151] For example, Figure 6 As shown, the user can first use an oscilloscope to observe the waveforms of the configurable peripheral input and output pins of the microcontroller chip;

[0152] If a need for delay compensation is observed, the user can manually send an I / O pin delay adjustment command through a specific serial input pin, specifying the configurable peripheral I / O pin that needs to be adjusted;

[0153] The user sends an input / output pin delay adjustment command including a delay adjustment character (i.e., a first adjustment step length) through the serial input pin, and the input / output delay adjustment circuit of the configurable peripheral input / output pin increases or decreases the delay of the configurable peripheral input / output pin by a specific step length after receiving the character, for example, A, B, and C are used to represent the three delay step lengths increased by the configurable peripheral input / output pin, and X, Y, and Z are used to represent the three delay step lengths decreased by the configurable peripheral input / output pin;

[0154] The user uses an oscilloscope to observe the adjusted delays of the configurable peripheral input and output pins. If the delays of the configurable peripheral input and output pins are not consistent, continue to adjust the delays of the configurable peripheral input and output pins.

[0155] The user manually sends a save command through a specific serial input pin to store the delay adjustment values ​​of all configurable peripheral input and output pins as the final first delay adjustment value in the non-volatile memory.

[0156] like Figure 7 As shown, the input-output delay adjustment circuit adjusts the clock delay or data delay in a certain step size within 0.5 clock cycles. If the delay of the latch clock signal is large, the data delay of the data input signal is increased; if the delay of the data input signal is large, the clock delay of the latch clock signal is increased;

[0157] Continuously measure the window width between the signal transition edge and the clock rising edge of a configurable peripheral input and output pin;

[0158] If the rising edge of the clock of the latched data and all the signal transition edges of a configurable peripheral input and output pin are not within the correct latch window, if the delay of the latched clock signal is large, then the data delay of the data input signal is increased; if the delay of the data input signal is large, then the clock delay of the latched clock signal is increased;

[0159] If the delay is large and the input data is a known special sequence, such as 'H55aa; the input-output delay adjustment circuit detects the target timing window that can correctly latch the special data sequence, and takes the delay middle value of the target timing window as the second delay adjustment value for latching the input data.

[0160] Record the clock delay or data delay of the configurable peripheral input / output pin. If the delay adjustment of all configurable peripheral input / output pins is completed, take the maximum clock delay value plus the first-level latch delay as the delay value of the second-level latch circuit of all configurable peripheral input / output pins of the peripheral chip; if there is no second-level latch, take the maximum value of the clock delay as the final delay adjustment value of the latch clock; take the sum of the delay adjustment values ​​of all configurable peripheral input / output pins and the clock delay adjustment value as the final delay adjustment value of all configurable peripheral input / output pins, that is, the second delay adjustment value.

[0161] The data or clock delay adjustment values ​​of all configurable peripheral input and output pins, including the secondary latch circuit delay value, are saved in the non-volatile memory as the second delay adjustment value, wherein a positive number represents a data delay adjustment value and a negative number represents a latch clock delay adjustment value.

[0162] like Figure 8 As shown, the user can manually specify the input pin that needs to be adjusted through a specific serial input pin;

[0163] The configurable peripheral input and output pins forward the internal clock and data signals to special chip high-speed output pins. Users use an oscilloscope to observe the clock and data delay differences in the configurable peripheral input and output pins.

[0164] The user sends an input / output pin delay adjustment command including a delay adjustment character (i.e., a first adjustment step length) through a serial input pin. After receiving the character, the input / output delay adjustment circuit of the configurable peripheral input / output pin increases or decreases the data delay or clock delay of the configurable peripheral input / output pin by a specific step length. For example, A, B, and C are used to represent the three delay step lengths increased by the configurable peripheral input / output pin, X, Y, and Z are used to represent the three delay step lengths decreased by the configurable peripheral input / output pin, E, F, and G are used to represent the three delay step lengths increased by the latch clock of the configurable peripheral input / output pin, and P, M, and N are used to represent the three delay step lengths decreased by the latch clock of the configurable peripheral input / output pin;

[0165] The user uses an oscilloscope to observe the differences in clock and data delays in each configurable peripheral input and output pin that have been adjusted. If they are not in the correct latch window, continue to adjust the data delay or clock delay of the configurable peripheral input and output pin;

[0166] The user manually sends a save command through a specific serial input pin to save the data or clock delay adjustment values ​​of all configurable peripheral input and output pins as the first delay adjustment value to the non-volatile memory, where positive numbers represent data delay adjustment values, negative numbers represent latch clock delay adjustment values, and the maximum delay value is used as the delay value of the secondary latch circuit.

[0167] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0168] Reference Fig. 9 , showing a schematic structural diagram of a delay compensation device for a configurable peripheral input / output pin according to an embodiment of the present invention, which is applied to a microcontroller chip, wherein the microcontroller chip is provided with a configurable peripheral input / output pin and an input / output delay adjustment circuit, and the configurable peripheral input / output pin is connected to a peripheral chip.

[0169] like Fig. 9 As shown, the delay compensation device for configurable peripheral input and output pins may include the following modules:

[0170] A detection module 901, used for the input and output delay adjustment circuit to detect whether there is a delay compensation requirement for the configurable peripheral input and output pins;

[0171] The adjustment module 902 is used for adjusting the delay of the configurable peripheral input / output pin by the input / output delay adjustment circuit when there is a delay compensation requirement for the configurable peripheral input / output pin.

[0172] In an optional embodiment of the present invention, the detection module 901 is used to detect whether an input / output pin delay adjustment command for a configurable peripheral input / output pin is input; when an input / output pin delay adjustment command for a configurable peripheral input / output pin is received, it is determined that there is currently a delay compensation requirement for the configurable peripheral input / output pin.

[0173] In an optional embodiment of the present invention, the configurable peripheral input and output pins include multiple, adjustment module 902, used to determine the input and output pins to be adjusted from multiple configurable peripheral input and output pins according to the input and output pin delay adjustment command; and a first adjustment step size; according to the first adjustment step size, delay compensation is performed on the input and output pins to be adjusted.

[0174] In an optional embodiment of the present invention, the input pins and output pins of the peripheral chip are connected to the configurable peripheral input and output pins, and the input pins and output pins of the peripheral chip are connected to an oscilloscope; the oscilloscope is used to display the input and output waveforms of the peripheral chip.

[0175] In an optional embodiment of the present invention, the device further comprises:

[0176] The first saving module is used to determine the first delay adjustment value for the configurable peripheral input and output pins; when receiving a saving command for the configurable peripheral input and output pins, the first delay adjustment value is saved in a preset non-volatile memory.

[0177] In an optional embodiment of the present invention, the detection module 901 is used to detect whether the clock rising edge and the signal transition edge of the latched data are within the preset latch window; when the clock rising edge and the signal transition edge of the latched data are not within the preset latch window, it is determined that there is currently a delay compensation requirement for the configurable peripheral input and output pins.

[0178] In an optional embodiment of the present invention, the adjustment module 902 is used to adjust the clock delay or data delay of the configurable peripheral input / output pin according to the second adjustment step size within a preset clock cycle.

[0179] In an optional embodiment of the present invention, the adjustment module 902 is used to determine a target timing window; use a delay intermediate value of the target timing window as a second delay adjustment value; and adjust the delay of a configurable peripheral input and output pin according to the second delay adjustment value.

[0180] In an optional embodiment of the present invention, the configurable peripheral input and output pins include a plurality of pins, and the device further includes:

[0181] The second storage module is used to determine the second delay adjustment value of each configurable peripheral input and output pin; and save the second delay adjustment value in a preset non-volatile memory.

[0182] In the embodiment of the present invention, the input-output delay adjustment circuit detects whether there is a delay compensation requirement for the configurable peripheral input-output pin; when there is a delay compensation requirement for the configurable peripheral input-output pin, the input-output delay adjustment circuit adjusts the delay of the configurable peripheral input-output pin. Through the embodiment of the present invention, the delay of the configurable peripheral input-output pin can be adjusted by the input-output delay adjustment circuit, thereby ensuring the flexibility of the user's circuit board routing design and improving the reliability of data communication with high-speed peripherals.

[0183] An embodiment of the present invention also provides an electronic device, including a processor, a memory, and a computer program stored in the memory and capable of running on the processor, and when the computer program is executed by the processor, the delay compensation method of the configurable peripheral input and output pins as described above is implemented.

[0184] An embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the delay compensation method for configurable peripheral input and output pins as described above is implemented.

[0185] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0186] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0187] Those skilled in the art will appreciate that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0188] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate a device for implementing the functions specified in one process or multiple processes in the flowchart and / or one box or multiple boxes in the block diagram.

[0189] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0190] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce computer-implemented processing, so that the instructions executed on the computer or other programmable terminal device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0191] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0192] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0193] The above provides a detailed introduction to a delay compensation method for a configurable peripheral input / output pin, a delay compensation device for a configurable peripheral input / output pin, an electronic device and a computer-readable storage medium. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for a person skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A delay compensation method for configurable peripheral input and output pins, characterized in that: Applied to a microcontroller chip, the microcontroller chip is provided with a configurable peripheral input / output pin and an input / output delay adjustment circuit, and the configurable peripheral input / output pin is connected to a peripheral chip; the method comprises: The input / output delay adjustment circuit detects whether there is a delay compensation requirement for the configurable peripheral input / output pins; When there is a delay compensation requirement for the configurable peripheral input / output pin, the input / output delay adjustment circuit adjusts the delay of the configurable peripheral input / output pin.

2. The method according to claim 1, characterized in that The detecting whether there is currently a delay compensation requirement for the configurable peripheral input / output pin comprises: detecting whether an input / output pin delay adjustment command for the configurable peripheral input / output pin is input; When an input / output pin delay adjustment command for the configurable peripheral input / output pin is received, it is determined that there is currently a delay compensation requirement for the configurable peripheral input / output pin.

3. The method according to claim 2, characterized in that The configurable peripheral input / output pins include a plurality of pins, and the step of adjusting the delay of the configurable peripheral input / output pins includes: According to the input / output pin delay adjustment command, determining the input / output pin to be adjusted from a plurality of configurable peripheral input / output pins; and a first adjustment step size; According to the first adjustment step size, delay compensation is performed on the input and output pins to be adjusted.

4. The method according to claim 2, characterized in that: The input pin and the output pin of the peripheral chip are connected to the configurable peripheral input and output pins, and the input pin and the output pin of the peripheral chip are connected to an oscilloscope; The oscilloscope is used to display the input and output waveforms of the peripheral chip.

5. The method according to claim 3, characterized in that: The method further comprises: Determining a first delay adjustment value currently for the configurable peripheral input / output pin; When a save command for the configurable peripheral input / output pin is received, the first delay adjustment value is saved in a preset non-volatile memory.

6. The method according to claim 1, characterized in that The detecting whether there is currently a delay compensation requirement for the configurable peripheral input / output pin comprises: Detect whether the clock rising edge and signal transition edge of the latched data are within the preset latch window; When the rising edge of the clock of the latched data and the signal transition edge are not within the preset latch window, it is determined that there is a delay compensation requirement for the configurable peripheral input / output pin.

7. The method according to claim 6, characterized in that The step of adjusting the delay of the configurable peripheral input / output pin comprises: In a preset clock cycle, the clock delay or data delay of the configurable peripheral input / output pin is adjusted according to a second adjustment step size.

8. The method according to claim 6, characterized in that The step of adjusting the delay of the configurable peripheral input / output pin comprises: Determine the target timing window; Using the delay intermediate value of the target timing window as a second delay adjustment value; The delay of the configurable peripheral input / output pin is adjusted according to the second delay adjustment value.

9. The method according to claim 6, characterized in that The configurable peripheral input and output pins include a plurality of pins, and the method further includes: determining a second delay adjustment value for each configurable peripheral input / output pin; The second delay adjustment value is stored in a preset non-volatile memory.

10. A delay compensation device capable of configuring peripheral input and output pins, characterized in that: Applied to a microcontroller chip, the microcontroller chip is provided with a configurable peripheral input / output pin and an input / output delay adjustment circuit, the configurable peripheral input / output pin is connected to a peripheral chip; the device comprises: A detection module, used for the input / output delay adjustment circuit to detect whether there is a delay compensation requirement for the configurable peripheral input / output pins; The adjustment module is used for adjusting the delay of the configurable peripheral input / output pin by the input / output delay adjustment circuit when there is a delay compensation requirement for the configurable peripheral input / output pin.

11. An electronic device, characterized in that: The invention comprises a processor, a memory and a computer program stored in the memory and capable of running on the processor, wherein when the computer program is executed by the processor, the delay compensation method for the configurable peripheral input and output pins as claimed in any one of claims 1 to 9 is implemented.

12. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the delay compensation method for configurable peripheral input and output pins as claimed in any one of claims 1 to 9 is implemented.

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