Method for manufacturing an electronic chip

Abstract

Embodiments of the present disclosure relate to methods for manufacturing electronic chips. A method for manufacturing an electronic chip includes: forming metallizations on a first side of a semiconductor substrate, the metallizations coupling contacts of adjacent integrated circuits to each other, in and on which a plurality of integrated circuits have been preformed. The method also includes: forming first trenches on the first side of the substrate, the first trenches extending through the first side of the substrate and separating adjacent integrated circuits in the lateral direction. The first trenches extend through the metallizations to form at least a portion of the metallizations at each of the adjacent circuits.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing an electronic chip. More specifically, the present invention relates to a method for manufacturing a so-called surface mount chip (SMD), i.e. a surface mount chip which comprises on at least one surface side one or more connection metallizations of connection areas intended to be soldered to an external device, e.g. a printed circuit board or another chip. Background Art

[0002] In some applications, a surface mount chip is required in which the connection metallization intended to be soldered to an external device extends to the flanks of the chip. Such a chip may be referred to as a chip with wettable flanks. During soldering, a portion of the soldering material rises to the flanks of the chip, which enables a visual inspection of the quality of the connection. This need exists, for example, in fields such as the automotive field or the medical field. Summary of the invention

[0003] It would be desirable to at least partially improve certain aspects of known methods for fabricating electronic chips having wettable flanks.

[0004] One embodiment provides a method for manufacturing an electronic chip, the method comprising the following steps:

[0005] a) forming a metallization coupling contacts of adjacent integrated circuits on a first face side of a semiconductor substrate in which and on which a plurality of integrated circuits have been preformed; and

[0006] b) forming first trenches on said first face side of the substrate, said first trenches laterally separating the integrated circuits and cutting through the metallizations coupling adjacent integrated circuits so as to form at least a portion of the metallization at each of the adjacent circuits.

[0007] According to one embodiment, step a) is followed by step b).

[0008] According to one embodiment, the first trench extends vertically in the substrate over a depth that is greater than a depth of the integrated circuit and less than a thickness of the substrate.

[0009] According to one embodiment, step b) is followed by a step c) of depositing a layer of a first resin over the entire first face, said first resin penetrating into the first trenches and covering said portion of said metallization.

[0010] According to one embodiment, step c) is followed by a step d) of planarizing the first face until the portion of the metallization is exposed.

[0011] According to one embodiment, step d) is performed until the portion of the metallization is exposed over a surface area that is sufficient for soldering the chip to a device different from the chip through the first side of the chip, and in some embodiments, planarization is performed until the portion of the metallization is exposed over a length greater than about 100 μm.

[0012] According to one embodiment, step a) is preceded by step e) of forming second trenches on the first face side which laterally separate the integrated circuits, the second trenches extending vertically in the substrate to a depth which is greater than the depth of the integrated circuits and less than the thickness of the substrate.

[0013] According to one embodiment, step a) is followed by a step f) of depositing a layer of a first resin over the entire first face, said first resin penetrating into the second trenches and covering said portion of said metallization.

[0014] According to one embodiment:

[0015] Step e) is preceded by step g): forming a bump vertically aligned with the integrated circuit; and

[0016] Between steps e) and a) a step h) is carried out in which a first layer of a first resin is deposited over the entire first face, the first resin penetrating into the second trenches and covering the bumps, and the first layer is planarized at least until the bumps are exposed.

[0017] According to one embodiment, the metallization is coupled to the integrated circuit by means of bumps.

[0018] According to one embodiment, step a) is followed by a step i) of depositing a second layer of the first resin on the first layer of the first resin.

[0019] According to one embodiment, step f) or i) is followed by a step j) of planarizing the first face in order to expose each metallization, which is exposed over a length of, for example, more than approximately 200 μm.

[0020] According to one embodiment, step d) or j) is followed by step k) of thinning the substrate through its second face situated opposite the first face, at least until the first resin is reached, and depositing a layer of a second resin on the second face.

[0021] According to one embodiment, step k) is followed by step l), which comprises the following steps:

[0022] partially removing the layer of the first resin at a height less than or equal to the height of said portion of said metallization so as to form an opening located opposite the trench and extending over a width greater than or equal to the width of the trench, thereby releasing at least part of the flank of each integrated circuit; and

[0023] The chips are singulated by cutting along a cutting path in the first trench at a width smaller than a width of the first trench.

[0024] According to one embodiment, step k) is followed by step b). BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above features and advantages as well as other features and advantages will be described in detail in the following description of specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings, in which:

[0026] Figure 1 The steps of a method for manufacturing an electronic chip according to a first embodiment are shown via cross-sectional views;

[0027] Figure 2 A further step of the method for manufacturing an electronic chip according to the first embodiment is shown via views (A) and (B), which are a cross-sectional view and a top view, respectively;

[0028] Figure 3 The top view shows Figure 2 Alternatives to the steps shown in ;

[0029] Figure 4 A further step of the method for manufacturing an electronic chip according to the first embodiment is shown via views (A) and (B), which are a cross-sectional view and a top view, respectively;

[0030] Figure 5 The top view shows Figure 4 Alternatives to the steps shown in ;

[0031] Figure 6 A further step of the method for producing an electronic chip according to the first embodiment is shown via a cross-sectional view;

[0032] Figure 7 A further step of the method for producing an electronic chip according to the first embodiment is shown via a cross-sectional view;

[0033] Figure 8 A further step of the method for producing an electronic chip according to the first embodiment is shown via a cross-sectional view;

[0034] Fig. 9A further step of the method for producing an electronic chip according to the first embodiment is shown via a cross-sectional view;

[0035] Fig.10 A further step of the method for producing an electronic chip according to the first embodiment is shown via a cross-sectional view;

[0036] Fig.11 The steps of a method for manufacturing an electronic chip according to a second embodiment are shown via cross-sectional views;

[0037] Fig.12 A further step of the method for producing an electronic chip according to the second embodiment is shown via a cross-sectional view;

[0038] Fig.13 A further step of the method for producing an electronic chip according to the second embodiment is shown via a cross-sectional view;

[0039] Fig.14 A further step of the method for producing an electronic chip according to the second embodiment is shown via a cross-sectional view;

[0040] Fig.15 A further step of the method for producing an electronic chip according to the second embodiment is shown via a cross-sectional view;

[0041] Fig.16 A further step of the method for producing an electronic chip according to the second embodiment is shown via a cross-sectional view;

[0042] Fig.17 A further step of the method for producing an electronic chip according to the second embodiment is shown via a cross-sectional view;

[0043] Fig.18 A further step of the method for producing an electronic chip according to the second embodiment is shown via a cross-sectional view;

[0044] Fig.19 The steps of a method for manufacturing an electronic chip according to a third embodiment are shown via cross-sectional views;

[0045] Fig. 20 A further step of the method for producing an electronic chip according to a third embodiment is shown via a cross-sectional view;

[0046] Fig.21 A further step of the method for producing an electronic chip according to a third embodiment is shown via a cross-sectional view;

[0047] Fig. 22 A further step of the method for producing an electronic chip according to a third embodiment is shown via a cross-sectional view;

[0048] Fig.23 A further step of the method for producing an electronic chip according to a third embodiment is shown via a cross-sectional view;

[0049] Fig.24 A further step of the method for producing an electronic chip according to a third embodiment is shown via a cross-sectional view;

[0050] Fig.25 A further step of the method for producing an electronic chip according to a third embodiment is shown via a cross-sectional view;

[0051] Fig.26 A further step of the method for producing an electronic chip according to a third embodiment is shown via a cross-sectional view;

[0052] Fig. 27 A further step of the method for producing an electronic chip according to a third embodiment is shown via a cross-sectional view;

[0053] Fig.28 A further step of the method for producing an electronic chip according to a third embodiment is shown via a cross-sectional view;

[0054] Fig.29 The steps of a method for manufacturing an electronic chip according to a fourth embodiment are shown via cross-sectional views;

[0055] Fig.30 A further step of the method for producing an electronic chip according to a fourth embodiment is shown via a cross-sectional view;

[0056] Fig.31 A further step of the method for producing an electronic chip according to a fourth embodiment is shown via a cross-sectional view;

[0057] Fig.32 A further step of the method for producing an electronic chip according to a fourth embodiment is shown via a cross-sectional view;

[0058] Fig.33 A further step of the method for producing an electronic chip according to a fourth embodiment is shown via a cross-sectional view;

[0059] Fig.34 A further step of the method for producing an electronic chip according to a fourth embodiment is shown via a cross-sectional view;

[0060] Fig.35 A further step of the method for producing an electronic chip according to a fourth embodiment is shown via a cross-sectional view;

[0061] Fig.36 A further step of the method for manufacturing an electronic chip according to a fourth embodiment is shown via a cross-sectional view; and

[0062] Fig.37 An alternative embodiment is shown via a perspective view. DETAILED DESCRIPTION

[0063] In the various drawings, similar features are indicated by similar reference numerals. In particular, the same structural features and / or functional features in various embodiments may have the same reference numerals, and may have the same structural characteristics, dimensional characteristics, and material characteristics.

[0064] For the sake of clarity, only the details and descriptions that are helpful for understanding the operation and elements of the embodiments described herein are described in detail. In particular, the implementation of the integrated circuits present in the described electronic chips is not described in detail.

[0065] Unless otherwise specified, when referring to two elements being connected together, it means a direct connection without any intermediate elements except conductors, and when referring to two elements being coupled together, it means the two elements may be connected or coupled through one or more other elements.

[0066] In the following disclosure, unless otherwise indicated, when referring to absolute position qualifiers (such as terms "front", "back", "top", "bottom", "left", "right", etc.) or relative position qualifiers (such as terms "upper", "lower", "higher", "lower", etc.) or direction qualifiers (such as "horizontal", "vertical", etc.), reference is made to the direction shown in the accompanying drawings.

[0067] Unless otherwise specified, the expressions "about," "approximately," "substantially," and "approximately" mean within 10%, and in some embodiments within 5%.

[0068] Figures 1 to 10 Successive steps of an example of a method for manufacturing an electronic chip according to a first embodiment are depicted in a schematic and partial manner.

[0069] Figure 1 The steps of a method for producing an electronic chip according to a first embodiment are illustrated via cross-sectional views.

[0070] More specifically, Figure 1 1 is a partial schematic diagram of an initial structure including a semiconductor substrate 11, in which and on which an integrated circuit 13 has been preformed. For example, except for the manufacturing dispersion, the circuit 13 is identical. The substrate 11 can correspond to a wafer of semiconductor material (for example, silicon). The substrate 11 has, for example, a thickness between about 50 μm and about 900 μm, for example a thickness of about 200 μm.

[0071] In the following description, Figure 1In the orientation shown, the top surface of the structure is considered the front surface and Figure 1 In the orientation shown, the bottom surface of the structure is considered the back surface.

[0072] Figure 1 The structure shown also comprises a stack 15 of conducting and insulating layers, called interconnect stack, covering the upper surface of the substrate 11. Elements for interconnecting the components of each circuit 13 are formed in this stack 15. For each integrated circuit 13, the interconnect stack 15 comprises in particular one or more metal contact pads 17 flush with the upper surface of the integrated circuit 13 and intended to be connected to devices external to the implemented chip.

[0073] Each integrated circuit 13 includes, for example, one or more electronic components (transistor, diode, thyristor, triac, etc.).

[0074] exist Figure 1 Three integrated circuits 13 are shown in FIG. 1 , it being understood that in practice the number of integrated circuits 13 formed in and on the substrate 11 may be much higher.

[0075] Figure 2 A further step of the method for manufacturing an electronic chip according to the first embodiment is shown via views (A) and (B), which are a cross-sectional view and a top view, respectively.

[0076] More specifically, Figure 2 The step of forming connection metallizations 19 on and in contact with metal pads 17 of two adjacent circuits 13 is shown via a partial schematic diagram. View (A) corresponds to a cross-sectional view according to the section plane AA shown in view (B).

[0077] The metallization 19 is produced by metal deposition on and in contact with the pad 17 through a mask (not shown). Figure 2 In the illustrated embodiment, the openings of the mask (not shown) are intentionally misaligned relative to the positions of the underlying contact pads 17. More specifically, the openings of the mask (not shown) are intentionally positioned between two contact pads 17 of two adjacent circuits 13 such that each opening is positioned opposite a portion of each of the two pads 17 of the two adjacent circuits 13.

[0078] Metal guided by the opening of the mask (not shown) between the two pads 17 of two adjacent circuits 13 is deposited on the two contact pads 17 while coupling them to form a bridge. The two bases of the bridge each contact the contact pad 17 of one of the two adjacent circuits 13.

[0079] This phenomenon, which is related to misalignment of the mask, is generally undesirable because it shorts two contact pads 17. In the present embodiment, this phenomenon is exploited by encouraging it to form part of a bridge or conductive loop coupling two contacts 17 of two separate circuits 13.

[0080] Thus, each metallization 19 is elongated between the two pads 17 of the two adjacent circuits 13 to which it couples.

[0081] In practice, the opening of the mask is circular, square or elongated in the direction coupling the two contacts 17 .

[0082] The metallization 19 may be made of a tin-based alloy, for example an alloy based on tin and silver (SnAg).

[0083] For example, the metallizations 19 are all oriented in the same direction (view (B)).

[0084] In practice, the substrate 11 may include a plurality of identical integrated circuits 13 arranged on the entire structure, all of which are intended to be chips with wettable flanks. The circuits located at the edge of the semiconductor wafer are incomplete due to the generally circular shape of the wafer. These incomplete circuits are usually lost. However, in the described embodiment, their contacts opposite to the contacts of the adjacent complete circuits are used to form bridges with the contacts of the adjacent complete circuits.

[0085] Figure 3 The top view shows Figure 2 Alternatives to the steps shown in .

[0086] Figure 3 The structure shown in Figure 2 The structure shown in (view (B)) differs in the fact that the metallization 19 is oriented in an orthogonal direction. More generally, the metallization 19 may be realized obliquely with respect to the alignment of the circuits, or couple the contacts 17 of the corners of two adjacent circuits 13 .

[0087] Figure 4 A further step of the method for manufacturing an electronic chip according to the first embodiment is shown via views (A) and (B), which are a cross-sectional view and a top view, respectively.

[0088] More specifically, Figure 4 The partial schematic diagram shows the Figures 1 to 3 The step shown is a step of forming a first trench 21 in the upper surface of the structure obtained at the end of the step. View (A) corresponds to a cross-sectional view according to the section plane AA shown in view (B).

[0089] The first trenches 21 extend between the circuits 13 such that, when viewed from above, each circuit 13 is separated from its neighboring circuits by the trenches 21. For example, each circuit 13 is completely defined laterally by the trenches 21. For example, the trenches may form a continuous grid extending between the integrated circuits 13 when viewed from above.

[0090] In the example shown, the trench 21 extends vertically from the upper surface of the stack 15 and continues into the substrate 11 to a depth greater than the depth of the integrated circuit 13. The trench 21 extends vertically.

[0091] The groove 21 is realized by sawing, for example. During the sawing step, the structure may be mounted on a support film (not shown) provided on the lower surface side of the substrate 11, which is then removed after the groove 21 is formed.

[0092] The sawing operation cuts the metallization 19 along the grooves 21, thereby separating each metallization 19 into two parts 19' of the metallization 19. This separation causes flanks 191 to appear on either side of the groove 21 on the parts 19'.

[0093] In other words, the metallization 19 is cut so as to form at least a portion 19 ′ of the metallization 19 at each of the adjacent circuits 13 .

[0094] In this example, the grooves 21 are non-through, that is, they do not exit at the lower side of the substrate 11. The grooves 21 extend vertically over a depth H1, for example, between about 30 μm and about 400 μm, in some embodiments between about 100 μm and about 200 μm. The grooves 21 have a width L1, for example, between about 5 μm and about 100 μm, in some embodiments, between about 30 μm and about 40 μm, and in some embodiments, the width L1 is equal to about 35 μm, for example, equal to 35 μm.

[0095] Figure 5 Described via top view Figure 4 Alternatives to the steps shown.

[0096] Figure 5 The structure shown is Figure 4 The structure shown in (view (B)) differs in the fact that the step of forming the groove 21 is based on Figure 3 The structure shown is carried out.

[0097] Figure 6 A further step of the method for producing an electronic chip according to the first exemplary embodiment is illustrated via a cross-sectional view.

[0098] More specifically, Figure 6 The partial schematic diagram shows the Figures 1 to 5 The steps shown end with a step of depositing an insulating layer on the upper surface of the structure obtained, which insulating layer may be a first layer 23 of a first resin in some embodiments.

[0099] The front side of the structure is completely covered (whole wafer), and in particular the trenches 21 are filled and the stack 13 and the part 19' of the metallization 19 are covered by the layer 23. The first resin is, for example, an epoxy resin.

[0100] Figure 7 A further step of the method for producing an electronic chip according to the first exemplary embodiment is illustrated via a cross-sectional view.

[0101] More specifically, Figure 7 The schematic diagram of the part shows that, for example, chemical mechanical polishing (CMP) is used to polish the Figures 1 to 6 The step shown ends with a step of planarization of the front side of the structure obtained. During this step, the upper part of the layer 23 is removed so as to expose a portion 19' of the metallization 19. More specifically, the planarization is carried out until the portion 19' is exposed over a length L2 greater than 20 μm (in the plane of the chip) and over a width greater than 100 μm.

[0102] Length L2 is, for example, between about 20 μm and about 600 μm, and in some embodiments between about 100 μm and about 500 μm. For example, width of portion 19 ′ is between about 100 μm and 600 μm, and in some embodiments between about 100 μm and about 400 μm. These dimensions are selected based on the width of trench 21 and the size of contact pad 17.

[0103] Figure 8 A further step of the method for producing an electronic chip according to the first exemplary embodiment is illustrated via a cross-sectional view.

[0104] More specifically, Figure 8 The partial schematic diagram shows the Figures 1 to 7 The structure obtained at the end of the steps shown has undergone a step of thinning its back side.

[0105] It should be noted that, relative to the cross-sectional views shown in the previous figures, Figure 8 In the example shown, the orientation of the structures is reversed.

[0106] The substrate 11 is polished through its back side ( Figure 8 In this embodiment, the substrate 11 is thinned via its back side until at least the bottom of the groove 21 is reached, so that after thinning, the first resin present in the groove 21 is flush with the back side of the substrate 11. At the end of this step, the integrated circuit 13 is only connected via the layer 23 and the support film ( Figure 8 The remaining parts (not shown) are coupled to each other.

[0107] Fig. 9 A further step of the method for producing an electronic chip according to the first exemplary embodiment is illustrated via a cross-sectional view.

[0108] More specifically, Fig. 9 is with Figure 8 Local cross-section with the same orientation, Fig. 9 Shown in Figures 1 to 8 The steps shown end with a step of depositing a second layer 25 of a second resin on the back side of the structure obtained.

[0109] The layer 25 of the second resin extends in a continuous manner and with a substantially constant thickness over the entire surface area (e.g., the entire wafer) of the back side of the structure. The layer 25 of the second resin has, for example, a thickness between about 10 μm and a thickness according to the final dimension of the box. In certain embodiments, the thickness of the layer 25 is between about 10 μm and about 100 μm, for example, about the order of 25 μm. The second resin can be an epoxy resin. The first resin and the second resin can have the same composition or different compositions.

[0110] Fig.10 A further step of the method for producing an electronic chip according to the first exemplary embodiment is illustrated via a cross-sectional view.

[0111] More specifically, Fig.10 The partial schematic diagram shows the Figures 1 to 9 The steps of forming an opening 27 on the front side of the structure obtained at the end of the steps shown, and cutting the structure into individual chips each comprising a single integrated circuit 13. Prior to this step, the structure is placed by its back side on a support film 21 (on the Fig.10 (not shown).

[0112] Opposite the first trench 21, each opening 27 is locally realized in a region originating from the same metallization 19 ( Figure 2 As an alternative, the openings 27 can be realized opposite all the grooves 21 and over the entire length of all the grooves 21 .

[0113] In order to realize the opening 27, a partial removal of the first resin (layer 23) located above the first groove 21 is realized. The partial removal of the first resin may be accompanied by - when viewed from above - the removal of a portion of the portion 19' located on either side of the groove 21, thereby reducing the length L2 ( Figure 7The opening 27 can be, for example, a groove parallel to the lower groove 21. The opening 27 extends, for example, over the entire length of the lower groove 21.

[0114] The formation of the openings results in the appearance of flanks 193 which correspond to the wettable metal flanks of the chip manufactured according to this embodiment.

[0115] The opening 27 extends vertically from the front side of the structure over a depth H2 and a width L3. The depth H2 is determined so as to optimize soldering of the chip to an external device and visual inspection of the soldering. For example, the depth H2 is therefore less than or equal to the remaining height of the portion 19 'of the metallization 19 (the distance between the upper surface of the stack 15 and the upper surface of the layer 23 of the first resin). In some embodiments, the depth H2 is greater than the flank 191 ( Fig. 9 For example, the depth H2 is between about 20 μm and about 400 μm, and in some embodiments, is on the order of about 100 μm.

[0116] Flank 193 corresponds to the Figure 7 The step shown corresponds to a flank 191 that is reduced in height, or corresponds to a flank that is set back if the width L3 is greater than the gap between two flanks 191 of the previous step.

[0117] Similar to the depth H2, the width L3 is selected so as to optimize the soldering of the chip on the external device and the visual inspection of the soldering. More specifically, in the present example, on the one hand, the width L3 of the opening 27 is selected to be large enough so as to allow the first resin to be removed from the flanks 193 of the portion 19' of each integrated circuit 13. On the other hand, the width L3 should generally be small enough so that a subsequent visual inspection of the soldering material, which rises on the flanks 193 of the portion 19' of each metallization, is feasible. In fact, if the width L3 is too large, the layer 23 of the first resin will interfere with the inspection. In addition, the width L3 should be small enough so as to remove only the flanks 193 of the portion 19', or to cut into the portion 19' of the metallization without removing the portion 19' over the entire length of the portion 19'.

[0118] Therefore, the opening 27 has a width L3, which is, for example, between about 10 μm and about 150 μm, in some embodiments between about 40 μm and about 60 μm, and in some embodiments, the width L3 is equal to about 50 μm, for example, equal to 50 μm.

[0119] The opening 27 may be realized, for example, by sawing using a cutting blade having a width greater than the width used to realize the first groove 21. As an alternative, the opening 27 may be realized by laser ablation.

[0120] After the opening 27 is formed, the flanks 193 of each portion 19' are exposed.

[0121] In order to cut the structure into individual chips, each of which includes a single integrated circuit 13, a cutting line 29 is implemented in the first resin (layer 23) and the second resin (layer 25), opposite the first groove 21 and the opening 27. More specifically, in this example, the cutting line 29 is formed opposite each first groove 21 and parallel to the first groove 21. In this example, the cut 29 extends over the entire length of the first groove 21. The cutting line 29 extends vertically from the upper surface of the structure to the lower surface of the layer 23 and exits on the back side. The width L4 of the cutting line 29 is less than the width of the groove 21, so that each chip remains covered by the first resin (layer 23) on its four sides. The width L4 of the cutting line 29 is, for example, between about 10 μm and about 50 μm, in some embodiments between about 20 μm and about 30 μm, and in some embodiments, the width L4 is equal to about 25 μm, for example, equal to 25 μm.

[0122] The cutouts 29 may be realized, for example, by sawing using a cutting blade having a width smaller than the width used to realize the grooves 21. As an alternative, the cutouts 29 may be realized by laser ablation.

[0123] At the end of this step, the structure obtained corresponds to a structure consisting only of the support membrane 10 ( Fig.10 Multiple electronic chips coupled (not shown).

[0124] The chips can then be removed from the support film in order to mount them in external devices.

[0125] As an alternative, the opening 27 can be produced from Figure 6 Starts when the steps shown are finished.

[0126] Figures 11 to 18 Successive steps of an example of a method for manufacturing an electronic chip according to a second embodiment are shown in a schematic and partial manner.

[0127] The second embodiment differs from the first embodiment mainly in that a trench 31 or recess which is substantially identical to the first trench 21 of the first embodiment is realized before the metallization 19 is formed.

[0128] Fig.11 The steps of a method for producing an electronic chip according to a second embodiment are illustrated via cross-sectional views.

[0129] More specifically, Fig.11 The partial schematic diagram shows the Figure 1 The initial structure of the method according to the first embodiment shown is the same as the initial structure.

[0130] Fig.12 A further step of the method for producing an electronic chip according to the second exemplary embodiment is illustrated via a cross-sectional view.

[0131] More specifically, Fig.12 The partial schematic diagram shows the Fig.11 The step shown is a step of forming a non-through recess 31 or a second trench in the front side of the structure obtained at the end of the step.

[0132] In the second embodiment, Fig.12 The groove 31 formed in the step shown is the same as that in the first embodiment. Figure 4 The first trench 21 formed in the step shown is substantially identical and differs in that the recess 31 is formed before the metallization 19 is realized.

[0133] Fig.13 A further step of the method for producing an electronic chip according to the second exemplary embodiment is illustrated via a cross-sectional view.

[0134] More specifically, Fig.13 The partial schematic diagram shows the Figure 11 to Figure 12 The step shown ends with a step of forming metallizations 19 on the front side of the structure obtained, these metallizations 19 being on and in contact with the metal pads 17 of two adjacent circuits 13 .

[0135] In the second embodiment, Fig.13 The metallization 19 formed in the step shown is similar to that in the first embodiment. Figure 2 The metallization 19 formed in the steps shown is substantially identical, with the difference that in the second embodiment the metallization is realized after the groove 31 .

[0136] Fig.14 A further step of the method for producing an electronic chip according to the second exemplary embodiment is illustrated via a cross-sectional view.

[0137] More specifically, Fig.14 The partial schematic diagram shows the Figures 11 to 13 The step shown ends with a step of depositing a first layer 23 of a first resin on the upper surface of the structure obtained.

[0138] This step is basically the same as that of the method according to the first embodiment. Figure 6 The steps are the same as those shown in Fig.14 In the step shown, the layer 23 of the first resin covers in particular the metallization 19 but not the portion 19 ′.

[0139] Fig.15A further step of the method for producing an electronic chip according to the second exemplary embodiment is illustrated via a cross-sectional view.

[0140] More specifically, Fig.15 The schematic diagram shows that, for example, chemical mechanical polishing (CMP) will Figures 11 to 14 The steps shown end with the step of planarization of the front side of the structure obtained.

[0141] During this step, the upper portion of the layer 23 of the first resin is removed, thereby exposing the metallization 19. More specifically, planarization is performed to expose the metallization 19 over a width greater than 50 μm and over a length L5 (in the plane of the chip), the length L5 being selected according to the length that is desired to be retained on the final chip to allow the chip to be soldered to an external device. At the end of this step, each metallization 19 is exposed over a length L5 greater than about 50 μm, for example, between about 50 μm and about 1270 μm, in some embodiments between about 300 μm and about 1040 μm. The width of the metallization 19 is greater than about 100 μm, for example, between about 100 μm and about 600 μm, in some embodiments between about 100 μm and about 400 μm.

[0142] These dimensions are selected according to the width of the recess 31 and the size of the contact pad 17 .

[0143] Fig.16 A further step of the method for producing an electronic chip according to the second exemplary embodiment is illustrated via a cross-sectional view.

[0144] Fig.17 A further step of the method for producing an electronic chip according to the second exemplary embodiment is illustrated via a cross-sectional view.

[0145] More specifically, Fig.16 and Fig.17 The partial schematic diagram shows the Figures 11 to 15 The structure obtained at the end of the steps shown passes through a step of thinning its back side, and a step of depositing a second layer 25 of a second resin on the back side of this structure.

[0146] It should be noted that, relative to the cross-sectional views shown in the previous figures, Fig.16 and Fig.17 In the example shown, the orientation of the structures is reversed.

[0147] These two steps are basically the same as in the method according to the first embodiment. Figure 8 and Fig. 9 The steps shown in are the same.

[0148] Fig.18A further step of the method for producing an electronic chip according to the second exemplary embodiment is illustrated via a cross-sectional view.

[0149] More specifically, Fig.18 The step of dicing the structure into individual chips each comprising a single integrated circuit 13 is shown via a partial schematic diagram.

[0150] Prior to this step, the structure is fixed by its back side on a support film 21, which is Fig.18 Not shown.

[0151] In order to cut the structure into individual chips each comprising a single integrated circuit 13 and to separate each metallization 19 into two metallization portions 19 ′, first trenches 33 are realized in the first resin and in the second resin opposite the recesses 31 .

[0152] In this step, the first groove 33 is substantially aligned with the Fig.10 The cutting lines 29 realized in the steps shown are identical and differ in that the formation of the first trenches 33 is sufficient (without forming the openings 27 ) to expose the metal surface originating from the metallization 19 on at least one flank 191 of each chip.

[0153] At the end of this step, the structure obtained corresponds to a structure consisting only of the support membrane 18 ( Fig.10 The chips may then be removed from the support film so that they may be mounted in or on an external device.

[0154] Figures 19 to 28 Successive steps of an example of a method for manufacturing an electronic chip according to a third embodiment are shown in a schematic and partial manner.

[0155] The third embodiment differs from the second embodiment mainly in the way in which the metallization 19 is realized.

[0156] Fig.19 The steps of a method for producing an electronic chip according to a third embodiment are illustrated via cross-sectional views.

[0157] More specifically, Fig.19 The partial schematic diagram shows the Fig.11 The initial structure of the method according to the second embodiment shown is the same as the initial structure.

[0158] Fig. 20 A further step of the method for producing an electronic chip according to the third exemplary embodiment is illustrated via a cross-sectional view.

[0159] More specifically, Fig. 20The step of forming conductive bumps 35 , which are on and in contact with metal pads 17 , is shown via a partial schematic diagram.

[0160] In this example, a bump 35 is formed on each pad 17. For example, when viewed from above, each bump 35 extends over the entire surface of the pad 17 below. The height H3 of the bump 35 is, for example, between about 1 μm and about 300 μm. The bump 35 can be formed, for example, by electrolytic growth. The bump 35 can be made of a tin-based alloy, such as an alloy based on tin and silver (SnAg).

[0161] Fig.21 A further step of the method for producing an electronic chip according to the third exemplary embodiment is illustrated via a cross-sectional view.

[0162] More specifically, Fig.21 The partial schematic diagram shows the Fig.19 and Fig. 20 The step shown is a step of forming a non-through recess 31 or a second trench in the upper surface of the structure obtained at the end of the step.

[0163] In the third embodiment, Fig.21 The groove 31 formed in the step shown is the same as that in the second embodiment. Fig.12 The grooves 31 formed in the steps shown are substantially the same.

[0164] Fig. 22 A further step of the method for producing an electronic chip according to the third exemplary embodiment is illustrated via a cross-sectional view.

[0165] More specifically, Fig. 22 The partial schematic diagram shows the Figures 19 to 21 The steps shown end with a step of depositing a first layer 231 of a first resin on the front side of the structure obtained.

[0166] More specifically, the front side of the structure is completely covered (whole wafer), and in particular the grooves 31 are filled and the stack 13 and the bumps 35 are covered by a first layer 231 of a first resin. The first resin is for example an epoxy resin.

[0167] Fig.23 A further step of the method for producing an electronic chip according to the third exemplary embodiment is illustrated via a cross-sectional view.

[0168] More specifically, Fig.23 The schematic diagram of the part shows that, for example, chemical mechanical polishing (CMP) is performed on the Figures 19 to 22The step shown ends with a step of planarization of the front side of the structure obtained. During this step, the upper part of the first resin is removed, thereby exposing the bumps 35. More specifically, planarization is performed until the bumps 35 are exposed over a surface area greater than, for example, 10 μm×10 μm.

[0169] Fig.24 A further step of the method for producing an electronic chip according to the third exemplary embodiment is illustrated via a cross-sectional view.

[0170] More specifically, Fig.24 The partial schematic diagram shows the Figures 19 to 23 The step shown ends with a step of forming a metallization 19 on the front side of the structure obtained, the metallization 19 being on and in contact with the bumps 35 of the two pads 17 of two adjacent circuits 13 .

[0171] exist Fig.24 In the embodiment shown, the metallization 19 is similar to the metallization 19 in the second embodiment. Figure 2 The metallization 19 produced in the steps shown is substantially identical and differs in that: Fig.24 The metallization 19 shown is realized on the bump 35 and makes contact with the bump 35 .

[0172] Fig.25 A further step of the method for producing an electronic chip according to the third exemplary embodiment is illustrated via a cross-sectional view.

[0173] More specifically, Fig.25 The partial schematic diagram shows the Figures 19 to 24 The step shown ends with a step of depositing a second layer 233 of a first resin on the front side of the structure obtained.

[0174] The front side of the structure is completely covered (whole wafer), and in particular the first layer 231 and the metallization 19 are covered by a second layer 233 of the first resin.

[0175] Fig.26 A further step of the method for producing an electronic chip according to the third exemplary embodiment is illustrated via a cross-sectional view.

[0176] More specifically, Fig.26 The schematic diagram of the part shows that, for example, chemical mechanical polishing (CMP) is performed on the Figures 19 to 25 The step shown ends with a step of planarization of the front side of the structure obtained. During this step, the upper part of the layer 23 of the first resin is removed so as to expose the metallization 19.

[0177] This step is Fig.15 The planarization steps of the second embodiment shown are substantially the same.

[0178] Fig. 27 A further step of the method for producing an electronic chip according to the third exemplary embodiment is illustrated via a cross-sectional view.

[0179] More specifically, Fig. 27 The partial schematic diagram shows the Figures 19 to 26 The structure obtained at the end of the steps shown passes through a step of thinning its back side, and a step of depositing a third layer 25 of a second resin on the back side of this structure.

[0180] It should be noted that, relative to the cross-sectional views shown in the previous figures, Fig. 27 In the example shown, the orientation of the structures is reversed.

[0181] This step is basically the same as that of the method according to the second embodiment. Fig.16 and Fig.17 The steps shown are the same.

[0182] Fig.28 A further step of the method for producing an electronic chip according to the third exemplary embodiment is illustrated via a cross-sectional view.

[0183] More specifically, Fig.28 The step of dicing the structure into individual chips each comprising a single integrated circuit 13 is shown via a partial schematic diagram.

[0184] This step is basically the same as that of the method according to the second embodiment. Fig.18 The steps are the same as shown in .

[0185] An advantage of the second and third embodiments is that they allow the formation of electronic chips having step-free wettable flanks.

[0186] Figures 29 to 36 Successive steps of an example of a method for manufacturing an electronic chip according to a fourth embodiment are shown in a schematic and partial manner.

[0187] The fourth embodiment differs from the second embodiment mainly in the shape and arrangement of the metallization 19 .

[0188] Fig.29 The steps of a method for producing an electronic chip according to a fourth embodiment are illustrated via cross-sectional views.

[0189] More specifically, Fig.29 The partial schematic diagram shows the Fig.11 The illustrated initial structure of the method according to the second embodiment is the same initial structure and differs in that the circuits are coupled to each other via the same conductive area 17 ′ defining a pad 17 and coupling two adjacent circuits 13 .

[0190] Fig.30 A further step of the method for producing an electronic chip according to a fourth exemplary embodiment is illustrated via a cross-sectional view.

[0191] More specifically, Fig.30 The step of forming a metallization 19 on and in contact with the region 17 ′ is shown via a partial schematic view.

[0192] The metallization 19 is produced by metal deposition on and in contact with the regions 17' through a mask. The deposited metal is guided by the openings of the mask opposite the regions 17'. The height of the metallization 19 is, for example, between approximately 1 μm and approximately 100 μm.

[0193] The metallization 19 may be made of a tin-based alloy, for example an alloy based on tin and silver (SnAg). As an alternative, the metallization 19 may be made of a copper-based alloy.

[0194] Fig.31 A further step of the method for producing an electronic chip according to a fourth exemplary embodiment is illustrated via a cross-sectional view.

[0195] More specifically, Fig.31 The partial schematic diagram shows the Figure 29 to Figure 30 The step shown ends with the step of forming a first trench 21 in the upper surface of the obtained structure.

[0196] In the fourth embodiment, Fig.31 The first groove 21 formed in the step shown is substantially the same as that in the first embodiment. Figure 4 The first trench 21 formed in the step shown is identical and differs in that the metallization 19 has, for example, the shape of a parallelepiped instead of the shape of a ring portion or a bridge.

[0197] At the end of this step, the structure comprises a portion 19 ′ of the metallization 19 .

[0198] Fig.32 A further step of the method for producing an electronic chip according to a fourth exemplary embodiment is illustrated via a cross-sectional view.

[0199] More specifically, Fig.32 The partial schematic diagram shows the Figure 29 to Figure 31 The steps shown end with a step of depositing a layer 23 of a first resin on the front side of the structure obtained.

[0200] This step is basically the same as that of the method according to the first embodiment. Figure 6 The steps shown are the same.

[0201] Fig.33A further step of the method for producing an electronic chip according to a fourth exemplary embodiment is illustrated via a cross-sectional view.

[0202] More specifically, Fig.33 The schematic diagram of the part shows that, for example, chemical mechanical polishing (CMP) is performed on the Figure 29 to Figure 32 The step shown is a step of planarization of the front side of the structure obtained at the end of the step.

[0203] During this step, the upper part of the layer 23 is removed, so that at least a part 19 ′ of the metallization 19 is exposed.

[0204] Fig.34 A further step of the method for producing an electronic chip according to a fourth exemplary embodiment is illustrated via a cross-sectional view.

[0205] More specifically, Fig.34 The partial schematic diagram shows the Figure 29 to Figure 33 The structure obtained at the end of the steps shown has undergone a step of thinning its back side.

[0206] It should be noted that, relative to the cross-sectional views shown in the previous figures, Fig.34 In the example shown, the orientation of the structures is reversed.

[0207] This step is basically the same as that of the method according to the first embodiment. Figure 8 The steps shown are the same.

[0208] Fig.35 A further step of the method for producing an electronic chip according to a fourth exemplary embodiment is illustrated via a cross-sectional view.

[0209] More specifically, Fig.35 is with Fig.34 Local cross-section with the same orientation, Fig.35 Shown in Figures 29 to 34 The steps shown end with a step of depositing a layer 25 of a second resin on the back side of the structure obtained.

[0210] This step is basically the same as that of the method according to the first embodiment. Fig. 9 The steps shown are the same.

[0211] Fig.36 A further step of the method for producing an electronic chip according to a fourth exemplary embodiment is illustrated via a cross-sectional view.

[0212] More specifically, Fig.36 The partial schematic diagram shows the Figure 29 to Figure 35The steps of forming an opening 27 on the front side of the structure obtained at the end of the steps shown, and cutting the structure into individual chips each comprising a single integrated circuit 13. Prior to this step, the structure is placed via its back side on a support film 21 which is formed on the Fig.36 Not shown.

[0213] In the fourth embodiment, Fig.36 The opening 27 formed in the step shown is the same as that in the first embodiment. Fig.10 The openings 27 formed in the steps shown are substantially identical and differ in the shape of the portion 19' of the metallization 19. The dimensions of the openings 27 formed in the fourth embodiment are selected in the same way as the dimensions of the openings 27 formed in the first embodiment. However, given the difference in the shape of the openings 27 between the two embodiments, their dimensions are not identical in value.

[0214] The opening 27 extends vertically from the front side of the structure over a depth H4 and a width L6. For example, the depth H4 is smaller than or equal to the remaining height of the portion 19' of the metallization 19. For example, the depth H4 is approximately 100 μm.

[0215] The opening 27 has a width L6, for example, between about 15 μm and about 80 μm, in some embodiments between about 40 μm and about 50 μm, and in some embodiments the width L6 is equal to about 45 μm, for example, equal to 45 μm.

[0216] In order to cut the structure into individual chips each comprising a single integrated circuit 13 , cutting lines 29 are implemented in the first resin and the second resin, the cutting lines being opposite the first trench 21 and the opening 27 .

[0217] Fig.36 The cutting line 29 shown is Fig.10 The cutting line 29 of the step of the first embodiment shown is substantially the same.

[0218] At the end of this step, the structure obtained corresponds to a structure consisting only of the support membrane ( Fig.36 The flanks of the portions 19' exposed in the step of forming the openings 27 correspond to the wettable flanks of the chips.

[0219] Then, the support film 10 ( Fig.10 The chips are removed from the device (not shown) so that they can be installed in external devices.

[0220] As an alternative, the opening 27 can be produced from Fig.32 Starts when the steps shown are finished.

[0221] Fig.37An alternative embodiment is shown via a perspective view.

[0222] More specifically, Fig.37 An alternative embodiment of the metallization 19 is shown.

[0223] like Fig.37 As shown, the metallization 19 has the shape of a non-circular bridge, the upper surface of which is almost flat.

[0224] The metallization 19 is characterized by its height d1, which separates the layer 15 from the lower surface of the central portion of the metallization 19. The height d1 is, for example, between about 5 μm and about 70 μm, in some embodiments between about 15 μm and about 50 μm.

[0225] Additionally, the metallization 19 is characterized by a thickness d2 across a central (horizontal) portion of the metallization 19. For example, the thickness d2 is between about 20 μm and about 400 μm, and in some embodiments between about 50 μm and about 250 μm.

[0226] In addition, the metallization 19 is characterized by its width d3. For example, the width d3 is between about 20 μm and about 600 μm, and in some embodiments between about 50 μm and about 400 μm.

[0227] Various embodiments and alternatives have been described. Those skilled in the art will appreciate that certain features of these embodiments may be combined, and those skilled in the art will readily appreciate other alternatives. In particular, the first and third embodiments may be combined, and the second and fourth embodiments may also be combined. The described embodiments are not limited to the exemplary dimensions and materials described above.

[0228] Finally, actual implementation of the embodiments and alternatives described herein is within the capabilities of those skilled in the art, based on the functional description provided above.

[0229] The various embodiments described above may be combined to provide additional embodiments. These and other changes may be made to the embodiments in light of the above detailed description. Generally, in the appended claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted as including all possible embodiments and the full range of equivalents to which these claims are entitled. Therefore, the claims are not limited by this disclosure.

Claims

1. A method for manufacturing an electronic chip, comprising: forming a metallization on a first side of a semiconductor substrate, the metallization coupling corresponding contacts of adjacent integrated circuits on the substrate to each other; as well as forming a first trench extending through the first side of the substrate and laterally separating adjacent integrated circuits, the first trench extending through the metallization coupling corresponding contacts of adjacent integrated circuits to form at least a portion of the metallization at each of the adjacent integrated circuits; A layer of a first resin is deposited over the entire first face, the first resin penetrating into the first trenches and covering the portion of the metallization. The method according to claim 1 , wherein the first trench is formed after forming the metallization. 3 . The method of claim 2 , wherein the first trench extends vertically in the substrate to a depth that is greater than a depth of the integrated circuit and less than a thickness of the substrate.

4. The method according to claim 3, further comprising: The first face is planarized until the portion of the metallization is exposed.

5. The method according to claim 4, further comprising: thinning the substrate from a second side of the substrate located opposite to the first side, at least until reaching the first resin; and A layer of a second resin is deposited on the second side. 6 . The method according to claim 4 , wherein the first side is planarized until the portion of the metallization is exposed over a surface area that is sufficient for soldering the chip to a component different from the chip via the first side of the chip.

7. The method according to claim 4, wherein the first face is planarized until the portion of the metallization is exposed over a length of more than 20 μm.

8. A method for manufacturing an electronic chip, comprising: forming a first trench extending through a first surface of a semiconductor substrate, the first trench laterally separating adjacent integrated circuits on the substrate from each other, the first trench extending vertically in the substrate to a depth greater than a depth of the integrated circuits and less than a thickness of the substrate; forming a metallization on the first side of the semiconductor substrate, the metallization coupling corresponding contacts of adjacent integrated circuits on the substrate to each other; as well as A second trench is formed extending through the metallization coupling corresponding contacts of adjacent ones of the integrated circuits to form at least a portion of the metallization at each of the adjacent ones of the integrated circuits.

9. The method according to claim 8, further comprising: A layer of a first resin is deposited across the first face of the substrate, the first resin penetrating into the first trench and covering the portion of the metallization.

10. The method according to claim 8, further comprising: Before forming the first trench, forming a bump vertically aligned with the integrated circuit; Before forming the metallization, depositing a first layer of a first resin over the entire first face, the first resin penetrating into the first grooves and covering the bumps; and The bumps are exposed by planarizing the first layer. The method of claim 10 , wherein the metallization is coupled to the integrated circuit through the bumps.

12. The method according to claim 10, further comprising: A second layer of the first resin is deposited over the first layer of the first resin.

13. The method according to claim 9, further comprising: Each of the metallizations is exposed by planarizing the first face, the metallization being exposed over a length of more than 200 μm.

14. The method according to claim 13, further comprising: forming an opening by partially removing the layer of the first resin at a height less than or equal to the height of the portion of the metallization, the opening being located opposite the second trench and extending over a width greater than or equal to the width of the second trench to release at least part of the flank of each integrated circuit; and The chips are singulated by cutting along a cutting path in the first groove at a width smaller than a width of the first groove.

15. The method according to claim 13, further comprising: thinning the substrate from a second side of the substrate located opposite to the first side, at least until reaching the first resin; and A layer of a second resin is deposited on the second side. 16 . The method of claim 15 , wherein the substrate is thinned from the second side of the substrate before forming the second trench.

17. A method for manufacturing an electronic chip, comprising: forming a plurality of metallizations on a first side of a semiconductor substrate, each of the metallizations coupling corresponding contacts of adjacent integrated circuits on the substrate to each other, the metallizations being spaced apart from the first side of the semiconductor substrate between adjacent integrated circuits; forming a trench extending through the first side of the substrate and laterally separating adjacent integrated circuits, the trench extending through the metallization between adjacent integrated circuits; forming an insulating layer on the first surface of the semiconductor substrate, wherein the insulating layer extends into the trench and between adjacent integrated circuits; as well as The semiconductor substrate is cut along the trench.

18. The method according to claim 17, further comprising: An opening is formed by removing a portion of the insulating layer between portions of the metallization between adjacent integrated circuits, the opening having a width greater than a width of the trench.

19. The method according to claim 18, further comprising: Before forming the opening, the surface of the metallization is partially exposed by planarizing the insulating layer.

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