Embedded substrate

Abstract

The application provides an embedded substrate, comprising: a wafer in a dielectric material of the embedded substrate; a thermoelectric generator arranged beside the wafer in the dielectric material, and a p-type electrode and an n-type electrode of the thermoelectric generator being connected in series. The embedded substrate provided by the application improves the heat dissipation of the embedded substrate.

Description

Technical Field

[0001] Embodiments of the present invention relate to an embedded substrate. Background Technology

[0002] Embedded chip components are widely used in the semiconductor field, and there are many types of chips. When embedding high-heat-generating chips, heat dissipation becomes particularly important. In the case of chips embedded in a substrate, heat sources are conducted towards the metal surfaces, and current technologies cannot effectively solve the heat dissipation problem for functional chips. Summary of the Invention

[0003] In view of the problems existing in related technologies, the purpose of this invention is to provide an embedded substrate to improve the heat dissipation of the embedded substrate.

[0004] To achieve the above objectives, the present invention provides an embedded substrate, comprising: a wafer located in a dielectric material of the embedded substrate; and a thermoelectric generator disposed next to the wafer in the dielectric material, wherein the p-type electrode and the n-type electrode of the thermoelectric generator are connected in series.

[0005] In one embodiment, the device further includes a first wiring structure located above the wafer and the thermoelectric generator. The first wiring structure includes pads located on the surface of the embedded substrate and a first via through the dielectric material to electrically connect the thermoelectric generator to the pads.

[0006] In one embodiment, the thermoelectric generator includes a second through-hole extending laterally, the lateral direction being the direction in which the p-type electrode and the n-type electrode extend, and the first through-hole contacts the second through-hole.

[0007] In one embodiment, the second through hole is a portion of a cylinder extending laterally, with the top surface of the portion parallel to the generatrix of the cylinder, and the first through hole contacting and perpendicular to the top surface.

[0008] In an embodiment, on a cross section perpendicular to the transverse direction, the ratio of the maximum thickness of the second through hole to the maximum width of the second through hole is in the range of 1 / 3 to 1 / 2, and the maximum width is the diameter of the cylinder and is in the range of 5 μm to 20 μm.

[0009] In one embodiment, the diameter of the first via decreases from the pad to the thermoelectric generator.

[0010] In one embodiment, viewed from a top view, multiple thermoelectric generators are arranged around the wafer.

[0011] In an embodiment, the thermoelectric generator includes multiple p-type electrodes and multiple n-type electrodes, with the multiple p-type electrodes located below the multiple n-type electrodes in a one-to-one correspondence.

[0012] In one embodiment, the top surface of the hotspot generator is higher than the top surface of the wafer.

[0013] In one embodiment, the outermost p-type and n-type electrodes of the thermoelectric generator are connected to a metal plate on the side away from the wafer. Attached Figure Description

[0014] Figures 1 to 9 A cross-sectional view is shown of an intermediate process for forming a circuit structure according to an embodiment of this application.

[0015] Figures 10 to 20 A cross-sectional view is shown of an intermediate process for forming a TEG according to an embodiment of this application.

[0016] Figures 21 to 38 A cross-sectional view is shown of an intermediate process for forming an embedded substrate according to an embodiment of this application.

[0017] Figures 39 to 50 A schematic diagram of the embedded substrate according to different embodiments of this application is shown. Detailed Implementation

[0018] To better understand the spirit of the embodiments of this application, the following description is based on some preferred embodiments of this application.

[0019] Embodiments of this application will be described in detail below. Throughout this specification, identical or similar components and components having identical or similar functions are indicated by similar reference numerals. The embodiments described herein with reference to the accompanying drawings are illustrative and diagrammatic in nature and are intended to provide a basic understanding of this application. The embodiments of this application should not be construed as limiting this application.

[0020] As used herein, the terms “approximately,” “generally,” “substantially,” and “about” are used to describe and indicate small variations. When used in conjunction with an event or situation, the terms may refer to examples in which the event or situation occurred precisely and examples in which the event or situation occurred very approximately. For example, when used in conjunction with numerical values, the terms may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two values ​​is less than or equal to ±10% of the average of the values ​​(e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%), then the two values ​​can be considered "substantially" the same.

[0021] In this specification, unless otherwise specified or limited, relative terms such as “central,” “longitudinal,” “lateral,” “front,” “rear,” “right,” “left,” “inner,” “outer,” “lower,” “higher,” “horizontal,” “vertical,” “above,” “below,” “above,” “below,” “top,” “bottom,” and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.) should be interpreted as referring to the directions described in the discussion or depicted in the accompanying drawings. These relative terms are used for descriptive convenience only and do not require that this application be constructed or operated in a particular orientation.

[0022] Additionally, quantities, ratios, and other numerical values ​​are sometimes presented in range format in this document. It should be understood that such range format is for convenience and brevity and should be interpreted flexibly to include not only the numerical values ​​explicitly specified as range limits, but also all individual numerical values ​​or subranges covered within the range, as if each numerical value and subrange were explicitly specified.

[0023] Furthermore, for ease of description, "first," "second," "third," etc., can be used in this article to distinguish different components of a figure or a series of figures. "First," "second," "third," etc., are not intended to describe the corresponding components.

[0024] In substrate design, uneven heat distribution between the thermally active and non-thermally active regions can easily lead to warping and cracking. This invention addresses this by embedding a thermoelectric generator (TEG) within the embedded chip structure. Electrical energy generates a temperature difference within the TEG, with the area closer to the embedded chip being the cooler region. Therefore, the heat generated by the chip can be conducted to the TEG from both sides. This thermoelectric generator (TEG) converts thermal energy into electrical energy to solve heat dissipation, thereby providing a heat transfer effect (replacing a heatsink).

[0025] The embedded substrate of this application will be explained in detail below with reference to the accompanying drawings.

[0026] Reference Figure 1 A first seed layer 12 is formed on the carrier 10. In this embodiment, the first seed layer 12 can be formed by a physical vapor deposition (PVD) process.

[0027] Reference Figure 2 A first mask layer 20 is formed on the first seed layer 12. The first mask layer 20 may include a photoresist (PR) material, and an exposure process 21 is performed to cure the first mask layer 20.

[0028] Reference Figure 3The first mask layer 20 is patterned and a first metal layer 30 is formed in the patterned first mask layer 20.

[0029] Reference Figure 4 Remove the patterned first mask layer 20, and use the first metal layer 30 as a mask to etch the first seed layer 20 so that the first seed layer 20 has the same pattern as the first metal layer 30.

[0030] Reference Figure 5 A first dielectric layer 50 is formed covering the first metal layer 30 and the first seed layer 20. In an embodiment, the first dielectric layer 50 may include a polyamide (PA) material, and the first dielectric layer 50 is subjected to an exposure process 51 for curing.

[0031] See Figure 6 An opening is formed in the first dielectric layer to expose the first metal layer 30, and a second seed layer 60 is formed in the opening and on the first dielectric layer 50.

[0032] See Figure 7 A second mask layer 70 is formed on the second seed layer 60. The second mask layer 70 may include a photoresist (PR) material, and an exposure process 71 is performed to cure the second mask layer 70.

[0033] See Figure 8 The second mask layer 70 is patterned to expose the second seed layer 60. A second metal layer 80 is then formed on the exposed second seed layer 60.

[0034] See Figure 9 The patterned second mask layer 70 is removed, and the second seed layer 60 is etched using the second metal layer 80 as a mask so that the second seed layer 60 has the same pattern as the second metal layer 80. This is to form the first circuit structure 90 on the first carrier 10.

[0035] See Figure 10 A first plate 100 is provided. In an embodiment, the first plate 100 comprises aluminum.

[0036] See Figure 11 A second dielectric layer 110 is formed covering the first plate 100. In an embodiment, the second dielectric layer 110 may include a polyamide (PA) material, and an exposure process 111 is performed on the second dielectric layer 110 to cure it.

[0037] See Figure 12The second dielectric layer 110 is patterned to form a first opening 121, a second opening 122, and a third opening 123 that are sequentially adjacent. The first thermoelectric material 124 is filled into the first opening 121 using a third mask 120 and an extrusion tool 125, wherein the opening of the third mask 120 is aligned with the first opening 121.

[0038] See Figure 13 The second thermoelectric material 134 is filled into the second opening 122 using a fourth mask 130 and an extrusion tool 125, wherein the opening of the fourth mask 130 is aligned with the second opening 122. In one embodiment, the first thermoelectric material 124 is a P-type material and the second thermoelectric material 125 is an N-type material. In other embodiments, the first thermoelectric material 124 is an N-type material and the second thermoelectric material 125 is a P-type material.

[0039] See Figure 14 A third seed layer 140 is formed in the third opening 123 and on the second dielectric layer 110. In an embodiment, the third seed layer 140 can be formed by a physical vapor deposition (PVD) process.

[0040] Reference Figure 15 A fifth mask layer 150 is formed on the third seed layer 140. The fifth mask layer 150 may include a photoresist (PR) material, and an exposure process 151 is performed to cure the fifth mask layer 150.

[0041] See Figure 16 The fifth mask layer 150 is patterned to expose the third seed layer 140. A third metal layer 160 is then formed on the exposed third seed layer 140.

[0042] See Figure 17 The patterned fifth mask layer 150 is removed, and the third seed layer 140 is etched using the third metal layer 160 as a mask so that the third seed layer 140 has the same pattern as the third metal layer 160. This forms the second circuit structure 170.

[0043] See Figure 18 A third dielectric layer 180 is formed covering the second circuit structure 170. In an embodiment, the third dielectric layer 180 may include a polyamide (PA) material, and an exposure process 181 is performed on the third dielectric layer 180 to cure it.

[0044] See Figure 19 The steps of forming thermoelectric material in the dielectric layer are repeated to form a plurality of circuit structures similar to the second circuit structure 170, and finally to form a thermoelectric generator (TEG) structure 190.

[0045] See Figure 20A cutting process 212 is performed on the TEG structure to obtain a monolithic TEG 200. The cutting process 212 exposes the third seed layer 140 and the third metal layer 160 to form a second through-hole 202.

[0046] See Figure 21 A second carrier 210 is provided, and a jig 214 is used to place the wafer 212 on the second carrier 210. During the clamping process, the jig 214 and the wafer 212 are in a vacuum state.

[0047] See Figure 22 The TEG200 is placed on the second carrier 210 and next to the chip 210.

[0048] See Figure 23 A packaging layer 230 is formed on the wafer 210 and TEG200, and the first carrier 10 and the first circuit structure 90 are placed on the wafer 210 and TEG200 in a flip-chip manner.

[0049] See Figure 24 The first circuit structure 90 is bonded to the encapsulation layer 230, and the first carrier 10 is removed. (See also 50) Figure 25 Laser processing 250 is applied to the first circuit structure 90 to form a shape such as Figure 26 The opening shown partially exposes the second via 202 of TEG200, partially exposes the wafer pads 262 of wafer 212, and partially exposes the second seed layer 60 of the first circuit structure 90. A fourth seed layer 260 is formed in the opening and on the first circuit structure 90.

[0050] Reference Figure 27 A sixth mask layer 270 is formed on the fourth seed layer 260. The sixth mask layer 270 may include a photoresist (PR) material, and an exposure process 271 is performed to cure the sixth mask layer 270.

[0051] See Figure 28 The sixth mask layer 270 is patterned to expose the fourth seed layer 260. A fourth metal layer 280 is then formed on the exposed fourth seed layer 260.

[0052] See Figure 29 Remove the patterned sixth mask layer 270, and use the fourth metal layer 280 as a mask to etch the fourth seed layer 260 so that the fourth seed layer 260 has the same pattern as the fourth metal layer 280 to form the first via 290.

[0053] See Figure 30 Remove the second carrier 210.

[0054] See Figure 31A fifth seed layer 310 is formed on the surface exposed after the removal of the second carrier 210.

[0055] Reference Figure 32 A seventh mask layer 320 is formed on the fifth seed layer 310. The seventh mask layer 320 may include a photoresist (PR) material, and an exposure process 321 is performed to cure the seventh mask layer 320.

[0056] See Figure 33 The seventh mask layer 320 is patterned to expose the fifth seed layer 310. A fifth metal layer 330 is then formed on the exposed fifth seed layer 310.

[0057] See Figure 34 The patterned seventh mask layer 320 is removed, and the fifth seed layer 310 is etched using the fifth metal layer 330 as a mask so that the fifth seed layer 310 has the same pattern as the fifth metal layer 330. A fourth dielectric layer 340 is formed covering the fifth metal layer 330. In an embodiment, the fourth dielectric layer 340 may include a polyamide (PA) material, and an exposure process 341 is performed on the fourth dielectric layer 340 to cure it.

[0058] See Figure 35 An opening is formed in the fourth dielectric layer 340 to expose the fifth metal layer 330, and a sixth seed layer 350 is formed in the opening and on the fourth dielectric layer 340.

[0059] See Figure 36 An eighth mask layer 360 is formed on the sixth seed layer 350. The eighth mask layer 360 may include a photoresist (PR) material, and the eighth mask layer 360 is cured by an exposure process 361.

[0060] See Figure 37 The eighth mask layer 360 is patterned to expose the sixth seed layer 350. A sixth metal layer 370 is then formed on the exposed sixth seed layer 350.

[0061] See Figure 38 The patterned eighth mask layer 360 is removed, and the sixth seed layer 350 is etched using the sixth metal layer 370 as a mask so that the sixth seed layer 350 has the same pattern as the sixth metal layer 370. This ultimately forms the embedded substrate 3800 of the embodiment of this application. In this embodiment, the total thickness of the embedded substrate 3800 is less than 100 μm.

[0062] refer to Figure 39 Compared to Figure 38 The embedded substrate 3800 and embedded substrate 3900 shown also include a sub-substrate 390 below the TEG200.

[0063] refer to Figure 40 Compared to Figure 38 , Figure 38 The TEG200 in the embedded substrate 3800 shown includes a single unit, while the TEG200 in the embedded substrate 4000 includes multiple units.

[0064] refer to Figure 41 The embedded substrate 4100 uses bumps 410 to connect the wafer 212 and the first circuit layer 90. In an embodiment, the bumps 410 include microbumps or solder.

[0065] refer to Figure 42 The embedded substrate 4200 also uses lead 420 to electrically connect the first via 290 to TEG 200.

[0066] refer to Figures 43A to 43B The top view shown, in which, Figure 43A In the illustrated embodiment, TEG200 is a block structure disposed around wafer 212. Figure 43B In the illustrated embodiment, TEG200 is a ring structure surrounding wafer 212. The encapsulation layer 230 may include organic dielectrics, such as bismaleimide triazine resin (BT), Ajinomoto build-up film (ABF), polyimide (PI), photosensitive epoxy resin, and / or non-photosensitive liquids and / or dry films including fibers; dielectrics including fibers; inorganic materials, such as oxides (SiOx, SiNx, TaOx), glass, silicon, ceramic materials, etc.

[0067] refer to Figure 44 The embedded substrate 4400 includes a side-mounted chip 212.

[0068] refer to Figure 45 The embedded substrate 4500 includes multiple chips 212.

[0069] refer to Figure 46 The embedded substrate 4600 includes multiple TEG200s arranged side by side.

[0070] This invention provides an embedded substrate 3800, reference Figure 38 It includes: a wafer 212 located in the dielectric material (encapsulation layer 230) of an embedded substrate 3800; and a thermoelectric generator 200 disposed next to the wafer 212 within the dielectric material, wherein the p-type electrode and n-type electrode of the thermoelectric generator 200 are connected in series. See also Figure 47The diagram shows an enlarged view of the electrodes of the TEG200, where the p-type electrodes are formed of a first thermoelectric material 124 and the n-type electrodes are formed of a second thermoelectric material 125. In an embodiment, the thermoelectric generator 200 includes multiple p-type electrodes and multiple n-type electrodes, with the p-type electrodes located one-to-one below the n-type electrodes. In another embodiment, the outermost p-type and n-type electrodes of the thermoelectric generator are connected to a metal plate (first plate 100) on the side away from the wafer. The p-type and n-type electrodes in the TEG200 are arranged in series. Heat is used to generate electrical energy through the multiple p-type and n-type electrodes.

[0071] In an embodiment, the device further includes a first circuit structure 90 located above the wafer 212 and the thermoelectric generator 200. The first circuit structure 90 includes a pad 291 (a portion of the fourth seed layer 260 and the fourth metal layer 280 exposed on the upper surface of the circuit layer 90) located on the surface of the embedded substrate, and a first via 290 passing through the dielectric material to electrically connect the thermoelectric generator to the pad.

[0072] In the embodiment, reference Figure 48 The thermoelectric generator 200 includes a second through hole 202 extending laterally, which is the direction in which the p-type electrode and the n-type electrode extend, and a first through hole 290 contacts the second through hole 202.

[0073] In the embodiment, reference Figure 49 The second through-hole 202 is a portion of a cylinder extending laterally, with its top surface parallel to the generatrix of the cylinder. The first through-hole 290 contacts and is perpendicular to the top surface. In an embodiment, in a cross-section perpendicular to the lateral direction, the ratio of the maximum thickness 202t of the second through-hole 202 to its maximum width is between 1 / 3 and 1 / 2, and the maximum width is the diameter D of the cylinder and is between 5 μm and 20 μm. In an embodiment, the diameter of the first through-hole 290 decreases from the pad to the thermoelectric generator 200. In an embodiment, the diameter 290d of the bottom portion of the first through-hole 290 is between 5 μm and 200 μm.

[0074] In one embodiment, the top surface of the thermoelectric generator 200 is higher than the top surface of the wafer 212. In another embodiment, viewed from a top view, multiple thermoelectric generators 200 are arranged around the wafer 212. (Reference) Figure 50 It includes multiple TEG200s, chip 212, substrate body 500, and through-hole structures in substrate body 500. Substrate body 500 and encapsulation layer 230 use several organic materials, such as ABF, PI, BT, resin and / or epoxy resin.

[0075] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An embedded substrate, characterized in that, include: The wafer is located in the dielectric material of the embedded substrate; A thermoelectric generator, disposed in the dielectric material adjacent to the wafer, wherein the p-type electrode and n-type electrode of the thermoelectric generator are connected in series; and A first wiring structure is located above the wafer and the thermoelectric generator. The first wiring structure includes pads located on the surface of the embedded substrate and a first via penetrating the dielectric material to electrically connect the thermoelectric generator to the pads. The thermoelectric generator includes a second through hole extending laterally, the lateral direction being the direction in which the p-type electrode and the n-type electrode extend, and the first through hole contacts the second through hole.

2. The embedded substrate according to claim 1, characterized in that, The second through hole is a portion of a cylinder extending laterally, the top surface of the portion being parallel to the generatrix of the cylinder, and the first through hole contacting and perpendicular to the top surface.

3. The embedded substrate according to claim 2, characterized in that, In a cross section perpendicular to the transverse direction, the ratio of the maximum thickness of the second through hole to the maximum width of the second through hole is between 1 / 3 and 1 / 2, and the maximum width is the diameter of the cylinder and is between 5 μm and 20 μm.

4. The embedded substrate according to claim 1, characterized in that, From the pad to the thermoelectric generator, the diameter of the first through hole decreases.

5. The embedded substrate according to claim 1, characterized in that, Viewed from above, multiple thermoelectric generators are arranged around the wafer.

6. The embedded substrate according to claim 1, characterized in that, The thermoelectric generator includes a plurality of p-type electrodes and a plurality of n-type electrodes, with the plurality of p-type electrodes located below the plurality of n-type electrodes in a one-to-one correspondence.

7. The embedded substrate according to claim 1, characterized in that, The top surface of the thermoelectric generator is higher than the top surface of the wafer.

8. The embedded substrate according to claim 1, characterized in that, The outermost p-type electrode and n-type electrode of the thermoelectric generator are connected to a metal plate on the side away from the wafer.

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