A superjunction structure for high-speed circuits

Abstract

The present invention discloses a superjunction structure in a high-speed circuit, which is applied to the field of semiconductor integrated circuits, and includes an N-type region and a P-type substrate; the number of the N-type regions is n, n>2, and n is a positive integer, and the N-type region is arranged on the P-type substrate below the metal interconnection of the high-speed signal channel, and the N-type region and the P-type substrate form a PN junction. The present invention does not add additional process levels, and can reduce the parasitic capacitance of the metal of the signal channel of the high-speed switch integrated circuit to the substrate at low cost and high efficiency.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuits, and in particular to a super junction structure in a high-speed circuit. Background Art

[0002] With the advent of the 5G era, portable mobile communications are developing more rapidly, and the frequency and bandwidth requirements for signal transmission circuits are getting higher and higher. Various high-frequency integrated circuits are constantly improving their frequency bandwidth performance. At the same time, in order to meet the requirements of various portable products for light, thin and small size, data transmission stability, and integration, the scale of integrated circuits is getting larger and larger. The trend of bandwidth improvement and integration has put forward higher requirements for high-speed integrated circuits to reduce signal attenuation. In the high-speed signal transmission channel, any capacitance to the ground will attenuate the high-speed signal and reduce the frequency bandwidth performance of the signal that can pass. Therefore, making the metal wires of the high-speed signal channel of the high-frequency circuit as narrow and short as possible is a way to reduce the capacitance to the ground. However, due to the requirements of integration, most high-speed circuits contain several or even dozens of high-frequency signal paths, and narrow and short metal routing is simply impossible to achieve.

[0003] In the prior art, the method to reduce the parasitic capacitance is usually to use the top metal for the high-speed channel interconnection line, and to increase the number of chip interconnection metal layers, such as using 5 or 6 layers of metal, so that the thickness of the interlayer dielectric between the top metal interconnection line and the substrate ground is increased, and the capacitance can be reduced. However, this method has high process costs and sharply increases the chip cost. In addition, there is also a technology that makes a PN junction directly below the metal routing line and introduces a series PN junction capacitor to reduce the capacitance to the substrate, but the effect of reducing parasitic capacitance is limited; there is also a technology that adds a deep trench with dielectric filling to reduce the parasitic capacitance of the high-speed channel routing to the ground, but its process is complicated.

[0004] Therefore, it is an urgent problem for those skilled in the art to propose a high-speed circuit structure that effectively reduces parasitic capacitance, has a simple process and is low in cost. Summary of the invention

[0005] In view of this, the present invention provides a super junction structure in a high-speed circuit, which has the technical effects of limited reduction of parasitic capacitance, simple process and low cost.

[0006] In order to achieve the above object, the present invention adopts the following technical solution:

[0007] A superjunction structure in a high-speed circuit includes an N-type region and a P-type substrate;

[0008] The number of N-type regions is n, where n>2 and n is a positive integer. The N-type regions are arranged on a P-type substrate below the metal interconnection of the high-speed signal channel, and a PN junction is formed between the N-type regions and the P-type substrate.

[0009] Preferably, the N-type region is a deep N-well, an N-well, or a deep well with an N-type buried layer (NBL).

[0010] Preferably, the N-type region is a strip-shaped N-type region or a unit-shaped N-type region.

[0011] Preferably, the strip-shaped N-type region and the high-speed signal channel metal line are arranged in an orthogonal manner.

[0012] Preferably, the unit-shaped N-type regions are distributed in a unit-shaped manner at a certain interval on the P-type substrate.

[0013] Preferably, the unit pattern of the unit-shaped N-type region may be circular, octagonal, hexagonal or rectangular, etc.

[0014] Preferably, the junction depth of the N-type region is in the range of 1 μm-7 μm, the width is in the range of 0.2 μm-5 μm, and the spacing is in the range of 3 μm-10 μm.

[0015] Preferably, two ends of the strip-shaped N-type region are active regions connected to a bias voltage.

[0016] Preferably, the unit-shaped N-type region is connected to the entire N-type buried layer, and then the active region is led out from the non-high-speed signal channel position and connected to the bias voltage.

[0017] Preferably, the N-type region is connected to a potential higher than that of the substrate through a resistor.

[0018] Preferably, the bias potential range of the N-type region is 0V-45V.

[0019] Preferably, when the N-type region is connected to a high bias potential, the resistance of the series resistor is greater than or equal to 1 Kohm.

[0020] It can be seen from the above technical solutions that, compared with the prior art, the present invention provides a super junction structure in a high-speed circuit: the present invention forms a thin strip PN junction or a unit distributed pattern orthogonal to the high-speed signal channel on the substrate below the high-speed signal channel metal interconnection line, and at the same time, by biasing the PN junction with a reverse bias voltage, uses the charge balance theory to form a lateral full depletion of the N-type region to the substrate surface and a certain junction depth, thereby reducing the parasitic capacitance between the top signal channel metal interconnection line and the substrate ground; by adjusting and optimizing the N-type region pattern width and spacing, increasing the bias voltage can achieve full depletion of the PN junction below the metal line; according to different N-type region junction depths, this method can achieve a reduction of more than 50% in the parasitic capacitance of the high-speed signal metal channel ground; without adding additional process levels, the parasitic capacitance of the high-speed switch integrated circuit signal channel metal to the substrate is reduced at low cost and efficiently. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0022] Figure 1 It is a metal top view of a high-speed switch signal channel in the prior art;

[0023] Figure 2 for Figure 1 Cross-section along the A-A' direction;

[0024] Figure 3 A top view of the super junction structure of the strip-shaped N-type region of the present invention;

[0025] Figure 4 for Figure 3 Cross-section along the A-A' direction;

[0026] Figure 5 A schematic diagram of a depletion layer of a super junction structure of a strip-shaped N-type region of the present invention;

[0027] Figure 6 A top view of the superjunction structure of a unit-shaped N-type region of the present invention; DETAILED DESCRIPTION

[0028] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0029] like Figure 1 The figure shows a top view of the metal of the high-speed switch signal channel of the prior art. The top metal 1 of the high-speed switch signal channel is connected from the input pin A to the high-speed switch MOS tube 4 (replaced by a box because it is not involved in the patent description) and then to the output pin A'; a P-well 2 is added around the metal routing of the high-speed channel, and a deep N-well 3 is provided outside the P-well 2. Figure 2 for Figure 1The longitudinal cross-sectional view along the line segment from point A to point A' shows the top metal 1 of the high-speed channel line, the P-type substrate 11, the dielectric thickness d2 between the top metal 1 and the P-well 2, the parasitic capacitance C1 from the top metal 1 to the P-well 2, the bias potential lead-out terminal 18 of the P-well 2; the bias potential lead-out terminal 17 of the deep N-well 3; the high-speed switch MOS tube 4, the shallow trench isolation dielectric 5, the metal one 6, the metal two 7, the lower dielectric layer 12, the lower metal interlayer dielectric layer 13, and the metal interlayer dielectric layer 8 below the top metal 1.

[0030] Depend on Figure 1 and 2 It can be seen that the P-well 2 and deep N-well 3 under the top metal interconnection line 1 of the high-speed channel introduce two PN junction capacitors, one is the PN junction capacitor C2 from the deep N-well 3 to the P-type substrate 11, and the other is the PN junction C3 between the P-well 2 and the deep N-well 3. The capacitance from the top metal interconnection line 1 to the P-type substrate 11 is only the dielectric capacitance, which becomes the dielectric capacitor C2 connected in series with C3 and C4, that is, the total capacitance to ground Ctotal is reduced from C2 to C1*C2*C3 / (C1C2+C2C3+C1C3). This is the idea of ​​reducing capacitance by introducing a series PN junction in the prior art.

[0031] The present application discloses a superjunction structure in a high-speed circuit, comprising an N-type region and a P-type substrate;

[0032] The number of N-type regions is n, where n>2 and n is a positive integer. The N-type regions are arranged on a P-type substrate below the metal interconnection of the high-speed signal channel, and a PN junction is formed between the N-type regions and the P-type substrate.

[0033] In a specific embodiment, the N-type region is a deep N-well, an N-well, or a deep well with an N-type buried layer.

[0034] In a specific embodiment, the N-type region is a stripe-shaped N-type region or a unit-shaped N-type region.

[0035] In a specific embodiment, the strip-shaped N-type region and the high-speed signal channel metal line are arranged orthogonally.

[0036] In a specific embodiment, the N-type region has a junction depth ranging from 1 μm to 7 μm, a width ranging from 0.2 μm to 5 μm, and a spacing ranging from 3 μm to 10 μm.

[0037] In a specific embodiment, the unit-shaped N-type regions are distributed in a unit-shaped manner at a certain interval on the P-type substrate.

[0038] In a specific embodiment, two ends of the strip-shaped N-type region are active regions connected to a bias voltage.

[0039] In a specific embodiment, the unit-shaped N-type region is connected to the entire N-type buried layer, and then the active region is led out from the non-high-speed signal channel position and connected to the bias voltage.

[0040] In a specific embodiment, the unit pattern of the unit-shaped N-type region can be circular, octagonal, hexagonal, rectangular, etc.

[0041] In a specific embodiment, the N-type region is connected to a potential higher than the substrate through a resistor.

[0042] In a specific embodiment, the bias potential range of the N-type region is 0V-45V; when the N-type region is connected to a high bias potential, the resistance value of the series resistor is greater than or equal to 1Kohm.

[0043] In a specific embodiment, Figure 3 As shown, a top view of a super junction structure of a strip N region is disclosed, the top metal 1 of the high-speed switch signal channel, the deep well B2 under the pressure pad metal of the high-speed signal channel and the deep N well B3 under the metal channel routing are arranged orthogonally to the top metal 1 of the high-speed switch signal channel, and the switch MOS tube 4 (since it is not related to the description of this patent, it is replaced by a box), as shown Figure 4 As shown, the N-type region starts from the bottom of the shallow trench isolation dielectric 5 and ends inside the P-type substrate 11; Figure 5 As shown, it is a schematic diagram of the depletion layer when the deep well B2 under the metal pad of the high-speed signal channel and the deep N-well B3 under the metal channel routing are biased to a high potential, the depletion layer boundary 9 in the N-well, and the depletion layer boundary 10 in the P substrate. When a certain high voltage is applied, the deep N-well and the P-well between them will reach charge balance and be completely depleted. At this time, the surface of the silicon substrate under the metal interconnection line of the high-speed signal channel is completely a depletion layer to a certain depth, and its capacitance to the substrate becomes the depletion layer capacitance C4 of the dielectric capacitance series super junction, thereby achieving the effect of greatly reducing the parasitic capacitance of the channel metal to the substrate ground.

[0044] In a specific embodiment, Figure 6 Shown is a top view of the super junction structure of a unit-shaped N-type region.

[0045] In addition, the superjunction PN junction of this patent is not limited to deep N-well and substrate, but can also be any N-well and P-well pattern. As long as the superjunction concept is utilized, through distributed strip or unit-shaped PN junction patterns, after reverse bias, the lateral depletion layer is fully expanded to form a vertical thick depletion layer space charge region in the substrate, thereby forming a series connection of depletion layer capacitance so that the metal-to-substrate capacitance is greatly reduced. All methods fall within the scope of the claims of this patent.

[0046] The above description of the disclosed embodiments is provided in a progressive manner to enable those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A superjunction structure in a high-speed circuit, characterized in that: including an N-type region and a P-type substrate; The number of N-type regions is n, n>2, n is a positive integer, the N-type region is arranged on the P-type substrate below the high-speed signal channel metal interconnection, the N-type region forms a PN junction with the P-type substrate, and the N-type region is a deep N-well, an N-well, or a deep well with an N-type buried layer; The N-type region is a strip-shaped N-type region or a unit-shaped N-type region; The N-type region is arranged orthogonally to the high-speed signal channel metal wires; The N-type region under the pad metal of the high-speed signal channel and the N-type region under the metal channel routing are arranged orthogonally and spaced apart from the top metal of the high-speed switch signal channel.

2. The super junction structure in a high-speed circuit according to claim 1, characterized in that: Both ends of the strip-shaped N-type region are active regions connected to a bias voltage.

3. The super junction structure in a high-speed circuit according to claim 1, characterized in that: The unit-shaped N-type regions are distributed in a unit-shaped manner at a certain interval on the P-type substrate.

4. The super junction structure in a high-speed circuit according to claim 3, characterized in that: The unit-shaped N-type region is connected to the entire N-type buried layer, and then the active region is led out from the non-high-speed signal channel position and connected to the bias voltage.

5. A super junction structure in a high-speed circuit according to any one of claims 1 to 4, characterized in that: The junction depth of the N-type region ranges from 1 -7 , width range is 0.2 -5 , the spacing range is 3 -10 .

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