Semiconductor module

Abstract

To provide a semiconductor module capable of more accurately performing a temperature detection.SOLUTION: A semiconductor module 1 includes: first to fourth semiconductor elements Q1 to Q4; a plurality of wiring patterns; a first power supply terminal 51; second power supply terminals 52 and 53; a first midpoint terminal 61; and a second midpoint terminal 62, in which a full bridge circuit is configured. The semiconductor module 1 further includes: a temperature detection element 90; first and second temperature detection wiring patterns 93 and 94; and first and second temperature detection terminals T1 and T2. The temperature detection element 90 is disposed in a region surrounded by a first switching path A and a second switching path B, and is configured to reduce noise based on a parasitic capacitance between a second wiring pattern 20 and the first temperature detection wiring pattern 93 and the parasitic capacitance between a fourth wiring pattern 40 and the first temperature detection wiring pattern 93.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a semiconductor module. [Background technology]

[0002] BACKGROUND ART Conventionally, in the technical field of semiconductor modules, semiconductor modules equipped with a temperature detection element (for example, a thermistor) have been known (see Non-Patent Document 1).

[0003] 14, a conventional semiconductor module 900 is a semiconductor module including an inverter circuit 910, and further including a thermistor 920 on the periphery thereof. According to the conventional semiconductor module 900, the thermistor 920 makes it possible to detect the temperature inside the semiconductor module 900. [Prior art documents] [Non-patent literature]

[0004] [Non-Patent Document 1] IGBT module T series CM35MXUA-24T datasheet, [online], Mitsubishi Electric Corporation, [searched March 1, 2024], Internet, <URL:https: / / www.mitsubishielectric.co.jp / semiconductors / powerdevices / datasheets / igbt / t_series / cm35mxua-24t_e.pdf> Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the technical field of semiconductor modules, there is a demand for more accurate temperature detection within semiconductor modules. For example, semiconductor modules using wide bandgap semiconductor elements (e.g., SiC semiconductor elements) are used at higher power than semiconductor modules using silicon semiconductor elements, and therefore tend to generate more heat and operate at higher temperatures. For this reason, semiconductor modules using wide bandgap semiconductor elements require more accurate temperature detection. Temperature control of semiconductor modules is a universally important technology in the technical field of semiconductor modules. For this reason, the benefits of more accurate temperature detection can also be enjoyed by semiconductor modules using silicon semiconductor elements.

[0006] SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has as its object to provide a semiconductor module that is capable of detecting temperature more accurately than conventional semiconductor modules. [Means for solving the problem]

[0007] [1] A semiconductor module according to one embodiment of the present invention is a semiconductor module comprising first to fourth semiconductor elements, a plurality of wiring patterns, a first power supply terminal, a second power supply terminal, a first neutral terminal, and a second neutral terminal, and comprising a full bridge circuit in which the first semiconductor element and the third semiconductor element are on the high side and the second semiconductor element and the fourth semiconductor element are on the low side, the semiconductor module further comprising: a temperature detection element having a first temperature detection electrode and a second temperature detection electrode; a first temperature detection wiring pattern connected to the first temperature detection electrode; a first temperature detection terminal which is a terminal for connecting to a temperature detection circuit and connected to the first temperature detection wiring pattern; a second temperature detection wiring pattern connected to the second temperature detection electrode; and a second temperature detection terminal which is a terminal for connecting to a ground or a control system power supply and connected to the second temperature detection wiring pattern; wherein a first switching path is a current path including a first current path from the first power supply terminal to the first neutral terminal and a second current path from the second neutral terminal to the second power supply terminal, and a second switching path is a current path that is a current path when the third semiconductor element and the second semiconductor element are both turned on and includes a third current path from the first power supply terminal to the second neutral terminal and a fourth current path from the first neutral terminal to the second power supply terminal, the temperature detection element is disposed in a region surrounded by the first switching path and the second switching path, and is configured to reduce noise due to parasitic capacitance between a wiring pattern that forms a common portion of the first current path and the fourth current path and the first temperature detection wiring pattern, and parasitic capacitance between a wiring pattern that forms a common portion of the second current path and the third current path and the first temperature detection wiring pattern.

[0008] [2] Furthermore, in a semiconductor module according to one embodiment of the present invention, the plurality of wiring patterns include a first wiring pattern on which the first semiconductor element is mounted and the first power supply terminal is connected, a second wiring pattern on which the second semiconductor element is mounted and the first midpoint terminal is connected, a third wiring pattern on which the third semiconductor element is mounted and the first power supply terminal is connected, and a fourth wiring pattern on which the fourth semiconductor element is mounted and the second midpoint terminal is connected, and it is preferable that the first temperature detection wiring pattern is disposed between the second wiring pattern and the fourth wiring pattern when the semiconductor module is viewed in a plane.

[0009] [3] Furthermore, in a semiconductor module according to one embodiment of the present invention (the semiconductor module of [2] above), it is preferable that the distance between the first temperature detection wiring pattern and the second wiring pattern is equal to the distance between the first temperature detection wiring pattern and the fourth wiring pattern.

[0010] [4] Furthermore, in a semiconductor module according to one embodiment of the present invention (the semiconductor module of [2] above), it is preferable that the second power supply terminal is a terminal for connecting to the ground, the plurality of wiring patterns further include a fifth wiring pattern to which the second power supply terminal is connected, and the fifth wiring pattern has an extension portion that extends in the direction in which the first temperature detection wiring pattern is arranged.

[0011] [5] Furthermore, in a semiconductor module according to one embodiment of the present invention (the semiconductor module of [2] above), it is preferable that the second temperature detection wiring pattern is arranged between the first temperature detection wiring pattern and the second wiring pattern, or between the first temperature detection wiring pattern and the fourth wiring pattern, and that the semiconductor module further includes a capacitive coupling reduction wiring pattern arranged on the side between the first temperature detection wiring pattern and the second wiring pattern and between the first temperature detection wiring pattern and the fourth wiring pattern, on the side where the second temperature detection wiring pattern is not arranged.

[0012] [6] In the semiconductor module according to one embodiment of the present invention (the semiconductor module according to [5] above), it is preferable that the capacitive coupling reducing wiring pattern is connected to the ground.

[0013] [7] Furthermore, in a semiconductor module according to one embodiment of the present invention (the semiconductor module of [6] above), it is preferable that the second power supply terminal is a terminal for connecting to the ground, the plurality of wiring patterns further include a fifth wiring pattern to which the second power supply terminal is connected, and the capacitive coupling reduction wiring pattern is connected to the fifth wiring pattern.

[0014] [8] Furthermore, in a semiconductor module according to one embodiment of the present invention (the semiconductor module of [2] above), when the semiconductor module is viewed in a plane, the first temperature detection wiring pattern and the first temperature detection terminal are arranged at a position overlapping a predetermined axis of symmetry, and at least a portion of the first temperature detection terminal and the first temperature detection wiring pattern have a shape that is linearly symmetrical with respect to the predetermined axis of symmetry, and it is preferable that the configuration consisting of the first to fourth semiconductor elements, the first to fourth wiring patterns, the first power supply terminal, the second power supply terminal, the first midpoint terminal and the second midpoint terminal, which are components of the semiconductor module, is linearly symmetrical with respect to the predetermined axis of symmetry. [Effects of the Invention]

[0015] In the semiconductor module of the present invention, the temperature detection element is disposed in an area surrounded by the first switching path and the second switching path in the full bridge circuit and close to the semiconductor element that is the heat source, thereby enabling the semiconductor module of the present invention to perform temperature detection more accurately than conventional semiconductor modules.

[0016] The semiconductor module of the present invention is configured to reduce noise due to "parasitic capacitance between the wiring pattern forming the common portion of the first current path and the fourth current path and the first temperature detection wiring pattern" and "parasitic capacitance between the wiring pattern forming the common portion of the second current path and the third current path and the first temperature detection wiring pattern." Therefore, according to the semiconductor module of the present invention, the parasitic capacitance between the first temperature detection wiring pattern and the first current path on the first switching path and the parasitic capacitance between the first temperature detection wiring pattern and the second current path on the first switching path are balanced, thereby reducing noise generated during switching. Furthermore, according to the semiconductor module of the present invention, the parasitic capacitance between the first temperature detection wiring pattern and the third current path on the second switching path and the parasitic capacitance between the first temperature detection wiring pattern and the fourth current path on the second switching path are balanced, thereby reducing noise generated during switching. As a result, the semiconductor module of the present invention stabilizes the output voltage of the temperature detection element, enabling more stable temperature detection. [Brief explanation of the drawings]

[0017] [Figure 1] 1 is a plan view of the internal configuration of the semiconductor module 1 according to embodiment 1. In Fig. 1, in order to show the internal configuration of the semiconductor module 1, only the outer edge of the sealing material M is shown, and portions that overlap with other components are not shown. The same applies to other plan views of the internal configuration, explanatory diagrams of current paths, and enlarged views of main parts, which will be described later. [Figure 2] FIG. 2 is an enlarged view of a main part of FIG. 1. [Figure 3] 1 is an equivalent circuit diagram of a semiconductor module 1 according to a first embodiment. [Figure 4]4 is an explanatory diagram of a current path of the semiconductor module 1 according to the embodiment 1. Note that Fig. 4 is a diagram in which a current path is added to the semiconductor module 1 shown in Fig. 1, and the configuration of the semiconductor module in Fig. 4 is the same as that in Fig. 1. However, in Fig. 4, some of the reference numerals indicating the components shown in Fig. 2 are omitted, and the reference numerals of the components necessary for explaining the current path are mainly shown. [Figure 5] 10 is a plan view of the internal configuration of a semiconductor module 2 according to a second embodiment. FIG. [Figure 6] FIG. 6 is an enlarged view of a main part of FIG. 5. [Figure 7] 10 is a plan view of the internal configuration of a semiconductor module 3 according to a third embodiment. FIG. [Figure 8] FIG. 8 is an enlarged view of a main part of FIG. 7. [Figure 9] 10 is a plan view of the internal configuration of a semiconductor module 4 according to a fourth embodiment. FIG. [Figure 10] FIG. 10 is an enlarged view of a main part of FIG. 9. [Figure 11] FIG. 2 is a plan view of the internal configuration of a semiconductor module 1A according to a comparative example. [Figure 12] FIG. 10 is an explanatory diagram of a current path in a semiconductor module 1A according to a comparative example. [Figure 13]13 is a graph showing noise characteristics of a semiconductor module 3 according to embodiment 3 and a semiconductor module 1A according to a comparative example. In FIG. 13, the upper, middle, and lower graphs are displayed vertically so that the horizontal axes (time) of the graphs are aligned. The upper graph (graph labeled "Q2") is a graph showing fluctuations in the voltage V and current I of the second semiconductor element Q2 when the full-bridge circuit is operating. The middle graph (graph labeled "Q4") is a graph showing fluctuations in the voltage V and current I of the fourth semiconductor element Q4 when the full-bridge circuit 100 is operating. The lower graph (graph labeled "1A" and "1") is a graph showing fluctuations in the voltage of the first temperature detection path TP1 when the full-bridge circuit is operating. The lower graph is divided into two graphs. The graph labeled "1A" is a graph showing fluctuations in voltage in the semiconductor module 1A according to the comparative example. The graph labeled "3" is a graph showing voltage fluctuations in the semiconductor module 3 according to embodiment 3. Voltage values ​​are shown at the left end of each graph, and current values ​​are shown at the right end of the upper and lower graphs. [Figure 14] FIG. 1 is an equivalent circuit diagram of a conventional semiconductor module 900. DETAILED DESCRIPTION OF THE INVENTION

[0018] The semiconductor module of the present invention will be described below based on the embodiments shown in the drawings. In the embodiments described below, components having the exact same or substantially the same functions will be designated by common reference numerals in the respective embodiments, even if their shapes are slightly different, and descriptions already given may be omitted. The embodiments described below do not limit the invention according to the claims. Furthermore, not all of the elements and combinations thereof described in the respective embodiments are necessarily essential to the solution of the present invention.

[0019] [Embodiment 1] 1. Configuration of semiconductor module 1 1 and 2, the semiconductor module 1 according to the first embodiment includes first to fourth semiconductor elements Q1 to Q4, multiple wiring patterns, a first power supply terminal 51, second power supply terminals 52 and 53, a first midpoint terminal 61, and a second midpoint terminal 62. The multiple wiring patterns include first to fifth wiring patterns 10 to 50 through which a main current (large current) flows. In the semiconductor module 1, a full-bridge circuit 100 is configured in which the first semiconductor element Q1 and the third semiconductor element Q3 form a high side and the second semiconductor element Q2 and the fourth semiconductor element Q4 form a low side (see FIG. 3). The full-bridge circuit 100 will be described later.

[0020] The semiconductor module 1 also includes a substrate 70, a temperature detection element 90, other wiring patterns, other terminals, and a sealing material M. The other wiring patterns include first and second temperature detection wiring patterns 93 and 94, first to fourth control wiring patterns 111 to 114, and first to fourth detection wiring patterns 121 to 124. The other terminals include first and second temperature detection terminals T1 and T2, first to fourth control terminals T11 to T14, and first to fourth detection terminals T21 to T24.

[0021] Each of the above components will be described below.

[0022] The first to fourth semiconductor elements Q1 to Q4 are MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) in the semiconductor module 1. The first to fourth semiconductor elements Q1 to Q4 each have a source electrode S, a drain electrode D, and a gate electrode G.

[0023] When the first to fourth semiconductor elements Q1 to Q4 are vertical transistor elements, the drain electrode D is present on the surface of the first to fourth semiconductor elements Q1 to Q4 that faces the first to fourth wiring patterns 10 to 40. The semiconductor module 1 illustrates a case where the first to fourth semiconductor elements Q1 to Q4 are vertical transistor elements. Therefore, when the semiconductor module 1 is viewed from above as in FIG. 1, the drain electrode D is not visible, and therefore the symbol "D" indicating the drain electrode is not shown in each drawing. Furthermore, the gate electrode G is present on the surface of the first to fourth semiconductor elements Q1 to Q4 that faces the source electrode S.

[0024] The first to fourth semiconductor elements Q1 to Q4 can be modified as appropriate without departing from the spirit of the present invention. The first to fourth semiconductor elements Q1 to Q4 are not limited to MOSFETs, but may be other semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors).

[0025] The first to fourth semiconductor elements Q1 to Q4 may be, for example, lateral transistor elements (e.g., GaN-HEMTs made of GaN-on-Si materials, or other compound semiconductor transistor elements made of Ga2O3-on-Si materials). Furthermore, the first to fourth semiconductor elements Q1 to Q4 are not limited to transistor elements, and may be modified in configuration by replacing the transistor elements with diode elements as appropriate depending on the circuit application. Such a modified configuration makes the present invention applicable to a totem-pole bridgeless PFC circuit, etc.

[0026] A source electrode S of the first semiconductor element Q1 is connected to the second wiring pattern 20 via a first connecting member 81. The first connecting member 81 and second to fourth connecting members 82 to 84, which will be described later, may be made of, for example, aluminum wire. A drain electrode D of the first semiconductor element Q1 is connected to the first wiring pattern 10.

[0027] The source electrode S of the second semiconductor element Q2 is connected to the fifth wiring pattern 50 via the second connecting member 82. The drain electrode D of the second semiconductor element Q2 is connected to the second wiring pattern 20.

[0028] The source electrode S of the third semiconductor element Q3 is connected to the fourth wiring pattern 40 via a third connecting member 83. The drain electrode D of the third semiconductor element Q3 is connected to the third wiring pattern 30.

[0029] The source electrode S of the fourth semiconductor element Q4 is connected to the fifth wiring pattern 50 via a fourth connecting member 84. In addition, the drain electrode D of the fourth semiconductor element Q4 is connected to the fourth wiring pattern 40.

[0030] The first to fifth wiring patterns 10 to 50 in the semiconductor module 1 are made of conductive materials arranged or formed on the base of the substrate 70. Note that other wiring patterns described later are similar to the first to fifth wiring patterns 10 to 50 in that they are also made of conductive materials arranged or formed on the base of the substrate 70.

[0031] In the semiconductor module 1, the substrate 70 can suitably be a DCB (Direct Copper Bonding) substrate in which metal (copper) is directly bonded to a base made of ceramic (alumina, aluminum nitride, silicon nitride, etc.).

[0032] The substrate in the semiconductor module of the present invention is not limited to a DCB substrate. Other ceramic substrates, such as an AMB (Active Metal Brazing) substrate, or a copper- or aluminum-based metal-based substrate may also be used. Furthermore, metals other than copper (e.g., aluminum) may also be used as the material for the multiple wiring patterns.

[0033] A first semiconductor element Q1 is mounted on the first wiring pattern 10, and a first power supply terminal 51 is connected to it. A second semiconductor element Q2 is mounted on the second wiring pattern 20, and a first midpoint terminal 61 is connected to it. A third semiconductor element Q3 is mounted on the third wiring pattern 30, and a first power supply terminal 51 is connected to it. A fourth semiconductor element Q4 is mounted on the fourth wiring pattern 40, and a second midpoint terminal 62 is connected to it. Second power supply terminals 52 and 53 are connected to the fifth wiring pattern 50.

[0034] The fifth wiring pattern 50 has an extension E that extends in the direction in which the first temperature detection wiring pattern 93 is arranged.

[0035] The first power supply terminal 51 and the second power supply terminals 52 and 53 are terminals for supplying power to the full-bridge circuit. In the semiconductor module 1, the first power supply terminal 51 is the current input side (high voltage side), and the second power supply terminal 52 is the current output side (ground side).

[0036] The first power supply terminal 51 is a substantially T-shaped member with a branched inner lead portion (a portion present inside the sealing material M). The first power supply terminal 51 straddles the fifth wiring pattern 50 without contacting it, and is connected to the first wiring pattern 10 and the third wiring pattern 30.

[0037] The second power supply terminals 52 and 53 are each connected to the fifth wiring pattern 50. The second power supply terminals 52 and 53 are arranged to sandwich the first power supply terminal 51. As described above, the second power supply terminals 52 and 53 are terminals for connection to ground (not shown).

[0038] A load (not shown) is connected to the first midpoint terminal 61 and the second midpoint terminal 62. The first midpoint terminal 61 is connected to the second wiring pattern 20, and the second midpoint terminal 62 is connected to the fourth wiring pattern 40.

[0039] The temperature detection element 90 has a first temperature detection electrode 91 and a second temperature detection electrode 92, and is disposed in an area surrounded by a first switching path A and a second switching path B. The first and second switching paths A and B will be described later in the section on the full bridge circuit 100 and current paths. In this specification, the term "temperature detection element" refers to an element whose electrical characteristics (e.g., resistance) change with temperature. A thermistor can be suitably used as the temperature detection element 90.

[0040] The first temperature detection wiring pattern 93 is connected to the first temperature detection electrode 91. The second temperature detection wiring pattern 94 is connected to the second temperature detection electrode 92. In the semiconductor module 1, the second temperature detection wiring pattern 94 is disposed between the first temperature detection wiring pattern 93 and the fourth wiring pattern 40.

[0041] The semiconductor module 1 is configured to reduce noise due to parasitic capacitance between the wiring pattern that forms the common portion of the first current path P1 and the fourth current path P4 and the first temperature detection wiring pattern 93, and parasitic capacitance between the wiring pattern that forms the common portion of the second current path P2 and the third current path P3 and the first temperature detection wiring pattern 93. In order to reduce noise due to the above-mentioned two parasitic capacitances, it is important to "balance the two parasitic capacitances" and "reduce the parasitic capacitance itself."

[0042] As will be described later, in the semiconductor module 1, the "wiring pattern forming the common portion of the first current path P1 and the fourth current path P4" is the second wiring pattern 20, and the "wiring pattern forming the common portion of the second current path P2 and the third current path P3" is the fourth wiring pattern. In the semiconductor module 1, the first temperature detection wiring pattern 93 is disposed between the second wiring pattern 20 and the fourth wiring pattern 40 when the semiconductor module 1 is viewed in a plan view.

[0043] Furthermore, in the semiconductor module 1, the distance between the first temperature detection wiring pattern 93 and the second wiring pattern 20 is equal to the distance between the first temperature detection wiring pattern 93 and the fourth wiring pattern 40. In this specification, "equal distance" means that the distances (shortest distances) are equal at the design stage. Therefore, even if there is a difference between the above two distances in an actual product, if the difference is due to an unintended event such as a manufacturing error, it can be evaluated as substantially "equal distance."

[0044] The first temperature detection terminal T1 is a terminal for connection to a temperature detection circuit (not shown), and is connected to the first temperature detection wiring pattern 93. In this specification, the term "temperature detection circuit" refers to a circuit formed to include a temperature detection element, which enables temperature detection based on changes in the electrical characteristics of the temperature detection element.

[0045] The second temperature detection terminal T2 is a terminal for connection to ground or a control system power supply (not shown), and is connected to the second temperature detection wiring pattern 94. In this specification, the "control system power supply" refers to a power supply device that supplies power to operate the temperature detection circuit. The control system power supply is a power supply device separate from the power supply (main power supply) that supplies power to the first and second power supply terminals. Note that the control system power supply in this specification may also supply power to circuits and devices other than the temperature detection circuit.

[0046] The first to fourth control wiring patterns 111 to 114 are connected to the gate electrodes G of the first to fourth semiconductor elements Q1 to Q4 via connecting members such as aluminum wires. The first to fourth control wiring patterns 111 to 114 are also connected to the corresponding first to fourth control terminals T11 to T14. Therefore, it can be said that the gate electrodes G of the first to fourth semiconductor elements Q1 to Q4 are connected to the first to fourth control terminals T11 to T14, respectively.

[0047] The first to fourth detection wiring patterns 121 to 124 are connected to the source electrodes S of the first to fourth semiconductor elements Q1 to Q4 via connecting members such as aluminum wires. The first to fourth detection wiring patterns 121 to 124 are also connected to the corresponding first to fourth detection wiring patterns 121 to 124. For this reason, it can be said that the source electrodes S of the first to fourth semiconductor elements Q1 to Q4 are also connected to the first to fourth detection terminals T21 to T24, respectively.

[0048] The sealing material M seals the first to fourth semiconductor elements Q1 to Q4, the wiring patterns, and the temperature detection element 90, and also seals the inner lead portions of the first power supply terminal 51, the second power supply terminals 52 and 53, the first midpoint terminal 61, the second midpoint terminal 62, the first temperature detection terminal T1, and the second temperature detection terminal T2. The sealing material M is made of, for example, resin.

[0049] Here, the shapes and arrangement of the components in the semiconductor module 1 will be described. When the semiconductor module 1 is viewed from above, the first temperature detection wiring pattern 93 and the first temperature detection terminal T1 are disposed at positions overlapping a predetermined axis of symmetry C. Furthermore, at least a portion of the first temperature detection terminal T1 and the first temperature detection wiring pattern 93 have shapes that are line-symmetric with respect to the predetermined axis of symmetry C. The first temperature detection terminal T1 in the semiconductor module 1 has a shape that is line-symmetric with respect to the predetermined axis of symmetry C. Note that when only a portion of the first temperature detection terminal T1 has a shape that is line-symmetric with respect to the predetermined axis of symmetry C, it is preferable that this portion include a portion of the first temperature detection terminal T1 that is connected to the first temperature detection wiring pattern 93, and it is even more preferable that this portion include an inner lead portion.

[0050] Furthermore, the configuration consisting of the first to fourth semiconductor elements Q1 to Q4, the first to fourth wiring patterns 10 to 40, the first power supply terminal 51, the second power supply terminals 52 and 53, the first midpoint terminal 61, and the second midpoint terminal 62, which are components of the semiconductor module 1, is line-symmetrical with respect to a predetermined axis of symmetry C. Note that in the semiconductor module 1, the configuration consisting of the fifth wiring pattern 50, the substrate 70, the first to fourth control wiring patterns 111 to 114, the first to fourth detection wiring patterns 121 to 124, the first to fourth control terminals T11 to T14, the first to fourth detection terminals T21 to T24, and the sealing material M is also line-symmetrical with respect to the predetermined axis of symmetry C.

[0051] 2. Full-bridge circuit 100 and current path in semiconductor module 1 Here, a description will be given of the full-bridge circuit 100 and current paths in the semiconductor module 1. In the semiconductor module 1, as shown in Figures 3 and 4, a full-bridge circuit 100 is configured in which a first switching path A and a second switching path B are formed exclusively by switching operations. In Figures 3 and 4, the first switching path A is indicated by a solid arrow, and the second switching path B is indicated by a dashed arrow.

[0052] The full-bridge circuit 100 in the semiconductor module 1 has a first semiconductor element Q1 and a third semiconductor element Q3 as the high side and a second semiconductor element Q2 and a fourth semiconductor element Q4 as the low side. In this full-bridge circuit, an operation in which the first semiconductor element Q1 and the fourth semiconductor element Q4 are both turned on and an operation in which the third semiconductor element Q3 and the second semiconductor element Q2 are both turned on are alternately repeated.

[0053] When the first semiconductor element Q1 and the fourth semiconductor element Q4 are both on, the third semiconductor element Q3 and the second semiconductor element Q2 are both off, and when the third semiconductor element Q3 and the second semiconductor element Q2 are both on, the first semiconductor element Q1 and the fourth semiconductor element Q4 are both off. In the following explanation, the description of the semiconductor elements being off will be omitted.

[0054] 3 and 4, the first switching path A is a current path when the first semiconductor element Q1 and the fourth semiconductor element Q4 are both turned on. The first switching path A is a current path including a first current path P1 from the first power supply terminal 51 to the first midpoint terminal 61 and a second current path P2 from the second midpoint terminal 62 to the second power supply terminals 52 and 53. The first current path P1 is a current path that passes through the first power supply terminal 51, the first wiring pattern 10, the first semiconductor element Q1, the second wiring pattern 20, and the first midpoint terminal 61. The second current path P2 is a current path that passes through the second midpoint terminal 62, the fourth wiring pattern 40, the fourth semiconductor element Q4, the fifth wiring pattern 50, and the second power supply terminals 52 and 53. 4, the second current path P2 is shown as passing through the second power supply terminal 53 but not through the second power supply terminal 52, but this is done to avoid complicating the drawing. In reality, the second current path P2 passes through both the second power supply terminals 52 and 53.

[0055] 3 and 4, a second switching path B is a current path when both the third semiconductor element Q3 and the second semiconductor element Q2 are turned on. The second switching path B is a current path including a third current path P3 extending from the first power supply terminal 51 to the second midpoint terminal 62 and a fourth current path P4 extending from the first midpoint terminal 61 to the second power supply terminals 52 and 53. The third current path P3 is a current path passing through the first power supply terminal 51, the third wiring pattern 30, the third semiconductor element Q3, the fourth wiring pattern 40, and the second midpoint terminal 62. The fourth current path P4 is a current path passing through the first midpoint terminal 61, the second wiring pattern 20, the second semiconductor element Q2, the fifth wiring pattern 50, and the second power supply terminals 52 and 53. 4, the fourth current path P4 is shown as passing through the second power supply terminal 52 but not through the second power supply terminal 53, but this is done to avoid complicating the drawing. In reality, the fourth current path P4 passes through both the second power supply terminals 52 and 53.

[0056] For this reason, in the semiconductor module 1, the "wiring pattern forming the common portion of the first current path P1 and the fourth current path P4" in which the parasitic capacitance between the first temperature detection wiring pattern 93 becomes an issue is the second wiring pattern 20 (see FIG. 4). Also, in the semiconductor module 1, the "wiring pattern forming the common portion of the second current path P2 and the third current path P3" in which the parasitic capacitance between the first temperature detection wiring pattern 93 becomes an issue is the fourth wiring pattern 40.

[0057] 3. Effects of the semiconductor module 1 according to the first embodiment In the semiconductor module 1 according to the first embodiment, the temperature detection element 90 is disposed in an area close to the semiconductor elements (the second semiconductor element Q2 and the fourth semiconductor element Q4) that are heat sources and that are surrounded by the first switching path A and the second switching path B in the full bridge circuit 100. Therefore, the semiconductor module 1 according to the first embodiment is a semiconductor module that can perform temperature detection more accurately than conventional semiconductor modules.

[0058] Furthermore, the semiconductor module 1 according to the first embodiment is configured to reduce noise due to "parasitic capacitance between the wiring pattern (second wiring pattern 20) constituting the common portion of the first current path P1 and the fourth current path P4 and the first temperature detection wiring pattern 93" and "parasitic capacitance between the wiring pattern (fourth wiring pattern 40) constituting the common portion of the second current path P2 and the third current path P3 and the first temperature detection wiring pattern 93." Therefore, according to the semiconductor module 1 according to the first embodiment, the parasitic capacitance between the first temperature detection wiring pattern 93 and the first current path P1 on the first switching path A and the parasitic capacitance between the first temperature detection wiring pattern 93 and the second current path P2 on the first switching path A are balanced, thereby reducing noise generated during switching. Furthermore, according to the semiconductor module 1 of the first embodiment, the parasitic capacitance between the first temperature detection wiring pattern 93 and the third current path P3 on the second switching path B and the parasitic capacitance between the first temperature detection wiring pattern 93 and the fourth current path P4 on the second switching path B are balanced, thereby reducing noise generated during switching. As a result, the semiconductor module 1 of the first embodiment is a semiconductor module in which the output voltage of the temperature detection element 90 is stabilized and temperature detection can be performed more stably.

[0059] Furthermore, in the semiconductor module 1 according to the first embodiment, the first temperature detection wiring pattern 93 is disposed between the second wiring pattern 20 and the fourth wiring pattern 40 when the semiconductor module 1 is viewed from above. Therefore, in the semiconductor module 1 according to the first embodiment, it is possible to easily balance the parasitic capacitance between the first temperature detection wiring pattern 93 and the first current path P1 on the first switching path A and the parasitic capacitance between the first temperature detection wiring pattern 93 and the second current path P2 on the first switching path A. Furthermore, in the semiconductor module 1 according to the first embodiment, it is also possible to easily balance the parasitic capacitance between the first temperature detection wiring pattern 93 and the third current path P3 on the second switching path B and the parasitic capacitance between the first temperature detection wiring pattern 93 and the fourth current path P4 on the second switching path B. Therefore, the semiconductor module 1 according to the first embodiment can further reduce noise generated during switching, further stabilize the output voltage of the temperature detection element 90, and perform temperature detection more stably.

[0060] Furthermore, in the semiconductor module 1 according to the first embodiment, the distance between the first temperature detection wiring pattern 93 and the second wiring pattern 20 is equal to the distance between the first temperature detection wiring pattern 93 and the fourth wiring pattern 40. Therefore, the semiconductor module 1 according to the first embodiment can more easily balance the parasitic capacitance between the first temperature detection wiring pattern 93 and the first current path P1 on the first switching path A and the parasitic capacitance between the first temperature detection wiring pattern 93 and the second current path P2 on the first switching path A. Furthermore, the semiconductor module 1 according to the first embodiment can more easily balance the parasitic capacitance between the first temperature detection wiring pattern 93 and the third current path P3 on the second switching path B and the parasitic capacitance between the first temperature detection wiring pattern 93 and the fourth current path P4 on the second switching path B.

[0061] Furthermore, in the semiconductor module 1 according to the first embodiment, the second power supply terminals 52, 53 are terminals for connection to ground, and the plurality of wiring patterns include a fifth wiring pattern 50 to which the second power supply terminals 52, 53 are connected, and the fifth wiring pattern 50 has an extension portion E that extends in the direction in which the first temperature detection wiring pattern 93 is disposed. Therefore, according to the semiconductor module 1 according to the first embodiment, by locating the fifth wiring pattern 50 connected to ground closer to the first temperature detection wiring pattern 93, it is possible to reduce the parasitic capacitance generated around the first temperature detection wiring pattern 93.

[0062] In the semiconductor module 1 according to the first embodiment, the first temperature detection wiring pattern 93 and the first temperature detection terminal T1 are disposed at positions overlapping a predetermined axis of symmetry C when the semiconductor module 1 is viewed from above. In the semiconductor module 1 according to the first embodiment, at least a portion of the first temperature detection terminal T1 and the first temperature detection wiring pattern 93 have shapes that are line-symmetric with respect to the predetermined axis of symmetry C. In addition, in the semiconductor module 1 according to the first embodiment, the configuration of the components of the semiconductor module 1, namely, the first to fourth semiconductor elements Q1 to Q4, the first to fourth wiring patterns 10 to 40, the first power supply terminal 51, the second power supply terminals 52 and 53, the first midpoint terminal 61, and the second midpoint terminal 62, is line-symmetric with respect to the predetermined axis of symmetry C. Therefore, in the semiconductor module 1 according to the first embodiment, by making the shapes of the first switching path A and the second switching path B closer to line symmetry, it becomes easier to balance the parasitic capacitance generated around the first temperature detection wiring pattern 93.

[0063] [Embodiment 2] The semiconductor module 2 according to the second embodiment basically has the same configuration as the semiconductor module 1 according to the first embodiment, but differs from the semiconductor module 1 according to the first embodiment in that it further includes a capacitive coupling reducing wiring pattern. The following describes the semiconductor module 2, focusing on the differences from the semiconductor module 1.

[0064] 5 and 6 , the semiconductor module 2 includes a capacitive coupling reduction wiring pattern 97. The capacitive coupling reduction wiring pattern 97 is arranged on the side of the semiconductor module 2 where the second temperature detection wiring pattern 94 is not arranged, between the first temperature detection wiring pattern 93 and the second wiring pattern 20 and between the first temperature detection wiring pattern 93 and the fourth wiring pattern 40. In the semiconductor module 2, the second temperature detection wiring pattern 94 is arranged between the first temperature detection wiring pattern 93 and the fourth wiring pattern 40. Therefore, the capacitive coupling reduction wiring pattern 97 in the semiconductor module 2 is arranged between the first temperature detection wiring pattern 93 and the second wiring pattern 20.

[0065] Although not shown, a full bridge circuit 100 equivalent to that of the semiconductor module 1 is configured in the semiconductor module 2, and when in use, a first switching path A and a second switching path B equivalent to those of the semiconductor module 1 are formed. The full bridge circuit 100, the first switching path A, and the second switching path B are similar to those described above in the semiconductor modules 3 and 4 described later.

[0066] The semiconductor module 2 according to the second embodiment differs from the semiconductor module 1 according to the first embodiment in that it further includes a capacitive coupling reducing wiring pattern, but the temperature detection element 90 is disposed in an area surrounded by the first switching path A and the second switching path B in the full bridge circuit 100 and close to the semiconductor elements (the second semiconductor element Q2 and the fourth semiconductor element Q4) that are heat sources. Therefore, like the semiconductor module 1 according to the first embodiment, the semiconductor module 2 according to the second embodiment is a semiconductor module that can perform temperature detection more accurately than conventional ones.

[0067] The semiconductor module 2 according to the second embodiment also includes a capacitive coupling reduction wiring pattern 97 that is arranged on the side where the second temperature detection wiring pattern 94 is not arranged, between the first temperature detection wiring pattern 93 and the second wiring pattern 20 and between the first temperature detection wiring pattern 93 and the fourth wiring pattern 40. According to the semiconductor module 2 according to the second embodiment, the presence of the capacitive coupling reduction wiring pattern 97 makes it possible to reduce the parasitic capacitance generated around the first temperature detection wiring pattern 93, as will be shown in examples described later.

[0068] The semiconductor module 2 according to the second embodiment has all the configurations of the semiconductor module 1 according to the first embodiment, and therefore has the same effects as the semiconductor module 1 according to the first embodiment.

[0069] [Embodiment 3] The semiconductor module 3 according to the third embodiment basically has the same configuration as the semiconductor module 2 according to the second embodiment, but differs from the semiconductor module 2 according to the second embodiment in that the capacitive coupling reduction wiring pattern is connected to a fifth wiring pattern. The following describes the semiconductor module 3, focusing on the differences from the semiconductor module 2.

[0070] 7 and 8, the semiconductor module 3 includes a capacitive coupling reduction connecting member 98. The capacitive coupling reduction connecting member 98 is a conductive member (e.g., an aluminum wire) that connects the capacitive coupling reduction wiring pattern 97 and the fifth wiring pattern 50. Therefore, in the semiconductor module 3, the capacitive coupling reduction wiring pattern 97 is connected to the fifth wiring pattern 50.

[0071] The second power supply terminals 52, 53 are terminals for connecting to ground and are connected to the fifth wiring pattern 50, so the capacitive coupling reducing wiring pattern 97 in the semiconductor module 3 is connected to ground.

[0072] The semiconductor module 3 according to the third embodiment differs from the semiconductor module 2 according to the second embodiment in that the capacitive coupling reducing wiring pattern is connected to the fifth wiring pattern, but the temperature detection element 90 is disposed in an area surrounded by the first switching path A and the second switching path B in the full bridge circuit 100 and close to the semiconductor elements (the second semiconductor element Q2 and the fourth semiconductor element Q4) that are heat sources. Therefore, like the semiconductor module 2 according to the second embodiment, the semiconductor module 3 according to the third embodiment is a semiconductor module that can perform temperature detection more accurately than conventional semiconductor modules.

[0073] Furthermore, according to the semiconductor module 3 of the third embodiment, the capacitive coupling reduction wiring pattern 97 is connected to the ground, and therefore, as will be shown in the examples described later, it is possible to further reduce the parasitic capacitance generated around the first temperature detection wiring pattern 93.

[0074] Furthermore, in the semiconductor module 3 according to the third embodiment, the second power supply terminals 52, 53 are terminals for connection to ground, the multiple wiring patterns include a fifth wiring pattern 50 to which the second power supply terminals 52, 53 are connected, and the capacitive coupling reduction wiring pattern 97 is connected to the fifth wiring pattern 50. Therefore, according to the semiconductor module 3 according to the third embodiment, it is possible to connect the capacitive coupling reduction wiring pattern 97 to ground via the fifth wiring pattern 50.

[0075] The semiconductor module 3 according to the third embodiment has all the configurations of the semiconductor module 2 according to the second embodiment, and therefore has the same effects as those of the semiconductor module 2 according to the second embodiment.

[0076] [Embodiment 4] 9 and 10, the semiconductor module 4 according to the fourth embodiment has a configuration similar to that of the semiconductor module 3 according to the third embodiment, but includes a connection wiring pattern 99 instead of the capacitive coupling reduction connecting member 98. The connection wiring pattern 99 is a wiring pattern that connects the capacitive coupling reduction wiring pattern 97 and the fifth wiring pattern 50.

[0077] The semiconductor module 4 according to the fourth embodiment has the same effects as those of the semiconductor module 3 according to the third embodiment.

[0078] [Example] The results of a simulation carried out by the inventors of the present invention regarding the effects of the semiconductor module of the present invention will be described below.

[0079] The simulation was carried out for the semiconductor modules 1 to 4 according to the first to fourth embodiments and the semiconductor module 1A according to the comparative example.

[0080] 11 and 12, the semiconductor module 1A has a configuration similar to that of the semiconductor module 1 according to the first embodiment, but does not consider the balance between the parasitic capacitance between the second wiring pattern and the first temperature detection wiring pattern and the parasitic capacitance between the fourth wiring pattern and the first temperature detection wiring pattern. The temperature detection element 90, the first temperature detection terminal T1, and the second temperature detection terminal T2 in the semiconductor module 1A are the same as the corresponding components in the semiconductor module 1, but are located in different positions. Due to the above differences, the semiconductor module 1A also includes a second wiring pattern 20A, a fourth wiring pattern 40A, a fifth wiring pattern 50A, a first temperature detection pattern 93A, and a second temperature detection pattern 94A, which have shapes different from those of the components with the same names in the semiconductor module 1.

[0081] First, for the semiconductor modules 1 to 4 according to embodiments 1 to 4 and the semiconductor module 1A according to the comparative example, the difference between the parasitic capacitance between the first temperature detection wiring patterns 93, 93A and the second wiring patterns 20, 20A and the parasitic capacitance between the first temperature detection wiring patterns 93, 93A and the fourth wiring patterns 40, 40A (hereinafter referred to as the "difference in parasitic capacitance") was measured.

[0082] As a result, the difference in parasitic capacitance in semiconductor module 1A was 307 fF. The difference in parasitic capacitance in semiconductor module 1 was 109 fF, the difference in parasitic capacitance in semiconductor module 2 was 98 fF, the difference in parasitic capacitance in semiconductor module 3 was 95 fF, and the difference in parasitic capacitance in semiconductor module 4 was 97 fF.

[0083] From the above results, it was confirmed that the semiconductor modules 1 to 4 according to the first to fourth embodiments have a better balance of the parasitic capacitance around the first temperature detection wiring pattern 93 than the semiconductor module 1A according to the comparative example. Furthermore, from the above results, it was also confirmed that the arrangement of the capacitive coupling reduction wiring pattern 97 further improves the balance of the parasitic capacitance, and that the connection of the capacitive coupling reduction wiring pattern 97 to ground further improves the balance of the parasitic capacitance.

[0084] Next, for the semiconductor module 3 according to the third embodiment and the semiconductor module 1A according to the comparative example, the frequency of the on / off operation of the full bridge circuit 100 was set to 20 kHz, and the noise (voltage fluctuation) generated in the first temperature detection path TP1 (the current path from the first temperature detection electrode 91 to the first temperature detection terminal T1; see Figures 1 and 12) during switching was measured.

[0085] 13, in the semiconductor module 3 according to the third embodiment, noise generated in the first temperature detection path TP1 is significantly reduced compared to the semiconductor module 1A according to the comparative example, and therefore, in the semiconductor module 3 according to the third embodiment, the output voltage of the temperature detection element 90 becomes stable.

[0086] Although the present invention has been described based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments and can be embodied in various forms without departing from the spirit of the present invention, and for example, the following modifications are also possible.

[0087] (1) The position, size, shape, etc. of each component element described in each of the above embodiments and shown in each drawing are examples and can be changed within the scope that does not impair the effects of the present invention.

[0088] (2) In the above third and fourth embodiments, the capacitive coupling reduction wiring pattern 97 is connected to ground via the fifth wiring pattern 50, but the present invention is not limited to this. The capacitive coupling reduction wiring pattern of the present invention may be connected to ground without going through the fifth wiring pattern. This configuration can be achieved, for example, by connecting a dedicated terminal to the capacitive coupling reduction wiring pattern.

[0089] (3) In the above-described second to fourth embodiments, the second temperature detection wiring pattern 94 is disposed between the first temperature detection wiring pattern 93 and the fourth wiring pattern 40, and the capacitive coupling reduction wiring pattern 97 is disposed between the first temperature detection wiring pattern 93 and the second wiring pattern 20. However, the present invention is not limited to this. The arrangement of the second temperature detection wiring pattern and the capacitive coupling reduction wiring pattern may be reversed. In this case, the arrangement of the temperature detection element and the second temperature detection terminal must also be adjusted.

[0090] (4) In the above third and fourth embodiments, the capacitive coupling reduction wiring pattern 97 is connected to ground, but the present invention is not limited to this. The capacitive coupling reduction wiring pattern may be connected to a connection destination other than ground. The connection destination other than ground is preferably a connection destination with a stable voltage. Examples of connection destinations with a stable voltage include various power sources (main power sources, control system power sources, etc.). This configuration also makes it possible to further reduce the parasitic capacitance generated around the first temperature detection wiring pattern. [Explanation of symbols]

[0091] 1, 2, 3, 4... semiconductor module, 10... first wiring pattern, 20... second wiring pattern, 30... third wiring pattern, 40... fourth wiring pattern, 50... fifth wiring pattern, 51... first power supply terminal, 52, 53... second power supply terminal, 61... first midpoint terminal, 62... second midpoint terminal, 90... temperature detection element, 91... first temperature detection electrode, 92... second temperature detection electrode, 93... first temperature detection wiring pattern, 94... 2 temperature detection wiring pattern, 97...capacitive coupling reduction wiring pattern, 100...full bridge circuit, A...first switching path, B...second switching path, P1...first current path, P2...second current path, P3...third current path, P4...fourth current path, Q1...first semiconductor element, Q2...second semiconductor element, Q3...third semiconductor element, Q4...fourth semiconductor element, T1...first temperature detection terminal, T2...second temperature detection terminal

Claims

1. A semiconductor module comprising first to fourth semiconductor elements, a plurality of wiring patterns, a first power supply terminal, a second power supply terminal, a first midpoint terminal, and a second midpoint terminal, and a full bridge circuit is configured in which the first semiconductor element and the third semiconductor element are on a high side and the second semiconductor element and the fourth semiconductor element are on a low side, a temperature detection element having a first temperature detection electrode and a second temperature detection electrode; a first temperature detection wiring pattern connected to the first temperature detection electrode; a first temperature detection terminal that is a terminal for connection to a temperature detection circuit and is connected to the first temperature detection wiring pattern; a second temperature detection wiring pattern connected to the second temperature detection electrode; a second temperature detection terminal which is a terminal for connection to a ground or a control system power supply and is connected to the second temperature detection wiring pattern; A first switching path is a current path when the first semiconductor element and the fourth semiconductor element are both turned on, the current path including a first current path from the first power supply terminal to the first midpoint terminal and a second current path from the second midpoint terminal to the second power supply terminal; and a second switching path is a current path when the third semiconductor element and the second semiconductor element are both turned on, the current path including a third current path from the first power supply terminal to the second midpoint terminal and a fourth current path from the first midpoint terminal to the second power supply terminal. the temperature detection element is disposed in an area surrounded by the first switching path and the second switching path; a wiring pattern that forms a common portion of the first current path and the fourth current path and the first temperature detection wiring pattern, and a wiring pattern that forms a common portion of the second current path and the third current path and the first temperature detection wiring pattern, wherein the semiconductor module is configured to reduce noise due to parasitic capacitance between the wiring pattern and the first temperature detection wiring pattern.

2. the plurality of wiring patterns include a first wiring pattern on which the first semiconductor element is mounted and the first power supply terminal is connected, a second wiring pattern on which the second semiconductor element is mounted and the first midpoint terminal is connected, a third wiring pattern on which the third semiconductor element is mounted and the first power supply terminal is connected, and a fourth wiring pattern on which the fourth semiconductor element is mounted and the second midpoint terminal is connected, 2. The semiconductor module according to claim 1, wherein the first temperature detection wiring pattern is disposed between the second wiring pattern and the fourth wiring pattern when the semiconductor module is viewed from above.

3. 3. The semiconductor module according to claim 2, wherein a distance between the first temperature detection wiring pattern and the second wiring pattern is equal to a distance between the first temperature detection wiring pattern and the fourth wiring pattern.

4. the second power supply terminal is a terminal for connection to the ground, the plurality of wiring patterns further include a fifth wiring pattern to which the second power supply terminal is connected; 3. The semiconductor module according to claim 2, wherein the fifth wiring pattern has an extension portion that extends in a direction in which the first temperature detection wiring pattern is arranged.

5. the second temperature detection wiring pattern is disposed between the first temperature detection wiring pattern and the second wiring pattern, or between the first temperature detection wiring pattern and the fourth wiring pattern, 3. The semiconductor module according to claim 2, further comprising a capacitive coupling reduction wiring pattern arranged on a side between the first temperature detection wiring pattern and the second wiring pattern and between the first temperature detection wiring pattern and the fourth wiring pattern, on which the second temperature detection wiring pattern is not arranged.

6. 6. The semiconductor module according to claim 5, wherein the capacitive coupling reducing wiring pattern is connected to the ground.

7. the second power supply terminal is a terminal for connection to the ground, the plurality of wiring patterns further include a fifth wiring pattern to which the second power supply terminal is connected; 7. The semiconductor module according to claim 6, wherein the capacitive coupling reducing wiring pattern is connected to the fifth wiring pattern.

8. When the semiconductor module is viewed from above, the first temperature detection wiring pattern and the first temperature detection terminal are arranged at positions overlapping a predetermined axis of symmetry, at least a portion of the first temperature detection terminal and the first temperature detection wiring pattern have shapes that are line-symmetric with respect to the predetermined axis of symmetry; The semiconductor module according to claim 2, characterized in that the configuration of the semiconductor module, consisting of the first to fourth semiconductor elements, the first to fourth wiring patterns, the first power supply terminal, the second power supply terminal, the first midpoint terminal and the second midpoint terminal, is linearly symmetrical with respect to the predetermined axis of symmetry.

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