Packaging Structure and Packaging Method of a Low Parasitic Parameter Power Module

Abstract

The present invention provides a packaging structure and a packaging method for a low-parasitic-parameter power module, including a PCB board. The PCB board has a built-in power circuit. The PCB board includes an upper-layer PCB board and a lower-layer PCB board which are arranged up and down and are electrically connected to each other. The power circuits in the upper-layer PCB board and the lower-layer PCB board have opposite current flow directions; a copper-clad substrate, including an insulating and heat-conducting layer and a DBC copper layer covering the upper surface of the insulating and heat-conducting layer. The PCB board is covered on the upper surface of the DBC copper layer, and a power switch tube chip is fixed on the DBC copper layer; the power switch tube chip is sequentially connected to the power circuits in the upper-layer PCB board and the lower-layer PCB board to form a power loop. The packaging structure and the packaging method adopt a double-layer structure, and the current directions in the upper and lower PCB board paths are opposite, so as to reduce the parasitic inductance of the commutation loop by the mutual inductance cancellation technology, and the shielding effect of the copper layer in the double-layer PCB board reduces the parasitic capacitance.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductor device packaging, and particularly to a packaging structure and method for a low parasitic parameter power module. Background Art

[0002] With the development of power electronics technology, using power electronic devices to achieve electric energy conversion has become a common means in the power field. In recent years, with the rapid development of fields such as transportation, aerospace, and new energy, higher requirements have also been put forward for existing power devices and converters, such as higher power density, higher efficiency, and smaller electromagnetic interference (EMI).

[0003] To achieve high power density, it is necessary to increase the switching frequency of power devices, but high switching frequency will bring higher switching losses and higher EMI. The switching performance of power devices is closely related to their packaging structure: the parasitic inductance in the packaging module affects the switching speed, thus affecting the magnitude of switching losses, while the parasitic capacitance determines the magnitude of EMI generated during the switching process of the module. Therefore, optimizing the packaging structure of power switch tube chips is an important way to improve their performance. However, for most existing commercial power devices, the parasitic inductance and parasitic capacitance are generally large. Taking the TO247 packaging structure as an example, the parasitic inductance of a single device is greater than 10 nH, and the drain-to-ground inductance of a single device can reach 30 pF under normal use conditions. This will cause large peak current voltages and oscillations during the high-speed switching process of power devices and result in significant EMI problems. Therefore, in order to improve the high-frequency application performance of power devices, it is necessary to reduce the parasitic capacitance and parasitic inductance generated in the packaging structure.

[0004] Currently, the packaging structures of power switch tube chips mainly include wire bonding structures, flat plate structures, and hybrid structures. Among them, the wire bonding structure has a simple structure and high reliability, but has a large single-sided packaging size and large parasitic inductance; the flat plate structure has small parasitic parameters and good heat dissipation, but has a complex process and poor reliability; the hybrid packaging structure is a combination of the wire bonding structure and the direct copper clad ceramic substrate technology, and has the advantages of the former two. However, the current designs of power switch tube chip packaging structures only consider parasitic inductance and ignore parasitic capacitance. Therefore, a new packaging structure is needed that can achieve as small a parasitic capacitance as possible while maintaining low parasitic inductance, and has a simple, reliable, and easy-to-fabricate structure. Summary of the Invention

[0005] The purpose of the present invention is to provide a packaging structure and method for a low parasitic parameter power module, which can achieve as small a parasitic capacitance as possible while maintaining low parasitic inductance, and has a simple, reliable, and easy-to-fabricate structure.

[0006] The present invention provides a packaging structure for a low parasitic parameter power module, including:

[0007] A PCB board, the PCB board is built with a power circuit, the PCB board includes an upper-layer PCB board and a lower-layer PCB board which are arranged up and down and electrically connected to each other, and the power circuits in the upper-layer PCB board and the lower-layer PCB board have opposite current flows;

[0008] A copper-clad substrate, including an insulating and heat-conducting layer and a DBC copper layer covering the upper surface of the insulating and heat-conducting layer, the PCB board is covered on the upper surface of the DBC copper layer, and a power switch tube chip is fixed on the DBC copper layer;

[0009] The power switch tube chip is sequentially connected to the power circuits in the upper-layer PCB board and the lower-layer PCB board to form a power loop.

[0010] Further, a drive circuit is provided on the upper-layer PCB board, the power output terminal of the power switch tube chip is connected to the power circuit of the upper-layer PCB board through a power bonding wire, the drive circuit is connected to the drive terminal of the power switch tube chip through a drive bonding wire to drive the power switch tube chip to turn on or off, and the power bonding wire and the drive bonding wire are perpendicular to each other.

[0011] Further, the power switch tube chip includes an upper-bridge-arm switch tube chip and a lower-bridge-arm switch tube chip connected in series;

[0012] The drive circuit is connected to the source and gate of the upper-bridge-arm switch tube chip and the lower-bridge-arm switch tube chip through multiple drive bonding wires to respectively control the switching of the upper-bridge-arm switch tube chip and the lower-bridge-arm switch tube chip;

[0013] An external input power supply is connected to the drain of the upper-bridge-arm switch tube chip through the input terminal on the PCB board, the sources of the upper-bridge-arm switch tube chip and the lower-bridge-arm switch tube chip are both power output terminals, the source of the upper-bridge-arm switch tube chip is connected to the upper-layer PCB board through a corresponding power bonding wire, the upper-layer PCB board is connected to the drain of the lower-bridge-arm switch tube chip through the lower-layer PCB board, and the source of the lower-bridge-arm switch tube chip is connected to the output terminal on the PCB board through a corresponding power bonding wire and a power circuit to output power externally.

[0014] Further, the upper surface of the upper-layer PCB board is covered with an upper-layer PCB board positive electrode, an upper-layer PCB board negative electrode and an upper-layer PCB board output electrode; the upper surface of the lower-layer PCB board is covered with a lower-layer PCB board positive electrode, a lower-layer PCB board negative electrode and a lower-layer PCB board output electrode; the DBC copper layer includes a DBC positive electrode, a DBC negative electrode and a DBC output electrode;

[0015] The drain of the upper-arm switching transistor chip is electrically connected to the positive electrode of the upper-layer PCB, the positive electrode of the lower-layer PCB, and the positive electrode of the DBC. The drain of the lower-arm switching transistor chip is electrically connected to the output terminal of the upper-layer PCB, the output terminal of the lower-layer PCB, and the output terminal of the DBC. The negative electrode of the upper-layer PCB is electrically connected to the negative electrode of the lower-layer PCB. The positive electrode of the upper-layer PCB is connected to the input terminal, and the negative electrode of the lower-layer PCB and the output terminal of the lower-layer PCB are both connected to the output terminal.

[0016] When both the upper-arm switching transistor chip and the lower-arm switching transistor chip are turned on, the current on the input terminal flows from the positive electrode of the upper-layer PCB into the positive electrode of the lower-layer PCB, the positive electrode of the DBC, the drain of the upper-arm switching transistor chip, the source of the upper-arm switching transistor chip, the output terminal of the upper-layer PCB, the output terminal of the lower-layer PCB, the output terminal of the DBC, the drain of the lower-arm switching transistor chip, the source of the lower-arm switching transistor chip, the negative electrode of the upper-layer PCB, the negative electrode of the lower-layer PCB in sequence, and is output from the output terminal.

[0017] Furthermore, there are several through-holes penetrating the upper and lower layers on the PCB. Electrical connectors are arranged in the through-holes. The drain of the upper-arm switching transistor chip is electrically connected to the positive electrode of the upper-layer PCB, the positive electrode of the lower-layer PCB, and the positive electrode of the DBC through the electrical connectors in the corresponding through-holes. The drain of the lower-arm switching transistor chip is electrically connected to the output terminal of the upper-layer PCB, the output terminal of the lower-layer PCB, and the output terminal of the DBC through the electrical connectors in the corresponding through-holes. The negative electrode of the upper-layer PCB is electrically connected to the negative electrode of the lower-layer PCB through the electrical connectors in the corresponding through-holes. All the through-holes are vertical holes.

[0018] A hollow window penetrating the upper-layer PCB and the lower-layer PCB is also opened on the PCB. The power switching transistor chip is exposed in the hollow window. There are two hollow windows, which expose the upper-arm switching transistor chip and the lower-arm switching transistor chip respectively. When the power bonding wire and the drive bonding wire connect the power switching transistor chip to the PCB, they both pass through the corresponding hollow windows.

[0019] Furthermore, the power switching transistor chip further includes two Schottky diode chips, and the upper-arm switching transistor chip and the lower-arm switching transistor chip are respectively anti-parallel connected to a Schottky diode chip.

[0020] Further, the drain of the upper-arm switching transistor chip and the cathode of the corresponding Schottky diode chip are both welded to the DBC positive electrode, and the source of the upper-arm switching transistor chip and the anode of the corresponding Schottky diode chip are both connected to the output pole of the upper-layer PCB board through corresponding power bonding wires; the drain of the lower-arm switching transistor chip and the cathode of the corresponding Schottky diode chip are both welded to the DBC output electrode, and the source of the lower-arm switching transistor chip and the anode of the corresponding Schottky diode chip are both connected to the negative pole of the upper-layer PCB board through corresponding power bonding wires.

[0021] Further, the upper surface of the upper-layer PCB board is also covered with an upper-arm MOS transistor source copper layer, an upper-arm MOS transistor gate copper layer, a lower-arm MOS transistor source copper layer, and a lower-arm MOS transistor gate copper layer. The upper-arm MOS transistor source copper layer, the upper-arm MOS transistor gate copper layer, the lower-arm MOS transistor source copper layer, and the lower-arm MOS transistor gate copper layer are the four connection terminals of the drive circuit;

[0022] The gate of the upper-arm switching transistor chip is connected to the upper-arm MOS transistor gate copper layer through a drive bonding wire, the source of the upper-arm switching transistor chip is connected to the upper-arm MOS transistor source copper layer through a drive bonding wire, the gate of the lower-arm switching transistor chip is connected to the lower-arm MOS transistor gate copper layer through a drive bonding wire, and the source of the lower-arm switching transistor chip is connected to the lower-arm MOS transistor source copper layer through a drive bonding wire.

[0023] Further, the packaging structure further includes a housing. The bottom of the housing is open and buckled on the upper surface of the upper-layer PCB board. The top of the housing is provided with a potting hole for pouring potting glue inward, and all drive bonding wires and all power bonding wires are immersed in the potting glue;

[0024] The copper-clad substrate further includes a bottom copper layer. The insulating and heat-conducting layer is sandwiched between the bottom copper layer and the DBC copper layer. The bottom copper layer is a heat-dissipating layer, and the insulating and heat-conducting layer is an aluminum nitride ceramic layer;

[0025] The DBC negative electrode is a frame structure, and the DBC positive electrode and the DBC output electrode are both sheet structures and are both located within the frame of the frame structure. The distance between the DBC positive electrode, the DBC negative electrode, and the DBC output electrode is greater than the electrical insulation distance corresponding to the maximum operating voltage of the power switch transistor chip; the lower-layer PCB board is fixed to the DBC copper layer by welding, and the area on the DBC copper layer for welding with the lower-layer PCB board includes the entire DBC negative electrode, the left side of the DBC positive electrode, and the left side of the DBC output electrode;

[0026] The positive electrode and negative electrode of the upper PCB board are both in a sheet structure, the output electrode of the upper PCB board is in a frame structure, the hollow window on the PCB board exposing the lower bridge arm switch tube chip is the lower bridge hollow window, and the hollow window exposing the upper bridge arm switch tube chip is the upper bridge hollow window. The lower bridge hollow window is located inside the frame of the output electrode of the upper PCB board. The positive electrode of the upper PCB board is covered on the upper surface of the upper PCB board to the left of the upper bridge hollow window, and the negative electrode of the upper PCB board is covered on the upper surface of the upper PCB board to the right of the lower bridge hollow window and is located inside the frame of the output electrode of the upper PCB board;

[0027] The positive electrode and output electrode of the lower PCB board are both in a sheet structure, the negative electrode of the lower PCB board is in a frame structure, both the upper bridge hollow window and the lower bridge hollow window are located inside the frame of the negative electrode of the lower PCB board. The positive electrode of the lower PCB board is covered on the upper surface of the lower PCB board to the left of the upper bridge hollow window and is located inside the frame of the negative electrode of the lower PCB board, and the output electrode of the lower PCB board is covered on the upper surface of the lower PCB board between the upper bridge hollow window and the lower bridge hollow window.

[0028] The present invention provides a packaging method for packaging a power module with low parasitic parameters, including the following steps:

[0029] S1: Manufacture a copper-clad substrate and a PCB board;

[0030] S2: Solder the PCB board on the DBC copper layer;

[0031] S3: Mount the power switch tube chip;

[0032] S4: Fix the housing to the PCB board, and inject potting glue into it through the potting holes on the housing until the potting glue submerges all driving bonding wires and all power bonding wires.

[0033] The technical effects of the present invention:

[0034] (1) By adopting a double-layer PCB board structure and utilizing the shielding effect of the copper layers in the upper PCB board and the lower PCB board, the grounding area of the upper bridge arm switch tube chip and the lower bridge arm switch tube chip to the midpoint copper layer (i.e., the DBC output electrode) of the half-bridge circuit can be effectively reduced, thereby reducing the parasitic capacitance and effectively reducing the common-mode electromagnetic interference generated during the operation of the power module;

[0035] (2) The flexibility of the double-layer PCB board is fully utilized to make the power circuits in the upper PCB board and the lower PCB board have opposite current flow directions, thereby further reducing the parasitic inductance of the commutation loop by using the mutual inductance cancellation technology and effectively reducing the oscillation and overvoltage during the switching process;

[0036] (3) The power bonding wire and the driving bonding wire are perpendicular to each other, so as to effectively reduce the coupling between the driving circuit and the power circuit, thereby reducing the crosstalk problem existing during the switching of the power module;

[0037] (4) The power terminals and signal terminals of the packaging structure of the power switching transistor chip of the present invention are equally arranged on the PCB board, which can be directly extended and interconnected with the external circuit, having good scalability, and can reduce the parasitic inductance and contact resistance introduced by the power leads, while reducing costs. Description of the Drawings

[0038] Figure 1 is an overall cross-sectional view of the packaging structure of a low-parasitic-parameter power module of the present invention;

[0039] Figure 2 is a schematic diagram of the copper-clad substrate of the packaging structure of a low-parasitic-parameter power module of the present invention;

[0040] Figure 3 is a schematic diagram of the upper-layer PCB board of the packaging structure of a low-parasitic-parameter power module of the present invention;

[0041] Figure 4 is a schematic diagram of the lower-layer PCB board of the packaging structure of a low-parasitic-parameter power module of the present invention;

[0042] Figure 5 is a schematic diagram of the principle of the half-bridge circuit of the packaging structure of a low-parasitic-parameter power module of the present invention;

[0043] Figure 6 is a schematic diagram of the semi-connection between the copper-clad substrate and the PCB of the packaging structure of a low-parasitic-parameter power module of the present invention;

[0044] Figure 7 is Figure 6 the top view of;

[0045] Figure 8 is a flowchart of the packaging method of a low-parasitic-parameter power module;

[0046] In the figure: 1 copper-clad substrate; 2 PCB board; 3 housing; 4 potting compound; 5 upper-bridge arm switching transistor chip; 6, 8 Schottky diode chips; 7 lower-bridge arm switching transistor chip; 9 DBC positive electrode; 10 DBC output electrode; 11 DBC negative electrode; 12 insulating and heat-conducting layer; 13 bottom copper layer; 14 upper-layer PCB board positive electrode; 15 upper-layer PCB board output electrode; 16 upper-layer PCB board negative electrode; 17 upper-bridge hollow window; 18 lower-bridge hollow window; 19 upper-bridge arm MOS transistor gate copper layer; 20 upper-bridge arm MOS transistor source copper layer; 21 lower-bridge arm MOS transistor gate copper layer; 22 lower-bridge arm MOS transistor source copper layer; 23 - 25 vias; 26 drive bonding wire; 27 power bonding wire; 28 potting hole; 29 lower-layer PCB board positive electrode; 30 lower-layer PCB board output electrode; 31 lower-layer PCB board negative electrode. Detailed implementation manner

[0047] To make the objectives, technical solutions and advantages of the present invention clearer, the embodiments of the present invention will be further described below in conjunction with the accompanying drawings.

[0048] Please refer to Figures 1 to 7 , the present invention provides a packaging structure for a low-parasitic-parameter power module, mainly including: a PCB board 2, a copper-clad substrate 1 and a power switching transistor chip. The PCB board 2 has a built-in power circuit. The PCB board 2 includes an upper-layer PCB board and a lower-layer PCB board which are arranged up and down and electrically connected to each other. The power circuits in the upper-layer PCB board and the lower-layer PCB board have opposite current flow directions. It includes an insulating and heat-conducting layer 12 and a DBC copper layer covering the upper surface of the insulating and heat-conducting layer. The PCB board 2 is covered on the upper surface of the DBC copper layer. The power switching transistor chip is sequentially connected to the power circuits in the upper-layer PCB board and the lower-layer PCB board to form a power loop. In this power loop, the current direction in the upper-layer PCB board is opposite to the current direction in the lower-layer PCB board. Thus, the magnetic fields generated by the current changes in the upper-layer PCB board and the lower-layer PCB board during the loop switching can cancel each other out, thereby effectively reducing the parasitic inductance of the commutation loop and effectively reducing the oscillation and overvoltage during the switching process.

[0049] A driving circuit is provided on the upper-layer PCB board 2. The power output terminal of the power switch transistor chip is connected to the power circuit of the upper-layer PCB board through a power bonding wire 27. The driving circuit is connected to the driving terminal of the power switch transistor chip through a driving bonding wire 26 to drive the power switch transistor chip to turn on or off. The power bonding wire 27 and the driving bonding wire 26 are perpendicular to each other, thereby effectively reducing the coupling between the driving circuit and the power circuit, and thus reducing the crosstalk problem existing during the switching of the power module. Specifically, a hollow window penetrating through the upper-layer PCB board and the lower-layer PCB board is also provided on the PCB board 2. The power switch transistor chip is exposed in the hollow window. When the power bonding wire 27 and the driving bonding wire 26 are connected to the power switch transistor chip and the PCB board 2, they both pass through the corresponding hollow window. That is, through the hollow window, the required lengths of the power bonding wire 27 and the driving bonding wire 26 can be effectively shortened, and at the same time, winding during the connection process can be avoided, making the connection intuitive and facilitating the realization of the connection. And in the driving loop formed by the driving circuit and the driving terminal, the connection method adopted is the Kelvin connection method, which can further eliminate the common-source inductance.

[0050] The power switch transistor chip includes an upper-bridge-arm switch transistor chip 5 and a lower-bridge-arm switch transistor chip 7 connected in series. There are two hollow windows, respectively exposing the upper-bridge-arm switch transistor chip 5 and the lower-bridge-arm switch transistor chip 7. The size of the hollow window matches the size of the power switch transistor chip to be encapsulated.

[0051] The driving circuit is connected to the source and gate of the upper-bridge-arm switch transistor chip 5 and the lower-bridge-arm switch transistor chip 7 through multiple driving bonding wires 26 to respectively control the switching of the upper-bridge-arm switch transistor chip 5 and the lower-bridge-arm switch transistor chip 7.

[0052] The upper surface of the upper-layer PCB board is covered with an upper-layer PCB board positive electrode 14, an upper-layer PCB board negative electrode 16, and an upper-layer PCB board output electrode 15. The upper surface of the lower-layer PCB board is covered with a lower-layer PCB board positive electrode 29, a lower-layer PCB board negative electrode 31, and a lower-layer PCB board output electrode 30. The DBC copper layer includes a DBC positive electrode 9, a DBC negative electrode 11, and a DBC output electrode 10. The drain of the upper-bridge-arm switch transistor chip 5 is electrically connected to the upper-layer PCB board positive electrode 14, the lower-layer PCB board positive electrode 29, and the DBC positive electrode 9. The drain of the lower-bridge-arm switch transistor chip 7 is electrically connected to the upper-layer PCB board output electrode 15, the lower-layer PCB board output electrode 30, and the DBC output electrode 10. The upper-layer PCB board negative electrode 16 and the lower-layer PCB board negative electrode 31 are electrically connected.

[0053] Adopt a double-layer PCB board structure. By utilizing the shielding effect of the copper layers in the upper-layer PCB board and the lower-layer PCB board, the grounding area of the upper-bridge-arm switch tube chip 5 and the lower-bridge-arm switch tube chip 7 with respect to the copper layer at the midpoint of the half-bridge circuit (i.e., the DBC output pole) can be effectively reduced, thereby reducing the parasitic capacitance and effectively reducing the common-mode electromagnetic interference generated during the operation of the power module.

[0054] The positive electrode 14 of the upper-layer PCB board is connected to the input terminal, and the negative electrode 31 and the output pole 30 of the lower-layer PCB board are both connected to output terminals. In the power switch tube chip packaging structure of the present invention, the power terminals and the signal terminals are arranged on the PCB board 2 and can be directly extended for interconnection with the external circuit, having good scalability, and can reduce the parasitic inductance and contact resistance introduced by the power leads, while reducing costs.

[0055] When both the upper-bridge-arm switch tube chip 5 and the lower-bridge-arm switch tube chip 7 are turned on, the current input from the external input power supply to the input terminal flows from the positive electrode 14 of the upper-layer PCB board into the positive electrode 29 of the lower-layer PCB board, the DBC positive electrode 9, the drain of the upper-bridge-arm switch tube chip 5, the source of the upper-bridge-arm switch tube chip 5, the output pole 15 of the upper-layer PCB board, the output pole 30 of the lower-layer PCB board, the DBC output pole 10, the drain of the lower-bridge-arm switch tube chip 7, the source of the lower-bridge-arm switch tube chip 7, the negative electrode 16 of the upper-layer PCB board, the negative electrode 31 of the lower-layer PCB board, and is output from the output terminal. In this embodiment, the positive electrode 14 of the upper-layer PCB board is connected to the input terminal, and the negative electrode 31 and the output pole 30 of the lower-layer PCB board are both connected to output terminals.

[0056] There are several through holes 23 - 25 penetrating up and down on the PCB board 2, and electrical connectors are arranged in the through holes 23 - 25. The drain of the upper-bridge-arm switch tube chip 5 is electrically connected to the positive electrode 14 of the upper-layer PCB board, the positive electrode 29 of the lower-layer PCB board, and the DBC positive electrode 9 through the electrical connectors in the corresponding through holes 23 - 25. The drain of the lower-bridge-arm switch tube chip 7 is electrically connected to the output pole 15 of the upper-layer PCB board, the output pole 30 of the lower-layer PCB board, and the DBC output pole 10 through the electrical connectors in the corresponding through holes 23 - 25. The negative electrode 16 of the upper-layer PCB board and the negative electrode 31 of the lower-layer PCB board are electrically connected through the electrical connectors in the corresponding through holes 23 - 25. All the through holes 23 - 25 are vertical holes.

[0057] The power switch tube chip further includes two Schottky diode chips 6 and 8. The upper bridge arm switch tube chip 5 and the lower bridge arm switch tube chip 7 are respectively anti-parallel connected with a Schottky diode chip 6 and 8. Preferably: The drain of the upper bridge arm switch tube chip 5 and the cathodes of the corresponding Schottky diode chips 6 and 8 are both welded (here, Sn96.5 / Ag3.0 / Cu0.5 high-temperature solder is used for welding) to the DBC positive electrode 9. The source of the upper bridge arm switch tube chip 5 and the anodes of the corresponding Schottky diode chips 6 and 8 are both connected to the output pole 15 of the upper layer PCB board through the corresponding power bonding wires 27. The drain of the lower bridge arm switch tube chip 7 and the cathodes of the corresponding Schottky diode chips 6 and 8 are both welded (here, Sn96.5 / Ag3.0 / Cu0.5 high-temperature solder is used for welding) to the DBC output pole 10. The source of the lower bridge arm switch tube chip 7 and the anodes of the corresponding Schottky diode chips 6 and 8 are both connected to the negative pole 16 of the upper layer PCB board through the corresponding power bonding wires 27.

[0058] The upper surface of the upper layer PCB board is also covered with an upper bridge arm MOS tube source copper layer 20, an upper bridge arm MOS tube gate copper layer 19, a lower bridge arm MOS tube source copper layer 22, and a lower bridge arm MOS tube gate copper layer 21. The upper bridge arm MOS tube source copper layer 20, the upper bridge arm MOS tube gate copper layer 19, the lower bridge arm MOS tube source copper layer 22, and the lower bridge arm MOS tube gate copper layer 21 are the four connection terminals of the drive circuit.

[0059] The gate of the upper bridge arm switch tube chip 5 is connected to the upper bridge arm MOS tube gate copper layer 19 through a drive bonding wire 26. The source of the upper bridge arm switch tube chip 5 is connected to the upper bridge arm MOS tube source copper layer 20 through a drive bonding wire 26. The gate of the lower bridge arm switch tube chip 7 is connected to the lower bridge arm MOS tube gate copper layer 21 through a drive bonding wire 26. The source of the lower bridge arm switch tube chip 7 is connected to the lower bridge arm MOS tube source copper layer 22 through a drive bonding wire 26. That is, in this embodiment, there are a total of 4 drive bonding wires 26 and 8 power bonding wires 27.

[0060] The encapsulation structure further includes a housing 3. The bottom of the housing 3 is open and buckled on the PCB board 2 for protecting the internal structure. Specifically, the housing 3 is fixed on the upper layer PCB by an adhesive bonding method. The top of the housing 3 is provided with a potting hole 28 for pouring potting glue 4 inward. Preferably, the aperture of the potting hole 28 is 2 mm - 4 mm. The potting glue 4 is poured into the space between the housing 3 and the PCB board 2 through the potting hole 28. The potting glue 4 described in this embodiment is a silicone gel with a working temperature exceeding 200 degrees Celsius. The height of the potting glue 4 is such that all bonding wires are immersed.

[0061] The copper-clad substrate 1 has three layers in total. The upper layer is the DBC copper layer, and the lower layer is the bottom copper layer 13. The copper used for the bottom copper layer 13 and the DBC copper layer is high-conductivity oxygen-free copper. The middle layer of the copper-clad substrate 1 is the insulating and heat-conducting layer 12, which is made of aluminum nitride ceramic. The insulating and heat-conducting layer 12 is used to support the DBC copper layer. The purpose of selecting aluminum nitride ceramic to make the insulating and heat-conducting layer 12 in this embodiment is to improve the heat-conducting performance, so as to efficiently conduct the heat generated by the power module into the bottom copper layer 13 for heat dissipation.

[0062] The DBC negative electrode 11 is of a frame structure. The DBC positive electrode 9 and the DBC output electrode 10 are both of a sheet structure and are both located inside the frame of the frame structure. The distance between the DBC positive electrode 9, the DBC negative electrode 11 and the DBC output electrode 10 is greater than the electrical insulation distance corresponding to the maximum operating voltage of the power switch tube chip. In the case of a working voltage of several hundred volts, the insulation distance should not be less than 1 mm. In this embodiment, the distance between the copper layers of the DBC positive electrode 9 and the DBC output electrode 10 is 3 mm, and the insulation distance between the copper layers of the DBC positive electrode 9, the DBC output electrode 10 and the DBC negative electrode 11 is 1 mm.

[0063] The lower-layer PCB board is fixed to the DBC copper layer by welding. The area on the DBC copper layer for welding with the lower-layer PCB board includes the entire DBC negative electrode 11, the left side of the DBC positive electrode 9 and the left side of the DBC output electrode 10.

[0064] The upper-layer PCB board positive electrode 14 and the upper-layer PCB board negative electrode 16 are both of a sheet structure. The upper-layer PCB board output electrode 15 is of a frame structure. The hollow window on the PCB board 2 that exposes the lower-bridge arm switch tube chip 7 is the lower-bridge hollow window 18, and the hollow window that exposes the upper-bridge arm switch tube chip 5 is the upper-bridge hollow window 17. The lower-bridge hollow window 18 is located inside the frame of the upper-layer PCB board output electrode 15. The upper-layer PCB board positive electrode 14 is covered on the upper surface of the upper-layer PCB board on the left side of the upper-bridge hollow window 17, and the upper-layer PCB board negative electrode 16 is covered on the upper surface of the upper-layer PCB board on the right side of the lower-bridge hollow window 18 and is located inside the frame of the upper-layer PCB board output electrode 15.

[0065] The lower-layer PCB board positive electrode 29 and the lower-layer PCB board output electrode 30 are both of a sheet structure. The lower-layer PCB board negative electrode 31 is of a frame structure. The upper-bridge hollow window 17 and the lower-bridge hollow window 18 are both located inside the frame of the lower-layer PCB board negative electrode 31. The lower-layer PCB board positive electrode 29 is covered on the upper surface of the lower-layer PCB board on the left side of the upper-bridge hollow window 17 and is located inside the frame of the lower-layer PCB board negative electrode 31. The lower-layer PCB board output electrode 30 is covered on the upper surface of the lower-layer PCB board between the upper-bridge hollow window 17 and the lower-bridge hollow window 18.

[0066] The power switch transistor chip can be a silicon MOSFET chip, an IGBT chip, a silicon carbide MOSFET chip, a gallium nitride MOSFET chip, etc.; preferably, a silicon carbide MOSFET chip is selected to achieve a higher switching speed and reduce the operating temperature. The Schottky diode chips 6 and 8 can be silicon SBD chips or silicon carbide SBD chips; preferably, silicon carbide SBD chips are selected.

[0067] Please refer to Figure 8 , the present invention also provides a packaging method for the packaging structure of the above low parasitic parameter power module, including the following steps:

[0068] S1: Manufacturing a copper-clad substrate 1 and a PCB board 2:

[0069] According to the power switch transistor chip to be packaged, the copper-clad substrate 1 and the PCB board 2 are prepared, and the DBC copper layer is divided into three parts: a DBC positive electrode 9, a DBC negative electrode 11, and a DBC output electrode 10 by etching.

[0070] The copper layers of the DBC positive electrode 9 and the DBC output electrode 10 match the size of the power switch transistor chip and are as small as possible; the number of the hollow windows is 2, and the window size matches the size of the power switch transistor chip to be packaged.

[0071] Before mounting the chips on the copper-clad substrate 1 and soldering the PCB board 2, the following process flow should also be included: the particulate matter and ionic impurities on the surfaces of the DBC copper layer and the PCB board 2 are removed by ultrasonic cleaning and chemical cleaning methods.

[0072] S2: Soldering the PCB board 2 on the DBC copper layer:

[0073] According to the structural characteristics of the DBC copper layer, a stencil is manufactured, and the high-temperature solder Sn96.5 / Ag3.0 / Cu0.5 is printed on the soldering surface of the DBC copper layer by screen printing.

[0074] S3: Mounting the power switch transistor chip:

[0075] The power switch transistor chip, the diode chip and the DBC copper layer are soldered by vacuum reflow soldering technology, and the power switch transistor chip and the diode chip are electrically connected to the PCB board by bonding wire connection. The number and thickness of the bonding wires can be selected according to the area of the chip electrodes and the magnitude of the current passing through, and no specific limitation is made here.

[0076] S4: Fixing the housing 3 to the PCB board 2, and injecting potting glue 4 through the potting hole 28 on the housing 3 until the potting glue 4 submerges all the driving bonding wires 26 and all the power bonding wires 27.

[0077] The outer shell 3 is made of a resin material and can completely surround the internal structure of the power module packaging structure. The silicone gel is filled into the outer shell 3 by the dispensing method. After potting, it is evacuated for 15 minutes to discharge air bubbles, and then left standing for 24 hours to wait for the silicone gel to cure.

[0078] In the case of no conflict, the above-mentioned embodiments in this article and the features in the embodiments can be combined with each other.

[0079] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A packaging structure of a low parasitic parameter power module, characterized in that, Comprising: A PCB board, which has a built-in power circuit. The PCB board includes an upper-layer PCB board and a lower-layer PCB board that are arranged vertically and electrically connected to each other. The power circuits in the upper-layer PCB board and the lower-layer PCB board have opposite current flow directions; A copper-clad substrate, including an insulating and heat-conducting layer and a DBC copper layer covering the upper surface of the insulating and heat-conducting layer. The PCB board is covered on the upper surface of the DBC copper layer, and the power switch tube chip is fixed to the DBC copper layer; the copper-clad substrate further includes a bottom copper layer, and the insulating and heat-conducting layer is sandwiched between the bottom copper layer and the DBC copper layer; The power switch tube chip is sequentially connected to the power circuits in the upper-layer PCB board and the lower-layer PCB board to form a power loop; A drive circuit is provided on the upper-layer PCB board. The power output terminal of the power switch tube chip is connected to the power circuit of the upper-layer PCB board through a power bonding wire. The drive circuit is connected to the drive terminal of the power switch tube chip through a drive bonding wire to drive the power switch tube chip to turn on or off. The power bonding wire and the drive bonding wire are perpendicular to each other; on the upper surface of the upper-layer PCB board, there are also covered with an upper-bridge-arm MOS tube source copper layer, an upper-bridge-arm MOS tube gate copper layer, a lower-bridge-arm MOS tube source copper layer, and a lower-bridge-arm MOS tube gate copper layer. The upper-bridge-arm MOS tube source copper layer, the upper-bridge-arm MOS tube gate copper layer, the lower-bridge-arm MOS tube source copper layer, and the lower-bridge-arm MOS tube gate copper layer are the four connection terminals of the drive circuit; The power switch tube chip includes an upper-bridge-arm switch tube chip and a lower-bridge-arm switch tube chip connected in series; The drive circuit is connected to the source and gate of the upper-bridge-arm switch tube chip and the lower-bridge-arm switch tube chip through multiple drive bonding wires to respectively control the switching of the upper-bridge-arm switch tube chip and the lower-bridge-arm switch tube chip; The external input power supply is connected to the drain of the upper-bridge-arm switch tube chip through the input terminal on the PCB board. The sources of the upper-bridge-arm switch tube chip and the lower-bridge-arm switch tube chip are both power output terminals. The source of the upper-bridge-arm switch tube chip is connected to the upper-layer PCB board through the corresponding power bonding wire. The upper-layer PCB board is connected to the drain of the lower-bridge-arm switch tube chip through the lower-layer PCB board. The source of the lower-bridge-arm switch tube chip is connected to the output terminal on the PCB board through the corresponding power bonding wire and the power circuit to output power externally; On the upper surface of the upper-layer PCB board, there are covered with an upper-layer PCB board positive electrode, an upper-layer PCB board negative electrode, and an upper-layer PCB board output electrode; on the upper surface of the lower-layer PCB board, there are covered with a lower-layer PCB board positive electrode, a lower-layer PCB board negative electrode, and a lower-layer PCB board output electrode; the DBC copper layer includes a DBC positive electrode, a DBC negative electrode, and a DBC output electrode; The drain of the upper-bridge-arm switching transistor chip is electrically connected to the positive electrode of the upper-layer PCB board, the positive electrode of the lower-layer PCB board, and the positive electrode of the DBC. The drain of the lower-bridge-arm switching transistor chip is electrically connected to the output terminal of the upper-layer PCB board, the output terminal of the lower-layer PCB board, and the output terminal of the DBC. The negative electrode of the upper-layer PCB board is electrically connected to the negative electrode of the lower-layer PCB board; the positive electrode of the upper-layer PCB board is connected to the input terminal, and the negative electrode of the lower-layer PCB board and the output terminal of the lower-layer PCB board are both connected to the output terminal. When both the upper-bridge-arm switching transistor chip and the lower-bridge-arm switching transistor chip are turned on, the current on the input terminal flows from the positive electrode of the upper-layer PCB board into the positive electrode of the lower-layer PCB board, the positive electrode of the DBC, the drain of the upper-bridge-arm switching transistor chip, the source of the upper-bridge-arm switching transistor chip, the output terminal of the upper-layer PCB board, the output terminal of the lower-layer PCB board, the output terminal of the DBC, the drain of the lower-bridge-arm switching transistor chip, the source of the lower-bridge-arm switching transistor chip, the negative electrode of the upper-layer PCB board, the negative electrode of the lower-layer PCB board, and is output from the output terminal.

2. The packaging structure of the low parasitic parameter power module according to claim 1, characterized in that: There are several through-holes penetrating the upper and lower layers on the PCB board, and electrical connectors are arranged in the through-holes. The drain of the upper-bridge-arm switching transistor chip is electrically connected to the positive electrode of the upper-layer PCB board, the positive electrode of the lower-layer PCB board, and the positive electrode of the DBC through the electrical connectors in the corresponding through-holes. The drain of the lower-bridge-arm switching transistor chip is electrically connected to the output terminal of the upper-layer PCB board, the output terminal of the lower-layer PCB board, and the output terminal of the DBC through the electrical connectors in the corresponding through-holes. The negative electrode of the upper-layer PCB board is electrically connected to the negative electrode of the lower-layer PCB board through the electrical connectors in the corresponding through-holes. All the through-holes are vertical holes. There are also hollow windows penetrating the upper-layer PCB board and the lower-layer PCB board on the PCB board. The power switching transistor chips are exposed in the hollow windows. There are two hollow windows, which expose the upper-bridge-arm switching transistor chip and the lower-bridge-arm switching transistor chip respectively. When the power bonding wires and the driving bonding wires are connected to the power switching transistor chips and the PCB board, they both pass through the corresponding hollow windows.

3. The encapsulation structure of the low parasitic parameter power module according to claim 1, characterized in that: The power switching transistor chip also includes two Schottky diode chips, and the upper-bridge-arm switching transistor chip and the lower-bridge-arm switching transistor chip are respectively anti-parallel connected to a Schottky diode chip.

4. The encapsulation structure of the low parasitic parameter power module according to claim 3, characterized in that: The drain of the upper-bridge-arm switching transistor chip and the cathode of the corresponding Schottky diode chip are both welded to the positive electrode of the DBC. The source of the upper-bridge-arm switching transistor chip and the anode of the corresponding Schottky diode chip are both connected to the output terminal of the upper-layer PCB board through the corresponding power bonding wires; the drain of the lower-bridge-arm switching transistor chip and the cathode of the corresponding Schottky diode chip are both welded to the output terminal of the DBC. The source of the lower-bridge-arm switching transistor chip and the anode of the corresponding Schottky diode chip are both connected to the negative electrode of the upper-layer PCB board through the corresponding power bonding wires.

5. The encapsulation structure of the low parasitic parameter power module according to claim 1, characterized in that: The gate of the upper-bridge switching transistor chip is connected to the copper layer of the upper-bridge MOS transistor gate through a driving bonding wire, and the source-drain of the upper-bridge switching transistor chip is connected to the copper layer of the upper-bridge MOS transistor source through a driving bonding wire. The gate of the lower-bridge switching transistor chip is connected to the copper layer of the lower-bridge MOS transistor gate through a driving bonding wire, and the source of the lower-bridge switching transistor chip is connected to the copper layer of the lower-bridge MOS transistor source through a driving bonding wire.

6. The encapsulation structure of the low parasitic parameter power module according to claim 2, characterized in that: The packaging structure further includes a housing. The bottom of the housing is open and buckles on the upper surface of the upper-layer PCB board. The top of the housing is provided with a potting hole for pouring potting glue inward, and all driving bonding wires and all power bonding wires are immersed in the potting glue. The bottom copper layer is a heat dissipation layer, and the insulating and heat-conducting layer is an aluminum nitride ceramic layer. The DBC negative electrode is a frame structure, and both the DBC positive electrode and the DBC output electrode are sheet structures and are both located within the frame of the frame structure. The distance between the DBC positive electrode, the DBC negative electrode, and the DBC output electrode is greater than the electrical insulation distance corresponding to the maximum operating voltage of the power switching transistor chip. The lower-layer PCB board is fixed to the DBC copper layer by welding. The area on the DBC copper layer for welding with the lower-layer PCB board includes the entire DBC negative electrode, the left side of the DBC positive electrode, and the left side of the DBC output electrode. Both the positive electrode of the upper-layer PCB board and the negative electrode of the upper-layer PCB board are sheet structures. The output electrode of the upper-layer PCB board is a frame structure. The hollow window on the PCB board exposing the lower-bridge switching transistor chip is the lower-bridge hollow window, and the hollow window exposing the upper-bridge switching transistor chip is the upper-bridge hollow window. The lower-bridge hollow window is located within the frame of the output electrode of the upper-layer PCB board. The positive electrode of the upper-layer PCB board covers the upper surface of the upper-layer PCB board on the left side of the upper-bridge hollow window. The negative electrode of the upper-layer PCB board covers the upper surface of the upper-layer PCB board on the right side of the lower-bridge hollow window and is located within the frame of the output electrode of the upper-layer PCB board. Both the positive electrode of the lower-layer PCB board and the output electrode of the lower-layer PCB board are sheet structures. The negative electrode of the lower-layer PCB board is a frame structure. Both the upper-bridge hollow window and the lower-bridge hollow window are located within the frame of the negative electrode of the lower-layer PCB board. The positive electrode of the lower-layer PCB board covers the upper surface of the lower-layer PCB board on the left side of the upper-bridge hollow window and is located within the frame of the negative electrode of the lower-layer PCB board. The output electrode of the lower-layer PCB board covers the upper surface of the lower-layer PCB board between the upper-bridge hollow window and the lower-bridge hollow window.

7. A packaging method for a packaging structure of a low-parasitic-parameter power module according to any one of claims 1 to 6, characterized in that, It includes the following steps: S1: Manufacture a copper-clad substrate and a PCB board. S2: Weld the PCB board to the DBC copper layer. S3: Mount the power switching transistor chip. S4: Fix the housing to the PCB board, and inject potting glue inward through the potting hole on the housing until all driving bonding wires and all power bonding wires are immersed in the potting glue.

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