An arc detector for vacuum coating pulse bias film power supply

Abstract

The present invention belongs to the fields of automatic control technology and power electronics technology, and specifically relates to an arc detector for a vacuum coating pulse bias film power supply. When the power supply outputs a high-frequency pulse, the arc detector continuously samples the inductor current value within the duty cycle of the power supply output pulse, and calculates the slope of the inductor current change. In this way, at the early stage of arc generation, the arc current begins to rise, and the controller has detected the arc, and then quickly cuts off the output energy of the power supply to reduce the arc energy. Since the arc detector adopts a method of directly sampling the inductor current and quickly calculating the current change rate, the occurrence of the arc can be detected at the early stage of the arc current climbing, and the power supply output can be cut off more quickly, so that the arc energy can be more effectively suppressed and the arc can be extinguished, thereby improving the coating quality, product yield and production efficiency.

Description

Technical Field

[0001] The invention belongs to the field of automatic control technology and power electronics technology, and in particular relates to an arc detector of a vacuum coating pulse bias film power supply. Background Art

[0002] The field of vacuum coating technology requires a lot of pulse bias deposition thin film technology. The load of the pulse bias power supply for vacuum coating is plasma. This load is very easy to produce arc phenomenon. The arc has a negative impact on the coating process, affects the coating quality, and even damages the workpiece. The traditional arc judgment method is to detect the arc current or arc voltage to judge the arc phenomenon of the load. The lower the arc current judgment threshold is set, the earlier the arc can be judged. In addition, the higher the arc voltage judgment threshold is set, the earlier the arc can be judged. However, the plasma load is not stable, and the output current of the power supply fluctuates. Therefore, the threshold cannot be set too low, otherwise the arc will be misjudged, the protection will be too sensitive, and the vacuum coating process cannot proceed normally. For the same type of vacuum coating pulse bias power supply, the output current of the pulse bias power supply is different for different coating processes and different process sections of the same coating process. Therefore, there is a big problem in detecting the occurrence of arcs based on the arc current judgment threshold: the staff is required to change the setting value of the arc current judgment threshold according to the load current size at different process stages. However, when the arc current judgment threshold is set relatively high, when the power load arcs, the arc current climbs to the arc current judgment threshold to detect the arc. The peak value of the arc current is relatively large, and the arc energy is high, which will damage the coated workpiece and have a fatal impact on the quality of the coating process. In addition, the output voltage of the bias power supply is different for different coating processes and different process sections of the same coating process. The setting of the arc voltage judgment threshold must also change accordingly, making the operation of the bias power supply during coating complicated. Due to the inductive and capacitive distribution parameters of the leads and loads between the power supply and the load, the pulse front edge of the pulse bias power supply output has oscillations. If the arc voltage judgment threshold is set high, the detection is too sensitive and misjudged as an arc, and the power supply mistakenly shuts off the output, affecting the coating process. The arc voltage judgment threshold is set too low, lower than the arc voltage, and the arc cannot be detected. When the pulse bias power supply outputs a low voltage of tens of volts to deposit a thin film, the coating voltage is close to the arc voltage, and the arc voltage judgment threshold is close to the former two. The boundaries between the coating voltage, the arc voltage judgment threshold and the arc voltage are not obvious. The method of using arc voltage to judge the arc cannot accurately judge the arc at this time. A vacuum coating power supply with fast and accurate arc detection and power arc management measures that do not require human intervention has a vital impact on the coating process. In addition, in order to reduce the adverse effects of arc discharge, it is hoped that the arc can be automatically judged in the early stage of the arc current climb, so as to shut down the power output energy as soon as possible and reduce the harm of the arc that has occurred. Summary of the invention

[0003] The purpose of the present invention is to provide an arc detector for a vacuum coating pulse bias power supply. When the power supply outputs a high-frequency pulse, the arc detector continuously samples the inductor current value within the duty cycle of the power supply output pulse and calculates the slope of the inductor current change. In this way, at the initial stage of arc generation, the arc current begins to rise, and the controller has detected the arc, and then quickly shuts off the output energy of the power supply to reduce the arc energy.

[0004] The technical solution of the present invention is as follows:

[0005] An arc detector for a vacuum coating pulse bias film power supply, comprising an arc suppression circuit, a current transformer LEM, an ADC adopting circuit and a programmable logic device, wherein the internal circuit of the programmable logic device comprises a multi-pulse enabling circuit, a first register, a second register, a subtractor, a divider, a slope comparison circuit, a PWM pulse forming circuit and an SPI serial port register;

[0006] The arc suppression circuit is connected to the positive output terminal of the output high-voltage pulse forming unit of the pulse power supply, and the inductance of the arc suppression circuit is used to suppress the maximum rising rate of the arc current;

[0007] The current transformer LEM is mounted on one end of the output line of the inductor of the arc suppression circuit to sense the magnitude of the inductor current and convert the inductor current into an isolated voltage weak current signal;

[0008] The programmable logic device controls the ADC sampling circuit to sample the voltage signal output by the current transformer LEM within the duty cycle time of the power supply PWM pulse drive signal, and calculates the timely slope of the current, compares the timely slope with the preset threshold of the current slope, and determines whether an arc is generated in the load. If an arc is generated, the power supply PWM pulse drive signal is blocked to shut down the high-voltage output pulse of the output high-voltage pulse forming unit of the power supply;

[0009] The arc suppression circuit is composed of an inductor L and at least one diode D connected in parallel, the positive output end of the output high-voltage pulse forming unit of the pulse power supply is connected to the cathode of the diode assembly, and the anode of the diode is connected to one end of the plasma load;

[0010] The current transformer LEM is sleeved on one end of the output line of the inductor of the arc suppression circuit, and the sampling signal output end of the current transformer LEM is connected in parallel with the sampling resistor to convert the inductor current into an isolated voltage signal;

[0011] The output resistance sampling signal of the current transformer LEM is connected to the analog signal input terminal of the ADC sampling circuit, and the ADC sampling circuit can sample the output resistance sampling signal of the current transformer LEM in a timely manner;

[0012] The parallel data output signal port Data, the sampling enable input signal port EN1, the chip select input signal port CS and the read data input signal port RD of the ADC sampling circuit are respectively connected to the I / O port of the programmable logic device, so that the programmable logic device can timely control the ADC to adopt the circuit to sample the analog input signal and read the sampled data;

[0013] The output I / O port of the programmable logic device is connected to the input end of the driving isolation circuit, and the output end of the driving isolation circuit is connected to the control input end of the output high-voltage pulse forming unit of the pulse power supply, so as to realize the driving and blocking control of the output pulse of the power supply;

[0014] The internal circuit of the programmable logic device includes a multi-pulse enabling circuit, two serially connected first-in-first-out registers, a subtractor, a divider, a slope comparison circuit, a PWM pulse forming circuit, and an SPI serial port register.

[0015] An arc detector for a vacuum coating pulse bias film power supply, wherein the PWM pulse forming circuit inside the programmable logic device outputs a driving signal of a switch tube of an output high-voltage pulse forming unit of the pulse power supply, the frequency range of the driving signal is 20kHz to 100kHz, and also outputs a synchronization signal of the driving signal of the output high-voltage pulse forming unit of the pulse power supply; the pulse leading edge of the synchronization signal lags behind the driving signal leading edge of the high-voltage pulse forming unit by 500ns to 2us, but the trailing edge is synchronized; the synchronization signal is transmitted to an input end of a multi-pulse enabling circuit inside the programmable logic device, so that the multi-pulse enabling circuit starts or stops outputting multi-channel enabling signals;

[0016] The internal multi-pulse enabling circuit of the programmable logic device also includes outputting first, second, third, fourth, fifth, and sixth enabling output signals, a chip select signal CS, and a read enable signal RD, which are respectively used to enable and control the ADC adopting circuit, the first register, the second register, the subtractor, the divider, and the slope comparison circuit;

[0017] The multi-pulse enable circuit inside the programmable logic device outputs a first enable output signal EN1 to the sampling enable input signal terminal of the ADC adopting circuit, the frequency of the first enable output signal EN1 is 1mHz, and the duty cycle is 50%, so as to control the sampling start and sampling cycle of the ADC adopting circuit, and the falling edge of the first enable output signal EN1 starts the sampling and holding function of the ADC adopting circuit;

[0018] The chip select signal CS and the read enable signal RD output by the internal multi-pulse enable circuit of the programmable logic device are respectively transmitted to the chip select input terminal CS and the read enable input terminal RD of the ADC circuit, and the falling edge of the chip select signal CS and the read enable signal RD lags behind the falling edge of the first enable output signal by 50ns.

[0019] An arc detector for a vacuum coating pulse bias film power supply, wherein the parallel data input end of the first register is connected to the sampling data parallel output end of an ADC adopting circuit, and the parallel data output end of the first register is connected to the parallel data input end of a second register.

[0020] An arc detector for a vacuum coating pulse bias film power supply, wherein the second enable output signal EN2 of the multi-pulse enable circuit is transmitted to the shift enable input terminal of the first register, and the third enable output signal EN3 of the multi-pulse enable circuit is transmitted to the shift enable input terminal of the second register;

[0021] The second enable output signal EN2 lags behind the falling edge of the read enable signal RD by 30 ns, and the falling edge of the third enable output signal EN3 lags behind the falling edge of the read enable signal RD by 20 ns, so that the data of the first register is shifted to the second register in parallel.

[0022] An arc detector for a vacuum coating pulse bias film power supply, wherein a first data input terminal of the subtractor is connected to a parallel data output terminal of a first register, and a second data input terminal of the subtractor is connected to a parallel data output terminal of a second register; a fourth enable output signal EN4 of a multi-pulse enable circuit is transmitted to the enable input terminal of the subtractor, and a falling edge of the fourth enable output signal EN4 lags behind a falling edge of a read enable signal RD by 40ns. At this falling edge, the subtractor performs subtraction of the first data from the second data, and the difference is used as output data of the subtractor;

[0023] An arc detector for a vacuum coating pulse bias film power supply, wherein the parallel data input terminal of the dividend of the divider is connected to the parallel data output terminal of the subtractor, and the divisor of the divider is fixed to 1. The fifth enable output signal EN5 of the multi-pulse enable circuit is transmitted to the enable input terminal of the divider, and the falling edge of the fifth enable output signal EN5 lags behind the falling edge of the read enable signal RD by 50ns, and the falling edge enables the division operation, and the quotient of the divider is the current current change rate, which is used as the output of the divider.

[0024] An arc detector for a vacuum coating pulse bias film power supply, wherein the positive parallel data input terminal of the slope comparison circuit is connected to the parallel data output terminal of the quotient of the divider, and the negative parallel data input terminal of the slope comparison circuit is connected to the parallel data output terminal of the SPI serial port register, and the SPI serial port register can modify the negative parallel data of the slope comparison circuit;

[0025] The sixth enable output signal EN6 of the multi-pulse enable circuit is transmitted to the enable input terminal of the slope comparison circuit. The falling edge of the sixth enable output signal EN6 lags behind the falling edge of the read enable signal RD by 60ns. The falling edge enables the slope comparison operation. When the positive parallel data of the slope comparison circuit is greater than the negative parallel data of the slope comparison circuit, the slope comparison circuit outputs a high level signal, otherwise it outputs a low level signal.

[0026] An arc detector for a vacuum coating pulse bias film power supply, wherein the shutdown enable input terminal of the PWM pulse forming circuit is connected to the output terminal of the slope comparison circuit, the drive signal output by the PWM pulse forming circuit is connected to the input terminal of the drive isolation circuit, and the output terminal of the drive isolation circuit is connected to the input terminal of the output high-voltage pulse forming unit of the pulse power supply; when the slope comparison circuit outputs a high level, the drive signal output by the PWM pulse forming circuit is turned off, and the drive signal is restored after the shutdown protection time.

[0027] An arc detector of a vacuum coating pulse bias film power supply, wherein the multi-pulse enabling circuit comprises a periodic pulse signal generator, a delay circuit A, a delay circuit B, a delay circuit C, a delay circuit D, a delay circuit E and a delay circuit F;

[0028] The periodic pulse signal generator counts and divides the clock signal CLOCK, and outputs a first enable output signal EN1, and SEN is a synchronization signal input terminal of the periodic pulse signal generator;

[0029] The first enable output signal EN1 is connected to the input end of the delay circuit A, and the delay circuit A outputs the chip select signal CS and the read enable signal RD;

[0030] The read enable signal RD is connected to the input end of the delay circuit B, and the delay circuit B outputs a third enable output signal EN3;

[0031] The third enable output signal EN3 is connected to the input end of the delay circuit C, and the delay circuit C outputs the second enable output signal EN2;

[0032] The second enable output signal EN2 is connected to the input end of the delay circuit D, and the delay circuit D outputs a fourth enable output signal EN4;

[0033] The fourth enable output signal EN4 is connected to the input end of the delay circuit E, and the delay circuit E outputs the fifth enable output signal EN5;

[0034] The fifth enable output signal EN5 is connected to the input end of the delay circuit F, and the delay circuit F outputs the sixth enable output signal EN6.

[0035] The beneficial effects of the present invention are:

[0036] Since the arc detector adopts the method of directly sampling the inductor current and quickly calculating the current change rate, it can detect the occurrence of arc in the early stage of arc current climbing and can shut down the power output more quickly, so as to more effectively suppress the arc energy and extinguish the arc, thereby improving the coating quality, product yield and production efficiency.

[0037] In addition, when using the traditional arc current judgment method and arc voltage judgment method to detect arcs, the user must first evaluate the timely values ​​of the load current and arc voltage under different coating processes, and then appropriately set the threshold of the arc current judgment and the threshold of the arc voltage judgment method. Improper threshold setting will cause excessive arc energy or the power supply to misjudge the arc generation and frequently shut down the power output, making the coating process quality impossible to guarantee. However, by using the method of directly detecting the rate of change of the inductor current, there is no need to manually and frequently set the threshold of the arc current judgment and the threshold of the arc voltage judgment method, thereby improving production efficiency; it can overcome the problem of low arc detection accuracy and uncertain arc detection time caused by inaccurate arc judgment threshold setting. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a block diagram of the hardware system structure of the present invention;

[0039] Figure 2 This is a schematic diagram of the multi-pulse enabling circuit of the present invention.

[0040] In the figure: 101, plasma load; 102, output high voltage pulse forming unit of pulse power supply; 103, ADC adopting circuit; 104, drive isolation circuit; 105, first register; 106, second register; 107, subtractor; 108, divider; 109, SPI serial port register; 110, slope comparison circuit; 111, PWM pulse forming circuit; 112, multi-pulse enabling circuit; 113, programmable logic device;

[0041] 201. Periodic pulse signal generator; 202. Delay circuit A; 203. Delay circuit B; 204. Delay circuit C; 205. Delay circuit D; 206. Delay circuit E; 207. Delay circuit F. DETAILED DESCRIPTION

[0042] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0043] See also Figure 1As shown, an embodiment of the present invention provides an arc detector for a vacuum coating pulse bias power supply, including an arc suppression circuit, a current transformer LEM, an ADC adopting circuit 103 and a programmable logic device 113. The internal circuit of the programmable logic device 113 includes a multi-pulse enabling circuit 112, a first register 105, a second register 106, a subtractor 107, a divider 108, a slope comparison circuit 110, a PWM pulse forming circuit 111 and an SPI serial port register 109.

[0044] Among them, the arc suppression circuit is connected to the positive output end of the output high-voltage pulse forming unit 102 of the pulse power supply, and the inductance of the arc suppression circuit is used to suppress the maximum rise rate of the arc current. The current transformer LEM is sleeved on the output line of one end of the inductance of the arc suppression circuit, and is used to sense the magnitude of the inductor current and convert the inductor current into an isolated voltage weak current signal. The programmable logic device 113 controls the ADC sampling circuit 103 to sample the voltage signal output by the current transformer LEM within the duty cycle time of the power supply PWM pulse drive signal, and calculates the timely slope of the current, compares the timely slope with the preset threshold of the current slope, and determines whether the load has generated an arc. If an arc is generated, the power supply PWM pulse drive signal is blocked to turn off the strong current output pulse of the output high-voltage pulse forming unit of the power supply.

[0045] The arc suppression circuit is composed of an inductor L and at least one diode D in parallel. The positive output terminal of the output high-voltage pulse forming unit 102 of the pulse power supply is connected to the cathode of the diode assembly, and the anode of the diode is connected to one end of the plasma load 101.

[0046] The current transformer LEM is sleeved on one end of the output line of the inductor of the arc suppression circuit, and the sampling signal output end of the current transformer LEM is connected in parallel with the sampling resistor to convert the inductor current into an isolated voltage signal.

[0047] The output resistance sampling signal of the current transformer LEM is connected to the analog signal input terminal of the ADC sampling circuit 103. The ADC sampling circuit 103 can sample the output resistance sampling signal of the current transformer LEM in a timely manner.

[0048] The parallel data output signal port Data, sampling enable input signal port EN1, chip select input signal port CS and read data input signal port RD of the ADC sampling circuit 103 are respectively connected to the I / O port of the programmable logic device 113, so that the programmable logic device 113 controls the ADC circuit 103 to sample the analog input signal and read the sampled data in a timely manner.

[0049] The output I / O port of the programmable logic device 113 is connected to the input end of the driving isolation circuit 104, and the output end of the driving isolation circuit 104 is connected to the control input end of the output high-voltage pulse forming unit 102 of the pulse power supply, thereby realizing the driving and blocking control of the power supply output pulse.

[0050] The internal circuit of the programmable logic device 113 includes a multi-pulse enable circuit 112, two first-in-first-out registers 105 and 106 connected in series, a subtractor 107, a divider 108, a slope comparison circuit 110, a PWM pulse forming circuit 111, and an SPI serial port register 109.

[0051] The PWM pulse forming circuit 111 inside the programmable logic device 113 outputs the driving signal of the switch tube of the output high-voltage pulse forming unit 102 of the pulse power supply, and the frequency range of the driving signal is 20kHz to 100kHz. It also outputs the synchronization signal of the driving signal of the output high-voltage pulse forming unit 102 of the pulse power supply. The pulse leading edge of the synchronization signal lags behind the leading edge of the driving signal of the high-voltage pulse forming unit by 500ns to 2us, but the trailing edge is synchronized. The synchronization signal is transmitted to an input end of the multi-pulse enabling circuit 112 inside the programmable logic device 113, so that the multi-pulse enabling circuit 112 starts or stops outputting multi-channel enabling signals.

[0052] The internal multi-pulse enable circuit 112 of the programmable logic device 113 also includes outputting first, second, third, fourth, fifth and sixth enable output signals EN1, EN2, EN3, EN4, EN5 and EN6, a chip select signal CS and a read enable signal RD, which are respectively used to enable and control the ADC adopting circuit 103, the first register 105, the second register 106, the subtractor 107, the divider 108 and the slope comparison circuit 110.

[0053] The multi-pulse enable circuit 112 inside the programmable logic device 113 outputs a first enable output signal EN1 to the sampling enable input signal terminal of the ADC adopting circuit 103. The frequency of the first enable output signal EN1 is 1mHz and the duty cycle is 50% to control the sampling start and sampling period of the ADC adopting circuit 103. The falling edge of the first enable output signal EN1 starts the sampling and holding function of the ADC adopting circuit 103.

[0054] The chip select signal CS and the read enable signal RD output by the multi-pulse enable circuit 112 inside the programmable logic device 113 are respectively transmitted to the chip select input terminal CS and the read enable input terminal RD of the ADC adopting circuit 103. The falling edge of the chip select signal CS and the read enable signal RD lags behind the falling edge of the first enable output signal by 50ns.

[0055] The parallel data input terminal of the first register 105 is connected to the sampled data parallel output terminal of the ADC adopting circuit 103 , and the parallel data output terminal of the first register 105 is connected to the parallel data input terminal of the second register 106 .

[0056] The second enable output signal EN2 of the multi-pulse enable circuit 112 is transmitted to the shift enable input terminal of the first register 105, and the third enable output signal EN3 of the multi-pulse enable circuit 112 is transmitted to the shift enable input terminal of the second register 106. The second enable output signal EN2 lags behind the falling edge of the read enable signal RD by 30ns, and the falling edge of the third enable output signal EN3 lags behind the falling edge of the read enable signal RD by 20ns, so that the data of the first register 105 is shifted to the second register 106 in parallel.

[0057] The first data input terminal of the subtractor 107 is connected to a parallel data output terminal of the first register 105, and the second data input terminal of the subtractor 107 is connected to the parallel data output terminal of the second register 106. The fourth enable output signal EN4 of the multi-pulse enable circuit 112 is transmitted to the enable input terminal of the subtractor 107. The falling edge of the fourth enable output signal EN4 lags behind the falling edge of the read enable signal RD by 40ns. At the falling edge, the subtractor 107 performs the subtraction of the first data from the second data, and the difference is used as the output data of the subtractor 107.

[0058] The parallel data input terminal of the dividend of the divider 108 is connected to the parallel data output terminal of the subtractor 107, and the divisor of the divider 108 is fixed to 1. The fifth enable output signal EN5 of the multi-pulse enable circuit 112 is transmitted to the enable input terminal of the divider 108, and the falling edge of the fifth enable output signal EN5 lags behind the falling edge of the read enable signal RD by 50ns, and the falling edge enables the division operation, and the quotient of the divider 108 is the current current change rate, which is used as the output of the divider 108.

[0059] The positive parallel data input terminal of the slope comparison circuit 110 is connected to the parallel data output terminal of the quotient of the divider 108, and the negative parallel data input terminal of the slope comparison circuit 110 is connected to the parallel data output terminal of the SPI serial port register 109. The SPI serial port register 109 can modify the negative parallel data of the slope comparison circuit 110.

[0060] The sixth enable output signal EN6 of the multi-pulse enable circuit 112 is transmitted to the enable input terminal of the slope comparison circuit 110. The falling edge of the sixth enable output signal EN6 lags behind the falling edge of the read enable signal RD by 60ns. The falling edge enables the slope comparison operation. When the positive parallel data of the slope comparison circuit 110 is greater than the negative parallel data of the slope comparison circuit 110, the slope comparison circuit 110 outputs a high level signal, otherwise it outputs a low level signal.

[0061] The shutdown enable input terminal of the PWM pulse forming circuit 111 is connected to the output terminal of the slope comparison circuit 110, the driving signal output by the PWM pulse forming circuit 111 is connected to the input terminal of the driving isolation circuit 104, and the output terminal of the driving isolation circuit 104 is connected to the input terminal of the output high-voltage pulse forming unit 102 of the pulse power supply. When the slope comparison circuit 110 outputs a high level, the driving signal output by the PWM pulse forming circuit 111 is turned off, and the driving signal is restored after the shutdown protection time.

[0062] The multi-pulse enabling circuit 112 includes a periodic pulse signal generator 201 , a delay circuit A 202 , a delay circuit B 203 , a delay circuit C 204 , a delay circuit D 205 , a delay circuit E 206 and a delay circuit F 207 .

[0063] The periodic pulse signal generator 201 counts and divides the clock signal CLOCK, and outputs a first enable output signal EN1 . SEN is a synchronization signal input terminal of the periodic pulse signal generator 201 .

[0064] The first enable output signal EN1 is connected to the input end of the delay circuit A202, and the delay circuit A202 outputs the chip select signal CS and the read enable signal RD.

[0065] The read enable signal RD is connected to the input terminal of the delay circuit B203, and the delay circuit B203 outputs a third enable output signal EN3.

[0066] The third enable output signal EN3 is connected to the input end of the delay circuit C204, and the delay circuit C204 outputs the second enable output signal EN2.

[0067] The second enable output signal EN2 is connected to the input end of the delay circuit D205, and the delay circuit D205 outputs a fourth enable output signal EN4.

[0068] The fourth enable output signal EN4 is connected to the input terminal of the delay circuit E206, and the delay circuit E206 outputs the fifth enable output signal EN5.

[0069] The fifth enable output signal EN5 is connected to the input terminal of the delay circuit F207, and the delay circuit F207 outputs the sixth enable output signal EN6.

Claims

1. An arc detector for a vacuum coating pulse bias film power supply, comprising an arc suppression circuit, a current transformer LEM, an ADC sampling circuit (103) and a programmable logic device (113), wherein the internal circuit of the programmable logic device (113) comprises a multi-pulse enabling circuit (112), a first register (105), a second register (106), a subtractor (107), a divider (108), a slope comparison circuit (110), a PWM pulse forming circuit (111) and an SPI serial port register (109); Features: The arc suppression circuit is composed of an inductor L and at least one diode D connected in parallel, the forward output end of the output high-voltage pulse forming unit (102) of the pulse power supply is connected to the cathode of the diode assembly, and the anode of the diode is connected to one end of the plasma load (101); The current transformer LEM is sleeved on one end of the output line of the inductor of the arc suppression circuit, and the sampling signal output end of the current transformer LEM is connected in parallel with the sampling resistor to convert the inductor current into an isolated voltage signal; The output resistance sampling signal of the current transformer LEM is connected to the analog signal input terminal of the ADC sampling circuit (103), and the ADC sampling circuit (103) can timely sample the output resistance sampling signal of the current transformer LEM; The parallel data output signal port Data, the sampling enable input signal port EN1, the chip select input signal port CS and the read data input signal port RD of the ADC sampling circuit (103) are respectively connected to the I / O port of the programmable logic device (113), so that the programmable logic device (113) controls the ADC sampling circuit (103) to sample the analog input signal and read the sampled data in a timely manner; The output I / O port of the programmable logic device (113) is connected to the input end of the drive isolation circuit (104), and the output end of the drive isolation circuit (104) is connected to the control input end of the output high-voltage pulse forming unit (102) of the pulse power supply, so as to realize the driving and blocking control of the output pulse of the power supply; The internal circuit of the programmable logic device (113) includes a multi-pulse enabling circuit (112), two first-in-first-out registers (105, 106) connected in series, a subtractor (107), a divider (108), a slope comparison circuit (110), a PWM pulse forming circuit (111), and an SPI serial port register (109).

2. The arc detector of the vacuum coating pulse bias film power supply according to claim 1, characterized in that: The PWM pulse forming circuit (111) inside the programmable logic device (113) outputs a driving signal of a switch tube of an output high-voltage pulse forming unit (102) of a pulse power supply, wherein the frequency range of the driving signal is 20kHz to 100kHz, and also outputs a synchronization signal of the driving signal of the output high-voltage pulse forming unit (102) of the pulse power supply; the pulse leading edge of the synchronization signal lags behind the leading edge of the driving signal of the high-voltage pulse forming unit by 500ns to 2us, but the trailing edge is synchronized; the synchronization signal is transmitted to an input end of a multi-pulse enabling circuit (112) inside the programmable logic device (113), so that the multi-pulse enabling circuit (112) starts or stops outputting multi-channel enabling signals; The multi-pulse enabling circuit (112) inside the programmable logic device (113) further includes outputting first, second, third, fourth, fifth and sixth enabling output signals, a chip selection signal CS and a read enable signal RD, which are respectively used to enable and control the ADC sampling circuit (103), the first register (105), the second register (106), the subtractor (107), the divider (108) and the slope comparison circuit (110); The multi-pulse enable circuit (112) inside the programmable logic device (113) outputs a first enable output signal EN1 to a sampling enable input signal terminal of the ADC sampling circuit (103), wherein the frequency of the first enable output signal EN1 is 1 MHz and the duty cycle is 50%, so as to control the sampling start and sampling cycle of the ADC sampling circuit (103), and the falling edge of the first enable output signal EN1 starts the sampling and holding function of the ADC sampling circuit (103); The chip select signal CS and the read enable signal RD outputted by the multi-pulse enable circuit (112) inside the programmable logic device (113) are respectively transmitted to the chip select input terminal CS and the read enable input terminal RD of the ADC sampling circuit (103), and the falling edges of the chip select signal CS and the read enable signal RD lag behind the falling edge of the first enable output signal by 50ns.

3. The arc detector of the vacuum coating pulse bias film power supply according to claim 1, characterized in that: The parallel data input terminal of the first register (105) is connected to the sampling data parallel output terminal of the ADC sampling circuit (103), and the parallel data output terminal of the first register (105) is connected to the parallel data input terminal of the second register (106).

4. The arc detector of the vacuum coating pulse bias film power supply according to claim 1, characterized in that: The second enable output signal EN2 of the multi-pulse enable circuit (112) is transmitted to the shift enable input terminal of the first register (105), and the third enable output signal EN3 of the multi-pulse enable circuit (112) is transmitted to the shift enable input terminal of the second register (106); The second enable output signal EN2 lags behind the falling edge of the read enable signal RD by 30ns, and the falling edge of the third enable output signal EN3 lags behind the falling edge of the read enable signal RD by 20ns, so that the data of the first register (105) is shifted to the second register (106) in parallel.

5. The arc detector of the vacuum coating pulse bias film power supply according to claim 1, characterized in that: The first data input terminal of the subtractor (107) is connected to a parallel data output terminal of the first register (105), and the second data input terminal of the subtractor (107) is connected to the parallel data output terminal of the second register (106); the fourth enable output signal EN4 of the multi-pulse enable circuit (112) is transmitted to the enable input terminal of the subtractor (107), and the falling edge of the fourth enable output signal EN4 lags behind the falling edge of the read enable signal RD by 40ns. At this falling edge, the subtractor (107) performs subtraction of the first data from the second data, and the difference is used as the output data of the subtractor (107).

6. The arc detector of the vacuum coating pulse bias film power supply according to claim 1, characterized in that: The parallel data input terminal of the dividend of the divider (108) is connected to the parallel data output terminal of the subtractor (107), the divisor of the divider (108) is fixed to 1, the fifth enable output signal EN5 of the multi-pulse enable circuit (112) is transmitted to the enable input terminal of the divider (108), the falling edge of the fifth enable output signal EN5 lags behind the falling edge of the read enable signal RD by 50ns, and the falling edge enables the division operation, and the quotient of the divider (108) is the current current change rate, which is used as the output of the divider (108).

7. The arc detector of the vacuum coating pulse bias film power supply according to claim 1, characterized in that: The positive parallel data input end of the slope comparison circuit (110) is connected to the parallel data output end of the quotient of the divider (108), and the negative parallel data input end of the slope comparison circuit (110) is connected to the parallel data output end of the SPI serial port register (109), and the SPI serial port register (109) can modify the negative parallel data of the slope comparison circuit (110); The sixth enable output signal EN6 of the multi-pulse enable circuit (112) is transmitted to the enable input terminal of the slope comparison circuit (110), the falling edge of the sixth enable output signal EN6 lags behind the falling edge of the read enable signal RD by 60ns, the falling edge enables the slope comparison operation, when the positive parallel data of the slope comparison circuit (110) is greater than the negative parallel data of the slope comparison circuit (110), the slope comparison circuit (110) outputs a high level signal, otherwise it outputs a low level signal.

8. The arc detector of the vacuum coating pulse bias film power supply according to claim 1, characterized in that: The shutdown enable input terminal of the PWM pulse forming circuit (111) is connected to the output terminal of the slope comparison circuit (110), the drive signal output by the PWM pulse forming circuit (111) is connected to the input terminal of the drive isolation circuit (104), and the output terminal of the drive isolation circuit (104) is connected to the input terminal of the output high-voltage pulse forming unit (102) of the pulse power supply; when the slope comparison circuit (110) outputs a high level, the drive signal output by the PWM pulse forming circuit (111) is shut off, and the drive signal is restored after a shutdown protection time.

9. The arc detector of the vacuum coating pulse bias film power supply according to claim 1, characterized in that: The multi-pulse enabling circuit (112) comprises a periodic pulse signal generator (201), a delay circuit A (202), a delay circuit B (203), a delay circuit C (204), a delay circuit D (205), a delay circuit E (206) and a delay circuit F (207); The periodic pulse signal generator (201) counts and divides the clock signal CLOCK, and outputs a first enable output signal EN1, and SEN is a synchronization signal input terminal of the periodic pulse signal generator (201); The first enable output signal EN1 is connected to the input end of the delay circuit A (202), and the delay circuit A (202) outputs a chip select signal CS and a read enable signal RD; The read enable signal RD is connected to the input terminal of the delay circuit B (203), and the delay circuit B (203) outputs a third enable output signal EN3; The third enable output signal EN3 is connected to the input end of the delay circuit C (204), and the delay circuit C (204) outputs the second enable output signal EN2; The second enable output signal EN2 is connected to the input end of the delay circuit D (205), and the delay circuit D (205) outputs a fourth enable output signal EN4; The fourth enable output signal EN4 is connected to the input end of the delay circuit E (206), and the delay circuit E (206) outputs a fifth enable output signal EN5; The fifth enable output signal EN5 is connected to the input terminal of the delay circuit F (207), and the delay circuit F (207) outputs the sixth enable output signal EN6.

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