Arithmetic device, arithmetic device operation method, and neural network processor

Abstract

Disclosed are an arithmetic device, an operation method of the arithmetic device, and a neural network processor. The arithmetic device includes: a first operand holding circuit configured to output a first operand according to a clock signal, generate an indication signal based on a bit value of high-order bit data including a most significant bit of the first operand, and gate the clock signal based on the indication signal, the clock signal being applied to a latch that latches the high-order bit data of the first operand; a second operand holding circuit configured to output a second operand according to the clock signal; and a calculation circuit configured to perform data gating on the high-order bit data of the first operand based on the indication signal, and output an operation result by performing an operation using the second operand and a modified first operand resulting from the data gating.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2019-0161679, filed with the Korean Intellectual Property Office on December 6, 2019, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This application relates to an arithmetic device, a method of operating the arithmetic device, and a neural network processor. More specifically, embodiments of this application relate to an arithmetic circuit that performs operations (such as convolution operations) using operands, a method of operating the arithmetic circuit, and a neural network processor that performs the operation method. Background Technology

[0003] Neural networks represent computational architectures that mimic the biological brain. With recent advancements in neural network technology, research is increasingly using neural network devices that implement neural network models for analysis in various electronic systems.

[0004] Neural network devices require the performance of numerous computations on complex input data, which consumes significant power. Therefore, a technique is desired that allows arithmetic devices (such as neural network devices) to perform computations efficiently and rapidly with reduced power consumption while analyzing input data and extracting information in real time. Summary of the Invention

[0005] Embodiments of this application relate to a method for reducing power consumption during the operation of an arithmetic device that uses operands.

[0006] According to one aspect of the embodiments, an arithmetic apparatus is provided, the arithmetic apparatus comprising: a first operand holding circuit configured to: generate an indication signal based on bit values ​​of high-order bit data of a first operand input to the first operand holding circuit, the high-order bit data of the first operand including the most significant bit of the first operand; gate a clock signal input to the first operand holding circuit based on the indication signal to generate a gated clock signal; apply the gated clock signal to a flip-flop that latches the high-order bit data of the first operand to generate latched high-order bit data of the first operand; and output bit data of the first operand. The first operand's bit data includes latched high-order bit data and low-order bit data of the first operand; the second operand holding circuit is configured to output a second operand to the second operand holding circuit based on a clock signal; and the arithmetic circuit is configured to: perform data gating on the latched high-order bit data of the first operand based on an indication signal to generate data-gated high-order bit data of the first operand, and output the operation result by performing an operation using the second operand and the modified first operand, wherein the modified first operand includes the data-gated high-order bit data of the first operand and the low-order bit data of the first operand.

[0007] According to another aspect of the embodiments, an arithmetic device is provided, the arithmetic device comprising: a first operand holding circuit configured to output a modified first operand based on a clock signal, the modified first operand including high-order data and low-order data of the first operand input to the first operand holding circuit; a second operand holding circuit configured to output a second operand input to the second holding circuit based on a clock signal; and an arithmetic circuit configured to perform an operation using the second operand and the modified first operand to output an operation result, wherein the arithmetic circuit comprises: a first clock gating circuit configured to generate a first-gated clock signal by selectively transmitting a clock signal based on the value of the high-order data of the first operand; a first flip-flop configured to latch the high-order data of the first operand based on the first-gated clock signal; and a second flip-flop configured to latch the low-order data of the first operand based on the clock signal.

[0008] According to one aspect of an embodiment, a neural network processor for accelerating a neural network is provided. The neural network processor includes: an input feature holding circuit configured to: output input feature values ​​based on a clock signal; generate an indication signal based on high-order bit data of the input feature corresponding to a predetermined number of high-order bit values ​​in the input feature values; and gate the clock signal according to a logic level of the indication signal, the clock signal being applied to a first flip-flop latching the high-order bit data of the input feature; a weight holding circuit configured to output weight values ​​based on the clock signal; and an arithmetic circuit configured to: perform data gating on the high-order bit data of the input feature according to the logic level of the indication signal; and output an operation result by performing multiplication and accumulation using the weight values ​​and modified input feature values ​​generated by the data gating.

[0009] According to one aspect of the embodiments, a neural network processor for accelerating neural networks is provided. The neural network processor includes: a weight holding circuit configured to: output weight values ​​based on a clock signal; generate an indication signal based on high-order bit data corresponding to a predetermined number of high-order bits in the weight values; and gate the clock signal according to a logic level of the indication signal, the clock signal being applied to a first flip-flop latching the high-order bit data of the weights; an input feature holding circuit configured to output input feature values ​​based on the clock signal; and an arithmetic circuit configured to perform data gating on the high-order bit data of the weights based on a logic level of the indication signal, and output an operation result by performing multiplication and accumulation using the input feature values ​​and modified weight values ​​generated by the data gating.

[0010] According to one aspect of the embodiments, a method for operating an arithmetic device is provided. The method includes: generating an indication signal based on the bit value of a high-order bit data of a first operand; gating a clock signal based on a logic level of the indication signal, the clock signal being applied to a flip-flop corresponding to the high-order bit data of the first operand; performing data gating on the high-order bit data of the first operand based on the logic level of the indication signal; and performing an operation using a second operand and a modified first operand generated by the data gating to output an operation result. Attached Figure Description

[0011] The embodiments of this application will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 An arithmetic apparatus according to an embodiment is shown;

[0013] Figure 2 A first operand holding circuit according to an embodiment is shown;

[0014] Figure 3 An arithmetic circuit according to an embodiment is shown;

[0015] Figure 4 An arithmetic circuit according to an embodiment is shown;

[0016] Figure 5 A clock gating circuit according to an embodiment is shown;

[0017] Figure 6 A data gating circuit according to an embodiment is shown;

[0018] Figure 7 An arithmetic circuit according to an embodiment is shown;

[0019] Figure 8A and Figure 8B The multiplication circuits according to the embodiments are shown respectively;

[0020] Figure 9 This is a flowchart of an operation method of an arithmetic device according to an embodiment;

[0021] Figure 10 An arithmetic apparatus according to an embodiment is shown;

[0022] Figure 11A and Figure 11B The multiplication circuits according to the embodiments are shown respectively;

[0023] Figure 12 An electronic system according to an embodiment is shown;

[0024] Figure 13 A neural network processor according to an embodiment is shown;

[0025] Figure 14 A neural network processor according to an embodiment is shown; and

[0026] Figure 15 A neural network processor according to an embodiment is shown. Detailed Implementation

[0027] In the following description, embodiments will be described in detail with reference to the accompanying drawings.

[0028] Figure 1 An arithmetic apparatus 10 according to an embodiment is shown. The arithmetic apparatus 10 can be implemented with any means that performs computational operations using operands. Operations can include at least one of a variety of operations. For example, operations can include mathematical operations (e.g., multiplication, addition, or convolution), at least one logical operation, or a combination of mathematical and logical operations. In one embodiment, the arithmetic apparatus 10 can be applied to a neural network processor that performs convolution.

[0029] The arithmetic device 10 may include a first operand holding circuit 100, a second operand holding circuit 200, and an arithmetic circuit 300.

[0030] The first operand holding circuit 100 can store a first operand and output the first operand according to the clock signal CK. For example, the first operand holding circuit 100 can output the first operand at the rising edge and / or falling edge of the clock signal CK. In other words, the first operand holding circuit 100 can output a first operand synchronized with the rising edge and / or falling edge of the clock signal CK.

[0031] The first operand may include first high-order bit data OP1_HO and first low-order bit data OP1_LO. For example, the first high-order bit data OP1_HO may include a predetermined number of high-order bit values ​​of the first operand, represented as a binary number, and the first low-order bit data OP1_LO may include other bit values ​​of the first operand besides the first high-order bit data OP1_HO. For example, the high-order bit data of the first operand may include the most significant bit of the first operand. As a non-limiting example for ease of description, the first operand may be 8 bits of data, the first high-order bit data OP1_HO may be 4 high-order bits of the first operand, and the first low-order bit data OP1_LO may be 4 low-order bits of the first operand.

[0032] In one embodiment, the first operand holding circuit 100 can generate an indication signal HZI based on the bit values ​​of the first higher-order bit data OP1_HO, and can provide the indication signal HZI to the arithmetic circuit 300. The indication signal HZI can indicate whether all bit values ​​of the first higher-order bit data are "0". For example, when all bit values ​​of the first higher-order bit data are "0", the indication signal HZI can have a first logic level (e.g., "0"), and when at least one bit value of the first higher-order bit data is not "0", the indication signal HZI can have a second logic level different from the first logic level (e.g., "1"). In other words, the first operand holding circuit 100 can monitor the higher-order bit values ​​of the first operand to output the indication signal HZI.

[0033] In one embodiment, the first operand-holding circuit 100 may include a first flip-flop that latches the first high-order data OP1_HO and a second flip-flop that latches the first low-order data OP1_LO. The first operand-holding circuit 100 may perform clock gating on the clock signal CK applied to the first flip-flop according to the logic level of the indicator signal HZI. In other words, the first operand-holding circuit 100 may generate a gated clock signal by selectively passing the clock signal CK (or, allowing the clock signal CK to pass) based on the logic level of the indicator signal HZI, and may provide the gated clock signal to the first flip-flop. The first flip-flop may latch the first high-order data OP1_HO according to the gated clock signal and output the latched first high-order data OP1_HO_L. The first operand-holding circuit 100 may provide the latched first high-order data OP1_HO_L, the indicator signal HZI, and the first low-order data OP1_LO to the arithmetic circuit 300.

[0034] The second operand holding circuit 200 can store the second operand OP2 and output the second operand OP2 according to the clock signal CK. For example, the second operand holding circuit 200 can output the second operand OP2 at the rising edge and / or falling edge of the clock signal CK. In other words, the second operand holding circuit 200 can output the second operand OP2 synchronized with the rising edge and / or falling edge of the clock signal CK.

[0035] Arithmetic circuit 300 can perform operations using the first operand and the second operand OP2 as input values, and output the operation result RES.

[0036] In one embodiment, arithmetic circuit 300 may perform data gating on latched first high-order bit data OP1_HO_L based on the logic level of indicator signal HZI. For example, arithmetic circuit 300 may selectively pass latched first high-order bit data OP1_HO_L (or, allow first high-order bit data OP1_HO_L to pass through) for arithmetic operations based on the logic level of indicator signal HZI. To achieve this functionality, arithmetic circuit 300 may include a reference... Figure 3 A detailed description of the data gating circuit.

[0037] In one embodiment, the arithmetic circuit 300 may include a third flip-flop and a fourth flip-flop. The third flip-flop latches the latched first high-order data OP1_HO_L, and the fourth flip-flop latches the first low-order data OP1_LO. The arithmetic circuit 300 may also perform clock gating on the clock signal CK applied to the third flip-flop based on the logic level of the indicator signal HZI. In other words, the arithmetic circuit 300 can generate a gating clock signal by selectively transmitting the clock signal CK based on the logic level of the indicator signal HZI, and can provide the gating clock signal to the third flip-flop. The third flip-flop can latch the latched first high-order data OP1_HO_L according to the gating clock signal.

[0038] Arithmetic circuit 300 can perform operations using a second operand OP2 and a modified first operand, the modified first operand being generated by at least one selected from the clock gating of the first operand holding circuit 100, the clock gating of the arithmetic circuit 300, and the data gating of the arithmetic circuit 300. Arithmetic circuit 300 can output an operation result RES. In one embodiment, the operation may include convolution, and more specifically, multiplication and accumulation. In one embodiment, arithmetic circuit 300 may include computational circuitry comprising multiplication and accumulation circuitry. (See reference...) Figure 3 , Figure 4 , Figure 7 , Figure 8A and Figure 8B Describe the arithmetic circuit 300 in detail.

[0039] According to an embodiment, the arithmetic device 10 can perform clock gating on the clock signal applied to a flip-flop associated with the first high-order bit data of the first operand. For example, when all bits of the first high-order bit data are "0", the arithmetic device 10 can perform clock gating such that the clock signal is not applied to the flip-flop latching the first high-order bit data, thereby eliminating unnecessary signal transitions in the signal lines transmitting the first high-order bit data. As the amount of unnecessary signal transitions is reduced, the power consumption of the arithmetic device 10 can be reduced.

[0040] Furthermore, the arithmetic device 10 can perform data gating on the first high-order bit data of the first operand. For example, when all bits of the first high-order bit data are "0", the arithmetic device 10 can perform data gating so that the first high-order bit data is not sent to the computing circuit, thereby eliminating unnecessary signal transitions in the signal lines transmitting the first high-order bit data. As the amount of unnecessary signal transitions is reduced, the power consumption of the arithmetic device 10 can be reduced.

[0041] Figure 2 A first operand holding circuit 100 according to an embodiment is shown. (Refer to...) Figure 1 describe Figure 2 .

[0042] The first operand holding circuit 100 may include a first operand buffer 110, a high-order bit zero determination circuit 120, a clock gating circuit 130, a low-order bit flip-flop 140, and a high-order bit flip-flop 150.

[0043] The first operand buffer 110 can store the first operand OP1. The first operand buffer 110 can provide the first operand OP1 to the high-order bit zero determination circuit 120. The first operand OP1 may include a first high-order bit data OP1_HO and a first low-order bit data OP1_LO according to the representation of the binary number. The first high-order bit data OP1_HO may include a predetermined number of high-order bit values ​​of the first operand OP1, and the first low-order bit data OP1_LO may include other bit values ​​of the first operand OP1 besides the first high-order bit data OP1_HO. The first operand buffer 110 can provide the first low-order bit data OP1_LO to the low-order bit flip-flop 140, and provide the first high-order bit data OP1_HO to the high-order bit flip-flop 150.

[0044] The high-order bit zero determination circuit 120 analyzes the high-order bit values ​​of the first operand OP1 to output an indication signal HZI. In one embodiment, the high-order bit zero determination circuit 120 monitors first high-order bit data OP1_HO included in the first operand OP1. For example, when all bits of the first high-order bit data OP1_HO are "0", the high-order bit zero determination circuit 120 generates an indication signal HZI with a first logic level (e.g., "0"). Similarly, when at least one bit value of the first high-order bit data OP1_HO is not "0", the high-order bit zero determination circuit 120 generates an indication signal HZI with a second logic level (e.g., "1"). The high-order bit zero determination circuit 120 provides the indication signal HZI to the clock gating circuit 130 and outputs the indication signal HZI to the first operand holding circuit 100.

[0045] Clock gating circuit 130 can perform clock gating on clock signal CK. Based on indicator signal HZI, the gated clock signal GCK is applied to higher-order flip-flop 150. For example, clock gating circuit 130 can use indicator signal HZI as an enable (EN) signal to perform clock gating on clock signal CK. For example, clock gating circuit 130 can generate gated clock signal GCK by selectively passing clock signal CK according to the logic level of indicator signal HZI. For example, clock gating circuit 130 can not pass clock signal CK in response to a first logic level of indicator signal HZI, and can output clock signal CK as gated clock signal GCK in response to a second logic level of indicator signal HZI. As a non-limiting example, when clock signal CK is not passed, gated clock signal GCK can continuously have the value "0". Clock gating circuit 130 can provide gated clock signal GCK to higher-order flip-flop 150. (Refer to...) Figure 5 Example of describing clock gating circuit 130.

[0046] The low-order bit flip-flop 140 can latch the first low-order bit data OP1_LO according to the clock signal CK. To achieve this function, the low-order bit flip-flop 140 may include various types and configurations of flip-flops or latches. However, the embodiments are not limited thereto. The low-order bit flip-flop 140 may be replaced by various types of memory, registers, or other structures that store multiple bits.

[0047] The high-order bit flip-flop 150 can latch the first high-order bit data OP1_HO according to the gated clock signal GCK. In other words, the high-order bit flip-flop 150 can output the first high-order bit data OP1_HO on the rising edge and / or falling edge of the gated clock signal GCK. The high-order bit flip-flop 150 can output the latched first high-order bit data OP1_HO_L. To achieve this function, the high-order bit flip-flop 150 can include various types and configurations of flip-flops or latches. However, the embodiments are not limited to this. The high-order bit flip-flop 150 can be replaced by various types of memory that store multiple bits.

[0048] When the gated clock signal GCK has a value of "0" according to the second logic level of the indicator signal HZI, the latched first high-order bit data OP1_HO_L output from the high-order bit flip-flop 150 can be maintained at the same value or a constant value, without being updated to a new value.

[0049] According to an embodiment, the first operand holding circuit 100 can perform clock gating on the clock signal CK applied to the high-order flip-flop 150 associated with the first high-order bit data OP1_HO of the first operand OP1. For example, when all bits of the first high-order bit data OP1_HO are "0", the clock gating circuit 130 can perform clock gating so that the clock signal CK is not applied to the high-order flip-flop 150, thereby eliminating unnecessary signal transitions in the signal lines transmitting the first high-order bit data. As the amount of unnecessary signal transitions is reduced, the power consumption of the first operand holding circuit 100 and the arithmetic device 10 can be reduced.

[0050] Figure 3 An arithmetic circuit 300 according to an embodiment is shown. (Refer to...) Figure 1 describe Figure 3 .

[0051] The arithmetic circuit 300 may include a data gating circuit 320 and a calculation circuit 340.

[0052] The data gating circuit 320 can perform data gating on the latched first high-order bit data OP1_HO_L based on the indication signal HZI. In other words, the data gating circuit 320 can selectively pass the latched first high-order bit data OP1_HO_L according to the logic level of the indication signal HZI. For example, the data gating circuit 320 can output the latched first high-order bit data OP1_HO_L as the first high-order bit data OP1_HO_DG in response to the first logic level of the indication signal HZI, and can output "0" as the first high-order bit data OP1_HO_DG in response to the second logic level of the indication signal HZI. To achieve this functionality, the data gating circuit 320 may include an AND gate that performs a logical AND operation using the indication signal HZI and the latched first high-order bit data OP1_HO_L. This will be referred to Figure 6 A detailed description is provided. The data gating circuit 320 can provide the first high-order bit data OP1_HO_DG of the data gating circuit to the computing circuit 340.

[0053] The calculation circuit 340 can perform operations using a second operand and a modified first operand, and can output the operation result RES. The modified first operand is generated by the clock gating of the first operand holding circuit 100 and / or the data gating of the arithmetic circuit 300. For example, the calculation circuit 340 can perform operations using the second operand OP2 and a modified first operand including data-gated first high-order data OP1_HO_DG and first low-order data OP1_LO, and can output the operation result RES. (See also...) Figures 7 to 8B Describe in detail various examples of computing circuit 340.

[0054] According to an embodiment, the arithmetic circuit 300 can perform data gating on the latched first high-order bit data OP1_HO_L. For example, when all bits of the first high-order bit data are "0", the data gating circuit 320 can perform data gating so that the latched first high-order bit data OP1_HO_L is not transmitted to the calculation circuit 340, thereby eliminating unnecessary signal transitions in the signal lines transmitting the first high-order bit data. When the amount of unnecessary signal transitions is reduced, the power consumption of the arithmetic circuit 300 and the arithmetic device 10 can be reduced.

[0055] Figure 4 An arithmetic circuit 300 according to an embodiment is shown. (Refer to...) Figure 1 describe Figure 4 .

[0056] The arithmetic circuit 300 may include a clock gate circuit 305, a high-order flip-flop 310, a low-order flip-flop 315, a data gate circuit 320, and a calculation circuit 340. The data gate circuit 320 may substantially be integrated with... Figure 3 The data gating circuit 320 operates in a similar manner to the calculation circuit 340. Figure 3 The computational circuit 340 operates in a similar manner. Therefore, its redundant description will be omitted.

[0057] Clock gating circuit 305 can perform clock gating on the clock signal CK applied to the higher-order flip-flop 310 based on the indicator signal HZI. For example, clock gating circuit 305 can use the indicator signal HZI as an enable (EN) signal to perform clock gating on the clock signal CK. For example, clock gating circuit 305 can generate a gated clock signal GCK2 by selectively passing the clock signal CK according to the logic level of the indicator signal HZI. For example, clock gating circuit 305 can not pass the clock signal CK in response to a first logic level of the indicator signal HZI, and can output the clock signal CK as the gated clock signal GCK2 in response to a second logic level of the indicator signal HZI. As a non-limiting example, when the clock signal CK is not passed, the gated clock signal GCK2 can continuously have the value "0". Clock gating circuit 305 can provide the gated clock signal GCK2 to the higher-order flip-flop 310. (Refer to...) Figure 5 Example describing clock gating circuit 305.

[0058] The high-order bit flip-flop 310 can latch the latched first high-order bit data OP1_HO_L according to the gated clock signal GCK2. In other words, the high-order bit flip-flop 310 can output the latched first high-order bit data OP1_HO_L on the rising edge and / or falling edge of the gated clock signal GCK2. The high-order bit flip-flop 310 can provide the latched first high-order bit data OP1_HO_L to the data gating circuit 320. To achieve this function, the high-order bit flip-flop 310 may include various types and configurations of flip-flops or latches. However, the embodiments are not limited to this. The high-order bit flip-flop 310 may be replaced by various types of memory that store multiple bits.

[0059] The low-order bit flip-flop 315 can latch the first low-order bit data OP1_LO according to the clock signal CK. To achieve this function, the low-order bit flip-flop 315 may include various types of flip-flops or latches. However, the embodiments are not limited thereto. The low-order bit flip-flop 315 may be replaced by various types of memory that store multiple bits.

[0060] When the gated clock signal GCK2 has a value of "0" according to the second logic level of the indicator signal HZI, the latched first high-order bit data OP1_HO_L output from the high-order bit flip-flop 310 can be maintained at a constant value without being updated to a new value.

[0061] According to an embodiment, the arithmetic circuit 300 can perform clock gating on the clock signal CK applied to the higher-order flip-flop 310. For example, when all bits of the first higher-order data OP1_HO are "0", the clock gating circuit 305 can perform clock gating so that the clock signal CK is not applied to the higher-order flip-flop 310, thereby eliminating unnecessary signal transitions in the signal lines of the latched first higher-order data OP1_HO_L. As the amount of unnecessary signal transitions is reduced, the power consumption of the arithmetic circuit 300 and the arithmetic device 10 can be reduced accordingly.

[0062] Figure 5 A clock gating circuit 50 according to an embodiment is shown. The clock gating circuit 50 may correspond to Figure 2 The clock gate circuit 130 and Figure 4 The clock gate circuit 305 in the middle.

[0063] The clock gating circuit 50 may include a latch circuit 51 and an AND gate 52.

[0064] The latch circuit 51 can latch the clock signal CK according to the enable signal EN. The latch circuit 51 can receive the indicator signal HZI as the enable signal HZI(EN). The latch circuit 51 can provide the latched clock signal to the first input terminal of the AND gate 52 according to the indicator signal HZI.

[0065] AND gate 52 can output a gated clock signal GCK by performing a logical AND operation using a clock signal CK and a latched clock signal received from latch circuit 51. To achieve this function, the latched clock signal can be input to the first input terminal of AND gate 52, and the clock signal CK can be input to the second input terminal of AND gate 52.

[0066] Although Figure 5 An example of a clock gating circuit 50 is shown, but embodiments are not limited thereto. The clock gating circuit 50 may include various types of circuits that perform the same function (i.e., selectively transmitting the clock signal CK according to the indication signal HZI).

[0067] Figure 6 A data gating circuit 320 according to an embodiment is shown. The data gating circuit 320 may correspond to Figure 3 and Figure 4 The data gating circuit 320 in the middle.

[0068] The data gating circuit 320 may include at least one AND gate. For example, the data gating circuit 320 may include first AND gates to m-th AND gates 322_1, 322_2 to 322_m. Here, "m" may be the number of bits in the latched first high-order bit data OP1_HO_L. In other words, at least one AND gate can perform a logical AND operation using the value of each bit in the latched first high-order bit data OP1_HO_L and the indication signal HZI.

[0069] At least one AND gate can output data-gated first high-order bit data OP1_HO_DG (e.g., OP1_HO_DG[m:1]) by performing a logical AND operation using an indicator signal HZI and latched first high-order bit data OP1_HO_L (e.g., OP1_HO_L[m:1]). For example, when the indicator signal HZI indicates a first logic level (e.g., "0"), the AND gate can output "0". Similarly, when the indicator signal HZI indicates a second logic level (e.g., "1"), the AND gate can output the latched first high-order bit data OP1_HO_L as data-gated first high-order bit data OP1_HO_DG.

[0070] Although Figure 6 An example of a data gating circuit 320 is shown, but embodiments are not limited thereto. The data gating circuit 320 may include various types of circuitry that perform the same function (i.e., selectively pass latched first high-order bit data OP1_HO_L according to the indication signal HZI).

[0071] Figure 7A computing circuit 340 according to an embodiment is shown. Specifically, the computing circuit 340 may correspond to an embodiment such as: Figure 1 The arithmetic circuit 300 in the diagram performs convolution using a first operand or a first set of operands including the first operand and a second operand or a second set of operands including the second operand OP2. Convolution can be implemented through operand multiplication and accumulation (addition, summation). (See reference...) Figure 1 and Figure 3 describe Figure 7 .

[0072] The calculation circuit 340 may include a multiplication circuit 342 and an accumulation circuit 349.

[0073] Multiplication circuit 342 can perform multiplication using a second operand OP2 and a modified first operand including data-gated first high-order data OP1_HO_DG and first low-order data OP1_LO. Multiplication circuit 342 can output a multiplication result RES_M. Multiplication circuit 342 can provide the multiplication result RES_M to accumulation circuit 349. Multiplication circuit 342 can... Figure 8A and Figure 8B The example described is used to implement this.

[0074] Accumulator circuit 349 can accumulate multiple values ​​of the multiplication result RES_M output by multiplication circuit 342. Accumulator circuit 349 can output operation result RES by adding multiple accumulated multiplication results RES_M with respect to a first operand set including a first operand and a second operand set including a second operand. To achieve this function, accumulator circuit 349 may include a memory (such as a buffer or register) for storing multiplication results RES_M and an adder for adding multiple multiplication results. Accumulator circuit 349 may store multiple multiplication results separately and then generate operation result RES by adding the multiplication results, but embodiments are not limited thereto. Accumulator circuit 349 may update a temporary sum value each time a multiplication result RES_M is received, and may output the last updated sum value as operation result RES.

[0075] Figure 8A and Figure 8B Multiplication circuits 342a and 342b according to embodiments are shown respectively. Multiplication circuits 342a and 342b can correspond to Figure 7 The multiplication circuit 342 in the diagram. Furthermore, refer to... Figures 1 to 3 and Figure 7 describe Figure 8A and Figure 8B .

[0076] Reference Figure 8AThe multiplication circuit 342a may include a first operand register 343a, a second operand register 345a, a multiplier 346a, and an output register 348a.

[0077] The first operand register 343a can temporarily store and output the modified first operand OP1_M. The modified first operand OP1_M may include the first high-order bit data OP1_HO_DG and the first low-order bit data OP1_LO of the data-gated array. For example, the modified first operand OP1_M can be formed by adding the first high-order bit data OP1_HO_DG of the data-gated array as a high-order bit to the first low-order bit data OP1_LO. In another embodiment, the modified first operand may include latched first high-order bit data and latched first low-order bit data. However, the examples are not limited to this; for example, the modified first operand may be generated by at least one selected from the clock gating of the first operand holding circuit, the clock gating of the arithmetic circuit, and the data gating of the arithmetic circuit.

[0078] Specifically, for example, when the indicator signal HZI has a first logic level, the first high-order bit data OP1_HO_DG of the data gating can be "0", and correspondingly, the modified first operand OP1_M can be formed by adding "0" as a high-order bit to the first low-order bit data OP1_LO. For example, when each of the first high-order bit data OP1_HO and the first low-order bit data OP1_LO is 4 bits and the indicator signal HZI has a first logic level, the modified first operand OP1_M can be formed by adding "0000" as a high-order bit to the first low-order bit data OP1_LO.

[0079] When the indicator signal HZI has the second logic level, the first high-order bit data OP1_HO_DG of the data gating can be the same as the first high-order bit data OP1_HO. Therefore, the modified first operand OP1_M can be the same as the data formed by adding the first high-order bit data OP1_HO to the first low-order bit data OP1_LO (i.e., the first operand OP1).

[0080] The second operand register 345a can temporarily store the second operand OP2 and output the second operand OP2.

[0081] Multiplier 346a can generate a multiplication result RES_M by performing multiplication using a second operand OP2 and a modified first operand OP1_M. For example, when each of the first operand OP1 and the second operand OP2 is 8-bit data, multiplier 346a can include an 8×8-bit multiplier or a 9×9-bit multiplier.

[0082] The output register 348a can temporarily store the multiplication result RES_M and can output the multiplication result RES_M as the output of the multiplication circuit 342a (e.g., output to the accumulator circuit 349).

[0083] Reference Figure 8B The multiplication circuit 342b may include a first operand low-order bit register 343_1b, a first operand high-order bit register 343_2b, a second operand register 345b, a first multiplier 346_1b, a second multiplier 346_2b, an adder 346_3b, a shifter 347b, and an output register 348b.

[0084] The first operand low-order bit register 343_1b can temporarily store the first low-order bit data OP1_LO. The first operand high-order bit register 343_2b can temporarily store the first high-order bit data of the data gating OP1_HO_DG. The second operand register 345b can temporarily store the second operand OP2.

[0085] The first multiplier 346_1b can output a first multiplication result M1 by multiplying a first low-order data OP1_LO with a second operand OP2. For example, when the first low-order data OP1_LO is 4 bits and the second operand OP2 is 8 bits, the first multiplier 346_1b may include a 4×8-bit multiplier or a 5×9-bit multiplier.

[0086] The second multiplier 346_2b outputs a second multiplication result M2 by multiplying the first high-order bit data OP1_HO_DG of the data gate with the second operand OP2. For example, when the first high-order bit data OP1_HO is 4 bits and the second operand OP2 is 8 bits, the second multiplier 346_2b may include a 4×8-bit multiplier or a 5×9-bit multiplier.

[0087] The shifter 347b can output the shifted second multiplication result M2_S by shifting the second multiplication result M2 by the number of bits in the first low-order bit data OP1_LO.

[0088] Adder 346_3b can output multiplication result RES_M by adding multiplication result M1 to the shifted second multiplication result M2_S.

[0089] Output register 348b can temporarily store the multiplication result RES_M, and output the multiplication result RES_M as the output of multiplication circuit 342b (e.g., output to accumulation circuit 349).

[0090] Figure 9 This is a flowchart illustrating the operation method of an arithmetic device according to an embodiment. (Refer to...) Figure 1 As described in Figure 8 Figure 9 .

[0091] In operation S120, the arithmetic device 10 may generate an indication signal HZI based on the high-order bit value of the first operand OP1. For example, the high-order bit zero determination circuit 120 of the first operand holding circuit 100 may monitor the first high-order bit data OP1_HO, which includes high-order bit values ​​in the first operand OP1, and may generate an indication signal HZI indicating whether all bit values ​​of the first high-order bit data OP1_HO are the same (e.g., "0").

[0092] In operation S140, the arithmetic device 10 can gate the clock signal CK applied to the flip-flop associated with the first high-order bit data OP1_HO based on the indication signal HZI. For example, the clock gating circuit 130 of the first operand holding circuit 100 can gate the clock signal CK applied to the high-order bit flip-flop 150 based on the logic level of the indication signal HZI. Similarly, for example, the clock gating circuit 305 of the arithmetic circuit 300 can gate the clock signal CK applied to the high-order bit flip-flop 310 based on the logic level of the indication signal HZI.

[0093] In operation S160, the arithmetic device 10 can perform data gating on the first high-order bit data OP1_HO based on the indication signal HZI. For example, the data gating circuit 320 of the arithmetic circuit 300 can generate the data-gated first high-order bit data OP1_HO_DG by gating the latched first high-order bit data OP1_HO_L based on the logic level of the indication signal HZI.

[0094] In operation S180, the arithmetic device 10 can output the operation result RES by performing an operation using the second operand OP2 and the modified first operand OP1_M. The modified first operand OP1_M may include the first high-order data OP1_HO_DG and the first low-order data OP1_LO of the data gating.

[0095] Figure 10 An arithmetic device 20 according to an embodiment is shown. The arithmetic device 20 may include a first operand holding circuit 100, a second operand holding circuit 200, and an arithmetic circuit 300. Focusing on the arithmetic device 20 and reference... Figures 1 to 9 The differences between the described arithmetic devices 10 are used to describe Figure 10 .

[0096] The first operand holding circuit 100 can be referenced Figures 1 to 9 The first operand holding circuit 100 described is essentially the same. However, Figures 1 to 9 The indicator signal HZI in the middle is renamed to the first indicator signal HZI_1.

[0097] and Figures 1 to 9The second operand holding circuit 200 for the output second operand OP2 is different from that in the previous example. Figures 1 to 9 The first operand holding circuit in the circuit is similar to 100. Figure 10 The second operand holding circuit 200 can output the second indicator signal HZI_2, the latched second high-order data OP2_HO_L and the second low-order data OP2_LO.

[0098] In other words, the second operand may include second high-order bit data OP2_HO and second low-order bit data OP2_LO. For example, the second high-order bit data may include a predetermined number of high-order bit values ​​of the second operand, which is represented as a binary number, and the second low-order bit data OP2_LO may include other bit values ​​of the second operand besides the second high-order bit data.

[0099] In one embodiment, the second operand holding circuit 200 can generate a second indication signal HZI_2 based on the bit value of the second higher-order bit data OP2_HO, and can provide the second indication signal HZI_2 to the arithmetic circuit 300. The second indication signal HZI_2 can indicate whether all bit values ​​of the second higher-order bit data are the same value (e.g., "0"). For example, when all bit values ​​of the second higher-order bit data are "0", the second indication signal HZI_2 can have a first logic level (e.g., "0"), and when at least one bit value of the second higher-order bit data is not "0", the second indication signal HZI_2 can have a second logic level different from the first logic level (e.g., "1"). In other words, the second operand holding circuit 200 can monitor the higher-order bit values ​​of the second operand to output the second indication signal HZI_2.

[0100] In one embodiment, the second operand-holding circuit 200 may include a high-order flip-flop that latches the second high-order data OP2_HO to generate latched second high-order data OP2_HO_L, and a low-order flip-flop that latches the second low-order data OP2_LO. The second operand-holding circuit 200 may perform clock gating on the clock signal CK applied to the high-order flip-flop according to the logic level of the second indication signal HZI_2. In other words, the second operand-holding circuit 200 may generate a gated clock signal by selectively passing the clock signal CK based on the logic level of the second indication signal HZI_2, and may provide the gated clock signal to the high-order flip-flop. The high-order flip-flop may latch the second high-order data OP2_HO according to the gated clock signal and output the latched second high-order data OP2_HO_L. The second operand-holding circuit 200 may provide the latched second high-order data OP2_HO_L, the second indication signal HZI_2, and the second low-order data OP2_LO to the arithmetic circuit 300.

[0101] The operation of arithmetic circuit 300 can be referenced. Figures 1 to 9 The operation of the described arithmetic circuit 300 is substantially the same or similar. Furthermore, the arithmetic circuit 300 can perform data gating on the latched second high-order bit data OP2_HO_L based on the second indicator signal HZI_2. The arithmetic circuit 300 can also gating the clock signal applied to the flip-flop associated with the latched second high-order bit data OP2_HO_L based on the second indicator signal HZI_2, and can perform operations based on the modified second operand generated by the clock gating and / or data gating. In other words, the arithmetic circuit 300 can output the operation result RES by performing operations using the modified first operand and the modified second operand.

[0102] Figure 11A and Figure 11B Multiplication circuits 342c and 342d according to embodiments are shown respectively. Specifically, Figure 11A and Figure 11B An example of a multiplication circuit included in the arithmetic circuit 300 of the arithmetic device 20 can be shown when the arithmetic circuit 300 performs convolution.

[0103] Reference Figure 11A The multiplication circuit 342c may include a first operand register 343c, a second operand register 345c, a multiplier 346c, and an output register 348c.

[0104] The first operand register 343c can temporarily store and output the modified first operand OP1_M. The modified first operand OP1_M may include the first high-order data OP1_HO_DG and the first low-order data OP1_LO of the data-gated array. For example, the modified first operand OP1_M can be formed by adding the first high-order data OP1_HO_DG of the data-gated array as a high-order bit to the first low-order data OP1_LO.

[0105] The second operand register 345c can temporarily store and output the modified second operand OP2_M. The modified second operand OP2_M may include the data-gated second high-order bit data OP2_HO_DG and the second low-order bit data OP2_LO. For example, the modified second operand OP2_M can be formed by adding the data-gated second high-order bit data OP2_HO_DG as a high-order bit to the second low-order bit data OP2_LO.

[0106] Multiplier 346c can generate multiplication result RES_M by performing multiplication using a modified first operand OP1_M and a modified second operand OP2_M. For example, when each of the first operand OP1 and the second operand OP2 is 8 bits of data, multiplier 346c can include an 8×8-bit multiplier or a 9×9-bit multiplier.

[0107] Output register 348c can temporarily store the multiplication result RES_M, and can output the multiplication result RES_M as the output of multiplication circuit 342c.

[0108] Reference Figure 11B The multiplication circuit 342d may include a first operand low-order register 343_1d, a first operand high-order register 343_2d, a second operand low-order register 345_1d, a second operand high-order register 345_2d, a first multiplier 346_1d, a second multiplier 346_2d, a third multiplier 346_3d, a fourth multiplier 346_4d, a first shifter 347_1d, a second shifter 347_2d, a third shifter 347_3d, an adder 346_5d, and an output register 348d.

[0109] The first operand low-order register 343_1d can temporarily store and output the first low-order data OP1_LO. The first operand high-order register 343_2d can temporarily store and output the first high-order data OP1_HO_DG of the data-gated operation. The second operand low-order register 345_1d can temporarily store and output the second low-order data OP2_LO. The second operand high-order register 345_2d can temporarily store and output the second high-order data OP2_HO_DG of the data-gated operation.

[0110] The first multiplier 346_1d outputs a first multiplication result M1 by multiplying a first low-order data OP1_LO with a second low-order data OP2_LO. For example, when both the first low-order data OP1_LO and the second low-order data OP2_LO are 4-bit data, the first multiplier 346_1d may include a 4×4-bit multiplier or a 5×5-bit multiplier.

[0111] The second multiplier 346_2d outputs a second multiplication result M2 by multiplying the first high-order bit data OP1_HO_DG of data gating with the second high-order bit data OP2_HO_DG of data gating. For example, when both the first and second high-order bit data are 4 bits, the second multiplier 346_2d may include a 4×4 bit multiplier or a 5×5 bit multiplier.

[0112] The third multiplier 346_3d outputs the third multiplication result M3 by multiplying the first high-order data OP1_HO_DG of the data gate with the second low-order data OP2_LO. For example, when the first high-order data is 4 bits and the second low-order data OP2_LO is 4 bits, the third multiplier 346_3d may include a 4×4 bit multiplier or a 5×5 bit multiplier.

[0113] The fourth multiplier 346_4d outputs the fourth multiplication result M4 by multiplying the first low-order data OP1_LO with the data-gated second high-order data OP2_HO_DG. For example, when the first low-order data OP1_LO is 4 bits and the second high-order data is 4 bits, the fourth multiplier 346_4d may include a 4×4-bit multiplier or a 5×5-bit multiplier.

[0114] The first shifter 347_1d can output the shifted second multiplication result M2_S by shifting the second multiplication result M2 by the sum of the number of bits in the first low-order bit data OP1_LO and the number of bits in the second low-order bit data OP2_LO.

[0115] The second shifter 347_2d can output the shifted third multiplication result M3_S by shifting the third multiplication result M3 by the number of bits in the first low-order data OP1_LO.

[0116] The third shifter 347_3d can output the shifted fourth multiplication result M4_S by shifting the fourth multiplication result M4 by the number of bits in the second low-order data OP2_LO.

[0117] Adder 346_5d can output multiplication result RES_M by adding the first multiplication result M1, the shifted second multiplication result M2_S, the shifted third multiplication result M3_S, and the shifted fourth multiplication result M4_S.

[0118] Output register 348d can temporarily store the multiplication result RES_M and output the multiplication result RES_M to the outside of multiplication circuit 342d.

[0119] Figure 12An electronic system 30 according to an embodiment is shown. The electronic system 30 can analyze input data in real time based on a neural network to obtain valid information, and based on this valid information, identify situations or control components of an electronic device equipped with the electronic system 30. For example, the electronic system 30 can be applied to drones, robotic devices (such as advanced driver assistance systems (ADAS)), smart TVs (TVs), smartphones, medical devices, mobile devices, image displays, measuring devices, Internet of Things (IoT) devices, etc. The electronic system 30 can be implemented in any of various other types of electronic devices. Hereinafter, the device using the accelerated neural network in the electronic system 30 is referred to as a neural network device.

[0120] Electronic system 30 may include a neural network processor (NPU) 1000, random access memory (RAM) 2000, processor 3000, memory 4000, and sensor module 5000. The components of electronic system 30 may be interconnected via one or more communication lines or buses. NPU 1000 may be referred to as neural network processor 1000.

[0121] The NPU 1000 can generate neural networks, train or learn neural networks, perform operations based on input data and generate information signals based on the operation results, or retrain neural networks. Neural network models can include, but are not limited to, various types of models (such as, convolutional neural networks (CNNs) (e.g., GoogleNet, AlexNet, or VGG networks), region-based neural networks with CNNs (R-CNN), region proposal networks (RPN), recurrent neural networks (RNNs), stacked deep neural networks (S-DNNs), state-space dynamic neural networks (S-SDNNs), deconvolutional networks, deep belief networks (DBNs), restricted Boltzmann machines (RBMs), fully convolutional networks, long short-term memory (LSTM) networks, and classification networks). The NPU 1000 may include at least one processor that performs operations according to the neural network model. The NPU 1000 may include separate memory for storing programs corresponding to each neural network model.

[0122] The NPU 1000 can receive various types of input data via the system bus and can generate information signals based on the input data. For example, the NPU 1000 can generate information signals by performing neural network operations on the input data, and the neural network operations may include convolution. The information signals generated by the NPU 1000 may include at least one selected from various types of recognition signals (such as speech recognition signals, object recognition signals, image recognition signals, and biometric recognition signals). For example, the NPU 1000 can receive frame data included in a video stream as input data and can generate recognition signals about objects included in an image represented by the frame data from the frame data. However, embodiments are not limited to this. The NPU 1000 can receive various types of input data and generate recognition signals based on the input data.

[0123] RAM 2000 can temporarily store programs, data, or instructions. Programs and / or data stored in memory 4000 can be temporarily loaded into RAM 2000 according to the control or boot code of processor 3000. RAM 2000 can be implemented using memory such as dynamic RAM (DRAM) or static RAM (SRAM).

[0124] The processor 3000 controls all operations of the electronic system 30. For example, the processor 3000 may be implemented as a central processing unit (CPU). The processor 3000 may include a single core or multiple cores. The processor 3000 can process or execute programs and / or data stored in RAM 2000 and memory 4000. For example, the processor 3000 can control the functions of the electronic system 30 by executing programs stored in memory 4000.

[0125] Memory 4000 is a storage device for storing data and can store, for example, an operating system (OS), various programs, and various types of data. Memory 4000 may include, but is not limited to, DRAM. Memory 4000 may include at least one selected from volatile memory and non-volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM). Volatile memory may include DRAM, SRAM, and synchronous DRAM (SDRAM). In one embodiment, memory 4000 may include at least one selected from hard disk drive (HDD), solid-state drive (SSD), compact flash memory (CF), secure digital storage (SD), micro SD, mini SD, extreme digital storage (xD), and memory stick.

[0126] Sensor module 5000 can collect ambient information of electronic system 30. Sensor module 5000 can sense or receive image signals from outside electronic system 30 and can convert image signals into image data (e.g., image frames). For this operation, sensor module 5000 may include at least one sensing device selected from various sensing devices (such as image pickup devices, image sensors, light detection and ranging (LIDAR) sensors, ultrasonic sensors, and infrared sensors), or may receive sensing signals from sensing devices. In one embodiment, sensor module 5000 may provide image frames to NPU 1000. For example, sensor module 5000 may include an image sensor and can generate a video stream by capturing images of the environment surrounding electronic system 30, and sequentially provide consecutive image frames from the video stream to NPU 1000.

[0127] According to an embodiment, the NPU 1000 of the electronic system 30 can be implemented as a reference. Figures 1 to 9 The described arithmetic device 10 or reference Figures 10 to 11B The arithmetic device 20 is described. This will refer to... Figures 13 to 15 Provide a detailed description.

[0128] Figure 13 A neural network processor 1000 according to an embodiment is shown. Figure 13 The neural network processor 1000 can correspond to Figure 12 The NPU 1000.

[0129] Figure 13 The neural network processor 1000 may include an input feature preservation circuit 1100, a weight preservation circuit 1200, and an arithmetic circuit 1300.

[0130] Specifically, Figure 13 References can be shown Figures 1 to 9 An example of the arithmetic device 10 described is applied to a neural network processor 1000.

[0131] The input feature holding circuit 1100 can correspond to Figure 1 The first operand holding circuit 100 and the weight holding circuit 1200 can correspond to Figure 1 The second operand holding circuit 200, and the arithmetic circuit 1300 can correspond to Figure 1 The arithmetic circuit 300 in the neural network processor 1000. The input feature values ​​may correspond to a first operand, and the weight value WV may correspond to a second operand. The input feature values ​​may be values ​​included in the input feature map used in the convolution operation of the neural network processor 1000. The weight value WV may be values ​​included in the weight matrix used in the convolution operation of the neural network processor 1000. The latched high-order bit data IFV_HO_L of the input feature may correspond to... Figure 1The first high-order bit data OP1_HO_L is latched in the input feature. The low-order bit data IFV_LO can correspond to... Figure 1 The first low-order bit data OP1_LO in the algorithm. The output eigenvalue OFV corresponds to the operation result RES.

[0132] Figure 14 A neural network processor 1000 according to an embodiment is shown. Figure 14 The neural network processor 1000 can correspond to Figure 12 The NPU 1000.

[0133] Figure 14 The neural network processor 1000 may include an input feature preservation circuit 1100, a weight preservation circuit 1200, and an arithmetic circuit 1300.

[0134] Specifically, Figure 14 References can be shown Figures 1 to 9 An example of the arithmetic device 10 described is applied to a neural network processor 1000.

[0135] The weight holding circuit 1200 can correspond to Figure 1 The first operand holding circuit 100 and the input feature holding circuit 1100 can correspond to Figure 1 The second operand holding circuit 200, and the arithmetic circuit 1300 can correspond to Figure 1 The arithmetic circuit 300 is used. The weight value can correspond to the first operand, and the input feature value IFV can correspond to the second operand. The latched higher-order weight data WV_HO_L can correspond to... Figure 1 The first high-order bit data OP1_HO_L is latched in the memory. The weighted low-order bit data WV_LO can correspond to... Figure 1 The first low-order bit data OP1_LO in the algorithm. The output eigenvalue OFV corresponds to the operation result RES.

[0136] Figure 15 A neural network processor 1000 according to an embodiment is shown. Figure 15 The neural network processor 1000 can correspond to Figure 12 The NPU 1000.

[0137] Figure 15 The neural network processor 1000 may include an input feature preservation circuit 1100, a weight preservation circuit 1200, and an arithmetic circuit 1300.

[0138] Specifically, Figure 15 References can be shown Figures 10 to 11B An example of the arithmetic device 20 described is applied to a neural network processor 1000.

[0139] The input feature holding circuit 1100 can correspond to Figure 10 The first operand holding circuit 100 and the weight holding circuit 1200 can correspond to Figure 10 The second operand holding circuit 200, and the arithmetic circuit 1300 can correspond to Figure 10 The arithmetic circuit 300 is used. The input feature value can correspond to the first operand, and the weight value can correspond to the second operand. The latched high-order bit data IFV_HO_L of the input feature can correspond to... Figure 10 The first high-order bit data OP1_HO_L is latched in the input feature. The low-order bit data IFV_LO can correspond to... Figure 10 The first low-order bit data OP1_LO in the latch. The latched weight high-order bit data WV_HO_L can correspond to Figure 10 The second high-order bit data OP2_HO_L is latched in the memory. The weighted low-order bit data WV_LO can correspond to... Figure 10 The second lowest-order bit data OP2_LO is used. The output eigenvalue OFV corresponds to the computation result RES.

[0140] While various aspects have been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the claims.

Claims

1. An arithmetic apparatus comprising: a first operand holding circuit configured to: generate an indication signal based on bit values of high-order bit data of a first operand input to the first operand holding circuit, the high-order bit data of the first operand including a most significant bit of the first operand, gate a clock signal input to the first operand holding circuit based on the indication signal to generate a gated clock signal, generate latched high-order bit data of the first operand based on the gated clock signal being applied to a flip-flop that latches the high-order bit data of the first operand, and output bit data of the first operand, the bit data of the first operand including the latched high-order bit data of the first operand and low-order bit data of the first operand; a second operand holding circuit configured to output a second operand input to the second operand holding circuit based on the clock signal; and an arithmetic circuit configured to: perform data gating of the latched high-order bit data of the first operand based on the indication signal to generate data-gated high-order bit data of the first operand, and output a result of an operation by performing the operation using the second operand and a modified first operand, the modified first operand including the data-gated high-order bit data of the first operand and the low-order bit data of the first operand. The first operand holding circuit includes a zero determination circuit configured to generate the indication signal having a first logic level based on all of the bit values of the high-order bit data of the first operand being "0" and generate the indication signal having a second logic level based on at least one of the bit values of the high-order bit data of the first operand not being "0".

2. The arithmetic device of claim 1, wherein, The first operand holding circuit includes:

3. The arithmetic device according to claim 1 or 2, wherein, a high-order bit flip-flop configured to latch the high-order bit data of the first operand based on the gated clock signal to generate the latched high-order bit data of the first operand; and a low-order bit flip-flop configured to latch the low-order bit data of the first operand based on the clock signal. The first operand holding circuit further includes a clock gating circuit configured to generate the gated clock signal by gating the clock signal according to the logic level of the indication signal and provide the gated clock signal to the high-order bit flip-flop.

4. The arithmetic device according to claim 3, wherein The arithmetic circuit includes:

5. The arithmetic device according to claim 1 or 2, wherein a data gating circuit configured to generate the data-gated high-order bit data of the first operand by selectively passing the latched high-order bit data of the first operand based on the logic level of the indication signal; and a computation circuit configured to generate the result of the operation by performing the operation using the data-gated high-order bit data of the first operand, the low-order bit data of the first operand, and the second operand. The arithmetic circuit further includes:

6. The arithmetic device of claim 5, wherein, a clock gating circuit configured to generate a second gated clock signal by gating the clock signal based on the logic level of the indication signal; a high-order bit flip-flop configured to latch the latched high-order bit data of the first operand based on the second gated clock signal; and a low-order bit flip-flop configured to latch the low-order bit data of the first operand based on the clock signal. The arithmetic circuit further includes:

7. The arithmetic device according to claim 5, wherein, ​ a multiplication circuit configured to generate a multiplication result by performing multiplication using the second operand and the modified first operand; and an accumulation circuit configured to output an operation result by accumulating and summing at least one value of the multiplication result.

8. The arithmetic device of claim 7, wherein, The multiplication circuit includes: a first multiplier configured to generate a first multiplication result by multiplying low-order bit data of the first operand with the second operand; a second multiplier configured to generate a second multiplication result by multiplying high-order bit data of the data-gated first operand with the second operand; a shifter configured to generate a shifted second multiplication result by shifting the second multiplication result by a number of bits in the low-order bit data of the first operand; and an adder configured to add the shifted second multiplication result with the first multiplication result.

9. The arithmetic device according to claim 1 or 2, wherein, The second operand holding circuit is further configured to generate a second indication signal based on a bit value of the high-order bit data of the second operand, gate a clock signal input to the second operand holding circuit based on the second indication signal to generate a gated clock signal, and generate the latched high-order bit data of the second operand based on the gated clock signal being applied to a flip-flop that latches the high-order bit data of the second operand, and wherein the arithmetic circuit is further configured to perform data gating on the latched high-order bit data of the second operand based on the second indication signal to generate the data-gated high-order bit data of the second operand.

10. The arithmetic device according to claim 9, wherein, The arithmetic circuit includes: a first multiplier configured to generate a first multiplication result by multiplying low-order bit data of the first operand with low-order bit data of the second operand; a second multiplier configured to generate a second multiplication result by multiplying high-order bit data of the data-gated first operand with high-order bit data of the data-gated second operand; a third multiplier configured to generate a third multiplication result by multiplying low-order bit data of the second operand with the high-order bit data of the data-gated first operand; a fourth multiplier configured to generate a fourth multiplication result by multiplying the low-order bit data of the first operand with the high-order bit data of the data-gated second operand; a first shifter configured to generate a shifted second multiplication result by shifting the second multiplication result by a sum of a number of bits in the low-order bit data of the first operand and a number of bits in the low-order bit data of the second operand; a second shifter configured to generate a shifted third multiplication result by shifting the third multiplication result by a number of bits in the low-order bit data of the first operand; a third shifter configured to generate a shifted fourth multiplication result by shifting the fourth multiplication result by a number of bits in the low-order bit data of the second operand; and an adder configured to sum the first multiplication result, the shifted second multiplication result, the shifted third multiplication result, and the shifted fourth multiplication result.

11. An arithmetic device comprising: a first operand holding circuit configured to output a modified first operand based on a clock signal, the first operand including high-order bit data of a first operand input to the first operand holding circuit and low-order bit data of the first operand; a second operand holding circuit configured to output a second operand input to the second operand holding circuit based on the clock signal; and an arithmetic circuit configured to output an operation result by performing an operation using the second operand and the modified first operand, wherein the arithmetic circuit comprises: a first clock gating circuit configured to generate a first-gated clock signal by selectively passing the clock signal based on a bit value of high-order bit data of the first operand; a first flip-flop configured to latch the high-order bit data of the modified first operand based on the first-gated clock signal; and a second flip-flop configured to latch low-order bit data of the first operand based on the clock signal, wherein the first operand holding circuit is configured to generate an indication signal based on the bit value of the high-order bit data of the first operand input to the first operand holding circuit, generate a second-gated clock signal by gating the clock signal input to the first operand holding circuit based on the indication signal, and generate the latched high-order bit data of the first operand by latching the high-order bit data of the first operand based on the second-gated clock signal, wherein the modified first operand includes the latched high-order bit data of the first operand and the low-order bit data of the first operand.

12. The arithmetic device of claim 11, wherein, The first operand holding circuit includes a zero determination circuit configured to generate the indication signal having a first logic level based on all of the bit values of the high-order bit data of the first operand being "0" and generate the indication signal having a second logic level based on at least one of the bit values of the high-order bit data not being "0", and wherein the first clock gating circuit generates the first-gated clock signal by selectively passing the clock signal based on the indication signal generated based on the bit value of the high-order bit data of the first operand.

13. The arithmetic device of claim 11, wherein, The first operand holding circuit includes: a third flip-flop configured to latch the high-order bit data of the first operand based on the second-gated clock signal; and a fourth flip-flop configured to latch the low-order bit data of the first operand based on the clock signal.

14. The arithmetic device according to claim 13, wherein, The first operand holding circuit includes a second clock gating circuit configured to generate a second-gated clock signal by gating the clock signal input to the first operand holding circuit based on a logic level of an indication signal generated based on the bit value of the high-order bit data of the first operand.

15. The arithmetic device of claim 11, wherein, The arithmetic circuit further includes a data gating circuit configured to selectively pass the latched high-order bit data of the modified first operand based on the logic level of the indication signal generated based on the bit value of the high-order bit data of the first operand, and wherein the calculation circuit is further configured to perform the operation using the low-order bit data of the first operand and the second operand based on the first logic level of the indication signal.

16. The arithmetic device according to claim 11 or 12, wherein, The arithmetic circuit is further configured to output an operation result by performing a convolution using a first operand set and a second operand set, the first operand set being provided from the first operand holding circuit and the second operand set being provided from the second operand holding circuit, and wherein the arithmetic circuit further comprises: a multiplication circuit configured to generate a multiplication result by performing multiplication using the second operand and the modified first operand; and an accumulation circuit configured to output an operation result by accumulating the multiplication result and summing a plurality of accumulated multiplication results.

17. The arithmetic device of claim 16, wherein, The multiplication circuit includes a multiplier configured to multiply the modified first operand and the second operand, the modified first operand including high-order bit data of the data-gated first operand or the latched high-order bit data of the modified first operand output from the first flip-flop and the latched low-order bit data of the first operand output from the second flip-flop. 18.A neural network processor for accelerating a neural network, the neural network processor comprising: an input feature holding circuit configured to: output an input feature value based on a clock signal, generate an indication signal based on input feature high-order bit data corresponding to high-order bit values of a predetermined number of bits in the input feature value, gate a clock signal applied to a first flip-flop that latches the input feature high-order bit data according to a logic level of the indication signal to generate a first gated clock signal, and latch the input feature high-order bit data based on the first gated clock signal to generate latched input feature high-order bit data; a weight holding circuit configured to output a weight value according to the clock signal; and an arithmetic circuit configured to: perform data gating of the latched input feature high-order bit data according to the logic level of the indication signal to generate data-gated input feature high-order bit data, and output an operation result by performing multiplication and accumulation using the weight value and a modified input feature value resulting from the data gating, wherein the modified input feature value includes the data-gated input feature high-order bit data and input feature low-order bit data of the input feature value, wherein the input feature value is included in an input feature map used in a convolution operation of the neural network processor. The input feature holding circuit includes:

19. The neural network processor of claim 18, wherein, a first clock gating circuit configured to generate the first gated clock signal by selectively passing the clock signal based on the logic level of the indication signal; a first flip-flop configured to latch the input feature high-order bit data based on the first gated clock signal; and a second flip-flop configured to latch the input feature low-order bit data based on the clock signal. The arithmetic circuit includes a data gating circuit configured to perform the data gating by performing a logical AND operation using the indication signal and the latched input feature high-order bit data, and 20. The neural network processor of claim 18 or 19, wherein, wherein the modified input feature value includes a result value of the logical AND operation and the input feature low-order bit data. ​

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